** Profile: "SCHEMATIC1-LM5069_Cap_1"  [ C:\faridi\lm5069_capacitor-pspicefiles\schematic1\lm5069_cap_1.sim ] 

** Creating circuit file "LM5069_Cap_1.cir" 
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

*Libraries: 
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Users\faridifa\AppData\Roaming\SPB_Data\cdssetup\OrCAD_PSpice/16.6.0/PSpice.ini file:
.lib "C:\Users\faridifa\Desktop\LM5069_simulation\Project_library\LM5069\lm5069-2_trans.lib" 
.lib "C:\faridi\Project_library\LM5069\LM5069_2\lm5069-2_trans.lib" 
.lib "C:\faridi\Project_library\LM5069\LM5069_1\lm5069-1_trans.lib" 
.lib "C:\Users\faridifa\Desktop\LM5069_simulation\Project_library\SMBJ30CA\SMBJ33A.lib" 
.lib "C:\Users\faridifa\Desktop\LM5069_simulation\Project_library\SMBJ30CA\SMBJ30CA.lib" 
.lib "C:\Users\faridifa\Desktop\LM5069_simulation\Project_library\BZT52C33\BZT52C33.lib" 
.lib "C:\Users\faridifa\Desktop\LM5069_simulation\Project_library\SIDR870ADP_PS_REVA\SiDR870ADP_PS_REVA.LIB" 
.lib "C:\Users\faridifa\Desktop\LM5069_simulation\Project_library\SIDR870ADP_PS_REVA\SiDR870ADP_PS_RC_REVA.LIB" 
.lib "C:\Users\faridifa\Desktop\LM5069_simulation\Project_library\SUP70060E\SUP70060E_PS_Rev_A.LIB" 
.lib "C:\Users\faridifa\Desktop\LM5069_simulation\Project_library\SUP70060E\SUP70060E_PS_RC_Rev_A.LIB" 
.lib "C:\faridi\2\PSM_SIMULATION-PSpiceFiles\SCHEMATIC1\SIM_NEW\Project_library\BZX384-C10\BZX384-C10.OLB" 
.lib "C:\Cadence\SPB_16.6\tools\pspice\library\nom.lib" 

*Analysis directives: 
.TRAN  0 100m 0 
.OPTIONS ADVCONV
.PROBE64 V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) 
.INC "..\SCHEMATIC1.net" 


.END
