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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Sep 11, 2017
*ECN S17-1420, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiDR870ADP D G S 
M1 3 GX S S NMOS W= 5178192u L= 0.25u 
M2 S GX S D PMOS W= 5178192u L= 3.581e-07 
R1 D 3 4.951e-03 6.350e-03 1.951e-05 
CGS GX S 2.040e-09 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 2.608e-04 -5.292e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 5178192u 
************************************************ 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.079e-05 NSUB = 1.616e+17 
+ KAPPA = 1.389e-05 NFS = 4.781e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.017e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 6.066e-08 TREF = 25 BV = 101 
+RS = 6.828e-03 N = 1.037e+00 IS = 1.084e-12 
+EG = 1.144e+00 XTI = 7.861e-01 TRS = 1.868e-03 
+CJO = 5.063e-10 VJ = 1.672e+01 M = 1.000e-00 ) 
.ENDS 
