Gain value used to scale the cell 1 voltage ADC measurements for reporting in mV.
This value is multiplied by the cell 1 voltage ADC result.
Gain value used to scale the stack voltage ADC measurements for reporting in mV.
This value is multiplied by the upper 16-bits of the stack voltage ADC result.
This value is added to the Cell 1 Gain value to obtain the Cell 2 Gain, which is then used to scale the cell 2 voltage ADC measurements for reporting in mV
This value is added to the Cell 1 Gain value to obtain the Cell 3 Gain, which is then used to scale the cell 3 voltage ADC measurements for reporting in mV
This value is added to the Cell 1 Gain value to obtain the Cell 4 Gain, which is then used to scale the cell 4 voltage ADC measurements for reporting in mV
This value is added to the Cell 1 Gain value to obtain the Cell 5 Gain, which is then used to scale the cell 5 voltage ADC measurements for reporting in mV
Gain value used to scale the coulomb counter CC2 measurement after the Curr Offset is subtracted, for reporting in userA
Offset value subtracted from the coulomb counter CC2 measurement before scaling by Curr Gain to report result in userA.
Gain value used to scale the coulomb counter CC1 measurement after the CC1 Offset is subtracted, for reporting in userA
Offset value subtracted from the coulomb counter CC1 measurement before scaling by CC1 Gain to report result in userA
Offset value subtracted from the TS pin ADC measurement before result is reported
Internal temperature gain value used to scale the internal temperature ADC measurement after the Int Temp Offset is subtracted, for reporting in degrees Celsius
Internal temperature offset value subtracted from the internal temperature ADC measurement before scaling by Int Temp Gain, to report result in degrees Celsius
This register contains several settings that affect the power of the device
Sets normal ADC scan loop speed by inserting current-only measurements after each voltage and temperature scan loop. This setting is used while cell balancing is not active.
| Setting | Description |
|---|---|
| 0 | Full speed |
| 1 | Half speed |
| 2 | Quarter speed |
| 3 | Eighth speed |
Sets ADC scan loop speed while cell balancing is active by inserting idle slots after each voltage and temperature scan loop. This can be used to slow down voltage measurements while balancing to increase the duty-cycle, since balancing must be paused during measurement of the cell.
| Setting | Description |
|---|---|
| 0 | Half speed |
| 1 | Quarter speed |
| 2 | Eighth speed |
| 3 | Sixteenth speed |
Determines whether the device will shutdown if the die HW overtemperature detector triggers a fault.
| Setting | Description |
|---|---|
| 0 | Do not shutdown when the HW OT triggers |
| 1 | Device enters shutdown when the HW OT triggers |
Determines whether the device will shutdown if the LFO watchdog triggers a fault.
| Setting | Description |
|---|---|
| 0 | Do not shutdown the device when an LFO watchdog fault occurs. |
| 1 | Shutdown the device when an LFO watchdog fault occurs. |
Determines whether or not to disable the Low Frequency Oscillator in DEEPSLEEP mode to conserve power.
| Setting | Description |
|---|---|
| 0 | Disable the Low Frequency Oscillator in DEEPSLEEP mode (recommended) |
| 1 | Enable the Low Frequency Oscillator in DEEPSLEEP mode |
Sets the default value of BatteryStatus()[SLEEP_EN] which enables or disables SLEEP mode. After initialization, SLEEP_EN can stil be changed via the SLEEP_ENABLE and SLEEP_DISABLE subcommands.
| Setting | Description |
|---|---|
| 0 | Disable SLEEP mode by default |
| 1 | Enable SLEEP mode by default |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LOOP_SLOW_1 | LOOP_SLOW_0 | CB_LOOP_SLOW_1 | CB_LOOP_SLOW_0 | OTSD | LFOWD | DPSLP_LFO | SLEEP_EN |
This register contains settings to control the REGOUT voltage regulator
Default value of enable for REG_EN. This value is used upon exit of CONFIG_UPDATE mode, but can be modified during operation using the REGOUT Control() command.
| Setting | Description |
|---|---|
| 0 | REGOUT is not enabled (default) |
| 1 | REGOUT is enabled |
Default value for the REGOUT LDO settings. This value is used upon exit of CONFIG_UPDATE mode, but can be modified during operation using the REGOUT Control() command.
| Setting | Description |
|---|---|
| 0 | Set to 1.8V |
| 1 | Set to 1.8V |
| 2 | Set to 1.8V |
| 3 | Set to 1.8V |
| 4 | Set to 2.5V |
| 5 | Set to 3.0V |
| 6 | Set to 3.3V (default) |
| 7 | Set to 5V |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | REG_EN | REGCTL_2 | REGCTL_1 | REGCTL_0 |
This register sets the I2C address for the serial communications interface
7-bit I2C Address.
| Setting | Description |
|---|---|
| 0 | The device will use address 0x08.All other values are used as the address directly. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0 | I2CADDR_6 | I2CADDR_5 | I2CADDR_4 | I2CADDR_3 | I2CADDR_2 | I2CADDR_1 | I2CADDR_0 |
This register includes configuration settings for the I2C address for the serial communications interface
SCL Short Low Timeout, times out I2C logic if SCL is detected low for ~25ms
| Setting | Description |
|---|---|
| 0 | Timeout is not enabled (default) |
| 1 | Timeout is enabled |
SCL Short High Timeout, times out I2C logic if SCL is detected high for duration given by I2CCSHTOT1:0
| Setting | Description |
|---|---|
| 0 | Timeout is not enabled (default) |
| 1 | Timeout is enabled |
SCL Short High Timeout Duration
| Setting | Description |
|---|---|
| 0 | Timeout occurs after 64 ms |
| 1 | Timeout occurs after 512 ms |
| 2 | Timeout occurs after 1 ms |
| 3 | Timeout occurs after 15 ms (default) |
Long Low Timeout, times out I2C logic if SCL or SCL and SDA are detected low for duration given by I2CLLTOT
| Setting | Description |
|---|---|
| 0 | Timeout occurs if SCL is detected low for duration I2CLLTOT (default) |
| 1 | Timeout occurs if both SCL and SDA are detected low for duration I2CLLTOT |
Long Low Timeout Duration
| Setting | Description |
|---|---|
| 0 | Timeout is disabled |
| 1 | Timeout occurs after 0.5 seconds |
| 2 | Timeout occurs after 1 seconds |
| 3 | Timeout occurs after 1.5 seconds |
| 4 | Timeout occurs after 2 seconds (default) |
| 5 | Timeout occurs after 2.5 seconds |
| 6 | Timeout occurs after 3 seconds |
| 7 | Timeout occurs after 3.5 seconds |
I2C Bus Busy Timeout, times out I2C logic if a transaction is detected longer than the duration given by I2CLLTOT2:0
| Setting | Description |
|---|---|
| 0 | Timeout is not enabled (default) |
| 1 | Timeout is enabled |
Controls whether the I2C serial communications interface uses CRC.
| Setting | Description |
|---|---|
| 0 | CRC is not used (default) |
| 1 | CRC is enabled |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| I2CCSLTO | I2CCSHTO | I2CCSHTOT_1 | I2CCSHTOT_0 | I2CLLTO | I2CLLTOT_2 | I2CLLTOT_1 | I2CLLTOT_0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_5 | RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | I2CBBTO | CRC |
This register includes configuration settings related to the device data acquisition
This bit controls whether the TS pin is used for external thermistor measurement or as a general purpose ADC input.
| Setting | Description |
|---|---|
| 0 | TS pin is used for external thermistor measurement, with the internal pullup resistor enabled during measurement, and the ADC used in ratiometric mode, using the internal REG18 LDO voltage for the pullup resistor bias and for the ADC reference. |
| 1 | TS pin is used for general purpose ADC voltage measurement, with the internal pullup resistor disabled during measurement, and the ADC using the internal bandgap for its reference. |
Selects coulomb counter mode. Note that CC1 Current() and accumulated charge integration only operates in modes where the coulomb counter is running continuously (0x00 NORMAL mode, or 0x01 NORMAL mode while no idle slots are being introduced, or 0x02 NORMAL mode)
| Setting | Description |
|---|---|
| 0 | NORMAL mode: Coulomb counter runs continuously, independent of the LOOP_SLOW or CB_LOOP_SLOW setting.SLEEP mode: Coulomb counter run continuously while the voltage ADC is running in SLEEP mode during a burst measurement. It stops at the conclusion of the measurement underway when the burst measurement completes.Startup mode (at initial powerup from SHUTDOWN or exit of DEEPSLEEP): Coulomb counter runs continuously while the voltage ADC is running during the Startup Sequence. It stops at the conclusion of the measurement underway when the Startup Sequence completes (default) |
| 1 | NORMAL mode: Coulomb counter runs continuously if LOOP_SLOW or CB_LOOP_SLOW is set to the fastest setting. When these parameters are modified to slower settings, the device inserts 1, 3, or 7 idle slots between each current measurement slot, thereby reducing the average output rate of the current measurements.SLEEP mode: Coulomb counter run continuously while the voltage ADC is running in SLEEP mode during a burst measurement. It stops at the conclusion of the measurement underway when the burst measurement completes.Startup mode (at initial powerup from SHUTDOWN or exit of DEEPSLEEP): Coulomb counter runs continuously while the voltage ADC is running during the Startup Sequence. It stops at the conclusion of the measurement underway when the Startup Sequence completes. |
| 2 | NORMAL mode: Coulomb counter runs continuously in low power mode (so only takes ~4 µA instead of ~60 µA).SLEEP mode: SLEEP mode: Coulomb counter takes one measurement at the beginning of each burst measurement using its low power mode.Startup mode (at initial powerup from SHUTDOWN or exit of DEEPSLEEP): Coulomb counter takes one measurement using its low power mode at the beginning of the Startup Sequence. |
| 3 | Coulomb counter is powered down and does not operate at all. This provides a low power mode for customers who do not need current measurement. |
Selects ADC conversion speed for cell voltage measurements. Higher speed results in higher noise in conversions.
| Setting | Description |
|---|---|
| 0 | 2.93 ms per conversion (default) |
| 1 | 1.46 ms per conversion |
| 2 | 732 µs per conversion |
| 3 | 366 µs per conversion |
Selects ADC conversion speed for current measurements. Higher speed results in higher noise in conversions.
| Setting | Description |
|---|---|
| 0 | 2.93 ms per conversion (default) |
| 1 | 1.46 ms per conversion |
| 2 | 732 µs per conversion |
| 3 | 366 µs per conversion |
Selects ADC conversion speed for Shared Slot measurements. Higher speed results in higher noise in conversions.
| Setting | Description |
|---|---|
| 0 | 2.93 ms per conversion (default) |
| 1 | 1.46 ms per conversion |
| 2 | 732 µs per conversion |
| 3 | 366 µs per conversion |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD0_6 | RSVD0_5 | RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | TSMODE |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCMODE_1 | CCMODE_0 | CVADCSPEED_1 | CVADCSPEED_0 | IADCSPEED_1 | IADCSPEED_0 | SSADCSPEED_1 | SSADCSPEED_0 |
Not every system will use all of the cell input pins. If the system has fewer cells than the device supports, some VC input pins must be shorted together. To prevent action being taken for cell under-voltage conditions on pins that are shorted, these bits should be set appropriately
Not every system will use all of the cell input pins. If thesystem has fewer cells than the device supports, some VC input pinsmust be shorted together. To prevent action being taken for cellunder-voltage conditions on pins that are shorted, these bitsshould be set appropriately..
| Setting | Description |
|---|---|
| 0 | All cell inputs are used for actual cells. |
| 1 | All cell inputs are used for actual cells. |
| 2 | Two actual cells are in use (VC5-VC4A, VC1-VC0), unused cell pins can be shorted to an adjacent cell pin at the device or connected through RC to the cells. |
| 3 | Three actual cells are in use (VC5-VC4A, VC2-VC1, VC1-VC0), unused cell pins can be shorted to an adjacent cell pin at the device or connected through RC to the cells. |
| 4 | Four actual cells are in use (VC5-VC4A, VC4B-VC3A, VC2-VC1, VC1-VC0), unused cell pins can be shorted to an adjacent cell pin at the device or connected through RC to the cells. |
| 5 | All cell inputs are used for actual cells. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | VCELL_2 | VCELL_1 | VCELL_0 |
This parameter sets the default value of the AlarmEnable() register. The default value is reloaded at reset (if programmed into OTP) and at exit of CONFIG_UPDATE mode
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the internally determined value of CDTOGGLE to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin. This flag is set whenever the debounced CHG Detector signal differs from the previous debounced value.
| Setting | Description |
|---|---|
| 0 | The CDTOGGLE signal is not included in Alarm Status() |
| 1 | The CDTOGGLE signal is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SSA | SSB | SAA | SAB | XCHG | XDSG | SHUTV | CB |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FULLSCAN | ADSCAN | WAKE | SLEEP | TIMER_ALARM | INITCOMP | CDTOGGLE | POR |
This bitfield includes settings related to the FET driver operation
The CHG Detector block is enabled and provides an output signal to the Alarm logic.
| Setting | Description |
|---|---|
| 0 | CHG Detector block is disabled |
| 1 | CHG Detector block is enabled |
Some systems need the ability to override the device's FET control and force the FETs to turn off through commands. If that functionality is not needed, it can be disabled to prevent commands from turning the FETs off.
| Setting | Description |
|---|---|
| 0 | Host FET turnoff control commands are ignored |
| 1 | Host FET turnoff control commands are allowed |
Some systems need the ability to override the device's FET control and force the FETs to turn on through commands. If that functionality is not needed, it can be disabled to prevent commands from turning the FETs on.
| Setting | Description |
|---|---|
| 0 | Host FET turnon control commands are ignored |
| 1 | Host FET turnon control commands are allowed |
The CHG FET can be disabled while in SLEEP mode to conserve power. This bit configures whether or not to allow the CHG FET to be enabled in SLEEP mode.
| Setting | Description |
|---|---|
| 0 | CHG FET is turned off in SLEEP mode |
| 1 | CHG FET may be enabled in SLEEP mode |
The device supports both series and parallel FET configurations. When the CHG and DSG FETs are in series, current may flow through the body diode of one of the FETs when the other is enabled. In this configuration, body diode protection is used to turn the FET on when current above a threshold is detected to be flowing through that FET. When the system has separate DSG and CHG paths and parallel FETs, body diode protection is not needed and should be disabled.
| Setting | Description |
|---|---|
| 0 | Parallel FET mode: Body diode protection is disabled |
| 1 | Series FET mode: Body diode protection is enabled |
This is the default value of the bit which enables or disables device autonomous control of the FET drivers. If autonomous FET control is disabled, the device is in FET Test mode, in which the FET states are entirely controlled by the FET Control command. This is typically used during manufacturing to test FET circuitry or manual host control. Note that the FETs may still be enabled for body diode protection in FET Test mode.
This bit is loaded into the active state upon exit of CONFIG_UPDATE mode. The active state in use is provided by BatteryStatus( [FET_EN]) and can be toggled during operation using the FET_ENABLE() subcommand.
| Setting | Description |
|---|---|
| 0 | Autonomous FET control is disabled by default upon exit of CONFIG_UPDATE mode. FET Test mode is enabled. Device will not turn on FETs unless FET Control command instructs it to do so. |
| 1 | Autonomous FET control is enabled by default upon exit of CONFIG_UPDATE mode. FET Test mode is disabled. FET Control commands can still be used, based on the settings of HOST_FETOFF_EN and HOST_FETON_EN. |
This bit enables or disables the capability for the host to use the FET driver PWM modes.
| Setting | Description |
|---|---|
| 0 | Host PWM commands are ignored. |
| 1 | How PWM commands are accepted. |
This bit enables or disables the capability to manually recover faults using the PROT_RECOVERY() subcommand.
| Setting | Description |
|---|---|
| 0 | PROT_RECOVERY() subcommand cannot be used in SEALED mode. |
| 1 | PROT_RECOVERY() subcommand can be used in SEALED mode. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHGDETEN | HOST_FETOFF_EN | HOST_FETON_EN | SLEEPCHG | SFET | FET_EN | PWM_EN | PROTRCVR |
This value sets the debounce timing used for the Charge Detect signal. The debounce delay is programmable in units of 100 ms, from 0 to 25.5 seconds
This bitfield includes settings to control the cell balancing operation
This setting determines the delay from when cell balancing is disabled before cell measurements begin, to allow voltage transients at the cell input pins to settle.
| Setting | Description |
|---|---|
| 0 | No delay |
| 1 | 1 ms delay |
| 2 | 2 ms delay |
| 3 | 4 ms delay |
| 4 | 8 ms delay |
| 5 | 16 ms delay |
| 6 | 32 ms delay |
| 7 | 64 ms delay |
This bit enables blocking writes to the CB_ACTIVE_CELLS() subcommand if host-controlled balancing is not desired. Readback of cell balancing status using this command is always enabled.
| Setting | Description |
|---|---|
| 0 | Writes to CB_ACTIVE_CELLS() are accepted. |
| 1 | Writes to CB_ACTIVE_CELLS() are ignored. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | CBDLY_2 | CBDLY_1 | CBDLY_0 | CB_NO_CMD |
When the measurement of the TS pin configured for a thermistor is above this value, cell balancing is not allowed. Value ranges from 0 to 32512 in steps of 256 16-bit ADC codes. When using an NTC, this value corresponds to the low temperature limit
When the measurement of the TS pin configured for a thermistor is below this value, cell balancing is not allowed. Value ranges from 0 to 32512 in steps of 256 16-bit ADC codes. When using an NTC, this value corresponds to the high temperature limit.
When the internal temperature is above this value, cell balancing is not allowed. Units are in °C signed
This bitfield enables or disables various protections. Protections which are enabled will set their corresponding Safety Status flags when a fault is detected.
Note that Settings:Protection:CHG FET Protections A, Settings:Protection:DSG FET Protections A, and Settings:Protection:Both FET Protections B must be appropriately configured to control the FET action taken when these faults are detected.
Cell Overvoltage Protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Cell Undervoltage Protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Short circuit in discharge protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Overcurrent in discharge protection 1
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Overcurrent in discharge protection 2
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Overcurrent in charge protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Current latch protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
REGOUT safety check
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COV | CUV | SCD | OCD1 | OCD2 | OCC | CURLATCH | REGOUT |
This bitfield enables or disables various protections. Protections which are enabled will set their corresponding Safety Status flags when a fault is detected. Note that Settings:Protection:CHG FET Protections A, Settings:Protection:DSG FET Protections A, and Settings:Protection:Both FET Protections B must be appropriately configured to control the FET action taken when these faults are detected
Overtemperature in Discharge Protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Overtemperature in Charge Protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Undertemperature in Discharge Protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Undertemperature in Charge Protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Internal Overtemperature Protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Host Watchdog Protection
| Setting | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_1 | RSVD0_0 | OTD | OTC | UTD | UTC | OTINT | HWD |
This bitfield configures which protections will disable the DSG FET.
Cell Undervoltage Protection
| Setting | Description |
|---|---|
| 0 | DSG FET is not disabled when protection is triggered. |
| 1 | DSG FET is disabled when protection is triggered. |
Short circuit in discharge protection
| Setting | Description |
|---|---|
| 0 | DSG FET is not disabled when protection is triggered. |
| 1 | DSG FET is disabled when protection is triggered. |
Overcurrent in discharge protection 1
| Setting | Description |
|---|---|
| 0 | DSG FET is not disabled when protection is triggered. |
| 1 | DSG FET is disabled when protection is triggered. |
Overcurrent in discharge protection 2
| Setting | Description |
|---|---|
| 0 | DSG FET is not disabled when protection is triggered. |
| 1 | DSG FET is disabled when protection is triggered. |
Host Watchdog Protection
| Setting | Description |
|---|---|
| 0 | DSG FET is not disabled when protection is triggered. |
| 1 | DSG FET is disabled when protection is triggered. |
Overtemperature in Discharge Protection
| Setting | Description |
|---|---|
| 0 | DSG FET is not disabled when protection is triggered. |
| 1 | DSG FET is disabled when protection is triggered. |
Undertemperature in Discharge Protection
| Setting | Description |
|---|---|
| 0 | DSG FET is not disabled when protection is triggered. |
| 1 | DSG FET is disabled when protection is triggered. |
Internal Overtemperature Protection
| Setting | Description |
|---|---|
| 0 | DSG FET is not disabled when protection is triggered. |
| 1 | DSG FET is disabled when protection is triggered. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CUV | SCD | OCD1 | OCD2 | HWD | OTD | UTD | OTINT |
This bitfield configures which protections will disable the CHG FET.
Cell Overvoltage Protection
| Setting | Description |
|---|---|
| 0 | CHG FET is not disabled when protection is triggered. |
| 1 | CHG FET is disabled when protection is triggered. |
Short Circuit in Discharge Protection
| Setting | Description |
|---|---|
| 0 | CHG FET is not disabled when protection is triggered. |
| 1 | CHG FET is disabled when protection is triggered. |
Overcurrent in Charge Protection
| Setting | Description |
|---|---|
| 0 | CHG FET is not disabled when protection is triggered. |
| 1 | CHG FET is disabled when protection is triggered. |
Host Watchdog Protection
| Setting | Description |
|---|---|
| 0 | CHG FET is not disabled when protection is triggered. |
| 1 | CHG FET is disabled when protection is triggered. |
Overtemperature in Charge Protection
| Setting | Description |
|---|---|
| 0 | CHG FET is not disabled when protection is triggered. |
| 1 | CHG FET is disabled when protection is triggered. |
Undertemperature in Charge Protection
| Setting | Description |
|---|---|
| 0 | CHG FET is not disabled when protection is triggered. |
| 1 | CHG FET is disabled when protection is triggered. |
Internal Overtemperature Protection
| Setting | Description |
|---|---|
| 0 | CHG FET is not disabled when protection is triggered. |
| 1 | CHG FET is disabled when protection is triggered. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COV | SCD | OCC | RSVD0 | HWD | OTC | UTC | OTINT |
This bitfield configures which protections will disable the Both FETs.
VREF Measurement Check
| Setting | Description |
|---|---|
| 0 | Both FETs are not disabled when protection is triggered. |
| 1 | Both FETs are disabled when protection is triggered. |
VSS Measurement Check
| Setting | Description |
|---|---|
| 0 | Both FETs are not disabled when protection is triggered. |
| 1 | Both FETs are disabled when protection is triggered. |
REGOUT flag
| Setting | Description |
|---|---|
| 0 | Both FETs are not disabled when protection is triggered. |
| 1 | Both FETs are disabled when protection is triggered. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | VREF | VSS | REGOUT |
This register sets the current threshold at which the device will enable the FET driver to protect the body diode.
To minimize power dissipation in the FET body diode, the FET is turned on when reverse current is detected and the other FET is on.
When measured discharge current is greater in magnitude than Settings:Protection:Body Diode Threshold and the DSG FET is on, the CHG FET is turned on.
When measured charge current is greater than Settings:Protection:Body Diode Threshold and the CHG FET is on, the DSG FET is turned on.
When in parallel FET mode (Settings:FET:FET Options[SFET] = 0), body diode protection is disabled and a FET will not be turned on in response to reverse current.
This register sets the timing for the cell open-wire checks in NORMAL mode.
In order to detect a broken connection between a cell in the stack and the PCB, the device periodically enables a current from each enabled cell input to VSS.
0 = Cell open-wire check is disabled in NORMAL mode, current is not enabled.
All other values = Cell open-wire check is enabled for one measurement slot per ADSCAN per cell, then is disabled for the number of FULLSCANs given by this value in NORMAL mode.
This register sets the timing for the cell open-wire checks in SLEEP mode
This setting determines the delay from when the cell open-wire current is disabled before cell measurements begin in NORMAL mode, to allow voltage transients at the cell input pins to settle.
| Setting | Description |
|---|---|
| 0 | No delay |
| 1 | 1 ms delay |
| 2 | 2 ms delay |
| 3 | 4 ms delay |
| 4 | 8 ms delay |
| 5 | 16 ms delay |
| 6 | 32 ms delay |
| 7 | 64 ms delay |
Enable cell open-wire checks during SLEEP mode.
| Setting | Description |
|---|---|
| 0 | Cell open-wire checks are disabled in SLEEP mode. |
| 1 | Cell open-wire checks are enabled in SLEEP mode. |
In order to detect a broken connection between a cell in the stack and the PCB, the device periodically enables a current from each enabled cell input to VSS.
| Setting | Description |
|---|---|
| 0 | Current sources are activated once every 8 burst measurements. |
| 1 | Current sources are activated once every 4 burst measurements. |
| 2 | Current sources are activated once every 2 burst measurements. |
| 3 | Current sources are activated once every burst measurement. |
| 4 | Current sources are activated twice every burst measurement. |
| 5 | Current sources are activated 4 times every burst measurement. |
| 6 | Current sources are activated 8 times every burst measurement. |
| 7 | Current sources are activated 16 times every burst measurement. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0 | COWDLY_2 | COWDLY_1 | COWDLY_0 | COWSEN | COWSTIME_2 | COWSTIME_1 | COWSTIME_0 |
This register sets the timing for the Host Watchdog timing. If communications are not received for this many seconds, the Host Watchdog Fault is triggered. The Host Watchdog Alert is triggered when the timer reaches half of the timeout.
0 ~ 15: 1 ~ 16 sec in 1-sec steps
16 ~ 255: 20 ~ 976-sec in 4-sec steps
This parameter sets the Cell Undervoltage Protection threshold in units of mV.
Minimum value = 0 (setting for 0 V)
Maximum value = 5500 (setting for 5.5 V)
This parameter sets the Cell Undervoltage Protection delay. Units are the number of ADSCAN measurements taken (timing will depend on the measurement speed settings and may be longer in SLEEP mode) and can range from 1 to 255
This parameter sets the Cell Undervoltage Protection recovery hysteresis threshold. The minimum cell voltage must be greater than or equal to the CUV threshold plus this hysteresis to recover from a CUV condition
This parameter sets the Cell Undervoltage Protection recovery hysteresis threshold. The minimum cell voltage must be greater than or equal to the CUV threshold plus this hysteresis to recover from a CUV condition.
| Setting | Description |
|---|---|
| 0 | no autonomous recovery |
| 1 | 50mV |
| 2 | 100mV |
| 3 | 200mV |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_5 | RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | CUVRCVR_1 | CUVRCVR_0 |
This parameter sets the Cell Overvoltage Protection threshold in units of mV.
Minimum value = 0 (setting for 0 V)
Maximum value = 5500 (setting for 5.5 V)
This parameter sets the Cell Overvoltage Protection delay. Units are the number of ADSCAN measurements taken (timing will depend on the measurement speed settings and may be longer in SLEEP mode) and can range from 1 to 255
This parameter sets the Cell Overvoltage Protection recovery hysteresis threshold. The maximum cell voltage must be less than or equal to the COV threshold minus this hysteresis to recover from a COV condition
This parameter sets the Cell Overvoltage Protection recovery hysteresis threshold. The maximum cell voltage must be less than or equal to the COV threshold minus this hysteresis to recover from a COV condition.
| Setting | Description |
|---|---|
| 0 | no autonomous recovery |
| 1 | 50mV |
| 2 | 100mV |
| 3 | 200mV |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_5 | RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | COVRCVR_1 | COVRCVR_0 |
This parameter sets the Overcurrent in Charge Protection threshold in units of 2mV.
Minimum value = 2 (setting for 4 mV)
Maximum value = 62 (setting for 124 mV)
This parameter sets the Overcurrent in Charge Protection delay.
0x00 = Fastest delay (~0.46 ms)
0x01 - 0x40 = 1.22 ms to 20.435 ms in steps of 0.305 ms
0x41 - 0x80 = 22.875 ms to 176.595 ms in steps of 2.44 ms
0x81 - 0xC0 = 181.475 ms to 488.915 ms in steps of 4.88 ms
0xC1 - 0xFF = 498.675 ms to 1103.795 ms in steps of 9.77 ms
This parameter sets the Overcurrent in Discharge 1 Protection threshold in units of 2mV.
Minimum value = 2 (setting for 4 mV)
Maximum value = 100 (setting for 200 mV)
This parameter sets the Overcurrent in Discharge 1 Protection delay.
0x00 = Fastest delay (~0.46 ms)
0x01 - 0x40 = 1.22 ms to 20.435 ms in steps of 0.305 ms
0x41 - 0x80 = 22.875 ms to 176.595 ms in steps of 2.44 ms
0x81 - 0xC0 = 181.475 ms to 488.915 ms in steps of 4.88 ms
0xC1 - 0xFF = 498.675 ms to 1103.795 ms in steps of 9.77 ms
This parameter sets the Overcurrent in Discharge 2 Protection threshold in units of 2mV.
Minimum value = 2 (setting for 4 mV)
Maximum value = 100 (setting for 200 mV)
This parameter sets the Overcurrent in Discharge 2 Protection delay.
0x00 = Fastest delay (~0.46 ms)
0x01 - 0x40 = 1.22 ms to 20.435 ms in steps of 0.305 ms
0x41 - 0x80 = 22.875 ms to 176.595 ms in steps of 2.44 ms
0x81 - 0xC0 = 181.475 ms to 488.915 ms in steps of 4.88 ms
0xC1 - 0xFF = 498.675 ms to 1103.795 ms in steps of 9.77 ms
This parameter sets the Short Circuit in Discharge Protection threshold for the sense resistor voltage
This parameter sets the Short Circuit in Discharge Protection threshold for the sense resistor voltage.
| Setting | Description |
|---|---|
| 0 | 10 mV |
| 1 | 20 mV |
| 2 | 40 mV |
| 3 | 60 mV |
| 4 | 80 mV |
| 5 | 100 mV |
| 6 | 125 mV |
| 7 | 150 mV |
| 8 | 175 mV |
| 9 | 200 mV |
| 10 | 250 mV |
| 11 | 300 mV |
| 12 | 350 mV |
| 13 | 400 mV |
| 14 | 450 mV |
| 15 | 500 mV |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | SCDTHR_3 | SCDTHR_2 | SCDTHR_1 | SCDTHR_0 |
This parameter sets the Short Circuit in Discharge Protection delay
This parameter sets the delay before the fault is triggered.
| Setting | Description |
|---|---|
| 0 | Fastest |
| 1 | 15 µs |
| 2 | 31 µs |
| 3 | 61 µs |
| 4 | 122 µs |
| 5 | 244 µs |
| 6 | 488 µs |
| 7 | 977 µs |
| 8 | 1953 µs |
| 9 | 3906 µs |
| 10 | 7797 µs |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | SCDDLY_3 | SCDDLY_2 | SCDDLY_1 | SCDDLY_0 |
This parameter configures the number of retries for recovery of the SCD, OCD1, OCD2, or OCC before the FETs will be latched as disabled.
This parameter configures the number of retries for recovery of the SCD, OCD1, OCD2, or OCC before the FETs will be latched as disabled. If the protection does not retrigger within 5-sec after a recovery, the counter will be reset to 0.
| Setting | Description |
|---|---|
| 0 | Latching is disabled |
| 1 | 2 retries before FETs are latched disabled |
| 2 | 4 retries before FETs are latched disabled |
| 3 | 8 retries before FETs are latched disabled |
| 4 | 16 retries before FETs are latched disabled |
| 5 | 32 retries before FETs are latched disabled |
| 6 | 48 retries before FETs are latched disabled |
| 7 | 96 retries before FETs are latched disabled |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | CURRLAT_2 | CURRLAT_1 | CURRLAT_0 |
This parameter configures the delay after which current protections will recover.
Programmable from 1-sec to 255-sec in 1-sec steps.
0x0 = disable auto recovery.
This parameter configures the threshold for the Overtemperature in Charge Protection. The protection is triggered when the TS measurement is below this threshold.
This sets the threshold measured at the TS pin from 0 to 13770 in steps of 54 16-bit ADC codes.
escription: This parameter configures the delay for the Overtemperature in Charge Protection in units of numbers of measurements.
The settings are from 0 (fastest) to 255 measurements.
This parameter configures the recovery threshold for the Overtemperature in Charge Protection. The protection recovers when the TS measurement is above this threshold.
This sets the threshold measured at the TS pin from 0 to 13770 in steps of 54 16-bit ADC codes.
This parameter configures the threshold for the Undertemperature in Charge Protection. The protection is triggered when the TS measurement is above this threshold.
This sets the threshold measured at the TS pins from 0 to 19635 in steps of 77 16-bit ADC codes.
This parameter configures the delay for the Undertemperature in Charge Protection in units of numbers of measurements.
The settings are from 0 (fastest) to 255 measurements.
This parameter configures the recovery threshold for the Undertemperature in Charge Protection. The protection recovers when the TS measurement falls below this threshold.
This sets the threshold measured at the TS pins from 0 to 19635 in steps of 77 16-bit ADC codes.
This parameter configures the threshold for the Overtemperature in Discharge Protection. The protection is triggered when the TS measurement is below this threshold.
This sets the threshold measured at the TS pin from 0 to 13770 in steps of 54 16-bit ADC codes.
This parameter configures the delay for the Overtemperature in Discharge Protection in units of numbers of measurements.
The settings are from 0 (fastest) to 255 measurements.
This parameter configures the recovery threshold for the Overtemperature in Discharge Protection. The protection recovers when the TS measurement rises above this threshold.
This sets the threshold measured at the TS pin from 0 to 13770 in steps of 54 16-bit ADC codes.
This parameter configures the threshold for the Undertemperature in Discharge Protection.
This sets the threshold measured at the TS pins from 0 to 19635 in steps of 77 16-bit ADC codes.
This parameter configures the delay for the Undertemperature in Discharge Protection in units of numbers of measurements.
The settings are from 0 (fastest) to 255 measurements.
This parameter configures the recovery threshold for the Undertemperature in Discharge Protection.
This sets the threshold measured at the TS pins from 0 to 19635 in steps of 77 16-bit ADC codes.
This parameter configures the threshold for the Internal Overtemperature Protection.
The settings set the temperature threshold from 25°C to 150°C in 1°C steps.
This parameter configures the delay for the Internal Overtemperature Protection in units of numbers of measurements.
The settings are from 0 (fastest) to 255 measurements.
This parameter configures the recovery threshold for the Internal Overtemperature Protection.
The settings set the temperature recovery threshold from 25°C to 150°C in 1°C steps.
Configures the current threshold above which the device will not enter SLEEP mode. If a current magnitude is measured above this value during a periodic measurement in SLEEP mode, SLEEP mode will be exited
This parameter sets how often the device wakes to measure voltages and temperatures while in SLEEP mode.
Units in seconds (unsigned), except a setting of 0 results in measurements every 250 ms.
This parameter sets the Wake Comparator Current threshold (designated as voltage across the sense resistor) in units of 500 µV. This includes a check in both directions, and will cause the device to exit SLEEP and return to NORMAL mode whenever the absolute value of the current detected exceeds the threshold.
Threshold = 500 µV * (setting).
NOTE - the minimum setting is 1 (500 µV), meaning 500 mA across 1mΩ. The maximum setting is 10 (5 mV).
Configures the cell voltage threshold at which the device will enter SHUTDOWN mode after a 10 sec delay. This threshold does not apply to VC pins not configured for use with actual cells.
0 = Cell-Voltage-based shutdown disabled
All other values = Cell voltage shutdown threshold in mV (signed).
Configures the stack voltage threshold at which the device will enter SHUTDOWN mode after a 10 sec delay.
0 = Top-of-Stack-Voltage-based shutdown disabled
All other values = Top-of-stack voltage shutdown threshold in mV (unsigned).
Configures the internal temperature threshold at which the device will shut down.
0 = Shutdown based on measured internal temperature disabled
All other values = Shutdown Internal Temperature threshold in °C (unsigned)
As a countermeasure to inadvertent wake from SHUTDOWN, the device can be configured to automatically enter SHUTDOWN again after a number of minutes defined by this parameter.
If valid communications occur, or if charge current or discharge current above the SLEEP current threshold is detected before this time expires, automatic shutdown is cancelled.
If none of those events occur, after this time expires, the device will re-enter SHUTDOWN mode.
0 = Auto-shutdown feature is disabled.
All other values = Auto-shutdown occurs after this many minutes if it is not cancelled (unsigned).
These bits configure the security settings of the device
Setting this bit causes the device to enter SEALED mode when reset (if saved in OTP) or exiting CONFIG_UPDATE mode. In production systems, this bit should generally be set for security purposes.
| Setting | Description |
|---|---|
| 0 | Device does not default to SEALED mode. |
| 1 | Device default state is SEALED. |
Setting this bit prevents entry into CONFIG_UPDATE mode. This prevents further modifications to the device configuration after CONFIG_UPDATE mode is exited.
| Setting | Description |
|---|---|
| 0 | Configuration parameters can be changed in CONFIG_UPDATE mode. |
| 1 | Configuration parameters cannot be changed, CONFIG_UPDATE mode cannot be entered. |
Setting this bit prevents unsealing the device once it is sealed. If this is not programmed to OTP, this setting will be lost on a full reset and the device will again be able to unseal.
| Setting | Description |
|---|---|
| 0 | The device can be unsealed by sending the correct security keys. |
| 1 | The device cannot be unsealed. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | SEAL | LOCK_CFG | PERM_SEAL |
-
This is the first word of the security key that must be sent to transition from SEALED to FULLACCESS mode. The word should not be chosen which is identical to a subcommand address
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FAKEY_15 | FAKEY_14 | FAKEY_13 | FAKEY_12 | FAKEY_11 | FAKEY_10 | FAKEY_9 | FAKEY_8 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FAKEY_7 | FAKEY_6 | FAKEY_5 | FAKEY_4 | FAKEY_3 | FAKEY_2 | FAKEY_1 | FAKEY_0 |
-
This is the second word of the security key that must be sent to transition from SEALED to FULLACCESS mode. The word should not be chosen which is identical to a subcommand address or the same as the first word.
It must be sent within 5 seconds of the first word of the key and with no other commands in between.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FAKEY_15 | FAKEY_14 | FAKEY_13 | FAKEY_12 | FAKEY_11 | FAKEY_10 | FAKEY_9 | FAKEY_8 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FAKEY_7 | FAKEY_6 | FAKEY_5 | FAKEY_4 | FAKEY_3 | FAKEY_2 | FAKEY_1 | FAKEY_0 |
Provides individual alert signals when enabled safety alerts have triggered.
Cell Overvoltage Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Cell Undervoltage Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Short Circuit in Discharge Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Overcurrent in Discharge 1 Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Overcurrent in Discharge 2 Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Overcurrent in Charge Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COV | CUV | SCD | OCD1 | OCD2 | OCC | RSVD0_1 | RSVD0_0 |
Provides individual fault signals when enabled safety faults have triggered.
Cell Overvoltage Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Cell Undervoltage Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Short Circuit in Discharge Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Overcurrent in Discharge 1 Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Overcurrent in Discharge 2 Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Overcurrent in Charge Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Current Protection Latch Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates the number of attempted current protection recoveries has not yet exceeded the latch count. |
| 1 | Indicates the number of attempted current protection recoveries has exceeded the latch count, and autorecovery based on time is disabled. |
REGOUT Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COV | CUV | SCD | OCD1 | OCD2 | OCC | CURLATCH | REGOUT |
Provides individual alert signals when enabled safety alerts have triggered.
Overtemperature in Discharge Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Overtemperature in Charge Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Undertemperature in Discharge Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Undertemperature in Charge Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Internal Overtemperature Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
Host Watchdog Safety Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
VREF Measurement Diagnostic Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
VSS Measurement Diagnostic Alert
| Setting | Description |
|---|---|
| 0 | Indicates protection alert has not triggered |
| 1 | indicates protection alert has triggered |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OTD | OTC | UTD | UTC | OTINT | HWD | VREF | VSS |
Provides individual fault signals when enabled safety faults have triggered.
Overtemperature in Discharge Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Overtemperature in Charge Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Undertemperature in Discharge Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Undertemperature in Charge Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Internal Overtemperature Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
Host Watchdog Safety Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
VREF Measurement Diagnostic Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
VSS Measurement Diagnostic Fault
| Setting | Description |
|---|---|
| 0 | Indicates protection fault has not triggered |
| 1 | indicates protection fault has triggered |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OTD | OTC | UTD | UTC | OTINT | HWD | VREF | VSS |
Provides flags related to battery status.
This flag asserts if the device is in SLEEP mode
| Setting | Description |
|---|---|
| 0 | Device is not in SLEEP mode |
| 1 | Device is in SLEEP mode |
This flag asserts if the device is in DEEPSLEEP mode
| Setting | Description |
|---|---|
| 0 | Device is not in DEEPSLEEP mode |
| 1 | Device is in DEEPSLEEP mode |
This flag asserts if an enabled safety alert is present.
| Setting | Description |
|---|---|
| 0 | Indicates an enabled safety alert is not present |
| 1 | Indicates an enabled safety alert is present |
This flag asserts if an enabled safety fault is present.
| Setting | Description |
|---|---|
| 0 | Indicates an enabled safety fault is not present |
| 1 | Indicates an enabled safety fault is present |
SEC1:0 indicate the present security state of the device.
When in SEALED mode, device configuration may not be read or written and some commands are restricted.
When in FULLACCESS mode, unrestricted read and write access is allowed and all commands areaccepted.
| Setting | Description |
|---|---|
| 0 | 0: Device has not initialized yet. |
| 1 | 1: Device is in FULLACCESS mode. |
| 2 | 2: Unused. |
| 3 | 3: Device is in SEALED mode. |
This bit is set when the device is in autonomous FET control mode. The default value of this bit is set by the Settings:FET Options[FET_EN] bit in Data Memory upon exit of CONFIG_UPDATE mode. Its value can be modified during operation using the FET_ENABLE() subcommand.
| Setting | Description |
|---|---|
| 0 | Device is not in autonomous FET control mode, FETs are only enabled through manual command. |
| 1 | Device is in autonomous FET control mode, FETs can be enabled by the device if no conditions or commands prevent them being enabled. |
This bit is set when the device fully resets. It is cleared upon exit of CONFIG_UPDATE mode. It can be used by the host to determine if any RAM configuration changes were lost due to a reset.
| Setting | Description |
|---|---|
| 0 | Full reset has not occurred since last exit of CONFIG_UPDATE mode. |
| 1 | Full reset has occurred since last exit of CONFIG_UPDATE and reconfiguration of any RAM settings is required. |
This bit indicates whether or not SLEEP mode is allowed based on configuration and commands. The Settings:Configuration:Power Config[SLEEP_EN] bit sets the default state of this bit. The host may send commands to enable or disable SLEEP mode based on system requirements. When this bit is set, the device may transition to SLEEP mode when other SLEEP criteria are met.
| Setting | Description |
|---|---|
| 0 | SLEEP mode is disabled by the host. |
| 1 | SLEEP mode is allowed when other SLEEP conditions are met. |
This bit indicates whether or not the device is in CONFIG_UPDATE mode. It will be set after the SET_CFGUPDATE() subcommand is received and fully processed. Configuration settings may be changed only while this bit is set.
| Setting | Description |
|---|---|
| 0 | Device is not in CONFIG_UPDATE mode. |
| 1 | Device is in CONFIG_UPDATE mode. |
This bit indicates whether the ALERT pin is asserted (pulled low).
| Setting | Description |
|---|---|
| 0 | ALERT pin is not asserted (stays in hi-Z mode). |
| 1 | ALERT pin is asserted (pulled low). |
This bit indicates whether the CHG driver is enabled.
| Setting | Description |
|---|---|
| 0 | CHG driver is disabled. |
| 1 | CHG driver is enabled. |
This bit indicates whether the DSG driver is enabled.
| Setting | Description |
|---|---|
| 0 | DSG driver is disabled. |
| 1 | DSG driver is enabled. |
This bit indicates the value of the debounced CHG Detector signal.
| Setting | Description |
|---|---|
| 0 | CHG Detector debounced signal is low. |
| 1 | CHG Detector debounced signal is high. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SLEEP | DEEPSLEEP | SA | SS | SEC_1 | SEC_0 | RSVD0 | FET_EN |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POR | SLEEP_EN | CFGUPDATE | ALERTPIN | CHG | DSG | CHGDETFLAG | RSVD0 |
16-bit voltage on cell 1.
16-bit voltage on cell 2.
16-bit voltage on cell 3.
16-bit voltage on cell 4.
16-bit voltage on cell 5.
Internal 1.8V regulator voltage measured using bandgap reference, used for diagnostic of VREF1 vs VREF2.
Measurement of VSS using ADC, used for diagnostic of ADC input mux
16-bit voltage on top of stack
This is the most recent measured internal die temperature.
ADC measurement of the TS pin.
32-bit raw current measurement
16-bit CC2 current measurement
16-bit CC1 current measurement
Latched signal used to assert the ALERT pin. Write a bit high to clear the latched bit.
This bit is latched when a bit in Safety Status A() is set, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when a bit in Safety Status B() is set, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when a bit in Safety Alert A() is set, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when a bit in Safety Alert B() is set, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when the CHG driver is disabled, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when the DSG driver is disabled, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when either a cell voltage has been measured below Shutdown Cell Voltage, or the stack voltage has been measured below Shutdown Stack Voltage. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when cell balancing is active, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when a full scan is complete (including cell voltages, top-of-stack voltage, temperature, and diagnostic measurements), and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when a voltage ADC measurement scan is complete (this includes the cell voltage measurements and one additional measurement), and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when the device is wakened from SLEEP mode, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when the device enters SLEEP mode, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when the programmable timer expires, and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when the device completes the startup measurement sequence (which runs after an initial powerup, after a device reset, when the device exits CONFIG_UPDATE mode, and when it exits DEEPSLEEP mode) and the bit is included in the mask. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when the debounced CHG Detector signal is different from the last debounced value.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is latched when the POR bit in Battery Status is asserted.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SSA | SSB | SAA | SAB | XCHG | XDSG | SHUTV | CB |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FULLSCAN | ADSCAN | WAKE | SLEEP | TIMER_ALARM | INITCOMP | CDTOGGLE | POR |
Unlatched value of flags which can be selected to be latched (using Alarm Enable()) and used to assert the ALERT pin.
This bit is set when a bit in Safety Status A() is set.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is set when a bit in Safety Status B() is set.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is set when a bit in Safety Alert A() is set.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is set when a bit in Safety Alert B() is set.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is set when the CHG driver is disabled.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is set when the DSG driver is disabled.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is set when either a cell voltage has been measured below Shutdown Cell Voltage, or the stack voltage has been measured below Shutdown Stack Voltage. The bit is cleared when written with a "1". A bit set here will cause the ALERT pin to be asserted low.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit is set when cell balancing is active.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit pulses high briefly when a full scan is complete (including cell voltages, top-of-stack voltage, temperature, and diagnostic measurements).
This bit pulses high briefly when a voltage ADC measurement scan is complete (this includes the cell voltage measurements and one additional measurement).
This bit pulses high briefly when the device is wakened from SLEEP mode.
This bit pulses high briefly when the device enters SLEEP mode.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
This bit pulses high briefly when the programmable timer expires.
This bit pulses high briefly when the device has completed the startup measurement sequence (after powerup or reset or exit of CONFIG_UPDATE mode or exit of DEEPSLEEP).
This bit is set when the CHG Detector output is set, indicating that the CHG pin has been detected above a level of approximately 2 V.
| Setting | Description |
|---|---|
| 0 | CHG Detector output is not set |
| 1 | CHG Detector output is set |
This bit is set if the POR bit in Battery Status is asserted.
| Setting | Description |
|---|---|
| 0 | Flag is not set |
| 1 | Flag is set |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SSA | SSB | SAA | SAB | XCHG | XDSG | SHUTV | CB |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FULLSCAN | ADSCAN | WAKE | SLEEP | TIMER_ALARM | INITCOMP | CDRAW | POR |
Mask for Alarm Status(). Can be written to change during operation to change which alarm sources are enabled. The default value of this parameter is set by Settings:Configuration:Default Alarm Mask.
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
Setting this bit allows the internally determined value of CDTOGGLE to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin. This flag is set whenever the debounced CHG Detector signal differs from the previous debounced value.
| Setting | Description |
|---|---|
| 0 | The CDTOGGLE signal is not included in Alarm Status() |
| 1 | The CDTOGGLE signal is included in Alarm Status() |
Setting this bit allows the corresponding bit in Alarm Raw Status() to be mapped to the corresponding bit in Alarm Status() and to control the ALERT pin.
| Setting | Description |
|---|---|
| 0 | This bit in Alarm Raw Status() is not included in Alarm Status() |
| 1 | This bit in Alarm Raw Status() is included in Alarm Status() |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SSA | SSB | SAA | SAB | XCHG | XDSG | SHUTV | CB |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FULLSCAN | ADSCAN | WAKE | SLEEP | TIMER_ALARM | INITCOMP | CDTOGGLE | POR |
FET Control: Allows host control of individual FET drivers.
CHG FET driver control.
This bit only operates if the HOST_FETOFF_EN bit in data memory is set.
| Setting | Description |
|---|---|
| 0 | CHG FET driver is allowed to turn on if other conditions are met. |
| 1 | CHG FET driver is forced off. |
DSG FET driver control.
This bit only operates if the HOST_FETOFF_EN bit in data memory is set.
| Setting | Description |
|---|---|
| 0 | DSG FET driver is allowed to turn on if other conditions are met. |
| 1 | DSG FET driver is forced off. |
CHG FET driver control.
This bit only operates if the HOST_FETON_EN bit in data memory is set.
| Setting | Description |
|---|---|
| 0 | CHG FET driver is allowed to turn on if other conditions are met. |
| 1 | CHG FET driver is forced on. |
DSG FET driver control.
This bit only operates if the HOST_FETON_EN bit in data memory is set.
| Setting | Description |
|---|---|
| 0 | DSG FET driver is allowed to turn on if other conditions are met. |
| 1 | DSG FET driver is forced on. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | CHG_OFF | DSG_OFF | CHG_ON | DSG_ON |
REGOUT Control: Changes voltage regulator settings.
Control for TS pullup to stay biased continuously.
| Setting | Description |
|---|---|
| 0 | TS pullup resistor is not continuously connected. |
| 1 | TS pullup resistor is continuously connected. |
REGOUT LDO enable.
| Setting | Description |
|---|---|
| 0 | REGOUT LDO is disabled |
| 1 | REGOUT LDO is enabled |
REGOUT LDO voltage control.
| Setting | Description |
|---|---|
| 0 | REGOUT LDO is set to 1.8V |
| 1 | REGOUT LDO is set to 1.8V |
| 2 | REGOUT LDO is set to 1.8V |
| 3 | REGOUT LDO is set to 1.8V |
| 4 | REGOUT LDO is set to 2.5 V |
| 5 | REGOUT LDO is set to 3.0 V |
| 6 | REGOUT LDO is set to 3.3 V |
| 7 | REGOUT LDO is set to 5 V |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0_2 | RSVD0_1 | RSVD0_0 | TS_ON | REG_EN | REGOUTV_2 | REGOUTV_1 | REGOUTV_0 |
Controls the PWM mode of the DSG FET driver. Values are not used until the second byte is written.
DSG FET driver PWM mode control
| Setting | Description |
|---|---|
| 0 | DSG FET driver PWM mode is disabled |
| 1 | DSG FET driver PWM mode is enabled |
Time the DSG FET driver is enabled when PWM mode is enabled.
Settings from 30.52 µs to 3.876 ms in steps of 30.52 µs
A setting of 0 disables PWM mode, such that this command has no effect.
Time the DSG FET driver is disabled each cycle when PWM mode is enabled.
Settings from 122.1 µs to 31.128 ms in steps of 122.1 µs
A setting of 0 disables PWM mode, such that this command has no effect.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DSGPWMEN | DSGPWMON_6 | DSGPWMON_5 | DSGPWMON_4 | DSGPWMON_3 | DSGPWMON_2 | DSGPWMON_1 | DSGPWMON_0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DSGPWMOFF_7 | DSGPWMOFF_6 | DSGPWMOFF_5 | DSGPWMOFF_4 | DSGPWMOFF_3 | DSGPWMOFF_2 | DSGPWMOFF_1 | DSGPWMOFF_0 |
Controls the PWM mode of the CHG FET driver. Values are not used until the second byte is written.
CHG FET driver PWM mode control
| Setting | Description |
|---|---|
| 0 | CHG FET driver PWM mode is disabled |
| 1 | CHG FET driver PWM mode is enabled |
Time the CHG FET driver is enabled when PWM mode is enabled.
Settings from 30.52 µs to 3.876 ms in steps of 30.52 µs
A setting of 0 disables PWM mode, such that this command has no effect.
Time the CHG FET driver is disabled each cycle when PWM mode is enabled.
Settings from 488.4 µs to 124.512 ms in steps of 488.4 µs
A setting of 0 disables PWM mode, such that this command has no effect.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHGPWMEN | CHGPWMON_6 | CHGPWMON_5 | CHGPWMON_4 | CHGPWMON_3 | CHGPWMON_2 | CHGPWMON_1 | CHGPWMON_0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHGPWMOFF_7 | CHGPWMOFF_6 | CHGPWMOFF_5 | CHGPWMOFF_4 | CHGPWMOFF_3 | CHGPWMOFF_2 | CHGPWMOFF_1 | CHGPWMOFF_0 |
Thte DEVICE_NUMBER subcommand reports the device number that identifies the product. \n The data is returned in little-endian format
Reports the device number that identifies the product. \n The data is returned in little-endian format.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DEVNUM_15 | DEVNUM_14 | DEVNUM_13 | DEVNUM_12 | DEVNUM_11 | DEVNUM_10 | DEVNUM_9 | DEVNUM_8 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DEVNUM_7 | DEVNUM_6 | DEVNUM_5 | DEVNUM_4 | DEVNUM_3 | DEVNUM_2 | DEVNUM_1 | DEVNUM_0 |
The FW_VERSION subcommand returns three 16-bit word values. \n Bytes 0-1: Device Number (Big-Endian): Device number in big-endian format for compatibility with legacy products. \n Bytes 3-2: Firmware Version (Big-Endian): Device firmware major and minor version number (Big-Endian). \n Bytes 5-4: Build Number (Big-Endian): Firmware build number in big-endian, binary coded decimal format for compatibility with legacy products
Build Number (Big-Endian): Firmware build number in big-endian, binary coded decimal format for compatibility with legacy products
Firmware Version (Big-Endian): Device firmware major and minor version number (Big-Endian)
Device Number (Big-Endian): Device number in big-endian format for compatibility with legacy products
| 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
| FVBLDNUM_15 | FVBLDNUM_14 | FVBLDNUM_13 | FVBLDNUM_12 | FVBLDNUM_11 | FVBLDNUM_10 | FVBLDNUM_9 | FVBLDNUM_8 |
| 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| FVBLDNUM_7 | FVBLDNUM_6 | FVBLDNUM_5 | FVBLDNUM_4 | FVBLDNUM_3 | FVBLDNUM_2 | FVBLDNUM_1 | FVBLDNUM_0 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| FVFWVER_15 | FVFWVER_14 | FVFWVER_13 | FVFWVER_12 | FVFWVER_11 | FVFWVER_10 | FVFWVER_9 | FVFWVER_8 |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| FVFWVER_7 | FVFWVER_6 | FVFWVER_5 | FVFWVER_4 | FVFWVER_3 | FVFWVER_2 | FVFWVER_1 | FVFWVER_0 |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FVDEVNUM_15 | FVDEVNUM_14 | FVDEVNUM_13 | FVDEVNUM_12 | FVDEVNUM_11 | FVDEVNUM_10 | FVDEVNUM_9 | FVDEVNUM_8 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FVDEVNUM_7 | FVDEVNUM_6 | FVDEVNUM_5 | FVDEVNUM_4 | FVDEVNUM_3 | FVDEVNUM_2 | FVDEVNUM_1 | FVDEVNUM_0 |
Hardware Version: Reports the device hardware version number
Hardware Version: Reports the device hardware version number.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HWVER_15 | HWVER_14 | HWVER_13 | HWVER_12 | HWVER_11 | HWVER_10 | HWVER_9 | HWVER_8 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HWVER_7 | HWVER_6 | HWVER_5 | HWVER_4 | HWVER_3 | HWVER_2 | HWVER_1 | HWVER_0 |
Accumulated charge lower 32-bits (little-endian byte-by-byte). \n Lower 32 bits of signed 48-bit result, with the full 48-bit field having units of userA-seconds.
Accumulated charge upper 16-bits sign-extended to a 32-bit field (little-endian byte-by-byte). \n Upper bits of signed 48-bit result, with the full 48-bit field having units of userA-seconds.
Accumulated Time (little-endian byte-by-byte), 32-bit unsigned integer in units of 250 ms.
Cell balancing active cells: \n When read, reports a bit mask of which cells are being actively balanced. \n When written, starts balancing on the specified cells. \n Write 0x00 to disable balancing
Cell balancing active cells: When read, reports a bit mask of which cells are being actively balanced. When written, starts balancing on the specified cells. Write 0x00 to turn balancing off.
Bit 7 is reserved, read/write 0 to this bit
Bit 6 is reserved, read/write 0 to this bit
Bit 5 corresponds to the fifth active cell
Bit 4 corresponds to the fourth active cell
Bit 3 corresponds to the third active cell
Bit 2 corresponds to the second active cell
Bit 1 corresponds to the first active cell (will be connected between VC1 and VC0)
Bit 0 is reserved, read/write 0 to this bit
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CBCELLS_7 | CBCELLS_6 | CBCELLS_5 | CBCELLS_4 | CBCELLS_3 | CBCELLS_2 | CBCELLS_1 | CBCELLS_0 |
Programmable timer, which allows the REGOUT LDO to be disabled and wakened after a programmed time or by alarm
Control to determine if REGOUT is wakened when an Alarm Status() bit asserts.
| Setting | Description |
|---|---|
| 0 | Do not re-enable the REGOUT LDO if any bit in Alarm Status() asserts while the timer is running (default). |
| 1 | If [REGOUT_SD] is set and any bit in Alarm Status() asserts while the timer is running, reenable the REGOUT LDO based on the setting of REGOUT Control(). |
Delay before REGOUT is disabled when the timer is initiated while REGOUT is powered, and [REGOUT_SD]=1.
| Setting | Description |
|---|---|
| 0 | Zero delay (default). |
| 1 | 250ms delay. |
| 2 | 1-sec delay. |
| 3 | 4-sec delay |
Control to determine if REGOUT is disabled when the command is sent.
| Setting | Description |
|---|---|
| 0 | do not disable the REGOUT LDO when command is sent (default). |
| 1 | disable the REGOUT LDO when the timer is initiated, after delay of [REGOUT_SD_DLY]. When the timer expires, re-enable the REGOUT LDO based on the setting of REGOUT Control() |
Timer value programmable from 250 ms to 4 seconds in 250 ms increments (settings 1 ~ 16), and from 5 seconds to 243 seconds in 1 second increments (settings 17 ~ 255).
A setting of zero disables the timer.
Whenever this field is written with a non-zero value, it initiates the timer.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | REGOUT_ALARM_WK | REGOUT_SD_DLY_1 | REGOUT_SD_DLY_0 | REGOUT_SD |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PROG_TMR_7 | PROG_TMR_6 | PROG_TMR_5 | PROG_TMR_4 | PROG_TMR_3 | PROG_TMR_2 | PROG_TMR_1 | PROG_TMR_0 |
This command enables the host to allow recovery of selected protection faults
Cell Overvoltage or Cell Undervoltage fault recovery
| Setting | Description |
|---|---|
| 0 | Recovery of an COV/CUV fault is not triggered |
| 1 | Recovery of an COV/CUV fault is triggered. |
Recovery for a VSS or VREF fault from Safety Status B()
| Setting | Description |
|---|---|
| 0 | Recovery of a VSS or VREF fault is not triggered |
| 1 | Recovery of a VSS or VREF fault is triggered. |
Short Circuit in Discharge fault recovery
| Setting | Description |
|---|---|
| 0 | Recovery of an SCD fault is not triggered |
| 1 | Recovery of an SCD fault is triggered. |
Overcurrent in Discharge 1 fault recovery
| Setting | Description |
|---|---|
| 0 | Recovery of an OCD1 fault is not triggered |
| 1 | Recovery of an OCD1 fault is triggered. |
Overcurrent in Discharge 2 fault recovery
| Setting | Description |
|---|---|
| 0 | Recovery of an OCD2 fault is not triggered |
| 1 | Recovery of an OCD2 fault is triggered. |
Overcurrent in Charge fault recovery
| Setting | Description |
|---|---|
| 0 | Recovery of an OCC fault is not triggered |
| 1 | Recovery of an OCC fault is triggered. |
Temperature fault recovery
| Setting | Description |
|---|---|
| 0 | Recovery of a temperature fault is not triggered |
| 1 | Recovery of a temperature fault is triggered. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VOLTREC | DIAGREC | SCDREC | OCD1REC | OCD2REC | OCCREC | OTREC | RSVD0 |