C2-EPR Compliance Test Report



Power Delivery 3.1 Tests- Result Summary

Sl No

Test ID

Test Name

Test Result

1

TEST.PD.PHY.ALL.2

TEST.PD.PHY.ALL.2 Transmitter Eye Diagram

PASS

Power Delivery 3.1 Tests - Detailed Test Result

Test Status

Test Description

  PASS

  1. TEST.PD.PHY.ALL.2 Transmitter Eye Diagram

 

                    1/1 captures completed

  PASS

 COMMON.PROC.BU.2:

  PASS

 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk:

 

                    SourceCap Packet#15

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet#17

  PASS

 Rev3ChkdSnk:

  PASS

                          fBitRateMeas - TEST.PD.PHY.ALL.2#1:

  PASS

 Eye diagram-1:

 

                    Valid Protocol response for BIST Request

  PASS

 Eye diagram-2:

 

                    Valid BIST response pattern

  PASS

 Eye diagram-3:

 

                    Eye diagram plot passed at Mid Crossing Level.

  PASS

                          pBitRateMeas - TEST.PD.PHY.ALL.2#2:

  PASS

 Eye diagram-4:

 

                    BIST pattern duration 45.0371500 mS (Limit <= 60ms)

  PASS

 BMC_PHY_TX_EYE_5:

 

                    Rise time:
                    Average value = 415.409674 nS
                    Minimum value = 411.618131 nS
                    Maximum value = 419.486216 nS
                    Minimum Limit = 300 ns
                    
                    Fall time:
                    Average value = 486.877219 nS
                    Minimum value = 479.538709 nS
                    Maximum value = 492.187171 nS
                    Minimum Limit = 300 ns
                    

Packet List (Click to View AMS Summary)

Index

   Start time(s.ms.μs.ns)

   Stop time(s.ms.μs.ns)

Message Origin

 Message

 

 Secondary Message

 SOP

 Port Type

 Msg ID

 PDO

 Header(MSB to LSB)

 Payload(LSB to MSB)

TEST_PD_PHY_ALL_2_Transmitter_Eye_Diagram

Port A Packet Details

4

321.384590 mS

321.384590 mS

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

9

322.100520 mS

322.100520 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

10

347.840700 mS

347.840700 mS

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

11

349.540340 mS

349.540340 mS

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

12

349.557050 mS

349.557050 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

13

499.639160 mS

499.639160 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

15

556.379530 mS

556.976940 mS

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V .1A;

0x11A1

0x0A-0x90-0x01-0x08-

16

557.028340 mS

557.525740 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

17

561.620970 mS

562.250970 mS

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A

0x1082

0x00-0x00-0x80-0x13-

18

562.296370 mS

562.765780 mS

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

19

564.376390 mS

564.845790 mS

T->

Accept

SOP

DFP/Source/R3

1

0x03A3

20

564.909390 mS

565.406600 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

21

887.380460 mS

887.849860 mS

T->

PS_RDY

SOP

DFP/Source/R3

2

0x05A6

22

887.913460 mS

888.410670 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

24

888.449450 mS

888.449450 mS

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

25

896.431930 mS

896.929330 mS

<-D

PR_Swap

SOP

UFP/Sink/R3

1

0x028A

26

896.974130 mS

897.443520 mS

T->

GoodCRC

SOP

DFP/Source/R1

1

0x0321

27

899.377350 mS

899.846750 mS

T->

Reject

SOP

DFP/Source/R3

3

0x07A4

28

899.901550 mS

900.398960 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

3

0x0641

36

1.826.398.086

1.826.996.027

T->

BIST

SOP

DFP/Source/R3

4

BIST_Carrier_Mode0

0x19A3

0x00-0x00-0x00-0x50-

37

1.827.054.027

1.827.551.047

<-D

GoodCRC

SOP

UFP/Sink/R2

4

0x0841

39

1.827.969.007

1.873.006.022

<-D

BIST

BIST_CM2_Response

NONE

NONE/NONE/R-

0

0x0000

41

6.827.681.032

6.827.681.032

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

42

6.827.681.086

6.827.681.086

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

43

6.830.688.047

6.830.688.047

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

AMS Summary

AMS Index

AMS Name

AMS Start

AMS Stop

AMS Status

Child AMS Count

0

Power_Negotiation

15

22

COMPLETE

0

1

Power_Role_Swap

25

28

COMPLETE

0

2

Built_in_Self_Test_BIST

36

39

PARTIAL_TESTER_GOODCRC_MISSING

0

DUT Information

Manufacturer

TI

Model Number

TPS659xx

Serial Number

1

Test Information

Test Lab

Test_Engineer

Test_Engineer

Remarks

Remarks

Date_and_Time

2023/11/23 16:31:30

Controller and Instrument Information

Parameter

Value

GRL_USB_PD_Controller_Serial_No

GRL-C2-EPR-2022098

GRL_USB_PD_Software_Version

1.6.19.0

GRL_USB_PD_Firmware_Version

1.1.72

GRL USB-PD Ethernet Buffer Size

62K

GRL USB-PD Eload Firmware Version

1.5 / 1.5

GRL USB-PD PPS Firmware Version

4.0 / 4.0

Board Calibration

Calibration Success

RX mask Power selection

Neutral Power

Device_Type

DRP

Cable Type

GRL_SPL_EPR_CABLE_1

Impedance (milli ohm)

12

PD_Merged CTS Version

v.Q4-2023

VIF_File_Name

TI__TPS659xx__1__0-1123-01.xml

Noise Pattern Generation:

Two-Tone Noise

Application mode

Informational

Disabled all Pop-up during test execution

False

Pop-up Timer

0

Execution Time(In Minutes)

2

Power Delivery 3.1 Tests Information

Parameter

Value

Connect EPR Test Fixture

False

FR_Swap AUTO Box Connected

False