C2-EPR Compliance Test Report



Power Delivery 3.1 Tests- Result Summary

Sl No

Test ID

Test Name

Test Result

1

TEST.PD.USB4.EUSB.4

TEST.PD.USB4.EUSB.4 – DR_Swap after Entering USB4 Mode entry

FAIL

Power Delivery 3.1 Tests - Detailed Test Result

Test Status

Test Description

  FAIL

  1. TEST.PD.USB4.EUSB.4 – DR_Swap after Entering USB4 Mode entry

  PASS

 COMMON.PROC.BU.2:

  PASS

 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk:

 

                    SourceCap Packet#15

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet#17

  FAIL

 Rev3ChkdSnk:

  NA

                          DR_Swap PD Message response check - TEST.PD.USB4.EUSB.4#1:

  PASS

                          Tester Enter_USB PD Message response check - TEST.PD.USB4.EUSB.4#3:

 

                                   UUT respond Accept for Enter_USB PD Message

  FAIL

                          DR_Swap PD Message response check - TEST.PD.USB4.EUSB.4#4:

 

                                   UUT respond Reject to DR_Swap PD Message

  FAIL

                          SOP1 Enter_USB PD Message response check - TEST.PD.USB4.EUSB.4#5:

  FAIL

                          SOP2 Enter_USB PD Message response check - TEST.PD.USB4.EUSB.4#6:

  FAIL

                          SOP Enter_USB PD Message parameters of EUDO check - TEST.PD.USB4.EUSB.4#7:

  FAIL

                          SOP Enter_USB PD Message response expiry time check - TEST.PD.USB4.EUSB.4#8:

  FAIL

                          DR_Swap PD Message response check - TEST.PD.USB4.EUSB.4#9:

  FAIL

                          Tester Enter_USB PD Message response check - TEST.PD.USB4.EUSB.4#10:

Packet List (Click to View AMS Summary)

Index

   Start time(s.ms.μs.ns)

   Stop time(s.ms.μs.ns)

Message Origin

 Message

 

 Secondary Message

 SOP

 Port Type

 Msg ID

 PDO

 Header(MSB to LSB)

 Payload(LSB to MSB)

TEST_PD_USB4_EUSB_4_DR_Swap_after_Entering_USB4_Mode_entry

Port A Packet Details

4

360.481230 mS

360.481230 mS

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

9

361.194560 mS

361.194560 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

10

418.419780 mS

418.419780 mS

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

11

420.119510 mS

420.119510 mS

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

12

420.136130 mS

420.136130 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

13

570.218240 mS

570.218240 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

15

627.475890 mS

628.073300 mS

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V .1A;

0x11A1

0x0A-0x90-0x01-0x08-

16

628.124700 mS

628.622100 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

17

632.721130 mS

633.351120 mS

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A

0x1082

0x00-0x00-0x80-0x13-

18

633.395920 mS

633.865340 mS

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

19

635.469550 mS

635.938910 mS

T->

Accept

SOP

DFP/Source/R3

1

0x03A3

20

636.002790 mS

636.499960 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

21

958.473630 mS

958.943150 mS

T->

PS_RDY

SOP

DFP/Source/R3

2

0x05A6

22

959.006670 mS

959.504040 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

24

959.543170 mS

959.543170 mS

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

25

967.288900 mS

967.786300 mS

<-D

PR_Swap

SOP

UFP/Sink/R3

1

0x028A

26

967.830500 mS

968.299910 mS

T->

GoodCRC

SOP

DFP/Source/R1

1

0x0321

27

969.472150 mS

969.941520 mS

T->

Reject

SOP

DFP/Source/R3

3

0x07A4

28

969.996320 mS

970.493720 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

3

0x0641

31

1.862.188.088

1.862.188.088

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

33

1.862.475.063

1.862.475.063

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

38

1.906.474.046

1.907.071.086

T->

Enter_USB

SOP

DFP/Source/R3

4

0x19A8

0x00-0x20-0x8C-0x24-

39

1.907.135.046

1.907.632.087

<-D

GoodCRC

SOP

UFP/Sink/R2

4

0x0841

40

1.911.726.050

1.912.223.090

<-D

Accept

SOP

UFP/Sink/R3

2

0x0483

41

1.912.269.070

1.912.739.010

T->

GoodCRC

SOP

DFP/Source/R1

2

0x0521

43

1.912.798.007

1.912.798.007

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

44

3.904.306.026

3.904.306.026

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

46

3.904.481.069

3.904.481.069

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

48

3.915.478.062

3.915.948.002

T->

DR_Swap

SOP

DFP/Source/R3

5

0x0BA9

49

3.916.011.062

3.916.509.003

<-D

GoodCRC

SOP

UFP/Sink/R2

5

0x0A41

50

3.920.609.006

3.921.106.026

<-D

Reject

SOP

UFP/Sink/R3

3

0x0684

51

3.921.152.026

3.921.621.067

T->

GoodCRC

SOP

DFP/Source/R1

3

0x0721

53

3.921.677.035

3.921.677.035

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

55

5.913.485.091

5.913.485.091

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

56

5.914.966.013

5.914.966.013

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

59

5.935.484.049

5.936.081.089

T->

Enter_USB

SOP

DFP/Source/R3

6

0x1DA8

0x00-0x20-0x8C-0x24-

60

5.936.136.069

5.936.633.090

<-D

GoodCRC

SOP

UFP/Sink/R2

6

0x0C41

61

5.940.725.073

5.941.223.013

<-D

Accept

SOP

UFP/Sink/R3

4

0x0883

62

5.941.266.093

5.941.736.034

T->

GoodCRC

SOP

DFP/Source/R1

4

0x0921

64

5.941.791.061

5.941.791.061

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

65

6.933.403.037

6.933.403.037

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

67

6.933.496.044

6.933.496.044

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

68

6.943.777.007

6.943.777.007

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

69

6.943.777.060

6.943.777.060

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

70

6.947.106.064

6.947.106.064

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

AMS Summary

AMS Index

AMS Name

AMS Start

AMS Stop

AMS Status

Child AMS Count

0

Power_Negotiation

15

22

COMPLETE

0

1

Power_Role_Swap

25

28

COMPLETE

0

2

Enter_USB

38

41

COMPLETE

0

3

Data_Role_Swap

48

51

COMPLETE

0

4

Enter_USB

59

62

COMPLETE

0

DUT Information

Manufacturer

TI

Model Number

TPS659xx

Serial Number

1

Test Information

Test Lab

Test_Engineer

Test_Engineer

Remarks

Remarks

Date_and_Time

2023/11/23 16:35:55

Controller and Instrument Information

Parameter

Value

GRL_USB_PD_Controller_Serial_No

GRL-C2-EPR-2022098

GRL_USB_PD_Software_Version

1.6.19.0

GRL_USB_PD_Firmware_Version

1.1.72

GRL USB-PD Ethernet Buffer Size

62K

GRL USB-PD Eload Firmware Version

1.5 / 1.5

GRL USB-PD PPS Firmware Version

4.0 / 4.0

Board Calibration

Calibration Success

RX mask Power selection

Neutral Power

Device_Type

DRP

Cable Type

GRL_SPL_EPR_CABLE_1

Impedance (milli ohm)

12

PD_Merged CTS Version

v.Q4-2023

VIF_File_Name

TI__TPS659xx__1__0-1123-01.xml

Noise Pattern Generation:

Two-Tone Noise

Application mode

Informational

Disabled all Pop-up during test execution

False

Pop-up Timer

0

Execution Time(In Minutes)

6

Power Delivery 3.1 Tests Information

Parameter

Value

Connect EPR Test Fixture

False

FR_Swap AUTO Box Connected

False