C2-EPR Compliance Test Report



Power Delivery 3.1 Tests- Result Summary

Sl No

Test ID

Test Name

Test Result

1

TEST.PD.PROT.PORT3.4

TEST.PD.PROT.PORT3.4 Invalid Battery Capabilities Reference

FAIL

Power Delivery 3.1 Tests - Detailed Test Result

Test Status

Test Description

  FAIL

  1. TEST.PD.PROT.PORT3.4 Invalid Battery Capabilities Reference

  PASS

 COMMON.PROC.BU.2:

  PASS

 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk:

 

                    SourceCap Packet#15

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet#17

  PASS

 COMMON.PROC.BU.2 - REVISION_3_0 Rev3UnchkdSnk:

 

                    SourceCap Packet#72

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet#74

  PASS

 COMMON.PROC.BU.1:

  PASS

 COMMON.PROC.BU.1 - REVISION_3_0 Rev3ChkdSrc:

  PASS

                          First source capability timer - COMMON.PROC.BU.1#1:

 

                                   Vbus up time: 6.45s and Sourcecap time: 6.565s
                                   [PASS] Max = 250ms. Obtained time difference is 114.989ms

  PASS

                          DUT responded with accept message - COMMON.PROC.BU.1#2:

 

                                   Packet#142

  PASS

                          tSrcTransReq timer check - COMMON.PROC.BU.1#3:

 

                                   [PASS] Max = 325ms. Obtained time difference is 36.115ms
                                    Packet#144

  PASS

 COMMON.PROC.BU.1 - REVISION_3_0 Rev3UnchkdSrc:

  PASS

                          First source capability timer - COMMON.PROC.BU.1#1:

 

                                   Vbus up time: 9.268s and Sourcecap time: 9.383s
                                   [PASS] Max = 250ms. Obtained time difference is 114.989ms

  PASS

                          DUT responded with accept message - COMMON.PROC.BU.1#2:

 

                                   Packet#191

  PASS

                          tSrcTransReq timer check - COMMON.PROC.BU.1#3:

 

                                   [PASS] Max = 325ms. Obtained time difference is 36.127ms
                                    Packet#193

  FAIL

 Rev3ChkdSnk:

  FAIL

                          Get_Sink_Cap_Ext check - TEST.PD.PROT.PORT3.4#1:

 

                                   UUT respond Not_Supported to Get_Sink_Cap_Ext message

  PASS

                          Get_Battery_Cap check - TEST.PD.PROT.PORT3.4#2:

 

                                   UUT respond Not_Supported message

  FAIL

 Rev3UnchkdSnk:

  FAIL

                          Get_Sink_Cap_Ext check - TEST.PD.PROT.PORT3.4#1:

 

                                   UUT respond Not_Supported to Get_Sink_Cap_Ext message

  PASS

                          Get_Battery_Cap check - TEST.PD.PROT.PORT3.4#2:

 

                                   UUT respond Not_Supported message

  PASS

 Rev3ChkdSrc:

  PASS

                          Get_SourceCap_Extended check - TEST.PD.PROT.PORT3.4#1:

 

                                   UUT respond Not_Supported to Get_SourceCap_Extended message

  PASS

                          Get_Battery_Cap check - TEST.PD.PROT.PORT3.4#2:

 

                                   UUT respond Not_Supported message

  PASS

 Rev3UnchkdSrc:

  PASS

                          Get_SourceCap_Extended check - TEST.PD.PROT.PORT3.4#1:

 

                                   UUT respond Not_Supported to Get_SourceCap_Extended message

  PASS

                          Get_Battery_Cap check - TEST.PD.PROT.PORT3.4#2:

 

                                   UUT respond Not_Supported message

Packet List (Click to View AMS Summary)

Index

   Start time(s.ms.μs.ns)

   Stop time(s.ms.μs.ns)

Message Origin

 Message

 

 Secondary Message

 SOP

 Port Type

 Msg ID

 PDO

 Header(MSB to LSB)

 Payload(LSB to MSB)

TEST_PD_PROT_PORT_3_4_Invalid_Battery_Cap

Port A Packet Details

4

311.853600 mS

311.853600 mS

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

9

312.566000 mS

312.566000 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

10

363.079810 mS

363.079810 mS

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

11

364.779380 mS

364.779380 mS

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

12

364.796160 mS

364.796160 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

13

514.878280 mS

514.878280 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

15

571.849770 mS

572.447170 mS

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V .1A;

0x11A1

0x0A-0x90-0x01-0x08-

16

572.498570 mS

572.995980 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

17

577.088010 mS

577.717810 mS

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A

0x1082

0x00-0x00-0x80-0x13-

18

577.763410 mS

578.232820 mS

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

19

579.849830 mS

580.319230 mS

T->

Accept

SOP

DFP/Source/R3

1

0x03A3

20

580.382830 mS

580.880240 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

21

902.850700 mS

903.320100 mS

T->

PS_RDY

SOP

DFP/Source/R3

2

0x05A6

22

903.383700 mS

903.881110 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

24

903.919950 mS

903.919950 mS

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

25

911.792170 mS

912.289570 mS

<-D

PR_Swap

SOP

UFP/Sink/R3

1

0x028A

26

912.335570 mS

912.804980 mS

T->

GoodCRC

SOP

DFP/Source/R1

1

0x0321

27

914.847590 mS

915.317000 mS

T->

Reject

SOP

DFP/Source/R3

3

0x07A4

28

915.371800 mS

915.869200 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

3

0x0641

32

1.813.852.083

1.813.852.083

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

33

1.814.057.099

1.814.057.099

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

37

1.835.853.007

1.836.322.042

T->

Get_Sink_Cap_Ext

SOP

DFP/Source/R3

4

0x09B6

38

1.836.380.050

1.836.877.088

<-D

GoodCRC

SOP

UFP/Sink/R2

4

0x0841

39

1.840.977.031

1.841.474.083

<-D

Not_Supported

SOP

UFP/Sink/R3

2

0x0490

40

1.841.520.035

1.841.989.072

T->

GoodCRC

SOP

DFP/Source/R1

2

0x0521

42

1.842.047.096

1.842.047.096

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

44

1.873.696.021

1.873.696.021

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

46

1.873.853.039

1.873.853.039

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

48

1.884.851.085

1.885.449.025

T->

Get_Battery_Cap

SOP

DFP/Source/R3

5

Ext/Chk#0/Res/#1

0x9BA3

0x01-0x80-0x08-0x00-

49

1.885.500.085

1.885.998.006

<-D

GoodCRC

SOP

UFP/Sink/R2

5

0x0A41

50

1.890.091.089

1.890.589.009

<-D

Not_Supported

SOP

UFP/Sink/R3

3

0x0690

51

1.890.634.029

1.891.103.070

T->

GoodCRC

SOP

DFP/Source/R1

3

0x0721

53

1.891.156.086

1.891.156.086

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

56

2.182.854.080

2.182.854.080

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

57

2.183.683.086

2.183.683.086

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

58

2.194.144.092

2.194.144.092

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

59

2.194.145.042

2.194.145.042

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

60

2.197.155.098

2.197.155.098

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

61

3.195.847.028

3.195.847.028

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

66

3.196.566.071

3.196.566.071

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

67

3.214.573.007

3.214.573.007

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

68

3.216.272.068

3.216.272.068

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

69

3.216.289.043

3.216.289.043

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

70

3.366.371.054

3.366.371.054

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

72

3.422.857.026

3.423.454.067

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V .1A;

0x11A1

0x0A-0x90-0x01-0x09-

73

3.423.512.067

3.424.010.007

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

74

3.428.102.030

3.428.732.031

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A

0x1082

0x00-0x00-0x80-0x13-

75

3.428.777.031

3.429.246.071

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

76

3.430.857.033

3.431.326.073

T->

Accept

SOP

DFP/Source/R3

1

0x03A3

77

3.431.390.033

3.431.887.073

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

78

3.752.856.060

3.753.326.000

T->

PS_RDY

SOP

DFP/Source/R3

2

0x05A6

79

3.753.389.060

3.753.887.001

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

81

3.753.925.086

3.753.925.086

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

82

3.761.825.027

3.762.322.067

<-D

PR_Swap

SOP

UFP/Sink/R3

1

0x028A

83

3.762.367.007

3.762.836.058

T->

GoodCRC

SOP

DFP/Source/R1

1

0x0321

84

3.764.853.049

3.765.322.089

T->

Reject

SOP

DFP/Source/R3

3

0x07A4

85

3.765.377.069

3.765.875.010

<-D

GoodCRC

SOP

UFP/Sink/R2

3

0x0641

88

4.697.664.011

4.697.664.011

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

90

4.697.859.006

4.697.859.006

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

94

4.719.856.000

4.720.325.040

T->

Get_Sink_Cap_Ext

SOP

DFP/Source/R3

4

0x09B6

95

4.720.383.040

4.720.880.081

<-D

GoodCRC

SOP

UFP/Sink/R2

4

0x0841

96

4.724.974.064

4.725.471.084

<-D

Not_Supported

SOP

UFP/Sink/R3

2

0x0490

97

4.725.516.084

4.725.986.025

T->

GoodCRC

SOP

DFP/Source/R1

2

0x0521

99

4.726.049.073

4.726.049.073

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

102

4.757.858.094

4.757.858.094

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

103

4.757.957.070

4.757.957.070

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

105

4.768.857.098

4.769.423.038

T->

Get_Battery_Cap

SOP

DFP/Source/R3

5

UnChunked

0x8BA3

0x01-0x00-0x08-

106

4.769.487.018

4.769.984.039

<-D

GoodCRC

SOP

UFP/Sink/R2

5

0x0A41

107

4.774.073.042

4.774.570.082

<-D

Not_Supported

SOP

UFP/Sink/R3

3

0x0690

108

4.774.614.082

4.775.084.022

T->

GoodCRC

SOP

DFP/Source/R1

3

0x0721

110

4.775.149.053

4.775.149.053

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

112

5.066.634.064

5.066.634.064

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

114

5.066.859.091

5.066.859.091

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

115

5.078.148.019

5.078.148.019

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

116

5.078.148.076

5.078.148.076

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

117

5.081.153.069

5.081.153.069

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

118

6.079.853.008

6.079.853.008

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

123

6.080.562.060

6.080.562.060

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SNK

0x0000

124

6.124.782.040

6.124.782.040

<-D

Attach

Rp_4_7k_3A_Detected

NONE

NONE/NONE/-

0

Rp_4_7k_3A_Detected

0x0000

125

6.129.582.050

6.129.582.050

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SNK -> FSM_State_AttachWait_SNK

0x0000

126

6.329.596.020

6.329.596.020

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SNK -> FSM_State_Unattached_SNK

0x0000

127

6.429.527.015

6.429.527.015

<-D

Attach

Rp_4_7k_3A_Detected

NONE

NONE/NONE/-

0

Rp_4_7k_3A_Detected

0x0000

128

6.434.327.025

6.434.327.025

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SNK -> FSM_State_AttachWait_SNK

0x0000

129

6.552.016.089

6.552.646.089

<-D

VendorDefined

SOP1

NONE/DFP_UFP/R3/VdmR2/

0

 Discover ID;Initiator;

0x108F

0x01-0xA0-0x00-0xFF-

130

6.552.695.069

6.553.165.010

C->

GoodCRC

SOP1

NONE/CablePlug/R1

0

0x0101

131

6.558.865.034

6.559.974.075

C->

VendorDefined

SOP1

NONE/CablePlug/R3/VdmR2/

0

 Discover ID;ACK;

0x518F

0x41-0xA8-0x00-0xFF-0x7F-0x22-0x00-0x1C-0x00-0x00-0x00-0x00-0x00-0x00-0x03-0x00-0x52-0x28-0x08-0x00-

132

6.560.026.055

6.560.523.075

<-D

GoodCRC

SOP1

NONE/DFP_UFP/R2

0

0x0041

133

6.564.617.058

6.565.645.039

<-D

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V 5A; FS: 9V 5A; FS: 15V 5A; FS: 20V 4.8A;

0x41A1

0xF4-0x91-0x01-0x2F-0xF4-0xD1-0x02-0x00-0xF4-0xB1-0x04-0x00-0xE0-0x41-0x06-0x00-

134

6.566.657.040

6.567.685.021

<-D

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V 5A; FS: 9V 5A; FS: 15V 5A; FS: 20V 4.8A;

0x41A1

0xF4-0x91-0x01-0x2F-0xF4-0xD1-0x02-0x00-0xF4-0xB1-0x04-0x00-0xE0-0x41-0x06-0x00-

135

6.568.688.002

6.569.715.082

<-D

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V 5A; FS: 9V 5A; FS: 15V 5A; FS: 20V 4.8A;

0x41A1

0xF4-0x91-0x01-0x2F-0xF4-0xD1-0x02-0x00-0xF4-0xB1-0x04-0x00-0xE0-0x41-0x06-0x00-

136

6.570.670.092

6.570.670.092

<-D

Rp_Detected

Rp_4_7k_3A_Detected

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Detected

0x0000

137

6.584.409.036

6.584.409.036

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SNK -> FSM_State_Attached_SNK

0x0000

138

6.746.627.039

6.747.655.019

<-D

SourceCap

SOP

DFP/Source/R3

1

 FS: 5V 5A; FS: 9V 5A; FS: 15V 5A; FS: 20V 4.8A;

0x43A1

0xF4-0x91-0x01-0x2F-0xF4-0xD1-0x02-0x00-0xF4-0xB1-0x04-0x00-0xE0-0x41-0x06-0x00-

139

6.747.705.019

6.748.174.060

T->

GoodCRC

SOP

UFP/Sink/R1

1

0x0201

140

6.749.862.001

6.750.459.041

T->

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0.1A; MaxCurrent = 0.1A

0x1082

0x0A-0x28-0x00-0x11-

141

6.750.517.021

6.751.014.062

<-D

GoodCRC

SOP

DFP/Source/R2

0

0x0161

142

6.755.106.065

6.755.603.085

<-D

Accept

SOP

DFP/Source/R3

2

0x05A3

143

6.755.647.065

6.756.117.006

T->

GoodCRC

SOP

UFP/Sink/R1

2

0x0401

144

6.792.232.014

6.792.729.034

<-D

PS_RDY

SOP

DFP/Source/R3

3

0x07A6

145

6.792.777.054

6.793.246.094

T->

GoodCRC

SOP

UFP/Sink/R1

3

0x0601

146

6.793.977.027

6.793.977.027

<-D

Rp_Detected

Rp_12k_1_5A_Detected

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Detected

0x0000

147

6.811.024.088

6.811.522.028

<-D

DR_Swap

SOP

DFP/Source/R3

4

0x09A9

148

6.811.571.028

6.812.040.069

T->

GoodCRC

SOP

UFP/Sink/R1

4

0x0801

149

6.813.859.030

6.814.328.071

T->

Accept

SOP

UFP/Sink/R3

1

0x0283

150

6.814.380.011

6.814.877.051

<-D

GoodCRC

SOP

DFP/Source/R2

1

0x0361

151

6.816.259.068

6.816.259.068

<-D

Rp_Detected

Rp_4_7k_3A_Detected

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Detected

0x0000

155

7.584.863.063

7.585.333.004

T->

Get_SourceCap_Extended

SOP

DFP/Sink/R3

2

0x04B1

156

7.585.390.084

7.585.888.024

<-D

GoodCRC

SOP

UFP/Source/R2

2

0x0541

157

7.589.993.007

7.590.490.048

<-D

Not_Supported

SOP

UFP/Source/R3

5

0x0B90

158

7.590.534.008

7.591.003.048

T->

GoodCRC

SOP

DFP/Sink/R1

5

0x0A21

160

7.625.862.035

7.626.459.076

T->

Get_Battery_Cap

SOP

DFP/Sink/R3

3

Ext/Chk#0/Res/#1

0x96A3

0x01-0x80-0x08-0x00-

161

7.626.511.056

7.627.008.076

<-D

GoodCRC

SOP

UFP/Source/R2

3

0x0741

162

7.631.107.079

7.631.605.020

<-D

Not_Supported

SOP

UFP/Source/R3

6

0x0D90

163

7.631.651.084

7.632.123.080

T->

GoodCRC

SOP

DFP/Sink/R1

6

0x0C21

164

7.927.156.063

7.927.156.063

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SNK -> FSM_State_Disabled

0x0000

165

7.927.157.025

7.927.157.025

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

166

7.930.169.018

7.930.169.018

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

167

8.928.859.042

8.928.859.042

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

172

8.929.571.036

8.929.571.036

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SNK

0x0000

173

8.942.852.006

8.942.852.006

<-D

Attach

Rp_4_7k_3A_Detected

NONE

NONE/NONE/-

0

Rp_4_7k_3A_Detected

0x0000

174

8.947.652.013

8.947.652.013

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SNK -> FSM_State_AttachWait_SNK

0x0000

175

9.147.665.083

9.147.665.083

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SNK -> FSM_State_Unattached_SNK

0x0000

176

9.247.596.078

9.247.596.078

<-D

Attach

Rp_4_7k_3A_Detected

NONE

NONE/NONE/-

0

Rp_4_7k_3A_Detected

0x0000

177

9.252.396.088

9.252.396.088

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SNK -> FSM_State_AttachWait_SNK

0x0000

178

9.370.006.071

9.370.636.072

<-D

VendorDefined

SOP1

NONE/DFP_UFP/R3/VdmR2/

0

 Discover ID;Initiator;

0x108F

0x01-0xA0-0x00-0xFF-

179

9.370.685.032

9.371.154.072

C->

GoodCRC

SOP1

NONE/CablePlug/R1

0

0x0101

180

9.376.870.097

9.377.980.037

C->

VendorDefined

SOP1

NONE/CablePlug/R3/VdmR2/

0

 Discover ID;ACK;

0x518F

0x41-0xA8-0x00-0xFF-0x7F-0x22-0x00-0x1C-0x00-0x00-0x00-0x00-0x00-0x00-0x03-0x00-0x52-0x28-0x08-0x00-

181

9.378.032.016

9.378.529.038

<-D

GoodCRC

SOP1

NONE/DFP_UFP/R2

0

0x0041

182

9.382.622.081

9.383.650.062

<-D

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V 5A; FS: 9V 5A; FS: 15V 5A; FS: 20V 4.8A;

0x41A1

0xF4-0x91-0x01-0x2F-0xF4-0xD1-0x02-0x00-0xF4-0xB1-0x04-0x00-0xE0-0x41-0x06-0x00-

183

9.384.660.063

9.385.688.043

<-D

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V 5A; FS: 9V 5A; FS: 15V 5A; FS: 20V 4.8A;

0x41A1

0xF4-0x91-0x01-0x2F-0xF4-0xD1-0x02-0x00-0xF4-0xB1-0x04-0x00-0xE0-0x41-0x06-0x00-

184

9.386.691.024

9.387.719.005

<-D

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V 5A; FS: 9V 5A; FS: 15V 5A; FS: 20V 4.8A;

0x41A1

0xF4-0x91-0x01-0x2F-0xF4-0xD1-0x02-0x00-0xF4-0xB1-0x04-0x00-0xE0-0x41-0x06-0x00-

185

9.401.541.028

9.401.541.028

<-D

Rp_Detected

Rp_4_7k_3A_Detected

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Detected

0x0000

186

9.402.478.099

9.402.478.099

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SNK -> FSM_State_Attached_SNK

0x0000

187

9.564.626.061

9.565.654.022

<-D

SourceCap

SOP

DFP/Source/R3

1

 FS: 5V 5A; FS: 9V 5A; FS: 15V 5A; FS: 20V 4.8A;

0x43A1

0xF4-0x91-0x01-0x2F-0xF4-0xD1-0x02-0x00-0xF4-0xB1-0x04-0x00-0xE0-0x41-0x06-0x00-

188

9.565.701.022

9.566.170.062

T->

GoodCRC

SOP

UFP/Sink/R1

1

0x0201

189

9.567.867.063

9.568.465.004

T->

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0.1A; MaxCurrent = 0.1A

0x1082

0x0A-0x28-0x80-0x11-

190

9.568.520.004

9.569.017.024

<-D

GoodCRC

SOP

DFP/Source/R2

0

0x0161

191

9.573.108.091

9.573.606.008

<-D

Accept

SOP

DFP/Source/R3

2

0x05A3

192

9.573.650.008

9.574.119.048

T->

GoodCRC

SOP

UFP/Sink/R1

2

0x0401

193

9.610.246.036

9.610.743.056

<-D

PS_RDY

SOP

DFP/Source/R3

3

0x07A6

194

9.610.792.076

9.611.262.017

T->

GoodCRC

SOP

UFP/Sink/R1

3

0x0601

195

9.612.046.089

9.612.046.089

<-D

Rp_Detected

Rp_12k_1_5A_Detected

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Detected

0x0000

196

9.629.055.050

9.629.552.070

<-D

DR_Swap

SOP

DFP/Source/R3

4

0x09A9

197

9.629.602.050

9.630.071.091

T->

GoodCRC

SOP

UFP/Sink/R1

4

0x0801

198

9.631.868.012

9.632.337.053

T->

Accept

SOP

UFP/Sink/R3

1

0x0283

199

9.632.388.093

9.632.886.033

<-D

GoodCRC

SOP

DFP/Source/R2

1

0x0361

200

9.634.329.031

9.634.329.031

<-D

Rp_Detected

Rp_4_7k_3A_Detected

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Detected

0x0000

204

10.433.871.001

10.434.340.005

T->

Get_SourceCap_Extended

SOP

DFP/Sink/R3

2

0x04B1

205

10.434.398.004

10.434.895.007

<-D

GoodCRC

SOP

UFP/Source/R2

2

0x0541

206

10.438.997.003

10.439.494.005

<-D

Not_Supported

SOP

UFP/Source/R3

5

0x0B90

207

10.439.538.003

10.440.007.007

T->

GoodCRC

SOP

DFP/Sink/R1

5

0x0A21

209

10.474.869.008

10.475.435.002

T->

Get_Battery_Cap

SOP

DFP/Sink/R3

3

UnChunked

0x86A3

0x01-0x00-0x08-

210

10.475.487.000

10.475.984.002

<-D

GoodCRC

SOP

UFP/Source/R2

3

0x0741

211

10.480.076.006

10.480.574.000

<-D

Not_Supported

SOP

UFP/Source/R3

6

0x0D90

212

10.480.623.004

10.481.092.008

T->

GoodCRC

SOP

DFP/Sink/R1

6

0x0C21

213

10.776.162.005

10.776.162.005

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SNK -> FSM_State_Disabled

0x0000

214

10.776.163.001

10.776.163.001

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

215

10.779.167.007

10.779.167.007

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

AMS Summary

AMS Index

AMS Name

AMS Start

AMS Stop

AMS Status

Child AMS Count

0

Power_Negotiation

15

22

COMPLETE

0

1

Power_Role_Swap

25

28

COMPLETE

0

2

Getting_Sink_Extended_Capabilities

37

40

COMPLETE

0

3

Getting_Battery_Capabilities

48

51

COMPLETE

0

4

Power_Negotiation

72

79

COMPLETE

0

5

Power_Role_Swap

82

85

COMPLETE

0

6

Getting_Sink_Extended_Capabilities

94

97

COMPLETE

0

7

Getting_Battery_Capabilities

105

108

COMPLETE

0

8

Discover_Identity

129

132

COMPLETE

0

9

Power_Negotiation

133

145

COMPLETE

0

10

Data_Role_Swap

147

150

COMPLETE

0

11

Getting_Source_Extended_Capabilities

155

158

COMPLETE

0

12

Getting_Battery_Capabilities

160

163

COMPLETE

0

13

Discover_Identity

178

181

COMPLETE

0

14

Power_Negotiation

182

194

COMPLETE

0

15

Data_Role_Swap

196

199

COMPLETE

0

16

Getting_Source_Extended_Capabilities

204

207

COMPLETE

0

17

Getting_Battery_Capabilities

209

212

COMPLETE

0

DUT Information

Manufacturer

TI

Model Number

TPS659xx

Serial Number

1

Test Information

Test Lab

Test_Engineer

Test_Engineer

Remarks

Remarks

Date_and_Time

2023/11/23 16:33:08

Controller and Instrument Information

Parameter

Value

GRL_USB_PD_Controller_Serial_No

GRL-C2-EPR-2022098

GRL_USB_PD_Software_Version

1.6.19.0

GRL_USB_PD_Firmware_Version

1.1.72

GRL USB-PD Ethernet Buffer Size

62K

GRL USB-PD Eload Firmware Version

1.5 / 1.5

GRL USB-PD PPS Firmware Version

4.0 / 4.0

Board Calibration

Calibration Success

RX mask Power selection

Neutral Power

Device_Type

DRP

Cable Type

GRL_SPL_EPR_CABLE_1

Impedance (milli ohm)

12

PD_Merged CTS Version

v.Q4-2023

VIF_File_Name

TI__TPS659xx__1__0-1123-01.xml

Noise Pattern Generation:

Two-Tone Noise

Application mode

Informational

Disabled all Pop-up during test execution

False

Pop-up Timer

0

Execution Time(In Minutes)

4

Power Delivery 3.1 Tests Information

Parameter

Value

Connect EPR Test Fixture

False

FR_Swap AUTO Box Connected

False