Sl No |
Test ID |
Test Name |
Test Result |
---|---|---|---|
1 |
TEST.PD.USB4.DRST.2 |
TEST.PD.USB4.DRST.2 –Data_Reset command response of UFP UUT, Invalid Sequence |
FAIL |
Test Status |
Test Description |
---|---|
  |
  |
  |
 COMMON.PROC.BU.2: |
  |
 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk: |
  |
                    SourceCap Packet#15 |
  |
                          UUT should respond with request - - COMMON.PROC.BU.2#1: |
  |
                                   Request Packet#17 |
  |
 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk: |
  |
                    SourceCap Packet#71 |
  |
                          UUT should respond with request - - COMMON.PROC.BU.2#1: |
  |
                                   Request Packet#73 |
  |
 Rev3ChkdSnk: |
  |
                          Data_Reset command response check - TEST.PD.USB4.DRST.2#1: |
  |
                                   UUT respond Accept to Data_Reset command at protocol index 39 |
  |
                          Error recovery check - TEST.PD.USB4.DRST.2#3: |
  |
                                   UUT did error recovery at 11.6529 mS after recieving the Get_Sink_Cap |
  |
 Rev3ChkdSnk: |
  |
                          Data_Reset command response check - TEST.PD.USB4.DRST.2#2: |
  |
                                   UUT respond Accept to Data_Reset command at protocol index 95 |
  |
                          Error recovery check - TEST.PD.USB4.DRST.2#4: |
  |
                                   UUT failed to do error recovery |
Index |
   Start time(s.ms.μs.ns) |
   Stop time(s.ms.μs.ns) |
Message Origin |
 Message |
  |
 Secondary Message |
 SOP |
 Port Type |
 Msg ID |
 PDO |
 Header(MSB to LSB) |
 Payload(LSB to MSB) |
|||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST_PD_USB4_DRST_2_Data_Reset_command_response_of_UFP_UUT_Invalid_Sequence |
|||||||||||||||||||
Port A Packet Details |
|||||||||||||||||||
4 |
322.389040 mS |
322.389040 mS |
T-> |
Ra_Asserted |
NONE |
NONE/NONE/R- |
0 |
Ra_CC2 |
0x0000 |
||||||||||
9 |
323.097480 mS |
323.097480 mS |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Disabled -> FSM_State_Unattached_SRC |
0x0000 |
||||||||||
10 |
326.123560 mS |
326.123560 mS |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||||||||||
11 |
327.823250 mS |
327.823250 mS |
T-> |
Attach |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|||||||||
12 |
327.839910 mS |
327.839910 mS |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC |
0x0000 |
||||||||||
13 |
477.922020 mS |
477.922020 mS |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC |
0x0000 |
||||||||||
15 |
534.384430 mS |
534.981840 mS |
T-> |
SourceCap |
SOP |
DFP/Source/R3 |
0 |
 FS: 5V .1A; |
0x11A1 |
0x0A-0x90-0x01-0x08- |
|||||||||
16 |
535.033440 mS |
535.530640 mS |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
0 |
0x0041 |
|||||||||||
17 |
539.622870 mS |
540.252880 mS |
<-D |
Request |
SOP |
UFP/Sink/R3 |
0 |
PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A |
0x1082 |
0x00-0x00-0x80-0x13- |
|||||||||
18 |
540.298080 mS |
540.767480 mS |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
0 |
0x0121 |
|||||||||||
19 |
542.384490 mS |
542.853900 mS |
T-> |
Accept |
SOP |
DFP/Source/R3 |
1 |
0x03A3 |
|||||||||||
20 |
542.917500 mS |
543.414900 mS |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
1 |
0x0241 |
|||||||||||
21 |
864.390170 mS |
864.859580 mS |
T-> |
PS_RDY |
SOP |
DFP/Source/R3 |
2 |
0x05A6 |
|||||||||||
22 |
864.923180 mS |
865.420580 mS |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
2 |
0x0441 |
|||||||||||
24 |
865.458800 mS |
865.458800 mS |
T-> |
Rp_Asserted |
Rp_4_7k_3A_Asserted |
NONE |
NONE/NONE/R- |
0 |
Rp_4_7k_3A_Asserted |
0x0000 |
|||||||||
25 |
872.911040 mS |
873.408440 mS |
<-D |
PR_Swap |
SOP |
UFP/Sink/R3 |
1 |
0x028A |
|||||||||||
26 |
873.452640 mS |
873.922050 mS |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
1 |
0x0321 |
|||||||||||
27 |
875.385460 mS |
875.854860 mS |
T-> |
Reject |
SOP |
DFP/Source/R3 |
3 |
0x07A4 |
|||||||||||
28 |
875.909660 mS |
876.407070 mS |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
3 |
0x0641 |
|||||||||||
32 |
1.824.388.055 |
1.824.388.055 |
T-> |
Rp_Asserted |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/R- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|||||||||
33 |
1.824.943.039 |
1.824.943.039 |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||||||||||
37 |
1.846.388.011 |
1.846.857.052 |
T-> |
Data_Reset |
SOP |
DFP/Source/R3 |
4 |
0x09AE |
|||||||||||
38 |
1.846.908.092 |
1.847.406.032 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
4 |
0x0841 |
|||||||||||
39 |
1.851.498.075 |
1.851.995.096 |
<-D |
Accept |
SOP |
UFP/Sink/R3 |
2 |
0x0483 |
|||||||||||
40 |
1.852.042.056 |
1.852.511.096 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
2 |
0x0521 |
|||||||||||
41 |
2.054.386.051 |
2.054.855.086 |
T-> |
Get_Sink_Cap |
SOP |
DFP/Source/R3 |
5 |
0x0BA8 |
|||||||||||
42 |
2.054.907.034 |
2.055.404.072 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
5 |
0x0A41 |
|||||||||||
43 |
2.066.508.031 |
2.066.508.031 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Attached_SRC -> FSM_State_Unattached_SRC |
0x0000 |
||||||||||
44 |
2.066.508.080 |
2.066.508.080 |
T-> |
Detach |
NONE |
NONE/NONE/- |
0 |
NONE |
0x0000 |
||||||||||
45 |
2.068.683.068 |
2.068.683.068 |
<-D |
NONE |
LOAD_CURRENT |
NONE |
NONE/NONE/R- |
0 |
LOAD_CURRENT:0A |
0x0000 |
|||||||||
46 |
3.067.515.052 |
3.067.515.052 |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||||||||||
47 |
3.069.215.013 |
3.069.215.013 |
T-> |
Attach |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|||||||||
48 |
3.069.231.087 |
3.069.231.087 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC |
0x0000 |
||||||||||
49 |
3.219.313.099 |
3.219.313.099 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC |
0x0000 |
||||||||||
51 |
3.276.392.073 |
3.276.990.013 |
T-> |
SourceCap |
SOP |
DFP/Source/R3 |
0 |
 FS: 5V .1A; |
0x11A1 |
0x0A-0x90-0x01-0x08- |
|||||||||
52 |
3.277.041.053 |
3.277.538.094 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
0 |
0x0041 |
|||||||||||
53 |
3.281.631.037 |
3.282.261.037 |
<-D |
Request |
SOP |
UFP/Sink/R3 |
0 |
PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A |
0x1082 |
0x00-0x00-0x80-0x13- |
|||||||||
54 |
3.282.306.037 |
3.282.775.078 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
0 |
0x0121 |
|||||||||||
55 |
3.284.389.059 |
3.284.858.099 |
T-> |
Accept |
SOP |
DFP/Source/R3 |
1 |
0x03A3 |
|||||||||||
56 |
3.284.922.059 |
3.285.420.000 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
1 |
0x0241 |
|||||||||||
57 |
3.346.680.009 |
3.346.680.009 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Attached_SRC -> FSM_State_Disabled |
0x0000 |
||||||||||
58 |
3.346.680.067 |
3.346.680.067 |
T-> |
Detach |
NONE |
NONE/NONE/- |
0 |
NONE |
0x0000 |
||||||||||
59 |
3.348.699.036 |
3.348.699.036 |
<-D |
NONE |
LOAD_CURRENT |
NONE |
NONE/NONE/R- |
0 |
LOAD_CURRENT:0A |
0x0000 |
|||||||||
60 |
4.346.387.088 |
4.346.387.088 |
T-> |
Ra_Asserted |
NONE |
NONE/NONE/R- |
0 |
Ra_CC2 |
0x0000 |
||||||||||
65 |
4.347.099.096 |
4.347.099.096 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Disabled -> FSM_State_Unattached_SRC |
0x0000 |
||||||||||
66 |
4.370.381.023 |
4.370.381.023 |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||||||||||
67 |
4.372.080.096 |
4.372.080.096 |
T-> |
Attach |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|||||||||
68 |
4.372.097.058 |
4.372.097.058 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC |
0x0000 |
||||||||||
69 |
4.522.179.069 |
4.522.179.069 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC |
0x0000 |
||||||||||
71 |
4.579.394.075 |
4.579.992.016 |
T-> |
SourceCap |
SOP |
DFP/Source/R3 |
0 |
 FS: 5V .1A; |
0x11A1 |
0x0A-0x90-0x01-0x08- |
|||||||||
72 |
4.580.043.076 |
4.580.540.096 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
0 |
0x0041 |
|||||||||||
73 |
4.584.633.039 |
4.585.263.040 |
<-D |
Request |
SOP |
UFP/Sink/R3 |
0 |
PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A |
0x1082 |
0x00-0x00-0x80-0x13- |
|||||||||
74 |
4.585.308.040 |
4.585.777.080 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
0 |
0x0121 |
|||||||||||
75 |
4.587.391.061 |
4.587.861.002 |
T-> |
Accept |
SOP |
DFP/Source/R3 |
1 |
0x03A3 |
|||||||||||
76 |
4.587.924.082 |
4.588.422.002 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
1 |
0x0241 |
|||||||||||
77 |
4.909.394.009 |
4.909.863.049 |
T-> |
PS_RDY |
SOP |
DFP/Source/R3 |
2 |
0x05A6 |
|||||||||||
78 |
4.909.927.009 |
4.910.424.049 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
2 |
0x0441 |
|||||||||||
80 |
4.910.463.052 |
4.910.463.052 |
T-> |
Rp_Asserted |
Rp_4_7k_3A_Asserted |
NONE |
NONE/NONE/R- |
0 |
Rp_4_7k_3A_Asserted |
0x0000 |
|||||||||
81 |
4.918.167.095 |
4.918.665.036 |
<-D |
PR_Swap |
SOP |
UFP/Sink/R3 |
1 |
0x028A |
|||||||||||
82 |
4.918.709.036 |
4.919.178.076 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
1 |
0x0321 |
|||||||||||
83 |
4.920.392.057 |
4.920.861.097 |
T-> |
Reject |
SOP |
DFP/Source/R3 |
3 |
0x07A4 |
|||||||||||
84 |
4.920.916.077 |
4.921.414.018 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
3 |
0x0641 |
|||||||||||
88 |
5.848.396.065 |
5.848.396.065 |
T-> |
Rp_Asserted |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/R- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|||||||||
89 |
5.848.884.074 |
5.848.884.074 |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||||||||||
93 |
5.870.396.066 |
5.870.866.006 |
T-> |
Data_Reset |
SOP |
DFP/Source/R3 |
4 |
0x09AE |
|||||||||||
94 |
5.870.917.066 |
5.871.414.087 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
4 |
0x0841 |
|||||||||||
95 |
5.875.507.030 |
5.876.004.050 |
<-D |
Accept |
SOP |
UFP/Sink/R3 |
2 |
0x0483 |
|||||||||||
96 |
5.876.051.010 |
5.876.520.051 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
2 |
0x0521 |
|||||||||||
97 |
9.383.692.087 |
9.383.692.087 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Attached_SRC -> FSM_State_Disabled |
0x0000 |
||||||||||
98 |
9.383.693.044 |
9.383.693.044 |
T-> |
Detach |
NONE |
NONE/NONE/- |
0 |
NONE |
0x0000 |
||||||||||
99 |
9.386.696.066 |
9.386.696.066 |
<-D |
NONE |
LOAD_CURRENT |
NONE |
NONE/NONE/R- |
0 |
LOAD_CURRENT:0A |
0x0000 |
AMS Index |
AMS Name |
AMS Start |
AMS Stop |
AMS Status |
Child AMS Count |
---|---|---|---|---|---|
0 |
Power_Negotiation |
15 |
22 |
COMPLETE |
0 |
1 |
Power_Role_Swap |
25 |
28 |
COMPLETE |
0 |
2 |
Data_Reset |
37 |
40 |
PARTIAL_TESTER_PACKET_MISSING |
0 |
3 |
Get_Sink_Capabilities |
41 |
42 |
PARTIAL_DUT_PACKET_MISSING |
0 |
4 |
Power_Negotiation |
51 |
56 |
PARTIAL_TESTER_PACKET_MISSING |
0 |
5 |
Power_Negotiation |
71 |
78 |
COMPLETE |
0 |
6 |
Power_Role_Swap |
81 |
84 |
COMPLETE |
0 |
7 |
Data_Reset |
93 |
96 |
PARTIAL_TESTER_PACKET_MISSING |
0 |
Manufacturer |
TI |
Model Number |
TPS659xx |
Serial Number |
1 |
Test Lab |
|
Test_Engineer |
Test_Engineer |
Remarks |
Remarks |
Date_and_Time |
2023/11/23 16:34:31 |
Parameter |
Value |
---|---|
GRL_USB_PD_Controller_Serial_No |
GRL-C2-EPR-2022098 |
GRL_USB_PD_Software_Version |
1.6.19.0 |
GRL_USB_PD_Firmware_Version |
1.1.72 |
GRL USB-PD Ethernet Buffer Size |
62K |
GRL USB-PD Eload Firmware Version |
1.5 / 1.5 |
GRL USB-PD PPS Firmware Version |
4.0 / 4.0 |
Board Calibration |
Calibration Success |
RX mask Power selection |
Neutral Power |
Device_Type |
DRP |
Cable Type |
GRL_SPL_EPR_CABLE_1 |
Impedance (milli ohm) |
12 |
PD_Merged CTS Version |
v.Q4-2023 |
VIF_File_Name |
TI__TPS659xx__1__0-1123-01.xml |
Noise Pattern Generation: |
Two-Tone Noise |
Application mode |
Informational |
Disabled all Pop-up during test execution |
False |
Pop-up Timer |
0 |
Execution Time(In Minutes) |
5 |
Parameter |
Value |
---|---|
Connect EPR Test Fixture |
False |
FR_Swap AUTO Box Connected |
False |