C2-EPR Compliance Test Report



Power Delivery 3.1 Tests- Result Summary

Sl No

Test ID

Test Name

Test Result

1

TEST.PD.PHY.ALL.1

TEST.PD.PHY.ALL.1 Transmit Bit Rate and the Drift

PASS

Power Delivery 3.1 Tests - Detailed Test Result

Test Status

Test Description

  PASS

  1. TEST.PD.PHY.ALL.1 Transmit Bit Rate and the Drift

 

                    1/1 captures completed

  PASS

 COMMON.PROC.BU.2:

  PASS

 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk:

 

                    SourceCap Packet#15

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet#17

  PASS

 Rev3ChkdSnk:

  PASS

                          fBitRateMeas - TEST.PD.PHY.ALL.1#1:

  PASS

 Bit Rate-1:

 

                    Valid Protocol response for BIST Request

  PASS

 Bit Rate-2:

 

                    Valid BIST response pattern

  PASS

 Bit Rate-3:

 

                    Bit Rate is 301.641 Kbps. Test limit (270 ~ 330) Kbps
                    

  PASS

                          pBitRateMeas - TEST.PD.PHY.ALL.1#2:

  PASS

 Bit Rate-4:

 

                    Bit Rate is 0.003 %. Test limit: X < 0.25%
                    

  PASS

                          tBISTContMode Limits validation - TEST.PD.PHY.ALL.1#3:

  PASS

 Bit Rate-5:

 

                    BIST pattern duration 45.0501400 mS (Limit <= 60ms)

Packet List (Click to View AMS Summary)

Index

   Start time(s.ms.μs.ns)

   Stop time(s.ms.μs.ns)

Message Origin

 Message

 

 Secondary Message

 SOP

 Port Type

 Msg ID

 PDO

 Header(MSB to LSB)

 Payload(LSB to MSB)

TEST_PD_PHY_ALL_1_Transmit_Bit_Rate_and_the_Drift

Port A Packet Details

4

325.361180 mS

325.361180 mS

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

9

326.070980 mS

326.070980 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

10

326.298970 mS

326.298970 mS

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

11

327.998570 mS

327.998570 mS

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

12

328.015320 mS

328.015320 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

13

478.097420 mS

478.097420 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

15

535.358360 mS

535.955760 mS

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V .1A;

0x11A1

0x0A-0x90-0x01-0x08-

16

536.007160 mS

536.504570 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

17

540.596000 mS

541.226000 mS

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A

0x1082

0x00-0x00-0x80-0x13-

18

541.272000 mS

541.741410 mS

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

19

543.355220 mS

543.824620 mS

T->

Accept

SOP

DFP/Source/R3

1

0x03A3

20

543.888220 mS

544.385630 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

21

866.356100 mS

866.825500 mS

T->

PS_RDY

SOP

DFP/Source/R3

2

0x05A6

22

866.889100 mS

867.386510 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

24

867.427070 mS

867.427070 mS

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

25

875.393170 mS

875.890570 mS

<-D

PR_Swap

SOP

UFP/Sink/R3

1

0x028A

26

875.936970 mS

876.406380 mS

T->

GoodCRC

SOP

DFP/Source/R1

1

0x0321

27

878.356190 mS

878.825590 mS

T->

Reject

SOP

DFP/Source/R3

3

0x07A4

28

878.880390 mS

879.377800 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

3

0x0641

31

1.827.084.087

1.827.084.087

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

33

1.827.360.016

1.827.360.016

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

39

1.849.374.086

1.849.972.024

T->

BIST

SOP

DFP/Source/R3

4

BIST_Carrier_Mode0

0x19A3

0x00-0x00-0x00-0x50-

40

1.850.030.024

1.850.527.044

<-D

GoodCRC

SOP

UFP/Sink/R2

4

0x0841

42

1.850.913.045

1.895.963.059

<-D

BIST

BIST_CM2_Response

NONE

NONE/NONE/R-

0

0x0000

45

6.869.659.011

6.869.659.011

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

46

6.869.659.056

6.869.659.056

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

47

6.872.665.035

6.872.665.035

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

AMS Summary

AMS Index

AMS Name

AMS Start

AMS Stop

AMS Status

Child AMS Count

0

Power_Negotiation

15

22

COMPLETE

0

1

Power_Role_Swap

25

28

COMPLETE

0

2

Built_in_Self_Test_BIST

39

42

PARTIAL_TESTER_GOODCRC_MISSING

0

DUT Information

Manufacturer

TI

Model Number

TPS659xx

Serial Number

1

Test Information

Test Lab

Test_Engineer

Test_Engineer

Remarks

Remarks

Date_and_Time

2023/11/23 16:30:32

Controller and Instrument Information

Parameter

Value

GRL_USB_PD_Controller_Serial_No

GRL-C2-EPR-2022098

GRL_USB_PD_Software_Version

1.6.19.0

GRL_USB_PD_Firmware_Version

1.1.72

GRL USB-PD Ethernet Buffer Size

62K

GRL USB-PD Eload Firmware Version

1.5 / 1.5

GRL USB-PD PPS Firmware Version

4.0 / 4.0

Board Calibration

Calibration Success

RX mask Power selection

Neutral Power

Device_Type

DRP

Cable Type

GRL_SPL_EPR_CABLE_1

Impedance (milli ohm)

12

PD_Merged CTS Version

v.Q4-2023

VIF_File_Name

TI__TPS659xx__1__0-1123-01.xml

Noise Pattern Generation:

Two-Tone Noise

Application mode

Informational

Disabled all Pop-up during test execution

False

Pop-up Timer

0

Execution Time(In Minutes)

1

Power Delivery 3.1 Tests Information

Parameter

Value

Connect EPR Test Fixture

False

FR_Swap AUTO Box Connected

False