{"text_format":"1","workbook":"xlsx","n_sheets":12,"sheets":["InputSheet","DeviceCalculator","Sheet1","6A_SchematicChecklist","6A_LayoutChecklist","12Ato20A_SchematicChecklist","12Ato20A_LayoutChecklist","Std. R and C Values","partData","Extra","revisionNotes","Disclaimer"],"not_rendered":{"charts":4,"images":13,"macros":1,"external_links":3,"defined_names":241,"comments":1,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900"}

{"sheet":"InputSheet","index":0,"n_rows":56,"n_cols":8,"rows_kept":56,"cut":false,"hidden":false,"merged":[]}
["Parameter","Units","Type","Default","*selected*",null,"end"]
["Rail Name",null,"Req",null,"EVM Example","charger"]
["Part Number",null,"Req",null,"TPS54J061","TPS54J061"]
["Vin_min","V","Opt","Vin_nom*0.8",9.6,9]
["Vin_nom","V","Req",null,12,12,null,"Sheet Descriptions:"]
["Vin_max","V","Opt","Vin_nom*1.1",13.2,15,null,"InputSheet = sheet with simplified input for checking component values with the macros described below"]
["Vout","V","Req",null,1.8,3.63,null,"DeviceCalculator = sheet where all calculations are done. This sheet can be used by itself to select or check component values."]
["Iout","A","Opt","Io_max_IC",6,1]
["dVo_ripple_perc",null,"Opt",0.01,0.01,0.01,null,"Macro Directions:"]
["dVo_trans_perc",null,"Opt",0.04,2.5000000000000001E-2,0.03,null,"Check/Calculate Selected Column"]
["Io_step","A","Opt","Iout*0.5",3,0.5,null,"Select any cell in the column of the design you would like to check."]
["R_mode",null,"Req","R_mode_rec","Connect to AGND","Connect to VCC",null,"Click on the Check/Calculate to send the input values to the DeviceCalculator worksheet."]
["fsw_select","kHz","Calc",null,1100,1100,null,"The calculated results on the DeviceCalculator worksheet are then pulled back to this sheet to check the component values used."]
["LL_mode_select",null,"Calc",null,"FCCM","DCM"]
["Lout","µH","Opt","L_rec",1,3.3,null,"Insert New Design"]
["DCR","mΩ","Opt","Rdson_LS",9.1999999999999993,25.9,null,"Click on Insert New Design to add another column to check another design."]
["Tol_L",null,"Opt",0.2,0.2,0.2,null,"To delete a design that is no longer needed, right click on the column letter then select delete."]
["Rtrip","kΩ","Opt","Rtrip_NSV",4.99,44.2]
["Io_max_min","A","Calc",null,5.6159499281892806,0.57699236227915407,null,"Pull Values from DeviceCalculator Sheet"]
["N_cer",null,"Opt",1,6,2,null,"The DeviceCalculator worksheet has more details to aid in the design."]
["Cout_single_cer","µF","Opt","Cout_min",47,10,null,"Updates to the design can be mode in the DeviceCalculator sheet."]
["ESR_single_cer","mΩ","Opt",1,5,1,null,"After making updates, click on Pull Values to use the values on the DeviceCalculator sheet and check them."]
["Cer_derating",null,"Opt",0.8,0.6,0.8]
["N_bulk",null,"Opt",0,0,0,null,"Check/Calculate All Columns"]
["Cout_single_bulk","µF","Opt",0.1,0.1,0.1,null,"This will run Check/Calculate Selected Column on all designs"]
["ESR_single_bulk","mΩ","Opt",1,1,1]
["Vo_undershoot","mV","Calc",null,11.12358051393387,12.922124698033441]
["Vo_overshoot","mV","Calc",null,14.77532638695989,7.1018288629687909]
["Vo_ripple","mV","Calc",null,2.1092641915363495,8.58122975996333]
["Vi_ripple_percent",null,"Opt",0.04,0.04,0.04]
["Cin_cer","µF","Opt","Cin_min",20,10]
["Cin_derating",null,"Opt",0.5,0.5,0.5]
["Vi_ripple","mV","Calc",null,41.548295454545453,21.87777777777778]
["Rfb_b","kΩ","Opt","Rfb_b_rec",0.499,1]
["Rfb_t","kΩ","Opt","Rfb_t_NSV",1,5.0999999999999996]
["Vout_calc","V","Calc",null,1.8024048096192382,3.6599999999999997]
["Cff","pF","Opt","Cff_NSV",4700,680]
["Rff","kΩ","Opt","Rff_NSV",0,0.26]
["Css","nF","Opt",22,22,22]
["Tss","ms","Calc",null,1.5,1.5]
["Ren_b","kΩ","Opt",0,100,10]
["Ren_t","kΩ","Opt",0,470,16.899999999999999]
["Vstart_typ","kΩ","Calc",null,7.0495666666666681,3.2852363333333332]
["Vstop_typ","kΩ","Calc",null,5.8939000000000012,2.7466729999999999]
["Cvcc","µF","Opt","Cvcc_rec",4.7,2.2000000000000002]
["Cboot","µF","Opt","Cboot_rec",0.22,0.1]
["Rboot","Ω","Opt","Rboot_rec",0,0]
["Rpg","kΩ","Opt","Rpg_rec",3.3,10]
["R_mode_check",null,"Check",null,"Pass","Pass"]
["Lout_check",null,"Check",null,"Pass","Pass"]
["Rtrip_check",null,"Check",null,"Caution: Decrease Rtrip for higher current limit. Current limit may be hit when accounting for inductance and current limit tolerance. Recommended value is 4.64 kOhm.","Caution: Decrease Rtrip for higher current limit. Current limit may be hit when accounting for inductance and current limit tolerance. Recommended value is 22.1 kOhm."]
["Cout_check",null,"Check",null,"Pass","Pass"]
["Cin_check",null,"Check",null,"Pass","Pass"]
["FB_network_check",null,"Check",null,"Pass","Pass"]
["EN_divider_check",null,"Check",null,"Pass","Pass"]
["Cvcc_Cboot_Rpg_check",null,"Check",null,"Pass","Pass"]

{"sheet":"DeviceCalculator","index":1,"n_rows":163,"n_cols":20,"rows_kept":163,"cut":false,"hidden":false,"merged":[[139,1,139,7],[154,1,154,7],[19,17,19,19],[118,1,118,7],[134,1,134,7],[45,1,45,7],[71,1,71,7],[70,1,70,7],[59,1,59,7],[107,1,107,7],[108,1,108,7],[45,9,46,14],[150,1,150,7],[0,1,0,7],[35,1,35,7],[29,1,29,7],[7,1,7,7],[44,1,44,7],[1,1,6,1],[1,2,6,2],[1,3,6,3],[1,4,6,4],[1,5,6,5],[1,6,6,6],[1,7,6,7]]}
[null,"Design Calculations",null,null,null,null,null,null,null,"Key"]
[null,"Parameter","Input","Recommended","Selected Value","Calculated with Selected Value","Units","Description",null,"User Entered Value"]
[null,null,null,null,null,null,null,null,null,"Fixed IC Parameter"]
[null,null,null,null,null,null,null,null,null,"Calculated Parameter"]
[null,null,null,null,null,null,null,null,null,"Recommended Component Value"]
[null,null,null,null,null,null,null,null,null,"Design Caution"]
[null,null,null,null,null,null,null,null,null,"Design Warning"]
[null,"Choose Device"]
[null,"Part Number","TPS54J061",null,null,null,null,"Select IC part number"]
[null,"Vin_min_bias",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,14,FALSE)","v":2.7},null,null,null,"V","IC rated minimum input voltage with external bias"]
[null,"Vin_min_IC",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,2,FALSE)","v":4},null,null,null,"V","IC rated minimum input voltage with internal bias"]
[null,"Vin_max_IC",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,3,FALSE)","v":16},null,null,null,"V","IC rated maximum input voltage"]
[null,"Vref",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,10,FALSE)","v":0.6},null,null,null,"V","Internal voltage reference"]
[null,"Io_max_IC",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,4,FALSE)","v":6},null,null,null,"A","IC rated maximum output current"]
[null,"Vcc",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,13,FALSE)","v":3},null,null,null,"V","Internal VCC regulator output voltage"]
[null,"Iss",{"$f":"VLOOKUP($C$9,partData!$A$3:$S$10,19,FALSE)","v":9},null,null,null,"µA","SS/REFIN sourcing current"]
[null,"EN_rise",{"$f":"VLOOKUP($C$9,partData!$A$3:$U$10,20,FALSE)","v":1.22},null,null,null,"V","EN rising voltage threshold"]
[null,"EN_fall",{"$f":"VLOOKUP($C$9,partData!$A$3:$U$10,21,FALSE)","v":1.02},null,null,null,"V","EN falling voltage threshold"]
[null,"OCF_response",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,11,FALSE)","v":"Hiccup"},null,null,null,null,"Over current fault response"]
[null,"OVF_response",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,12,FALSE)","v":"Latch Off"},null,null,null,null,"Over voltage fault response",null,null,null,null,null,null,null,null,null,"Calculated component values summary"]
[null,"OC_clamp",{"$f":"VLOOKUP($C$9,partData!$A$3:$N$10,8,FALSE)","v":9.5},null,null,null,"A","Valley current limit maximum clamp",null,null,null,null,null,null,null,null,null,"MODE",{"$f":"D41","v":"Connect to VCC"},"kΩ"]
[null,"Rtrip_gain",{"$f":"VLOOKUP($C$9,partData!$A$3:$R$10,18,FALSE)","v":30000},null,null,null,null,"Gain for Rtrip calculation",null,null,null,null,null,null,null,null,null,"Lout",{"$f":"Lout","v":3.3},"µH"]
[null,"Rtrip_min",{"$f":"VLOOKUP($C$9,partData!$A$3:$Y$10,23,FALSE)","v":3.74},null,null,null,"kΩ",null,null,null,null,null,null,null,null,null,null,"Cout",{"$f":"Cout","v":2.4010000000000002},"µF"]
[null,"Rtrip_max",{"$f":"VLOOKUP($C$9,partData!$A$3:$Y$10,24,FALSE)","v":30.1},null,null,null,"kΩ",null,null,null,null,null,null,null,null,null,null,"Rtrip",{"$f":"Rtrip","v":22},"kΩ"]
[null,"Ioc_neg_max",{"$f":"VLOOKUP($C$9,[2]partData!$A$3:$V$10,22,FALSE)","v":-2.8},null,null,null,"A","Worst case negative current limit threshold",null,null,null,null,null,null,null,null,null,"Cin",{"$f":"Cin_cer","v":10},"µF"]
[null,"ton_min",{"$f":"VLOOKUP($C$9,partData!$A$3:$P$10,9,FALSE)","v":70},null,null,null,"ns","Typical minimum on-time",null,null,null,null,null,null,null,null,null,"Rfb_b",{"$f":"Rfb_b","v":1},"kΩ"]
[null,"toff_min_max",{"$f":"VLOOKUP($C$9,partData!$A$3:$P$10,15,FALSE)","v":220},null,null,null,"ns","Worst case minimum off-time",null,null,null,null,null,null,null,null,null,"Rfb_b",{"$f":"Rfb_b","v":1},"kΩ"]
[null,"Rdson_HS",{"$f":"VLOOKUP($C$9,partData!$A$3:$Q$10,16,FALSE)","v":25},null,null,null,"mΩ","High-side FET Rdson",null,null,null,null,null,null,null,null,null,"Rfb_t",{"$f":"Rfb_t","v":5.05},"kΩ"]
[null,"Rdson_LS",{"$f":"VLOOKUP($C$9,partData!$A$3:$Q$10,17,FALSE)","v":9.1999999999999993},null,null,null,"mΩ","Low-side FET Rdson",null,null,null,null,null,null,null,null,null,"Cff",{"$f":"Cff","v":680},"pF"]
[null,"Input System Parameters",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Css",{"$f":"Css","v":22},"nF"]
[null,"Vin_min",9,null,null,null,"V","Minimum input voltage",null,null,null,null,null,null,null,null,null,"Ren_t",{"$f":"Ren_t","v":16.899999999999999},"kΩ"]
[null,"Vin_nom",12,null,null,null,"V","Nominal input voltage",null,null,null,null,null,null,null,null,null,"Ren_b",{"$f":"Ren_b","v":10},"kΩ"]
[null,"Vin_max",15,null,null,null,"V","Maximum input voltage",null,null,null,null,null,null,null,null,null,"Cvcc",{"$f":"MAX(1,Cvcc)","v":2.2000000000000002},"µF"]
[null,"Vout",3.63,null,null,null,"V","Output voltage",null,null,null,null,null,null,null,null,null,"Cboot",{"$f":"MAX(0.1,Cboot)","v":0.1},"µF"]
[null,"Iout",1,null,null,null,"A","Maximum output current",null,null,null,null,null,null,null,null,null,"Rpg",{"$f":"Rpg","v":10},"kΩ"]
[null,"Select the Switching Frequency and Light Load operation mode (MODE pin)"]
[null,"fsw_input",1100,null,null,null,"kHz","Input desired fsw option"]
[null,"LL_mode_input","DCM",null,null,null,null,"Input desired light load operation mode"]
[null,"fsw_max_ton",null,{"$f":"Vout/Vin_max*1/(ton_min_sec)*0.001","v":3457.1428571428569},null,null,"kHz","Maximum fsw limited by Vin_max and minimum on-time"]
[null,"fsw_max_toff",null,{"$f":"(Vin_min-Vout-Iout*2*(DCR_Ohm+Rdson_HS_Ohm))/(toff_min_max_sec*(Vin_min-Iout*2*(Rdson_HS_Ohm-Rdson_LS_Ohm)))*10^-3","v":2670.0820253739384},null,null,"kHz","Maximum fsw allowed limited by Vin_min and minimum off-time (Depends on inductor DCR and includes 2x multiplier on resistance for margin)"]
[null,"R_mode_rec",null,{"$f":"VLOOKUP(CONCATENATE(C37,C38),partData!E15:H20,4,0)","v":"Connect to VCC"},null,null,"kΩ","MODE pin connection or resistor to AGND with input values"]
[null,"R_mode",null,null,"Connect to VCC",null,"kΩ","Selected MODE pin connection or resistor to AGND"]
[null,"fsw_select",null,null,null,{"$f":"VLOOKUP(R_mode,partData!H15:J20,2,0)","v":1100},"kHz","fsw with selected MODE configuration"]
[null,"LL_mode_select",null,null,null,{"$f":"VLOOKUP(R_mode,partData!H15:J20,3,0)","v":"DCM"},null,"Light load operation mode with selected MODE configuration"]
[null,"Choose the Output Inductor (Lout)"]
[null,"The inductance is selected based on a p-p ripple current target. Smaller L reduces solution size while larger L reduces AC loss.",null,null,null,null,null,null,null,"NOTE: The TPS54J060 and TPS54J061 do not have a VSNS- pin. For these IC's, the the FB divider and SS capacitor must be returned to the AGND pin."]
[null,"Kind",0.2,null,null,null,null,"Target ripple/Iout ratio (typically between 0.2 to 0.4)"]
[null,"L_target",null,{"$f":"((Vin_max-Vout)*Vout)/(Iout*Kind*Vin_max*fsw_select)*1000","v":12.507},null,null,"µH","Target inductor value"]
[null,"L_min",null,{"$f":"((Vin_max-Vout)*Vout)/(Io_max_IC*0.5*Vin_max*fsw_select)*1000","v":0.83379999999999999},null,null,"µH","Minimum recommended inductance (ripple = 50% Iout_max_IC)"]
[null,"L_max",null,{"$f":"((Vin_max-Vout)*Vout)/(Io_max_IC*0.1*Vin_max*fsw_select)*1000","v":4.1689999999999987},null,null,"µH","Maximum recommended inductance (ripple = 10% Iout_max_IC)"]
[null,"L_rec",null,{"$f":"MIN(MAX(D49,D48),D50)","v":4.1689999999999987},null,null,"µH","Recommended inductance value"]
[null,"Lout",null,null,3.3,null,"µH","Selected inductance"]
[null,"DCR",null,null,25.9,null,"mΩ","DC resistance of selected inductor"]
[null,"Tol_L",null,null,0.2,null,null,"Tolerance of inductance for selected inductor"]
[null,"Iripple_max",null,null,null,{"$f":"1000*((Vin_max-Vout)*Vout)/(Lout*(1-Tol_L)*Vin_max*fsw_select)","v":0.94750000000000001},"A","Inductor ripple current at Vin_max (Includes Tol_L. Used for DC ripple calculations. If red, risk of hitting negative OC)"]
[null,"Ipeak",null,null,null,{"$f":"Iout+(Iripple_max/2)","v":1.4737499999999999},"A","Full load peak current at Vin_max"]
[null,"Irms",null,null,null,{"$f":"SQRT(Iout^2+(Iripple_max^2)/12)","v":1.0367318943841428},"A","Inductor rms current at Vin_max"]
[null,"Iripple_min",null,null,null,{"$f":"1000*((Vin_min-Vout)*Vout)/(Lout*(1+Tol_L)*Vin_min*fsw_select)","v":0.49722222222222229},null,"Inductor ripple current at Vin_min (includes Tol_L)"]
[null,"Ivalley",null,null,null,{"$f":"Iout-(Iripple_min/2)","v":0.75138888888888888},"A","Full load valley current at Vin_min (used for I_lim calculations)"]
[null,"Set current limit (Rtrip)"]
[null,"Tol_Ilim",0.15,null,null,null,null,"Ilim tolerance"]
[null,"I_limval_rec",null,{"$f":"MIN(Ivalley*1/(1-Tol_Ilim),OC_clamp)","v":0.88398692810457513},null,null,"A","Recommended valley current limit setting\n(Includes margin  for Tol_L and Ilim tolerance)"]
[null,"I_lim_target",{"$f":"Ivalley","v":0.75138888888888888},null,null,null,"A","Input target valley current limit setting "]
[null,"Rtrip_calc",null,{"$f":"VLOOKUP($C$9,partData!$A$3:$AAB$10,25,FALSE)","v":22.524396397805798},null,null,"kΩ","Calculated Rtrip. This calculation includes the tolerance of the current limit."]
[null,"Rtrip_NSV",null,{"$f":"partData!W18","v":22.1},null,null,"kΩ","Round down to nearest E96 standard value"]
[null,"Rtrip",null,null,22,null,"kΩ","Selected Rtrip"]
[null,"I_lim_typ",null,null,null,{"$f":"MIN(Rtrip_gain/(Rtrip*1000),OC_clamp)","v":1.3636363636363635},"A","Estimated typical valley current limit with selected Rtrip"]
[null,"Io_max_min",null,null,null,{"$f":"VLOOKUP($C$9,partData!$A$3:$AAB$10,26,FALSE)+Iripple_min/2","v":1.0362730084547549},"A","Estimated minimum Iout at current limit"]
[null,"Io_max_typ",null,null,null,{"$f":"I_lim_typ+1/2*(Vin_nom-Vout)*Vout/(Lout_H*Vin_nom*fsw_Hz)","v":1.7123863636363637},"A","Estimated typical Iout at current limit"]
[null,"Io_max_max",null,null,null,{"$f":"I_lim_typ*(1+Tol_Ilim)+Iripple_max/2","v":2.0419318181818178},"A","Estimated maximum Iout at current limit"]
[null,"Choose the Output Capacitor (Cout)"]
[null,"The output capacitance is deteremind based on the output ripple, transient and stability requirements."]
[null,"Io_step",0.5,null,null,null,"A","Iout load transient step"]
[null,"dVo_trans_perc",0.03,null,null,null,null,"Target Vout overshoot/undershoot after load step as a percentage of Vout"]
[null,"dVo_ripple_perc",0.01,null,null,null,null,"Target steady state Vout voltage ripple as a percentage of Vout"]
[null,"dVo_trans",null,{"$f":"dVo_trans_perc*Vout","v":0.1089},null,null,"V","Target Vout overshoot/undershoot after load step"]
[null,"dVo_ripple",null,{"$f":"dVo_ripple_perc*Vout","v":3.6299999999999999E-2},null,null,"V","Target steady state Vout voltage ripple"]
[null,"Cout_ripple",null,{"$f":"Iripple_max/(8*dVo_ripple*fsw_Hz)*10^6","v":2.966128224392687},null,null,"µF","Min Cout for DC ripple requirement (ignores ESR)"]
[null,"Cout_undershoot",null,{"$f":"((Lout*Io_step^2)*(Vout/(Vin_min*fsw_Hz)+toff_min_max_sec))/(2*dVo_trans*Vout*((Vin_min-Vout)/(Vin_min*fsw_Hz)-toff_min_max_sec))","v":1.898686109212425},null,null,"µF","Min Cout for undershoot requirement"]
[null,"Cout_overshoot",null,{"$f":"Lout*Io_step^2/(2*Vout*dVo_trans)","v":1.0434927790299691},null,null,"µF","Min Cout for overshoot requirement"]
[null,"Cout_stability",null,{"$f":"(15/(PI()*fsw_Hz))^2*1/Lout_H*1000000","v":5.7093078686516403},null,null,"µF","Min Cout for stability (f_LC < fsw/30)"]
[null,"Cout_min",null,{"$f":"(MAX(D78:D81))","v":5.7093078686516403},null,null,"µF","Recommended min Cout (must include any derating due to DC/AC bias, temp and/or tolerance)"]
[null,"Cout_max",null,{"$f":"2500/(PI()^2*fsw_Hz^2*Lout_H)*1000000","v":63.436754096129341},null,null,"µF","Max Cout for stability (f_LC > fsw/100) (Exceeding this may be ok but further validation is required)"]
[null,"ESR_trans",null,{"$f":"dVo_trans/Io_step*1000","v":217.79999999999998},null,null,"mΩ","Max effective ESR to meet load step transient requirement"]
[null,"ESR_ripple",null,{"$f":"dVo_ripple/Iripple_max*1000","v":38.311345646437992},null,null,"mΩ","Max effective ESR to meet ripple requirement"]
[null,"ESR_max",null,{"$f":"MIN(D84:D85)","v":38.311345646437992},null,null,"mΩ","Recommanded max effective ESR \n(when using mixed type output capacitors, it may be possible for bulk capacitance to have higher ESR)"]
[null,"Cout_single_cer",null,null,3,null,"µF","Nominal value of a Single Ceramic Output Capacitor"]
[null,"Cer_derating",null,null,0.8,null,null,"Percentage of Nominal Ceramic Capacitance remaining after Tolerance, Thermal, and DC Bias derating"]
[null,"ESR_single_cer",null,null,1,null,"mΩ","Single Ceramic Capacitor ESR"]
[null,"N_cer",null,null,1,null,null,"Number of Ceramic Capacitors"]
[null,"Cout_cer",null,null,null,{"$f":"IF(N_cer=0,0.001,N_cer*E87*Cer_derating)","v":2.4000000000000004},"uF","Total Ceramic Output Capacitance"]
[null,"ESR_cer",null,null,null,{"$f":"IF(N_cer=0,0,E89/N_cer)","v":1},"mΩ","Effective Ceramic Capacitance ESR"]
[null,"Cout_single_bulk",null,null,0.1,null,"uF","Nominal value of a Single Bulk/Polymer/Electrolytic Output Capacitor"]
[null,"Bulk_derating",null,null,1,null,null,"Percentage of Nominal Bulk Capacitance remaining after Tolerance, Thermal, and DC Bias derating"]
[null,"ESR_single_bulk",null,null,1,null,"mΩ","Single Bulk Capacitor ESR"]
[null,"N_bulk",null,null,0,null,null,"Number of Bulk Capacitors"]
[null,"Cout_bulk",null,null,null,{"$f":"IF(N_bulk=0,0.001,N_bulk*E93*Bulk_derating)","v":1E-3},"µF","Total Bulk Output Capacitance"]
[null,"ESR_bulk",null,null,null,{"$f":"IF(N_bulk=0,10^9,E95/N_bulk)","v":1000000000},"mΩ","Effective Bulk Capacitance ESR"]
[null,"Cout",null,null,null,{"$f":"Cout_bulk+Cout_cer","v":2.4010000000000002},"uF","Total Bulk + Ceramic Output Capacitance "]
[null,"Vo_undershoot",null,null,null,{"$f":"(Lout_H*Io_step^2)*(Vout/(Vin_min*fsw_Hz)+toff_min_max_sec)/(2*Cout_F*Vout*((Vin_min-Vout)/(Vin_min*fsw_Hz)-toff_min_max_sec))*10^3","v":86.117000122129554},"mV","Estimated undershoot (ignores ESR and ESL)"]
[null,"Vo_overshoot",null,null,null,{"$f":"(Lout_H*Io_step^2/(2*Vout*Cout_F))*10^3","v":47.328764529930709},"mV","Estimated overshoot (ignores ESR and ESL)"]
[null,"Zout_fsw",null,null,null,{"$f":"1/(1/(SQRT((ESR_bulk*10^-3)^2+1/(2*PI()*fsw_select*10^3*Cout_bulk*10^-6)^2))+1/(SQRT((ESR_cer*10^-3)^2+1/(2*PI()*fsw_select*10^3*Cout_cer*10^-6)^2)))*1000","v":60.294252891163879},"mΩ","Output Impedance at Swiching Frequency"]
[null,"Vo_ripple",null,null,null,{"$f":"Iripple_max*Zout_fsw","v":57.128804614377778},"mV","Estimated capacitive + resistive DC ripple (ignores ESL)"]
[null,"Stability",null,null,null,{"$f":"IF(Stability>2,\"GOOD\",\"BAD\")","v":"GOOD"},null,"If BAD, increase Cout, increase L and/or use lower ESR capacitors"]
[null,"f_LC",null,null,null,{"$f":"1/(2*PI()*SQRT(Lout_H*Cout_F))*0.001","v":56.541468218774746},"kHz","LC resonant frequency \n(if yellow, feedforward cap recommended)"]
[null,"f_ESR_cer",null,null,null,{"$f":"1/(2*PI()*Cout_cer*10^-6*ESR_cer*10^-3)*10^-3","v":66314.559621623048},"kHz","Ceramic capacitor ESR zero frequency \n(if yellow, ESR zero may affect loop stability)"]
[null,"f_ESR_bulk",null,null,null,{"$f":"IF(N_bulk=0,\"N/A\",1/(2*PI()*Cout_bulk*10^-6*ESR_bulk*10^-3)*10^-3)","v":"N/A"},"kHz","Bulk capacitor ESR zero frequency \n(if yellow, ESR zero may affect loop stability)"]
[null,"Choose the Input Capacitor (Cin)"]
[null,"The input capacitance is deteremind based on the input ripple requirements. Additional bulk input capacitance may be needed for transients. 0.1µF high frequency bypass capacitors are also required."]
[null,"Vi_ripple_percent",0.04,null,null,null,null,"Target DC input ripple voltage percentage"]
[null,"Vi_ripple_target",null,{"$f":"Vin_min*C110*1000","v":360},null,null,"mV","Target DC input voltage ripple (Vi_ripple_percent of min Vin)"]
[null,"Q_input",null,{"$f":"(Iout*(1-Vout/Vin_min)*Vout)/(fsw_Hz*Vin_min)*10^6","v":0.21877777777777779},null,null,"µC","Charge per switching cycle (Vin_min)"]
[null,"Cin_min",null,{"$f":"MAX(Q_input/Vi_ripple_target*10^3,10)","v":10},null,null,"µF","Minimum input capacitance required"]
[null,"Cin_cer",null,null,10,null,"µF","Selected total input ceramic capacitance"]
[null,"Cin_derating",null,null,0.5,null,null,"Percentage of Nominal Ceramic Capacitance remaining after Tolerance, Thermal, and DC Bias derating"]
[null,"Cin_eff",null,null,null,{"$f":"Cin_cer*Cin_derating","v":5},"µF","Effective total input ceramic capacitance"]
[null,"Vi_ripple",null,null,null,{"$f":"D112*1000/E114","v":21.87777777777778},"mV","Input DC ripple"]
[null,"Iin_rms",null,null,null,{"$f":"(Vout/Vin_min*((1-Vout/Vin_min)*Iout^2+ (Iripple_min^2)/12))^0.5","v":0.49896415550698187},"A","Input RMS current"]
[null,"Determine feedback network values (FB resistor divider and Cff)"]
[null,"Rfb_b_rec",null,2.61,null,null,"kΩ","Bottom feedback resistor (499-20k recommended)"]
[null,"Rfb_b",null,null,1,null,"kΩ","Selected bottom feedback resistor"]
[null,"Rfb_t_target",null,{"$f":"Rfb_b*(Vout/Vref-1)","v":5.05},null,null,"kΩ","Calculated top resistor"]
[null,"Rfb_t_NSV",null,{"$f":"partData!U16","v":4.99},null,null,"kΩ","Nearest Standard Value 1%"]
[null,"Rfb_t",null,null,5.05,null,"kΩ","Selected top resistor"]
[null,"Vout_calc",null,null,null,{"$f":"Vref*(1+Rfb_t/Rfb_b)","v":3.63},"V","Calculated Vout (yellow if not within 1% of target Vout)"]
[null,"FF_cap?",null,{"$f":"IF(OR(Vout>1.8,f_LC<fsw_select/60),\"YES\",\"NO\")","v":"YES"},null,null,null,"Feedforward cap recommended? (if f_LC < fsw/60 OR Vout > 1.8)"]
[null,"fz_cff_div_f_LC",null,{"$f":"IF(Vout<1.8,3,-0.625*Vout+4.125)","v":1.8562500000000002},null,null,null,"Recommended location of fz_cff relative to f_LC (if Vout <1.8 then 3, if Vout = 5 then 1)"]
[null,"Cff_calc",null,{"$f":"1/(2*PI()*(fz_cff_div_f_LC*f_LC)*Rfb_t)*1000000","v":300.2791689092785},null,null,"pF","Recommended feedforward cap value"]
[null,"Cff_NSV",null,{"$f":"IF(Cff_calc<10000,VLOOKUP((10^(LOG(Cff_calc)-INT(LOG(Cff_calc)))),c_s1:C_f1,1),VLOOKUP((10^(LOG(Cff_calc)-INT(LOG(Cff_calc)))),C_s2:C_f2,1))*10^INT(LOG(Cff_calc))","v":270},null,null,"pF","Nearest Standard Value"]
[null,"Cff",null,null,680,null,"pF","Selected feedforward cap value"]
[null,"Rff_rec",null,{"$f":"Rfb_t/20","v":0.2525},null,null,"kΩ","Recommended feedforward resistor"]
[null,"Rff_NSV",null,{"$f":"(IF((10^(LOG(D131)-INT(LOG(D131)))*100)-VLOOKUP((10^(LOG(D131)-INT(LOG(D131)))*100),E96_s:E96_f,1)<VLOOKUP((10^(LOG(D131)-INT(LOG(D131)))*100),E96_s:E96_f,2)-(10^(LOG(D131)-INT(LOG(D131)))*100),VLOOKUP((10^(LOG(D131)-INT(LOG(D131)))*100),E96_s:E96_f,1),VLOOKUP((10^(LOG(D131)-INT(LOG(D131)))*100),E96_s:E96_f,2)))*10^INT(LOG(D131))/100","v":0.255},null,null,"kΩ","Rff nearest E96 standard value"]
[null,"Rff",null,null,0.26,null,"kΩ","Selected feedforward resistor value"]
[null,"fz_cff",null,null,null,{"$f":"IF(Cff<>0,1/(2*PI()*Cff*0.000000001*(Rfb_t+Rff)*1000),\"N/A\")","v":44.077473992438065},"kHz","Frequency of zero added by the feedforward cap"]
[null,"Soft-start capacitor (SS/REFIN)"]
[null,"Tss_target",5,null,null,null,"ms","Target soft-start time (minimum is 1.5 ms)"]
[null,"C_ss_calc",null,{"$f":"MAX(1,Iss*Tss_target/Vref)","v":75},null,null,"nF","Calculated SS capacitor"]
[null,"Css",null,null,22,null,"nF","Selected SS capacitor"]
[null,"Tss",null,null,null,{"$f":"MAX(1.5,Css*Vref/Iss)","v":1.5},"ms","SS time with selected SS capacitor (0 to 100%)"]
[null,"EN pin resistor divider"]
[null,"Vstart_target",3.3,null,null,null,"V","Target turn on voltage set by EN resistor divider"]
[null,"Ren_b_rec",null,10]
[null,"Ren_b",null,null,10,null,"kΩ","Selected bottom resistor (1k-100k recommended)"]
[null,"Ren_b_eff",null,null,null,{"$f":"Ren_b*6000/(Ren_b+6000)","v":9.9833610648918469},"kΩ","Effective bottom resistance including 6-MΩ internal pull-down resistance on EN pin"]
[null,"Ren_t_calc",null,{"$f":"Ren_b_eff*Vstart_target/EN_rise-Ren_b_eff","v":17.020812307356593},null,null,"kΩ","Calculated top resistor"]
[null,"Ren_t_NSV",null,{"$f":"partData!U17","v":16.899999999999999},null,null,"kΩ","Nearest Standard Value 1%"]
[null,"Ren_t",null,null,16.899999999999999,null,"kΩ","Selected top resistor"]
[null,"Vstart_typ",null,null,null,{"$f":"IF(OR(Ren_b=0,Ren_t=0),\"N/A\",EN_rise*(Ren_b_eff+Ren_t)/Ren_b_eff)","v":3.2852363333333332},"V","Estimated typical turn on voltage with selected resistors\n(Red if below Vin_min, Yellow if near Vin_min)"]
[null,"Vstop_typ",null,null,null,{"$f":"IF(OR(Ren_b=0,Ren_t=0),\"N/A\",EN_fall*(Ren_b_eff+Ren_t)/Ren_b_eff)","v":2.7466729999999999},"V","Estimated typical turn off voltage with selected resistors"]
[null,"Ven_max",null,null,null,{"$f":"IF(OR(Ren_b=0,Ren_t=0),\"N/A\",Vin_max*Ren_b_eff/(Ren_t+Ren_b_eff))","v":5.5703755052021124},"V","Estimated maximum voltage at EN pin at max input voltage (Red if >6V)"]
[null,"Operating Input Voltage Range"]
[null,"fsw_select",null,null,null,{"$f":"fsw_select","v":1100},"kHz","Chosen switching frequency"]
[null,"Minimum Vin",null,null,null,{"$f":"IF(2*Iout*(Rdson_HS_Ohm-Rdson_LS_Ohm)-(Vout+2*Iout*(DCR_Ohm+Rdson_LS_Ohm))/(fsw_Hz*toff_min_max_sec-1)<Vin_min_IC,Vin_min_IC,2*Iout*(Rdson_HS_Ohm-Rdson_LS_Ohm)-(Vout+2*Iout*(DCR_Ohm+Rdson_LS_Ohm))/(fsw_Hz*toff_min_max_sec-1))","v":4.9131303430079152},"V","Minimum input voltage allowed for proper function, based on fsw and minimum off time"]
[null,"Maximum Vin",null,null,null,{"$f":"IF(Vout/fsw_Hz*1/(ton_min_sec)*0.95>Vin_max_IC,Vin_max_IC,Vout/fsw_Hz*1/(ton_min_sec)*0.95)","v":16},"V","Maximum input voltage allowed for proper function, based on fsw and minimum on time"]
[null,"VCC bypass capacitor, BOOT bypass capacitor, PGOOD resistor"]
[null,"Cvcc_rec",null,2.2000000000000002,null,null,"µF","At least 1 µF required"]
[null,"Cvcc",null,null,2.2000000000000002,null,"µF","Selected Cvcc"]
[null,"Cboot_rec",null,0.1,null,null,"µF","At least 0.1µF required"]
[null,"Cboot",null,null,0.1,null,"µF","Selected Cboot"]
[null,"Rboot_rec",null,{"$f":"IF(AND(C33=\"TPS543820\",Vin_max>13.5),2.2,0)","v":0},null,null,"µF","0-Ω series BOOT resistor placeholder recommended in case SW voltage overshoot needs to be reduced."]
[null,"Rboot",null,null,0,null,"µF","Selected Rboot."]
[null,"Rpg_rec",null,10,null,null,"kΩ","1k-100k recommended"]
[null,"Rpg",null,null,10,null,"kΩ","Selected Rpg"]

{"sheet":"Sheet1","index":2,"n_rows":18,"n_cols":2,"rows_kept":18,"cut":false,"hidden":true,"merged":[]}
[1,2]
["Part #","Kramp"]
[{"$f":"partData!A3","v":"TPS548A28"},{"$f":"300000*(0.000000000005+IF(OR(fsw_select=partData!E3,fsw_select=partData!F3),0.00000000000125,0))","v":1.4999999999999998E-6}]
[{"$f":"partData!A4","v":"TPS548A29"},{"$f":"300000*(0.000000000005+IF(OR(fsw_select=partData!E4,fsw_select=partData!F4),0.00000000000125,0))","v":1.4999999999999998E-6}]
[{"$f":"partData!A5","v":"TPS548B27"},{"$f":"300000*(0.000000000005+IF(OR(fsw_select=partData!E5,fsw_select=partData!F5),0.00000000000125,0))","v":1.4999999999999998E-6}]
[{"$f":"partData!A6","v":"TPS548B28"},{"$f":"300000*(0.000000000005+IF(OR(fsw_select=partData!E6,fsw_select=partData!F6),0.00000000000125,0))","v":1.4999999999999998E-6}]
[{"$f":"partData!A7","v":"TPS54J060"},{"$f":"650000*(0.000000000001125+IF(OR(fsw_select=partData!E7,fsw_select=partData!G7),0.00000000000338,0)+IF(fsw_select=partData!G7,0.000000000001745,0))","v":2.9282499999999999E-6}]
[{"$f":"partData!A8","v":"TPS54J061"},{"$f":"B7","v":2.9282499999999999E-6}]
[{"$f":"partData!A9","v":"TPS54JA20"},{"$f":"300000*(0.000000000005+IF(OR(fsw_select=partData!E9,fsw_select=partData!F9),0.00000000000125,0))","v":1.4999999999999998E-6}]
[{"$f":"partData!A10","v":"TPS54JB20"},{"$f":"300000*(0.000000000005+IF(OR(fsw_select=partData!E10,fsw_select=partData!F10),0.00000000000125,0))","v":1.4999999999999998E-6}]
[]
["Selected device",{"$f":"DeviceCalculator!C9","v":"TPS54J061"}]
["fsw_select",{"$f":"fsw_select","v":1100}]
["Kramp",{"$f":"VLOOKUP(B12,A3:B10,2,FALSE)","v":2.9282499999999999E-6}]
["Stability_zout",{"$f":"Lout_H*Vout/(40*K*Vref*Zout_fsw*10^-3)","v":2.82699638460105}]
["Stability_old",{"$f":"(Cout_F*Lout_H*(1-Tol_L)*Vout*fsw_Hz)/(5*K*Vref*SQRT(64*Cout_F^2*ESR_Ohm^2*fsw_Hz^2+1))","v":{"$error":"#N/A"}}]
[]
["dVramp_nom",{"$f":"(Vin_nom/5-Vout/5)/K*Vout/Vin_nom*1/fsw_Hz*0.125","v":1.96512422095108E-2}]

{"sheet":"6A_SchematicChecklist","index":3,"n_rows":26,"n_cols":8,"rows_kept":26,"cut":false,"hidden":false,"merged":[[1,0,1,7],[6,0,6,7],[15,0,15,7]]}
["Pin","Name","Purpose","Connection For Functional Use","Reasoning","Recommended Component Values from Design Calculations","Status","Comments"]
["Control"]
[6,"FB divider","Output feedback input","Ensure that the feedback divider network gives the appropriate Vout based on the Vref chosen. The FB pin must be connected to the AGND pin.",null,{"$f":"CONCATENATE(\"Rfb_t = \",ROUND(DeviceCalculator!D122,3),\" kΩ\",\"\nRfb_b = \",ROUND(Rfb_b,3),\" kΩ\")","v":"Rfb_t = 5.05 kΩ\nRfb_b = 1 kΩ"},"Open"]
[6,"FB Cff","Output feedback input","Add a capacitor in parallel with the top feedback resistor","Improves transient response and may be required for sufficient phase margin or minimizing output ripple",{"$f":"CONCATENATE(\"Cff = \",ROUND(DeviceCalculator!D128,0),\" pF\")","v":"Cff = 300 pF"},"Open"]
[6,"FB Rff","Output feedback input","Add a resistor in series with the Cff capacitor","In some applications, noise on FB can cause charge to accumulate on Cff resulting in the output starting to droop at high loads. Adding a small series resistance prevents the charge from accumulating.",{"$f":"CONCATENATE(\"Rff = \",ROUND(Rff_NSV*1000,0),\" Ω\")","v":"Rff = 255 Ω"},"Open"]
[]
["Configuration"]
[12,"MODE","fsw and DCM/CCM selection","Connect a resistor from MODE pin to AGND pin. 10% or better tolerance resistor is required. Use Table 1 to select the desired mode.",null,{"$f":"CONCATENATE(R_mode,\" kΩ\")","v":"Connect to VCC kΩ"},"Open"]
[12,"MODE fsw setting","fsw selection","Selected fsw should be below the maximum limits calculated in the calculator tab","When exceeding fsw_max_ton, the fsw will decrease but the output will still be regulated. \nWhen exceeding fsw_max_toff, the output will become unregulated and UVP may trip.",{"$f":"CONCATENATE(\"fsw_max_ton = \",ROUND(DeviceCalculator!D39,0),\" kHz\",\"\nfsw_max_toff = \",ROUND(DeviceCalculator!D40,0),\" kHz\")","v":"fsw_max_ton = 3457 kHz\nfsw_max_toff = 2670 kHz"},"Open"]
[4,"TRIP","OCL detection threshold setting pin","Connect the resistor from the TRIP pin to the AGND pin. Use WEBENCH or calculator to calculate the RTRIP resistor value. Recommend 1% or better resistors for RTRIP.",null,{"$f":"CONCATENATE(\"Valley ILIM = \",ROUND(I_lim_target,2),\" A\n\",\"RTRIP = \",ROUND(Rtrip,2),\" kΩ\")","v":"Valley ILIM = 0.75 A\nRTRIP = 22 kΩ"},"Open"]
[8,"SS/REFIN","Soft-start time","Connecting a capacitor from this pin to AGND pin programs soft-start time. Minimum soft-start time (1.5 ms) is fixed internally. \nA minimum 1-nF capacitor is required. ",null,{"$f":"CONCATENATE(\"CSSREFIN = \",ROUND(DeviceCalculator!D137,0),\" nF\")","v":"CSSREFIN = 75 nF"},"Open"]
[9,"PGOOD","Open drain power good flag","Connect a 1k-100k resistor to pull-up this pin. Recommend pulling up to VCC but not required.","PGOOD pin is an open-drain output so a pull-up is required when used",null,"Open"]
[5,"EN","Enable pin","Floating this pin is not recommended. To start switching, this pin must be pulled high.\nThe recommended max voltage rating on the EN pin is 6V. Do not connect EN pin directly to VIN unless the max VIN for your application is below 6V. \nWhen using VIN or VDD to drive the EN pin, use a resistor divider and ensure that the voltage stays below 6V.",null,{"$f":"CONCATENATE(\"Ren_t = \",ROUND(DeviceCalculator!D145,3),\" kΩ\",\"\nRen_b = \",ROUND(Ren_b,3),\" kΩ\")","v":"Ren_t = 17.021 kΩ\nRen_b = 10 kΩ"},"Open"]
[7,"AGND","Ground reference for control circuits","AGND must be connected to PGND",null,null,"Open"]
[]
["Power Stage"]
["3 (VIN), \n1, 14 (PGND)","VIN-PGND cap","Conversion power input","A minimum of 10-µF input capacitance is required","The input capacitor Cin should be able to give minimum ripple voltage desired for the application. Use WEBENCH or calculator to calculate the input capacitance. ",{"$f":"CONCATENATE(\"Cin > \",ROUND(DeviceCalculator!D113,1),\" µF\")","v":"Cin > 10 µF"},"Open"]
["3 (VIN),\n1, 14 (PGND)","VIN-PGND hf cap","Conversion power input","Include a 10nF-100nF 0402 input capacitor","Minimizes high frequency voltage overshoots and undershoots from switching","Cin_hf >= 10 nF","Open"]
[10,"BOOT cap","Supply input for high-side FET gate driver","Connect at least 100-nF capacitor from the BOOT pin to the SW pin. The BOOT capacitor should be at least 10-V rated, X5R, and 0402 size.","10-V rating, X5R or better dielectric, and 0402 size or larger ensure stable capacitance across all operating conditions",{"$f":"CONCATENATE(\"Cboot >= \",ROUND(DeviceCalculator!D158,2),\" µF\")","v":"Cboot >= 0.1 µF"},"Open"]
[10,"BOOT resistor","Supply input for high-side FET gate driver","Include a 0-Ω resistor in series with the BOOT capacitor with an 0402 or larger package size. Optional but highly recommended in case of layout related issues.","If the SW pin overshoot is too high, populating a 4.7-Ω resistor in series with the BOOT capacitor minimizes high frequency voltage overshoots on rising edge of SW pin","Rboot = 0 Ω","Open"]
["2, 11","SW","Switching node","Connect this pin to the output inductor",null,null,"Open"]
["2, 11","SW snubber","Switching node","Optional RC Snubber from SW to PGND. This component can be not populated.\nCapacitor: typ 220 pF with 0402 package and 25V rating\nResistor: typ near 6.8-Ω with minimum 0603 package","If the SW pin ringing is too high, helps minimize high frequency voltage overshoots and undershoots from switching\nCapacitor: Minimum 25V rating to support LL voltage\nResistor: Minimum 0805 package to support power loss","Csnub = 220 pF\nRsnub = 6.8 Ω","Open"]
["N/A","Lout","Output inductor","Use the recommended inductance in WEBENCH or calculator to meet design requirements",null,{"$f":"CONCATENATE(ROUND(DeviceCalculator!D49,2),\" < Lout < \",ROUND(DeviceCalculator!D50,2),\" µH\")","v":"0.83 < Lout < 4.17 µH"},"Open"]
["N/A","Cout","Output capacitors","Use the recommended capacitance in WEBENCH or calculator to meet ripple and transient requirements","The maximum Cout is a recommendation only. Exceeding this may be acceptable but the stability should be evaluated by measuring the load step response or bode plot.",{"$f":"CONCATENATE(ROUND(DeviceCalculator!D82,1),\" < Cout < \",ROUND(DeviceCalculator!D83,1),\" µF\")","v":"5.7 < Cout < 63.4 µF"},"Open"]
[13,"VCC","Internal 3-V LDO output","Require at least 1-µF, 6.3-V rating ceramic capacitor from VCC pin to PGND pins as the bypass capacitor. 2.2-µF recommended.","Minimum capacitance required for stability of the internal regulator.","Cvcc >= 1 µF","Open"]
[13,"VCC","Internal 3-V LDO output","An external bias with 3.3-V can be connected to this pin to save the power losses on the internal LDO",null,null,"Open"]

{"sheet":"6A_LayoutChecklist","index":4,"n_rows":17,"n_cols":7,"rows_kept":17,"cut":false,"hidden":false,"merged":[[10,0,10,6],[1,0,1,6]]}
["Pin","Name","Purpose","Placement or Routing?","Remarks","Status","Comments"]
["Power Stage"]
["3 (VIN), \n1, 14 (PGND)","VIN-PGND caps","Conversion power input","Placement","A 0402 sized 0.01-μF to 0.1-μF bypass capacitor must be placed as close as possible to the VIN and PGND pins to bypass high frequency noise and help reduce switch node ringing. It must be placed on the same side of the PCB as the IC.\nLarger VIN bypass capacitors should also be placed as close as possible to VIN and PGND pins behind this capacitor to minimize the input AC-current loop.","Open"]
[13,"VCC cap","Internal 3-V LDO output","Placement","Place the VCC bypass capacitor as close as possible to the IC on the same side of the PCB. If multiple capacitors are used, provide PGND vias for each capacitor and ensure the return path is as short as possible.","Open"]
["1, 14","PGND",null,"Routing","Include a large PGND pour connected to the PGND pins of the IC and include as many vias as possible for best thermal performance.","Open"]
["N/A","Cout and Lout","Output filter inductor and capacitors","Placement and Routing","Highly recommended to place output and inductor on the same side of the PCB as the IC to minimize PCB parasitic impedance. If components must be placed on the other side of the PCB due to space constraints, ensure multiple vias are used to minimize the added PCB parasitic impedance.","Open"]
[10,"BOOT cap and resistor","Supply input for high-side FET gate driver","Placement","Place the BOOT resistor (if used) as close as possible to the pin, followed by the BOOT capacitor. ","Open"]
["2, 11","SW","Switching node","Routing","The PCB trace which connects the SW pins and high-voltage side of the inductor, should be as short and wide as possible to minimize PCB resistance and radiated noise.","Open"]
["2, 11","SW snubber","Switching node","Placement and Routing","If used, keep the snubber path short for low inductance and the best possible performance. Also, to minimize inductance, avoid using vias for the RC snubber routing anduse very wide traces. To be most effective, the RC snubber should be connected between a large SW and PGND copper pour on the same side of the PCB as the IC.","Open"]
[]
["Control and Configuration"]
[7,"AGND","Ground reference for control circuits","Routing","Create a quite AGND island for the return of noise sensitive pins. Connect AGND to PGND at a single point. For example, use vias to connect to an internal ground plane.","Open"]
["4, 6, 8","TRIP, FB, SS/REFIN","Current limit, Output feedback input, and soft-start timing","Placement","Place the components connected to TRIP, FB and SS/REFIN as close as possible to the IC to minimize the length of trace connected to them. These components must also be returned to quite area of AGND.","Open"]
[6,"FB","Output feedback input","Routing","Connect the FB divider to the output voltage near the desired point of regulation. Avoid routing near noisy signals or power planes.","Open"]
[12,"MODE","Light load mode and fsw selection","Routing","The MODE pin resistor must be returned to the quiet AGND to ensure accurate pin detection.","Open"]
[9,"PGOOD","Open drain power good","Placement and Routing","Keep the PGOOD pull-up resistor and traces away from fast switching voltage and current paths.","Open"]
[8,"EN","Enable pin","Placement and Routing","All components and routing for the EN pin should be placed away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise coupling."]

{"sheet":"12Ato20A_SchematicChecklist","index":5,"n_rows":28,"n_cols":8,"rows_kept":28,"cut":false,"hidden":false,"merged":[[1,0,1,7],[9,0,9,7],[18,0,18,7],[14,5,16,5],[14,6,16,6]]}
["Pin","Name","Purpose","Connection For Functional Use","Reasoning","Recommended Component Values from Calculator","Component units","Status"]
["Sensing and Control"]
[7,"FB","Output voltage feedback input."," A resistor divider from the VOUT to VSNS–  (tapped to FB pin) sets the output voltage. Regardless of remote sensing or single-end sensing connection, FB voltage divider, RFB_HS and RFB_LS, should be always placed as close as possible to the device.","Recommend between 1k to 20k for the RFB_LS.",null,null,"Open"]
[7,"FB Cff, FB divider","Output feedback input","The RC time constant between RfbTop and Cff should be less than 1.5*Tsw, where Tsw is the switching period. If a larger Cff is required, RfbTop and RfbBottom should be reduced accordingly while still maintaining the desired voltage divider ratio. For example, if Cff is doubled, RfbTop and RfbBottom should both be halved.\n\nTypically in general, Cff is not needed for Vout < 2.5 V. It is typically needed for Vout > 2.5V","Larger Cff helps improve transient response, but can put a low frequency zero which can cause instability"]
[6,"VSNS-","The return connection for a remote voltage sensing configuration","For single-end sensing, connect the higher FB resistor to a high-frequency local bypass capacitor of 0.1- μF or higher, and short VSNS– to AGND with shortest trace.",null,null,null,"Open"]
[6,"VSNS-","The return connection for a remote voltage sensing configuration","For remote sensing, the connections from the FB voltage divider resistors to the remote location should be a pair of PCB traces with at least 12-mil trace width, and should implement Kelvin sensing across a high bypass capacitor of 0.1-μF or higher. The ground connection of the remote sensing signal must be connected to VSNS– pin. The VOUT connection of the remote sensing signal must be connected to the feedback resistor divider with the lower feedback resistor terminated at VSNS– pin. To maintain stable output voltage and minimize the ripple, the pair of remote sensing lines should stay away from any noise sources such as inductor and SW nodes, or high frequency clock lines. And it is recommended to shield\nthe pair of remote sensing lines with ground planes above and below.",null,null,null,"Open"]
[6,"VSNS-","The return connection for a remote voltage sensing configuration","It is also used as ground for the internal reference. Short to AGND for single-end sense configuration                                                                                                                 ",null,null,null,"Open"]
[2,"AGND","Reference point for the internal control circuits. ","Use a separate ground symbol for AGND","This is expected to be a clean ground",null,null,"Open"]
[]
["Configuration"]
[8,"EN","The enable pin turns the DC/DC switching converter on or off.","Floating EN pin before startup disables the converter. DO NOT connect EN pin to VIN pin directly.","The recommended max voltage on the EN pin is 5.5V. Typical turn on threshold voltage is 1.2 V for the converter.   The LDO turns on at 0.7V enable threshold",null,null,"Open"]
[4,"MODE","The MODE pin sets the forced continuous-conduction mode (FCCM) or Skipmode operation. It also selects the operating frequency","Connect a resistor from MODE pin to AGND pin. ±1% tolerance resistor is recommended. Use Table 1 to select the desired mode",null,{"$f":"R_mode","v":"Connect to VCC"},"kΩ","Open"]
[3,"TRIP","Current limit setting pin. ","Connect a resistor to AGND to set the current limit trip\npoint. ±1% tolerance resistor is highly recommended.",null,{"$f":"DeviceCalculator!D64","v":22.524396397805798},"kΩ","Open"]
[9,"PGOOD","Open-drain power-good status signal","When the FB voltage moves outside the specified limits, PGOOD goes low after 2-µs delay.  Enable and UVLO asserts PGOOD low. "," Use a 1k to 100k resistor",null,null,"Open"]
[5,"SS/REFIN","Dual-function pin. Soft-start function.  REFIN function: The device always looks at the voltage on this SS/REFIN pin as the reference for the control loop","Connecting a capacitor to VSNS– pin programs soft-start time. Minimum soft-start time (1.5 ms) is fixed internally. A minimum 1-nF capacitor is required for this pin to avoid overshoot during the charge of soft-start capacitor. ",null,{"$f":"DeviceCalculator!D137","v":75},"nF","Open"]
[5,"SS/REFIN","Dual-function pin. Soft-start function.  REFIN function: The device always looks at the voltage on this SS/REFIN pin as the reference for the control loop","The SS/REFIN capacitor must use the VSNS– pin for its ground.  If an existing design uses both SS/REFIN-to-VSNS- and SS/REFIN-to-AGND capacitors,  the SS/REFIN-to-AGND capacitor should be smaller. Noise can be coupled into the SS/REFIN pin and affect stability when SS/REFIN-to-AGND capacitor is too large.  Keep SSREFIN to AGND less than 22nF",null,null,null,"Open"]
[5,"SS/REFIN","Dual-function pin. Soft-start function.  REFIN function: The device always looks at the voltage on this SS/REFIN pin as the reference for the control loop","This device doesn't require a capacitor from the SS/REFIN pin to AGND and adding one is not recommenced. If the user adds a capacitor from SS/REFIN to AGND, place the capacitor from SS/REFIN to VSNS- closer to the pin with shortest trace to VSNS– pin.",null,null,null,"Open"]
[]
["Power Stage"]
[1,"BOOT","supply rail for the high-side gate driver","Connect the bootstrap capacitor from this pin to SW node.","TI recommends using a 0.1-µF to 1-µF bootstrap capacitor with 10-V rating. It is good practice to use a 0-Ω resistor in series with BOOT capacitor.",null,null,"Open"]
[20,"SW","SW is the output switching terminal of the power converter. ","Output switching terminal of the power converter. Connect this pin to the output\ninductor",null,null,null,"Open"]
["10, 21","VIN","VIN is the conversion power-supply input pins","Place the decoupling input capacitors from VIN pins to PGND pins as close as possible.","VIN decoupling capacitors are important for FET robustness. ",null,null,"Open"]
["10, 21","VIN","VIN is the conversion power-supply input pins","1uF/25V/X6S/0402 ceramic capacitor on VIN pin 21 is required. The PGND vias for this decoupling capacitor should be placed so that the decoupling capacitor is closer to IC than the PGND vias. To lower ESL from via connection, two 8-mil vias are recommended for the PGND connection to inner PGND plane. ",null,null,null,"Open"]
["10, 21","VIN","VIN is the conversion power-supply input pins","A 1uF/25V/X6S/0402 ceramic capacitor on VIN pin 10 is highly recommended. If this 0402 size capacitor is not used, the bigger size VIN decoupling capacitors (0603 or 0805 size) are required to be placed as close as possible to IC pin 10 and pin 11.",null,null,null,"Open"]
["10, 21","VIN","VIN is the conversion power-supply input pins","Two 1uF/25V/X6S/0402 ceramic capacitors on bottom layer are recommended for high current applications (Iout > 13A). One of these two capacitors should be centered between VIN pin 10 and pin 21. To have good connection for this capacitor, a VIN copper on bottom layer and two VIN vias are needed. The other one can be placed close to IC package just like a mirrored copy to the 0402 capacitor on top layer.",null,null,null,"Open"]
["11, 12, 13, 14, 15, 16, 17, 18","PGND","These ground pins are connected to the return of the internal low-side MOSFET.","Power ground of internal low-side MOSFET. At least 6 PGND vias are required to be placed as close as possible to the PGND pins. This minimizes parasitic impedance and also lowers thermal resistance",null,null,null,"Open"]
[19,"VCC","Internal 3-V LDO output","Require a 2.2-µF, at least 6.3-V rating ceramic capacitor from VCC pin to PGND pins as the decoupling capacitor and the placement is required to be as close as possible.",null,null,null,"Open"]
[19,"VCC","Internal 3-V LDO output.  ","An external bias with 3.3-V (TPS54JA20, TPS548A28) 4.5V (TPS548A29) or higher voltage can be connected to this pin to save the power losses on the internal LDO",null,null,null,"Open"]

{"sheet":"12Ato20A_LayoutChecklist","index":6,"n_rows":17,"n_cols":8,"rows_kept":17,"cut":false,"hidden":false,"merged":[[1,0,1,6],[5,0,5,6],[11,0,11,6]]}
["Pin","Name","Purpose","Placement or Routing?","Remarks","Reasoning","Status","Comments"]
["Sensing and Control"]
[7,"FB","Output voltage feedback input.","Placement","Place the feedback resistor near the device to minimize the FB trace distance. Avoid routing near noisy signals or power planes.",null,"Open"]
[6,"VSNS-","The return connection for a remote voltage sensing configuration",null,"The return connection for a remote voltage sensing configuration. It is also used as ground for the internal reference. Short to AGND for single-end sense configuration",null,"Open"]
[]
["Configuration"]
[8,"EN","enable pin","Routing","All routing for the EN pin should be placed away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise coupling.  The recommended operating condition for EN pin is maximum 5.5-V. DO NOT connect EN pin to VIN pin directly.",null,"Open"]
["4, 3","MODE, TRIP",null,"Placement","Place the Mode/Frequency setting resistor (MODE), OCP setting resistor (RTRIP) as close to the device as possible. Use the common GND via to connect them to the GND plane. Route all of these traces away from the switch node and other noisy sig",null,"Open"]
[9,"PGOOD","open drain power good","Placement","Keep the PGOOD resistor local to the device and place it as close as possible to the PGOOD pin. The resistor should be kept away from fast switching voltage and current paths.",null,"Open"]
[5,"SS/REFIN","Dual function:  External Soft start or external reference input pin","Placement","Soft-start function: Connect a ground of SS capacitor to VSNS– pin.    If two capacitors are used on SS pin connect larger value SS cap to VSNS-.   Connect smaller value SS cap to AGND.\n",null,"Open"]
[]
["Power Stage"]
[1,"BOOT",null,null,"Place the boot resistor (if used) as close as possible to the pin, followed by the boot capacitor. ",null,"Open"]
[20,"SW",null,null,"The PCB trace defined as switch node, which connects the SW pins and high-voltage side of the inductor, should be as short and wide as possible.",null,"Open"]
["10, 21","VIN","Power Input",null,"To lower ESL from via connection, two 8-mil vias are\nrecommended for the PGND connection to inner PGND plane\nA 1uF/25V/X6S/0402 ceramic capacitor on VIN pin 10 is highly recommended. If this 0402 size capacitor is\nnot used, the bigger size VIN decoupling capacitors (0603 or 0805 size) are required to be placed as close as\npossible to IC pin 10 and pin 11.\nTwo 1uF/25V/X6S/0402 ceramic capacitors on bottom layer are recommended for high current applications\n(Iout > 13A). One of these two capacitors should be centered between VIN pin 10 and pin 21. To have good\nconnection for this capacitor, a VIN copper on bottom layer and two VIN vias are needed. The other one can\nbe placed close to IC package just like a mirrored copy to the 0402 capacitor on top layer.",null,"Open"]
["11, 12, 13, 14, 15, 16, 17, 18","PGND","These ground pins are connected to the return of the internal low-side MOSFET.",null,"Have a large solid ground plane for GND",null,"Open"]
[19,"VCC",null,null,"Place the VCC decoupling capacitor (2.2uF/6.3V/X6S/0402 or 2.2uF/6.3V/X7R/0603) as close as possible to\nthe device. Ensure the VCC decoupling loop is smallest.",null,"Open"]

{"sheet":"Std. R and C Values","index":7,"n_rows":99,"n_cols":17,"rows_kept":99,"cut":false,"hidden":true,"merged":[[2,4,2,5],[2,6,2,7],[9,4,9,5],[22,4,22,5],[47,4,47,5]]}
["Hide Sheet"]
[null,null,null,null,"Std. Resistors",null,null,null,null,"Capacitors"]
[null,"Enter resistor value",100,null,"E6",null,"E96",null,null,"Cap value",8.2000000000000006E-8,"pF"]
[null,null,null,null,100,150,100,102,null,null,{"$f":"IF(K3*10^12<10000,IF((10^(LOG(K3*10^12)-INT(LOG(K3*10^12))))-VLOOKUP((10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),c_s1:C_f1,1)<VLOOKUP((10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),c_s1:C_f1,2)-(10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),VLOOKUP((10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),c_s1:C_f1,1),VLOOKUP((10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),c_s1:C_f1,2))*10^INT(LOG(K3*10^12)),IF((10^(LOG(K3*10^12)-INT(LOG(K3*10^12))))-VLOOKUP((10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),C_s2:C_f2,1)<VLOOKUP((10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),C_s2:C_f2,2)-(10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),VLOOKUP((10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),C_s2:C_f2,1),VLOOKUP((10^(LOG(K3*10^12)-INT(LOG(K3*10^12)))),C_s2:C_f2,2))*10^INT(LOG(K3*10^12)))*10^-12","v":6.8E-8},"pF"]
[null,"Closest E6 Value",{"$f":"(IF((10^(LOG(C3)-INT(LOG(C3)))*100)-VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E6_s:E6_f,1)<VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E6_s:E6_f,2)-(10^(LOG(C3)-INT(LOG(C3)))*100),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E6_s:E6_f,1),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E6_s:E6_f,2)))*10^INT(LOG(C3))/100","v":100},null,150,220,102,105]
[null,"Closest E12 Value",{"$f":"(IF((10^(LOG(C3)-INT(LOG(C3)))*100)-VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E12_s:E12_f,1)<VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E12_s:E12_f,2)-(10^(LOG(C3)-INT(LOG(C3)))*100),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E12_s:E12_f,1),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E12_s:E12_f,2)))*10^INT(LOG(C3))/100","v":100},null,220,330,105,107,null,"C values up to 10nF"]
[null,"Closest E24 Value",{"$f":"(IF((10^(LOG(C3)-INT(LOG(C3)))*100)-VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E24_s:E24_f,1)<VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E24_s:E24_f,2)-(10^(LOG(C3)-INT(LOG(C3)))*100),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E24_s:E24_f,1),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E24_s:E24_f,2)))*10^INT(LOG(C3))/100","v":100},null,330,470,107,110,null,1,1.2,{"$f":"IF((10^(LOG(K3)-INT(LOG(K3))))-VLOOKUP((10^(LOG(K3)-INT(LOG(K3)))),c_s1:C_f1,1)<VLOOKUP((10^(LOG(K3)-INT(LOG(K3)))),c_s1:C_f1,2)-(10^(LOG(K3)-INT(LOG(K3)))),VLOOKUP((10^(LOG(K3)-INT(LOG(K3)))),c_s1:C_f1,1),VLOOKUP((10^(LOG(K3)-INT(LOG(K3)))),c_s1:C_f1,2))","v":8.1999999999999993}]
[null,"Closest E48 Value",{"$f":"(IF((10^(LOG(C3)-INT(LOG(C3)))*100)-VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E48_s:E48_f,1)<VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E48_s:E48_f,2)-(10^(LOG(C3)-INT(LOG(C3)))*100),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E48_s:E48_f,1),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E48_s:E48_f,2)))*10^INT(LOG(C3))/100","v":100},null,470,680,110,113,null,1.2,1.5]
[null,"Closest E96 Value",{"$f":"(IF((10^(LOG(C3)-INT(LOG(C3)))*100)-VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E96_s:E96_f,1)<VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E96_s:E96_f,2)-(10^(LOG(C3)-INT(LOG(C3)))*100),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E96_s:E96_f,1),VLOOKUP((10^(LOG(C3)-INT(LOG(C3)))*100),E96_s:E96_f,2)))*10^INT(LOG(C3))/100","v":100},null,680,1000,113,115,null,1.5,1.8,null,null,null,null,"Notes:","If I use the value in column K it rounds up"]
[null,null,null,null,"E12",null,115,118,null,1.8,2.2000000000000002,null,null,null,null,null,"If I use the value in column J it rounds down"]
[null,null,null,null,100,120,118,121,null,2.2000000000000002,2.7]
[null,null,null,null,120,150,121,124,null,2.7,3.3]
[null,null,null,null,150,180,124,127,null,3.3,3.9]
[null,null,null,null,180,220,127,130,null,3.9,4.7]
[null,null,null,null,220,270,130,133,null,4.7,5.6]
[null,null,null,null,270,330,133,137,null,5.6,6.8]
[null,null,null,null,330,390,137,140,null,6.8,8.1999999999999993]
[null,null,null,null,390,470,140,143,null,8.1999999999999993,10]
[null,null,null,null,470,560,143,147,null,"C values greater than 10nF"]
[null,null,null,null,560,680,147,150,null,1,1.5,{"$f":"IF((10^(LOG(K3)-INT(LOG(K3))))-VLOOKUP((10^(LOG(K3)-INT(LOG(K3)))),C_s2:C_f2,1)<VLOOKUP((10^(LOG(K3)-INT(LOG(K3)))),C_s2:C_f2,2)-(10^(LOG(K3)-INT(LOG(K3)))),VLOOKUP((10^(LOG(K3)-INT(LOG(K3)))),C_s2:C_f2,1),VLOOKUP((10^(LOG(K3)-INT(LOG(K3)))),C_s2:C_f2,2))","v":6.8}]
[null,null,null,null,680,820,150,154,null,1.5,2.2000000000000002]
[null,null,null,null,820,1000,154,158,null,2.2000000000000002,3.3]
[null,null,null,null,"E24",null,158,162,null,3.3,4.7]
[null,null,null,null,100,110,162,165,null,4.7,6.8]
[null,null,null,null,110,120,165,169,null,6.8,10]
[null,null,null,null,120,130,169,174]
[null,null,null,null,130,150,174,178]
[null,null,null,null,150,160,178,182]
[null,null,null,null,160,180,182,187]
[null,null,null,null,180,200,187,191]
[null,null,null,null,200,220,191,196]
[null,null,null,null,220,240,196,200]
[null,null,null,null,240,270,200,205]
[null,null,null,null,270,300,205,210]
[null,null,null,null,300,330,210,215]
[null,null,null,null,330,360,215,221]
[null,null,null,null,360,390,221,226]
[null,null,null,null,390,430,226,232]
[null,null,null,null,430,470,232,237]
[null,null,null,null,470,510,237,243]
[null,null,null,null,510,560,243,249]
[null,null,null,null,560,620,249,255]
[null,null,null,null,620,680,255,261]
[null,null,null,null,680,750,261,267]
[null,null,null,null,750,820,267,274]
[null,null,null,null,820,910,274,280]
[null,null,null,null,910,1000,280,287]
[null,null,null,null,"E48",null,287,294]
[null,null,null,null,100,105,294,301]
[null,null,null,null,105,110,301,309]
[null,null,null,null,110,115,309,316]
[null,null,null,null,115,121,316,324]
[null,null,null,null,121,127,324,332]
[null,null,null,null,127,133,332,340]
[null,null,null,null,133,140,340,348]
[null,null,null,null,140,147,348,357]
[null,null,null,null,147,154,357,365]
[null,null,null,null,154,162,365,374]
[null,null,null,null,162,169,374,383]
[null,null,null,null,169,178,383,392]
[null,null,null,null,178,187,392,402]
[null,null,null,null,187,196,402,412]
[null,null,null,null,196,205,412,422]
[null,null,null,null,205,215,422,432]
[null,null,null,null,215,226,432,442]
[null,null,null,null,226,237,442,453]
[null,null,null,null,237,249,453,464]
[null,null,null,null,249,261,464,475]
[null,null,null,null,261,274,475,487]
[null,null,null,null,274,287,487,499]
[null,null,null,null,287,301,499,511]
[null,null,null,null,301,316,511,523]
[null,null,null,null,316,332,523,536]
[null,null,null,null,332,348,536,549]
[null,null,null,null,348,365,549,562]
[null,null,null,null,365,383,562,576]
[null,null,null,null,383,402,576,590]
[null,null,null,null,402,422,590,604]
[null,null,null,null,422,442,604,619]
[null,null,null,null,442,464,619,634]
[null,null,null,null,464,487,634,649]
[null,null,null,null,487,511,649,665]
[null,null,null,null,511,536,665,681]
[null,null,null,null,536,562,681,698]
[null,null,null,null,562,590,698,715]
[null,null,null,null,590,619,715,732]
[null,null,null,null,619,649,732,750]
[null,null,null,null,649,681,750,768]
[null,null,null,null,681,715,768,787]
[null,null,null,null,715,750,787,806]
[null,null,null,null,750,787,806,825]
[null,null,null,null,787,825,825,845]
[null,null,null,null,825,866,845,866]
[null,null,null,null,866,909,866,887]
[null,null,null,null,909,953,887,909]
[null,null,null,null,953,1000,909,931]
[null,null,null,null,null,null,931,953]
[null,null,null,null,null,null,953,976]
[null,null,null,null,null,null,976,1000]

{"sheet":"partData","index":8,"n_rows":578,"n_cols":29,"rows_kept":578,"cut":false,"hidden":true,"merged":[]}
[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,{"$f":"V1+1","v":23},{"$f":"W1+1","v":24},{"$f":"X1+1","v":25},26,27,28,0]
["Part #","VIN_min","VIN_max","Io,rated","Fsw_1","Fsw_2","Fsw_3","OC clamp","tonmin","Vref","OC Fault","OV Fault","VCC LDO Voltage","VIN_min_bias","toffmin","R_HS","R_LS","OC gain","I_ss","EN_rise","EN_fall","Ioc_neg_max","Rtrip_min","Rtrip_max","Rtrip_calc","Ilim_min","ILIM_Tol","Rboot_rec",{"$f":"AC98/10","v":1E-3}]
["TPS548A28",4,16,14,600,800,1000,15,70,0.6,"Hiccup","Latch Off",3,"2 .7",220,10.199999999999999,3.1,60000,36,{"$f":"T7","v":1.22},{"$f":"U7","v":1.02},-8,4,14.7,{"$f":"MAX(W3,MIN(X3,-5.078*LN( I_lim_target) + 17.066,R3*0.85/I_lim_target*10^-3))","v":14.7},{"$f":"MIN(I_lim_typ*0.85,28.4*EXP(-0.195*Rtrip))","v":0.38921987844516442},{"$f":"(Z3-I_lim_typ)/I_lim_typ","v":-0.71457208914021275},0,1.0200000000000001E-3]
["TPS548A29",4,16,14,600,800,1000,15,70,0.6,"Hiccup","Latch Off",4.5,"2 .7",220,8.1999999999999993,2.6,60000,36,{"$f":"T3","v":1.22},1.02,-8,4,14.7,{"$f":"Y3","v":14.7},{"$f":"Z3","v":0.38921987844516442},-0.71457208914021275,{"$f":"AB3","v":0},1.0500000000000002E-3]
["TPS548B27",4,16,20,600,800,1000,20.9,70,0.6,"Hiccup","Latch Off",3,"2 .7",220,7.2,2.2999999999999998,120000,36,{"$f":"T4","v":1.22},1.02,-8,0,20,{"$f":"MAX(W5,MIN(X5,-10.15*LN( I_lim_target) + 34.7,R5*0.9/I_lim_target*10^-3))","v":20},{"$f":"MIN(I_lim_typ*0.9,29.487*EXP(-0.097*Rtrip))","v":1.2272727272727273},-9.9999999999999922E-2,0,1.0700000000000002E-3]
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{"sheet":"Extra","index":9,"n_rows":6,"n_cols":2,"rows_kept":6,"cut":false,"hidden":true,"merged":[]}
[]
[]
[null,"Validation Options"]
[null,"Open"]
[null,"Complete"]
[null,"Not Applicable"]

{"sheet":"revisionNotes","index":10,"n_rows":9,"n_cols":2,"rows_kept":9,"cut":false,"hidden":false,"merged":[]}
["Date","Change"]
["2020-05-28","Added TPS54J060/1 schematic checklist (6aSchematicChecklist tab)"]
["2020-05-29","Added TPS54J060/1 layout checklist (6aLayoutChecklist tab)"]
["2020-06-29","Corrected equation for calculating Q_input. Added (1-D) term."]
["2020-08-18","Added calculation for EN max voltage"]
["2020-09-30","Added macros for design checks"]
["2020-12-22","Added Rff. Changed Rtrip selection to be based on current limit value for margin."]
["2021-04-20","Removed RC constant check on Cff and FB divider from 6A_SchematicChecklist. \nAdded check for Rff to 6A_ShematicChecklist."]
["2021-08-03","Added Simplis Export Variable "]

{"sheet":"Disclaimer","index":11,"n_rows":6,"n_cols":2,"rows_kept":6,"cut":false,"hidden":false,"merged":[]}
[]
[null,"Important notice and disclaimer"]
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[null,"These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements."]
[null,"These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources."]
[null,"TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products."]