*$
* source UCC287XX
*
*
*****************************************************************************
* (C) Copyright 2015 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer.
*****************************************************************************
*
* Released by: WEBENCH Design Center, Texas Instruments Inc.
* Part: UCC28704
* Date: 2/12/2015
* Model Type: Transient
* Simulator:  PSPICE
* Simulator Version: 16.2
* EVM Order Number: UCC28700EVM-068
* EVM Users Guide: SLUU968
* Datasheet: SLUSB41A  JULY 2012REVISED DECEMBER 2014
* Model Version: Final 1.0
* Release to Web.
*Version 1.1- Included the changes done by Arash to the model
***************************************************************************** source UCC28704
.SUBCKT TOP_UCC28704 NTC_SU VDD DRV CS GND VS  PARAMS: MASK_VDD_PULSE=0.0 VDD_PULSE_DELAY=0 

R_NTC NTC_SU 0 100meg


X_D66mask N16699211 VDD D_D1 
V_V1mask	N16699211 0 PULSE 0 {(1-{MASK_VDD_PULSE})*25.0} {VDD_PULSE_DELAY} 1u 1u 50u

R_R11         HI RTRY_LOFFZ  100 TC=0,0 
V_U_WUM_V27         U_WUM_HI 0 5
X_U_WUM_U30         U_WUM_N16761888 U_WUM_N16766451 U_WUM_N16766727
+  OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_WUM_U13         U_WUM_N16762502 U_WUM_N16761888 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_WUM_U57         VS U_WUM_N16763095 U_WUM_N16762798 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U_WUM_U28         U_WUM_N16761888 U_WUM_N16762798 U_WUM_N16760864
+  OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_WUM_S10    U_WUM_N16766735 0 U_WUM_N16766745 0 WUM_U_WUM_S10 
X_U_WUM_U59         U_WUM_N16760981 U_WUM_N16761403 U_WUM_N16761860
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_WUM_U29         N755760 U_WUM_N16760864 U_WUM_N16760880 OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
I_U_WUM_I4         0 U_WUM_N16760981 DC 1e-6Adc  
X_U_WUM_U55         U_WUM_N16760981 U_WUM_N16761403 d_d1 PARAMS:
X_U_WUM_U32         U_WUM_N16763801 U_WUM_N16766559 WAKE OR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U_WUM_U58         VS U_WUM_N16766511 U_WUM_N16766451 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U_WUM_U34         U_WUM_N16766559 N16766563 U_WUM_N16766451 U_WUM_HI
+  U_WUM_N16766523 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_WUM_V29         U_WUM_N16763095 0 0.05
C_U_WUM_C18         0 U_WUM_N16760981  10p  TC=0,0 
C_U_WUM_C19         0 U_WUM_N16766745  10p  TC=0,0 
X_U_WUM_S9    U_WUM_N16760880 0 U_WUM_N16760981 0 WUM_U_WUM_S9 
V_U_WUM_V31         U_WUM_N16766909 0 1
X_U_WUM_U9         WAIT EN_DLY U_WUM_N16762502 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_WUM_U33         U_WUM_N16763801 N16763909 U_WUM_N16762798 U_WUM_HI
+  U_WUM_N16763370 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_WUM_U61         U_WUM_N16761860 U_WUM_N16761888 N755760 U_WUM_N16763370
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_WUM_U60         U_WUM_N16766745 U_WUM_N16766909 U_WUM_N16766997
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U_WUM_V28         U_WUM_N16761403 0 1
V_U_WUM_V30         U_WUM_N16766511 0 2
X_U_WUM_U31         U_WUM_N16767005 U_WUM_N16766727 U_WUM_N16766735
+  OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_WUM_U56         U_WUM_N16766745 U_WUM_N16766909 d_d1 PARAMS:
I_U_WUM_I5         0 U_WUM_N16766745 DC 1e-6Adc  
X_U_WUM_U62         U_WUM_N16766997 U_WUM_N16761888 U_WUM_N16767005
+  U_WUM_N16766523 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_S1    EN_WZ 0 N755302 0 TOP_UCC28704_S1 
R_CNTLLAW_R20         CNTLLAW_N882713 CNTLLAW_N882805  69.95k TC=0,0 
X_CNTLLAW_U50         CNTLLAW_B0Z CNTLLAW_LOW_FZ CNTLLAW_N16779036
+  AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U43         CNTLLAW_LOW_F_FE CNTLLAW_N801161 CNTLLAW_LOW_FZ
+  CNTLLAW_N801161 CNTLLAW_N802830 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_S16    CNTLLAW_N16778656 0 N755066 CNTLLAW_N882821
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_S16 
X_CNTLLAW_U61         CNTLLAW_B0Z CNTLLAW_LOW_FZ CNTLLAW_NN_2 AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U63         B0 LOWF CNTLLAW_GG_0 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_U77         WAKE CNTLLAW_ENZ_DLY CNTLLAW_N16777606 CNTLLAW_NX_RESET
+  OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U80         CNTLLAW_NAX1 CNTLLAW_N801161 CNTLLAW_NAX2
+  CNTLLAW_N16777606 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U53         CNTLLAW_VLC_LIMITED CNTLLAW_N847549 CNTLLAW_N16779186
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_CNTLLAW_U57         VOH CNTLLAW_VOHZ INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_U51         LOWF CNTLLAW_B0Z CNTLLAW_N16778516 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
E_CNTLLAW_ABM2         VCX5 0 VALUE { {LIMIT((V(CNTLLAW_N882561) - V(0))*1,
+  0,500)}  
+ *1   }
V_CNTLLAW_V30         CNTLLAW_N849886 0 3.3
X_CNTLLAW_U74         CNTLLAW_N882821 CNTLLAW_N882479 d_d1 PARAMS:
X_CNTLLAW_U64         CNTLLAW_B0Z LOWF CNTLLAW_GG_2 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
E_CNTLLAW_ABM1         CNTLLAW_VLC_LIMITED 0 VALUE { {LIMIT((V(VLC) - V(0))*1,
+  0.4,5)}  
+ *1   }
X_CNTLLAW_U76         CNTLLAW_N16779186 CNTLLAW_N16778521 INV_DELAY_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=50n
X_CNTLLAW_U42         CNTLLAW_C3 CNTLLAW_Q3 CNTLLAW_N796812 OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U36         WAKE_L N16778373 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
X_CNTLLAW_U46         B0 CNTLLAW_B0Z INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_U34         CNTLLAW_Q4 N16793240 CNTLLAW_N16793003 CNTLLAW_Q3
+  CNTLLAW_NX_RESET 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U60         B0 CNTLLAW_LOW_FZ CNTLLAW_NN_0 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_S10    CNTLLAW_GG_0 0 CNTLLAW_N847549 CNTLLAW_N849886
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_S10 
X_CNTLLAW_F5    CNTLLAW_N882887 CNTLLAW_N882893 0 CNTLLAW_N882561
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_F5 
V_CNTLLAW_V29         CNTLLAW_N848476 0 2.7
V_CNTLLAW_V36         CNTLLAW_N882713 0 0.9375
X_CNTLLAW_S17    CNTLLAW_N16778668 0 CNTLLAW_VLC_LIMITED CNTLLAW_N882821
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_S17 
V_CNTLLAW_V34         CNTLLAW_HI 0 5
V_CNTLLAW_V31         CNTLLAW_N850893 0 3
V_CNTLLAW_V38         CNTLLAW_N788560 0 0.05
X_CNTLLAW_U56         EN_DLY CNTLLAW_ENZ_DLY INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_U48         ZCD_FIRST CNTLLAW_N16777666 BUF_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
X_CNTLLAW_S9    CNTLLAW_GG_2 0 CNTLLAW_N847549 CNTLLAW_N848476
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_S9 
X_CNTLLAW_U37         WAIT CNTLLAW_WAIT_Z INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_U31         CNTLLAW_Q2 CNTLLAW_N16793003 CNTLLAW_N16793009
+  CNTLLAW_N16793003 CNTLLAW_NX_RESET 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_U38         CNTLLAW_N16778587 CNTLLAW_N16778656 BUF_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_CNTLLAW_S8    CNTLLAW_NN_2 0 CNTLLAW_N847549 CNTLLAW_N847553
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_S8 
X_CNTLLAW_S19    CNTLLAW_NODE_G_S1 0 CNTLLAW_N882893 CNTLLAW_N882533
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_S19 
X_CNTLLAW_S7    CNTLLAW_NN_0 0 CNTLLAW_N847549 CNTLLAW_N850893
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_S7 
X_CNTLLAW_U30         LOWF CNTLLAW_LOW_FZ CNTLLAW_CL_CLK_BUFFERED
+  CNTLLAW_N16778521 CNTLLAW_N842890 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_U82         CNTLLAW_ENZ_DLY CNTLLAW_LOW_F_FE CNTLLAW_VOHZ
+  CNTLLAW_N842890 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U45         CL_CLK CNTLLAW_CL_CLK_BUFFERED BUF_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_CNTLLAW_U13         WAKE CNTLLAW_N16793149 WAKE_L CNTLLAW_NAX1
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_CNTLLAW_U81         CNTLLAW_Q4 CNTLLAW_B0Z CNTLLAW_ENZ_DLY CNTLLAW_N802830
+  OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U79         N755066 CNTLLAW_N781970 CNTLLAW_N788560 CNTLLAW_N785792
+  COMPHYS2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 T=10
X_CNTLLAW_U40         CNTLLAW_N16778587 CNTLLAW_N16778668 INV_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
V_CNTLLAW_V26         CNTLLAW_N847553 0 2.65
X_CNTLLAW_S20    CNTLLAW_VOHZ 0 CNTLLAW_N882713 CNTLLAW_N882805
+  CNTL_LAW_SIMPLIFIED_CNTLLAW_S20 
X_CNTLLAW_U62         LOWF CNTLLAW_N796812 CNTLLAW_N16792978 AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U47         CNTLLAW_N785792 CNTLLAW_N776773 INV_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
V_CNTLLAW_V37         CNTLLAW_N781970 0 1.2
R_CNTLLAW_R19         CNTLLAW_N882805 CNTLLAW_N882561  87.49k TC=0,0 
X_CNTLLAW_U12         CNTLLAW_ENZ_DLY CNTLLAW_C3 CNTLLAW_N16777966 CNTLLAW_NAX2
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
I_CNTLLAW_I5         CNTLLAW_N882479 CNTLLAW_N882533 DC 17.86uAdc  
X_CNTLLAW_U39         WAKE_L N16782446 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
V_CNTLLAW_V35         CNTLLAW_N882893 0 2.2
X_CNTLLAW_U33         CNTLLAW_Q1 CNTLLAW_N16793009 CNTLLAW_N16777666
+  CNTLLAW_N16793009 CNTLLAW_NX_RESET 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_CNTLLAW_U73         CNTLLAW_N882533 CNTLLAW_N882479 d_d1 PARAMS:
R_CNTLLAW_R18         CNTLLAW_N882533 CNTLLAW_N882887  44.79k TC=0,0 
X_CNTLLAW_U55         CNTLLAW_Q4 CNTLLAW_ENZ_DLY CNTLLAW_N16792978
+  CNTLLAW_N16793149 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U41         CNTLLAW_N16779036 WAKE_L CNTLLAW_N16778587 OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U78         CNTLLAW_VLC_SCALED_UP N754894 LR_MINP VLC_to_MINP PARAMS:
+   VTHRESH=0.5
X_CNTLLAW_U35         VORH N777488 CNTLLAW_CL_CLK_BUFFERED CNTLLAW_N776773
+  CNTLLAW_ENZ_DLY 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U32         CNTLLAW_Q3 N16793221 CNTLLAW_N16793003 CNTLLAW_HI
+  CNTLLAW_NX_RESET 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U58         CNTLLAW_N16778516 VORH CNTLLAW_N16777966
+  CNTLLAW_NODE_G_S1 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_CNTLLAW_U65         CNTLLAW_Q2 CNTLLAW_Q1 CNTLLAW_C3 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
E_CNTLLAW_E1         CNTLLAW_VLC_SCALED_UP 0 VLC 0 1.22
R_R8         N755624 VDD_SH  0.1 TC=0,0 
R_R5         0 CC_UV_TH  984.8k TC=0,0 
X_U63         N16803687 N16806075 one_shot PARAMS:  T=50
V_V28         HI 0 5
V_V29         B0 0 1
R_R7         N755924 VDD_SH  0.1 TC=0,0 
E_E3         CS_SH 0 CS GND 1
R_U_EMI_R21         U_EMI_N458297 VCX5  39.2k TC=0,0 
R_U_EMI_R22         U_EMI_N458545 U_EMI_N458297  400 TC=0,0 
R_U_EMI_R19         VC U_EMI_N458545  400 TC=0,0 
C_U_EMI_C1         0 VC  2p  TC=0,0 
R_U_EMI_R18         0 U_EMI_N458527  9.2k TC=0,0 
R_U_EMI_R20         U_EMI_N458537 VC  400 TC=0,0 
R_U_EMI_R17         U_EMI_N458527 U_EMI_N458537  400 TC=0,0 
R_R10         CC_UV_TH V5  1.015meg TC=0,0 
R_R4         N755302 V5  2.5k TC=0,0 
X_U_MOD1_U55         U_MOD1_N007271 U_MOD1_N16778558 d_d1 PARAMS:
X_U_MOD1_U43         U_MOD1_NUQ_0 U_MOD1_N16778544 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
R_U_MOD1_R18         GND U_MOD1_N16778420  100k TC=0,0 
X_U_MOD1_F1    GND U_MOD1_N16778536 0 U_MOD1_N16778420
+  Modulator_MODIFIED_U_MOD1_F1 
V_U_MOD1_V28         0 U_MOD1_N007271 0.000
X_U_MOD1_U37         EN U_MOD1_ENZ INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_U33         U_MOD1_N16778689 U_MOD1_N16778647 U_MOD1_DR_Z
+  U_MOD1_NXX_111 U_MOD1_ENZ 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U_MOD1_R5         U_MOD1_NXX_111 U_MOD1_N16778483  72.46e3  
X_U_MOD1_S8    U_MOD1_N16778647 0 U_MOD1_N16778649 U_MOD1_N16778655
+  Modulator_MODIFIED_U_MOD1_S8 
V_U_MOD1_V26         U_MOD1_N16778655 0 2.1
C_U_MOD1_C18         0 U_MOD1_N16778942  1p  TC=0,0 
V_U_MOD1_V29         U_MOD1_N16778919 U_MOD1_N007711 0.000
X_U_MOD1_U52         U_MOD1_N16778700 U_MOD1_N015071 WAIT AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U45         U_MOD1_ENZ U_MOD1_N16779778 U_MOD1_N16778812 OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U42         WAIT U_MOD1_N16778796 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
V_U_MOD1_V27         U_MOD1_N16778659 0 0.75
X_U_MOD1_D66         U_MOD1_N16778483 U_MOD1_NXX_111 d_d1 PARAMS: 
R_U_MOD1_UPCC_R18         U_MOD1_UPCC_N16798828 V5  500meg TC=0,0 
X_U_MOD1_UPCC_U50         U_MOD1_UPCC_N16790831 U_MOD1_UPCC_N16781361
+  U_MOD1_UPCC_N16780644 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_MOD1_UPCC_R13         GND DRV  200k  
X_U_MOD1_UPCC_U49         U_MOD1_UPCC_N16784328 U_MOD1_UPCC_N16794167
+  U_MOD1_UPCC_N16780426 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_D66         U_MOD1_UPCC_N16785964 U_MOD1_UPCC_N16779081 d_d1
+  PARAMS: 
X_U_MOD1_UPCC_U47         U_MOD1_UPCC_N16780644 U_MOD1_UPCC_N16786893
+  U_MOD1_UPCC_N16779501 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_MOD1_UPCC_R5         U_MOD1_UPCC_N16785964 U_MOD1_UPCC_N16779081  72.46e3  
C_U_MOD1_UPCC_C17         0 U_MOD1_UPCC_N16785964  1p  TC=0,0 
X_U_MOD1_UPCC_S8    U_MOD1_DR_Z 0 DRV GND PCC_CELL8_U_MOD1_UPCC_S8 
X_U_MOD1_UPCC_U40         EN_DLY U_MOD1_UPCC_N16786893 INV_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_U45         EN_DLY U_MOD1_UPCC_N16794167 INV_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_U13         U_MOD1_UPCC_N16794784 U_MOD1_UPCC_N16780426 FAULT_OC
+  N16794628 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_U_MOD1_UPCC_ABM1         U_MOD1_UPCC_N16815387 0 VALUE { {LIMIT((V(N755624) -
+  V(GND))*1, 0,10.50)}  
+ *1   }
X_U_MOD1_UPCC_U61         U_MOD1_UPCC_N16785964 U_MOD1_UPCC_N16778910
+  BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=30n
X_U_MOD1_UPCC_U56         CS_SH VC U_MOD1_UPCC_N16790831 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
R_U_MOD1_UPCC_R12         DRV U_MOD1_UPCC_N429302  40  
X_U_MOD1_UPCC_S15    U_MOD1_N16779705 0 U_MOD1_UPCC_N16798828 0
+  PCC_CELL8_U_MOD1_UPCC_S15 
E_U_MOD1_UPCC_E1         U_MOD1_UPCC_N16868329 GND U_MOD1_UPCC_N16815387 0 1
X_U_MOD1_UPCC_U43         U_MOD1_UPCC_N16782156 U_MOD1_UPCC_N16782718
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_U60         U_MOD1_UPCC_N16778910 U_MOD1_DR_Z INV_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_F2    U_MOD1_UPCC_N16868329 U_MOD1_UPCC_N427451 N755624 GND
+  PCC_CELL8_U_MOD1_UPCC_F2 
X_U_MOD1_UPCC_U62         U_MOD1_UPCC_N16782718 intermediate one_shot
+  PARAMS:  T=270



R_MOD_ONE_SHOT intermediate U_MOD1_UPCC_N16784328 1k
C_MOD_ONE_SHOT U_MOD1_UPCC_N16784328 0 1p





X_U_MOD1_UPCC_U42         U_MOD1_UPCC_N16782156 U_MOD1_UPCC_N16781361
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_U57         CS_SH U_MOD1_UPCC_N16812630 U_MOD1_UPCC_N16792247
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_UPCC_U58         U_MOD1_UPCC_N429302 U_MOD1_UPCC_N427451 d_d1 PARAMS:
E_U_MOD1_UPCC_ABM2         U_MOD1_UPCC_N16778037 0 VALUE {
+  (V(U_MOD1_UPCC_N16870446) * 5)/1    }
X_U_MOD1_UPCC_U48         U_MOD1_UPCC_N16784328 U_MOD1_DR_Z
+  U_MOD1_UPCC_N16782156 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_U52         U_MOD1_UPCC_N16792247 U_MOD1_UPCC_N16792266
+  U_MOD1_UPCC_N16794784 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_MOD1_UPCC_V34         U_MOD1_UPCC_N16812630 0 1.5
X_U_MOD1_UPCC_U44         U_MOD1_UPCC_N16780426 U_MOD1_UPCC_N16792266
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_U46         U_MOD1_UPCC_N16779081 U_MOD1_UPCC_N16778910
+  U_MOD1_UPCC_N16870446 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UPCC_U14         U_MOD1_ON_EDGE U_MOD1_UPCC_N16779501
+  U_MOD1_UPCC_N16779081 N16779692 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
G_U_MOD1_UPCC_ABM2I4         U_MOD1_UPCC_N427451 U_MOD1_UPCC_N429302 VALUE { 
+ {LIMIT((V(U_MOD1_UPCC_N16778037) - V(0))*15m, 0,30m)}    }
I_U_MOD1_I4         0 CS_SH DC 2e-6Adc  
R_U_MOD1_R6         U_MOD1_N16778942 U_MOD1_N16778865  72.46e3  
X_U_MOD1_U38         MINP U_MOD1_N16778468 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_U36         U_MOD1_DR_Z U_MOD1_N16778865 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_MOD1_S7    U_MOD1_N16778689 0 U_MOD1_N16778649 U_MOD1_N16778659
+  Modulator_MODIFIED_U_MOD1_S7 
X_U_MOD1_U48         LOWF LOWF LOW_PWR OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U_MOD1_UZD_C17         0 U_MOD1_UZD_N16692418  1p  TC=0,0 
X_U_MOD1_UZD_U7         EN_DLY U_MOD1_UZD_N416512 U_MOD1_UZD_N419465
+  AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
I_U_MOD1_UZD_I1         0 U_MOD1_UZD_N472888 DC 2.22uAdc  
V_U_MOD1_UZD_u_TIMER_V26         U_MOD1_UZD_u_TIMER_N00070 0 5
X_U_MOD1_UZD_u_TIMER_U46         U_MOD1_UZD_u_TIMER_N436855
+  U_MOD1_UZD_u_TIMER_N435973 U_MOD1_UZD_u_TIMER_N376887 OR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
V_U_MOD1_UZD_u_TIMER_V27         U_MOD1_UZD_u_TIMER_N377594 0 3
C_U_MOD1_UZD_u_TIMER_C2         0 U_MOD1_UZD_N472888  3.38p  TC=0,0 
X_U_MOD1_UZD_u_TIMER_U32         U_MOD1_UZD_N419975 U_MOD1_UZD_u_TIMER_N377086
+  U_MOD1_UZD_N408908 U_MOD1_UZD_u_TIMER_N00070 U_MOD1_UZD_u_TIMER_N376887 0
+  DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_u_TIMER_U42         U_MOD1_UZD_N419465 U_MOD1_UZD_u_TIMER_N435973
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_u_TIMER_U47         U_MOD1_UZD_N472888 U_MOD1_UZD_u_TIMER_N377594
+  U_MOD1_UZD_u_TIMER_N436855 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_UZD_u_TIMER_S13    U_MOD1_UZD_u_TIMER_N377086 0 U_MOD1_UZD_N472888 0
+  Timer_Cell_U_MOD1_UZD_u_TIMER_S13 
X_U_MOD1_UZD_U54         WAIT_EX U_MOD1_UZD_N16788418 INV_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U60         U_MOD1_UZD_N419975 U_MOD1_UZD_N420044 INV_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U15         U_MOD1_UZD_N430659 U_MOD1_UZD_N430659
+  U_MOD1_UZD_EN_DLY_Z U_MOD1_UZD_N447332 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U52         WAIT_EX U_MOD1_UZD_N416643 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U27         U_MOD1_UZD_N418289 U_MOD1_UZD_N430659
+  BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n
X_U_MOD1_UZD_U50         U_MOD1_UZD_N423909 U_MOD1_UZD_N416512 INV_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_MOD1_UZD_V26         U_MOD1_UZD_N418016 GND 0.02
X_U_MOD1_UZD_U33         ZCD_FIRST N408411 U_MOD1_UZD_N409026 U_MOD1_UZD_HI_5V
+  U_MOD1_UZD_N418495 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U61         0 U_MOD1_UZD_N408908 U_MOD1_UZD_N416643
+  U_MOD1_UZD_N420660 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U28         U_MOD1_UZD_N430659 U_MOD1_UZD_N430659
+  U_MOD1_UZD_EN_DLY_Z U_MOD1_UZD_N443772 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U4         U_MOD1_UZD_N409026 U_MOD1_VS_NEG BUF_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
R_U_MOD1_UZD_R5         U_MOD1_UZD_N16692418 EN_DLY  72.46e3  
X_U_MOD1_UZD_U13         TDM_START U_MOD1_UZD_N426972 U_MOD1_UZD_EN_DLY_Z
+  U_MOD1_UZD_N418495 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_D67         U_MOD1_UZD_N16786838 U_MOD1_UZD_HI_5V d_d1 PARAMS: 
X_U_MOD1_UZD_U12         U_MOD1_UZD_N16692418 U_MOD1_UZD_N16692574
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U39         U_MOD1_DR_Z U_MOD1_UZD_N426972 INV_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U19         U_MOD1_UZD_N16692574 U_MOD1_UZD_N432893 INV_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U34         U_MOD1_UZD_N423618 N408528 U_MOD1_UZD_N430044
+  U_MOD1_UZD_HI_5V U_MOD1_UZD_N430534 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U37         U_MOD1_UZD_N420735 N408936 U_MOD1_UZD_N420044
+  U_MOD1_UZD_N408908 U_MOD1_UZD_N447332 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_UTDM_U47         U_MOD1_UZD_UTDM_N432243 VCX5
+  U_MOD1_UZD_UTDM_N432126 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_UZD_UTDM_U41         TDM_START U_MOD1_UZD_UTDM_N430977
+  U_MOD1_UZD_N448059 U_MOD1_UZD_UTDM_HI_5V U_MOD1_UZD_UTDM_N430747 0
+  DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
I_U_MOD1_UZD_UTDM_I4         0 U_MOD1_UZD_UTDM_N432243 DC 2.534u  
C_U_MOD1_UZD_UTDM_C1         0 U_MOD1_UZD_UTDM_N432243  2.08p  TC=0,0 
V_U_MOD1_UZD_UTDM_V25         U_MOD1_UZD_UTDM_HI_5V 0 5
X_U_MOD1_UZD_UTDM_U46         U_MOD1_UZD_UTDM_N432126 U_MOD1_UZD_UTDM_N431317
+  U_MOD1_UZD_UTDM_N430747 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_UTDM_S13    U_MOD1_UZD_UTDM_N430977 0 U_MOD1_UZD_UTDM_N432243 0
+  TDM_U_MOD1_UZD_UTDM_S13 
X_U_MOD1_UZD_UTDM_U40         EN_DLY U_MOD1_UZD_UTDM_N431317 INV_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U67         EN_DLY U_MOD1_UZD_EN_DLY_Z INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
V_U_MOD1_UZD_V25         U_MOD1_UZD_HI_5V 0 5
X_U_MOD1_UZD_D66         U_MOD1_UZD_N16692418 EN_DLY d_d1 PARAMS: 
X_U_MOD1_UZD_U14         U_MOD1_UZD_N423909 U_MOD1_UZD_N424373 U_MOD1_ON_EDGE
+  N424988 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_UZD_U16         U_MOD1_UZD_N430659 U_MOD1_UZD_N430659 WAIT_EX
+  U_MOD1_UZD_EN_DLY_Z U_MOD1_UZD_N430534 OR4_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U40         U_MOD1_DR_Z U_MOD1_UZD_CLK_1 BUF_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_UZD_U45         U_MOD1_UZD_N409026 U_MOD1_UZD_N426305 INV_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U66         U_MOD1_UZD_N426972 TDM_START N755514 MINP
+  U_MOD1_UZD_N418289 OR4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
I_U_MOD1_UZD_I2         0 U_MOD1_UZD_N16786838 DC 2.22uAdc  
X_U_MOD1_UZD_U53         U_MOD1_UZD_N420660 U_MOD1_UZD_N420735
+  U_MOD1_UZD_N420735 U_MOD1_UZD_N423067 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U36         U_MOD1_UZD_N426523 N408791 U_MOD1_UZD_CLK_1
+  U_MOD1_UZD_HI_5V TDM_START 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U9         U_MOD1_UZD_N423713 N408655 U_MOD1_UZD_N432893
+  U_MOD1_UZD_HI_5V U_MOD1_UZD_N443772 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U18         U_MOD1_UZD_N423067 U_MOD1_UZD_N423618
+  U_MOD1_UZD_N423713 U_MOD1_UZD_N423909 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U48         U_MOD1_UZD_N430659 U_MOD1_UZD_N416307 INV_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_U6         U_MOD1_ZCD_FIRST_DLY U_MOD1_UZD_N416307
+  U_MOD1_UZD_N408908 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_UZD_S9    U_MOD1_UZD_N16788418 0 U_MOD1_UZD_N16786838
+  U_MOD1_UZD_N472888 ZCD_U_MOD1_UZD_S9 
X_U_MOD1_UZD_U38         U_MOD1_UZD_N418016 VS U_MOD1_UZD_N409026
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_UZD_U17         U_MOD1_UZD_N409026 U_MOD1_UZD_N430044
+  BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=25n
X_U_MOD1_UZD_U26         U_MOD1_UZD_N426972 U_MOD1_UZD_N426972
+  U_MOD1_UZD_EN_DLY_Z U_MOD1_UZD_N424373 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_MOD1_UZD_U51         U_MOD1_UZD_N426305 U_MOD1_UZD_N426523
+  U_MOD1_UZD_N448059 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U13         ZCD_FIRST U_MOD1_ENZ U_MOD1_N16779778 N16779782
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_U51         EN U_MOD1_N16778796 U_MOD1_N16779705 AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U35         FAULT_CS N16778834 U_MOD1_N16778468 U_MOD1_N16778942
+  U_MOD1_N16778812 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U41         U_MOD1_N16778700 N16779776 ZCD_FIRST LOWF U_MOD1_N16778503
+  0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U49         U_MOD1_ON_EDGE U_MOD1_ENZ U_MOD1_N16778464 OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U_MOD1_C17         0 U_MOD1_NXX_111  1p  TC=0,0 
X_U_MOD1_U57         MINP EN U_MOD1_N16778544 U_MOD1_N16778503 NAND3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
I_U_MOD1_I3         U_MOD1_N16778558 0 DC 2e-6Adc  
X_U_MOD1_U14         U_MOD1_N16778464 WAIT N16778398 WAIT_EX
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_U54         U_MOD1_N16778562 CS_SH d_d1 PARAMS:
X_U_MOD1_U46         U_MOD1_ENZ N755552 U_MOD1_N16778674 OR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U34         N16778978 FAULT_LLgen U_MOD1_DR_Z U_MOD1_NXX_111 0 U_MOD1_ENZ
+  DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3



X_U_MOD1_U51maskand FAULT_LLgen maskgen FAULT_LL AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3

vmaskgen maskgen 0 PULSE 0 1 {{VDD_PULSE_DELAY}*1.05} 1u 1u 1 2






X_U_MOD1_U50         ZCD_FIRST U_MOD1_NUQ_0 U_MOD1_NO_SMPL AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U15         ZCD_FIRST N755552 U_MOD1_N05559 N05884
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U_MOD1_V30         U_MOD1_N16778558 U_MOD1_N16778562 0.000
X_U_MOD1_F2    U_MOD1_N16778536 U_MOD1_N16778919 0 U_MOD1_N16778558
+  Modulator_MODIFIED_U_MOD1_F2 
X_U_MOD1_U39         U_MOD1_NUQ_0 N16779700 TDM_START U_MOD1_N16778749
+  U_MOD1_N16778674 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_D67         U_MOD1_N16778865 U_MOD1_N16778942 d_d1 PARAMS: 
X_U_MOD1_U58         ZCD_FIRST U_MOD1_ZCD_FIRST_DLY BUF_DELAY_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5 DELAY=20n
X_U_MOD1_U53         U_MOD1_N16778420 U_MOD1_N16778649 U_MOD1_N16778483
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_MOD1_U56         U_MOD1_N007711 VS d_d1 PARAMS:
X_U_MOD1_U44         N755552 U_MOD1_N015071 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U_MOD1_U_MINP_C17         0 U_MOD1_U_MINP_N16773613  1p  TC=0,0 
X_U_MOD1_U_MINP_U52         U_MOD1_U_MINP_N16772883 U_MOD1_U_MINP_N16773089
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_MOD1_U_MINP_R5         U_MOD1_U_MINP_N16773613 U_MOD1_U_MINP_N16773519 
+  72.46e3  
X_U_MOD1_U_MINP_U57         U_MOD1_U_MINP_N16773457 U_MOD1_U_MINP_N16773495
+  U_MOD1_U_MINP_N16773519 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U_MOD1_U_MINP_V35         U_MOD1_U_MINP_N16773495 0 4
X_U_MOD1_U_MINP_U86         EN U_MOD1_U_MINP_N16773089 U_MOD1_U_MINP_N16773395
+  NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
G_U_MOD1_U_MINP_G1         U_MOD1_U_MINP_N16788329 U_MOD1_U_MINP_N16773457
+  U_MOD1_U_MINP_N16787626 0 1e-6
X_U_MOD1_U_MINP_U69         U_MOD1_NO_SMPL WAKE_L U_MOD1_U_MINP_N16787552
+  OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U_MOD1_U_MINP_C1         0 U_MOD1_U_MINP_N16773457  7p  TC=0,0 
X_U_MOD1_U_MINP_U9         U_MOD1_U_MINP_N16773613 U_MOD1_U_MINP_N16773657
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U_MINP_U56         U_MOD1_U_MINP_N16773413 U_MOD1_U_MINP_N16772883
+  U_MOD1_U_MINP_N16772883 U_MOD1_U_MINP_N16773447 OR3_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_MOD1_U_MINP_U41         U_MOD1_U_MINP_N16773409 U_MOD1_U_MINP_N16773413
+  U_MOD1_N16778865 U_MOD1_U_MINP_HI U_MOD1_U_MINP_N16773395 0 DFFSR_RHPBASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U_MINP_U46         U_MOD1_U_MINP_N16773409 U_MOD1_U_MINP_N16772883
+  MINP OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_MOD1_U_MINP_D66         U_MOD1_U_MINP_N16773519 U_MOD1_U_MINP_N16773613
+  d_d1 PARAMS: 
V_U_MOD1_U_MINP_V34         U_MOD1_U_MINP_HI 0 5
E_U_MOD1_U_MINP_ABM2         U_MOD1_U_MINP_N16787626 0 VALUE { (IF 
+  (V(U_MOD1_U_MINP_N16787552)>0.3,  6*V(N754888), V(N754888)))    }
X_U_MOD1_U_MINP_U12         U_MOD1_U_MINP_N16773657 U_MOD1_U_MINP_N16772883
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_MOD1_U_MINP_V36         U_MOD1_U_MINP_N16788329 0 4
X_U_MOD1_U_MINP_S8    U_MOD1_U_MINP_N16773447 0 U_MOD1_U_MINP_N16773457 0
+  MINP_Range_MODIFIED_U_MOD1_U_MINP_S8 
X_U_MOD1_U59         ZCD_FIRST U_MOD1_N05559 CL_CLK AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
V_U_MOD1_V33         U_MOD1_N16778749 0 5
X_U_PM_U41         U_PM_N16848059 U_PM_N16848059 U_PM_N16848139 OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_U34         V5 U_PM_N16848891 U_PM_N16848036 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
R_U_PM_R15         U_PM_N16848898 U_PM_N16848864  1k TC=0,0 
X_U_PM_U76         U_PM_N16864238 U_PM_N16848291 INV_DELAY_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5 DELAY=100n
X_U_PM_U64         U_PM_N16848036 U_PM_N16848192 U_PM_N16848044 U_PM_N16848385
+  AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_F3    U_PM_N16848572 U_PM_N16848643 N755924 0 PWR_mgnt_U_PM_F3 
R_U_PM_R4         U_PM_N16848383 U_PM_N16848385  14.5e6  
X_U_PM_U10         U_PM_VDD_ON U_PM_N16848600 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
R_U_PM_R17         V5 U_PM_N16848870  100m TC=0,0 
X_U_PM_U13         U_PM_N16848064 U_PM_N16848576 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
R_U_PM_R22         U_PM_N16848572 U_PM_N16848053  2.5meg TC=0,0 
X_U_PM_U22         RTRY_LOFFZ U_PM_RTRY_LOFF_LATCHD BUF_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
X_U_PM_U7         U_PM_N16848482 EN_DLY INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_PM_U33         U_PM_N16848539 V4 U_PM_N16848064 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U_PM_S8    U_PM_N16848600 0 U_PM_N16848518 U_PM_N16848602 PWR_mgnt_U_PM_S8 
X_U_PM_U25         U_PM_CCUV_LTCH U_PM_N16848055 U_PM_N16849585 AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_S9    U_PM_N16848933 0 U_PM_N16848898 0 PWR_mgnt_U_PM_S9 
X_U_PM_U6         U_PM_N16848383 U_PM_N16848482 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_PM_D86         U_PM_N16848673 U_PM_N16848602 d_d1 PARAMS: 
R_U_PM_R12         U_PM_N16848539 N755924  2.28meg TC=0,0 
X_U_PM_U24         U_PM_RTRY_LOFF_LATCHD U_PM_N16848055 INV_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_U12         U_PM_N16848562 U_PM_N16848576 U_PM_VDD_ON U_PM_N16848566
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_PM_U11         U_PM_VDD_ON U_PM_N16848933 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_PM_U27         U_PM_N16848709 N16848707 U_PM_N16848120 U_PM_N16848704
+  U_PM_N16848508 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_D85         U_PM_N16848864 U_PM_N16848306 d_d1 PARAMS: 
X_U_PM_U23         U_PM_RTRY_LOFF_LATCHD U_PM_CCUV_LTCH U_PM_N16848066
+  AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_U28         FAULT_CS U_PM_N16848709 U_PM_N16848592 OR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_U8         U_PM_CCUV_LTCH U_PM_N16848044 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_PM_S10    U_PM_N16849585 0 U_PM_N16848643 0 PWR_mgnt_U_PM_S10 
R_U_PM_R18         0 V4  400k TC=0,0 
R_U_PM_R20         V4P6 V5  40k TC=0,0 
R_U_PM_R19         V4 V4P6  60k TC=0,0 
X_U_PM_U16         U_PM_N16848385 EN BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
X_U_PM_U17         U_PM_N16848147 U_PM_N16848139 U_PM_CCUV_LTCH U_PM_N16864238
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
C_U_PM_C10         0 U_PM_N16848864  500f IC=0 TC=0,0 
X_U_PM_U14         U_PM_N16848592 U_PM_N16848566 N16848691 U_PM_N16848192
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U_PM_V28         U_PM_N16848891 0  
+PWL 0 4.5 10u 4.5 10.1u 4.5 
X_U_PM_U36         U_PM_N16848398 N16848377 U_PM_VDD_ON U_PM_N16848420
+  U_PM_N16848365 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_PM_R14         0 U_PM_N16848562  5meg TC=0,0 
X_U_PM_U32         U_PM_N16848161 N16848137 U_PM_N16848120 U_PM_N16848178
+  U_PM_N16848124 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U_PM_C16         0 U_PM_N16848383  1p  TC=0,0 
V_U_PM_V26         U_PM_N16848539 U_PM_N16848673 21
I_U_PM_I1         0 U_PM_N16848864 DC 1uAdc  
X_U_PM_U38         U_PM_N16848403 N16848401 U_PM_VDD_ON U_PM_N16848398
+  U_PM_N16848365 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_F1    U_PM_N16848866 U_PM_N16848870 N755924 0 PWR_mgnt_U_PM_F1 
X_U_PM_U35         U_PM_N16848147 N16848164 U_PM_N16848120 U_PM_N16848161
+  U_PM_N16848124 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_PM_R16         0 V5  1.2meg TC=0,0 
X_U_PM_U31         FAULT_OV FAULT_LL FAULT_OC U_PM_N16848038 OR3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_D65         U_PM_N16848383 U_PM_N16848385 d_d1 PARAMS: 
X_U_PM_U39         U_PM_N16848420 U_PM_N16848365 U_PM_VDD_ON U_PM_N16848066
+  U_PM_N16848336 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_PM_R21         U_PM_N16848965 N755924  40meg TC=0,0 
X_U_PM_U37         U_PM_N16848178 U_PM_N16848124 U_PM_N16848120 FAULT_CCUV
+  U_PM_N16848139 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_PM_V25         U_PM_N16848306 0 5
E_U_PM_E1         U_PM_N16848866 0 U_PM_N16848864 0 1
V_U_PM_V27         U_PM_N16848965 U_PM_N16848976 7.7
E_U_PM_E2         U_PM_N16848053 0 U_PM_N16848965 0 770m
X_U_PM_U29         U_PM_N16848704 N16848533 U_PM_N16848120 U_PM_N16848730
+  U_PM_N16848508 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_U40         U_PM_N16848059 N16848744 U_PM_VDD_ON U_PM_N16848403
+  U_PM_N16848365 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_D87         U_PM_N16848976 0 d_d1 PARAMS: 
X_U_PM_U30         U_PM_N16848730 U_PM_N16848508 U_PM_N16848120 U_PM_N16848038
+  U_PM_N16848566 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_PM_U15         ZCD_FIRST U_PM_N16848120 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
X_U_PM_U63         U_PM_N16848291 U_PM_N16848336 one_shot PARAMS:  T=50
R_U_PM_R13         U_PM_N16848518 U_PM_N16848539  2.5meg TC=0,0 
X_U_PM_F2    U_PM_N16848602 0 0 U_PM_N16848562 PWR_mgnt_U_PM_F2 
X_U75         LR N16803687 LR_MINP N16810377 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
R_R9         0 NTC_SU  100meg TC=0,0 
X_U_SAMPLER_D88         U_SAMPLER_N16850829 U_SAMPLER_N167531850 d_d1 PARAMS: 
V_U_SAMPLER_U_op1_V5         U_SAMPLER_U_op1_N16693585 0 4.86Vdc
X_U_SAMPLER_U_op1_D63         U_SAMPLER_N2 U_SAMPLER_U_op1_N16693585 d_d1
+  PARAMS: 
E_U_SAMPLER_U_op1_E2         U_SAMPLER_U_op1_N16693617 0 U_SAMPLER_N4
+  U_SAMPLER_N1 10000
V_U_SAMPLER_U_op1_V6         U_SAMPLER_U_op1_N16693863 0 0.14Vdc
G_U_SAMPLER_U_op1_G1         0 U_SAMPLER_N2 U_SAMPLER_U_op1_N16693617 0 1m
R_U_SAMPLER_U_op1_R1         0 U_SAMPLER_N2  1k TC=0,0 
X_U_SAMPLER_U_op1_D64         U_SAMPLER_U_op1_N16693863 U_SAMPLER_N2 d_d1
+  PARAMS: 
X_U_SAMPLER_U1         EN_DLY U_SAMPLER_ENB INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_SAMPLER_S12    U_SAMPLER_WEZ 0 N755066 U_SAMPLER_N16862928
+  Sampler_U_SAMPLER_S12 
X_U_SAMPLER_U27         U_SAMPLER_N263355 U_SAMPLER_N260427 U_SAMPLER_N262375
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U_SAMPLER_R23         U_SAMPLER_N16795041 U_SAMPLER_N16790957  24.7k TC=0,0 
V_U_SAMPLER_V27         U_SAMPLER_N7 U_SAMPLER_N4 0.16Vdc
E_U_SAMPLER_E20         U_SAMPLER_N16782070 0 U_SAMPLER_N457025 0 1
X_U_SAMPLER_U28         U_SAMPLER_N16911773 U_SAMPLER_N16978808
+  U_SAMPLER_N16932844 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_SAMPLER_U66         U_SAMPLER_N16812037 U_SAMPLER_ZCURZ INV_DELAY_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=2N
X_U_SAMPLER_S8    U_SAMPLER_N259767 0 U_SAMPLER_N1 U_SAMPLER_N2
+  Sampler_U_SAMPLER_S8 
R_U_SAMPLER_R22         U_SAMPLER_N16782070 U_SAMPLER_N16795041  60.3k TC=0,0 
X_U_SAMPLER_U63         U_SAMPLER_N17006357 U_SAMPLER_N17008274 one_shot
+  PARAMS:  T=600
R_U_SAMPLER_R10         U_SAMPLER_N16832445 N755066  1.25meg TC=0,0 
R_U_SAMPLER_R15         U_SAMPLER_V4P0 V4  40k TC=0,0 
V_U_SAMPLER_V26         U_SAMPLER_N4 U_SAMPLER_N261871 0.16Vdc
X_U_SAMPLER_U62         U_SAMPLER_N802933 U_SAMPLER_N449859 one_shot PARAMS: 
+  T=300
X_U_SAMPLER_U13         TDM_START U_SAMPLER_N262793 N755552 U_SAMPLER_N259299
+  OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_U67         U_SAMPLER_N16846437 N16821672 N755552
+  U_SAMPLER_CCUV_COMP U_SAMPLER_N16845824 0 DFFSR_SHPBASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_SAMPLER_S6    U_SAMPLER_N16812037 0 U_SAMPLER_N16812576 NC
+  Sampler_U_SAMPLER_S6 
E_U_SAMPLER_E18         N755066 U_SAMPLER_N16825269 U_SAMPLER_N16825288 0 1
X_U_SAMPLER_D86         U_SAMPLER_N3 U_SAMPLER_N17076650 d_d1 PARAMS: 
R_U_SAMPLER_R12         LEAVE_FLOAT U_SAMPLER_M0  0.13k TC=0,0 
V_U_SAMPLER_V42         U_SAMPLER_N17075511 U_SAMPLER_N2 0.8
X_U_SAMPLER_S16    U_SAMPLER_N16812037 0 U_SAMPLER_N16893982
+  U_SAMPLER_N16869490 Sampler_U_SAMPLER_S16 
X_U_SAMPLER_S18    U_SAMPLER_N16812037 0 U_SAMPLER_N16832445
+  U_SAMPLER_N16893982 Sampler_U_SAMPLER_S18 
V_U_SAMPLER_U_AMP1_V5         U_SAMPLER_U_AMP1_N16693585 0 4.86Vdc
X_U_SAMPLER_U_AMP1_D63         VLC U_SAMPLER_U_AMP1_N16693585 d_d1 PARAMS: 
E_U_SAMPLER_U_AMP1_E2         U_SAMPLER_U_AMP1_N16693617 0 U_SAMPLER_N16893982
+  VLC 10000
V_U_SAMPLER_U_AMP1_V6         U_SAMPLER_U_AMP1_N16693863 0 0.14Vdc
G_U_SAMPLER_U_AMP1_G1         0 VLC U_SAMPLER_U_AMP1_N16693617 0 1m
R_U_SAMPLER_U_AMP1_R1         0 VLC  1k TC=0,0 
X_U_SAMPLER_U_AMP1_D64         U_SAMPLER_U_AMP1_N16693863 VLC d_d1 PARAMS: 
X_U_SAMPLER_U12         U_SAMPLER_N262375 U_SAMPLER_N259299 U_SAMPLER_ARMED
+  N261463 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_SAMPLER_U15         U_SAMPLER_ENB LOW_PWR U_SAMPLER_N16845824 OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_U5         U_SAMPLER_N259813 U_SAMPLER_N259937 TDM_START
+  U_SAMPLER_N263517 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_S2    U_SAMPLER_N259767 0 U_SAMPLER_N3 U_SAMPLER_N5
+  Sampler_U_SAMPLER_S2 
C_U_SAMPLER_C4         U_SAMPLER_N1 U_SAMPLER_N2  500f  TC=0,0 
X_U_SAMPLER_S14    U_SAMPLER_ENB 0 U_SAMPLER_N259041 0 Sampler_U_SAMPLER_S14 
V_U_SAMPLER_V46         U_SAMPLER_N16978808 0 1.4
E_U_SAMPLER_E19         U_SAMPLER_N16809688 0 U_SAMPLER_N457025 0 1
X_U_SAMPLER_U68         TDM_START U_SAMPLER_N259767 one_shot PARAMS:  T=370
X_U_SAMPLER_U26         CC_UV_TH U_SAMPLER_N16831051 U_SAMPLER_CCUV_COMP
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U_SAMPLER_V30         U_SAMPLER_N263355 U_SAMPLER_N635836 0.0
C_U_SAMPLER_C18         0 U_SAMPLER_N16911773  250f  TC=0,0 
V_U_SAMPLER_V41         U_SAMPLER_N167531850 N755066 1.2
X_U_SAMPLER_U65         ZCD_FIRST N755552 U_SAMPLER_ENB U_SAMPLER_N16802707
+  OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_D90         N755066 U_SAMPLER_N16838428 d_d1 PARAMS: 
X_U_SAMPLER_D87         U_SAMPLER_N5 U_SAMPLER_N17076682 d_d1 PARAMS: 
X_U_SAMPLER_U38         U_SAMPLER_CCUV_BLANK U_SAMPLER_N16846437 FAULT_CCUV
+  AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_SAMPLER_R6         U_SAMPLER_N2 U_SAMPLER_N1  600k TC=0,0 
X_U_SAMPLER_U36         FAULT_OV N16820363 N755552 U_SAMPLER_N16817931
+  U_SAMPLER_ENB 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_U29         U_SAMPLER_WE U_SAMPLER_WEZ INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_SAMPLER_D85         U_SAMPLER_N1 U_SAMPLER_N17075511 d_d1 PARAMS: 
X_U_SAMPLER_S19    LOW_PWR 0 0 U_SAMPLER_N16778800 Sampler_U_SAMPLER_S19 
X_U_SAMPLER_S4    U_SAMPLER_ARMED_P 0 U_SAMPLER_N259989 U_SAMPLER_N6
+  Sampler_U_SAMPLER_S4 
R_U_SAMPLER_R20         U_SAMPLER_N16874968 U_SAMPLER_N16862928  10k TC=0,0 
X_U_SAMPLER_U8         TDM_START U_SAMPLER_N16802707 N17037951
+  U_SAMPLER_N262793 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U_SAMPLER_R19         VLC U_SAMPLER_N16877262  100 TC=0,0 
V_U_SAMPLER_V47         U_SAMPLER_N16778803 0 5
R_U_SAMPLER_R21         U_SAMPLER_N16831051 VS_SH  100k TC=0,0 
X_U_SAMPLER_U24         U_SAMPLER_N5 U_SAMPLER_N7 U_SAMPLER_N259937
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_SAMPLER_U21         U_SAMPLER_N17015585 WAIT_EX U_SAMPLER_WE AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_U7         U_SAMPLER_N264183 U_SAMPLER_N259299 U_SAMPLER_N802933
+  N259805 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U_SAMPLER_R16         U_SAMPLER_N16852540 U_SAMPLER_N16850829  60k TC=0,0 
R_U_SAMPLER_R18         U_SAMPLER_N16778800 U_SAMPLER_N16778803  20Meg TC=0,0 
V_U_SAMPLER_V44         U_SAMPLER_N17071280 U_SAMPLER_N1 0.8
V_U_SAMPLER_V460         U_SAMPLER_N16838428 U_SAMPLER_N16834775 0.7
X_U_SAMPLER_D89         N755066 U_SAMPLER_N16838428 d_d1 PARAMS: 
C_U_SAMPLER_C15         0 U_SAMPLER_N16831051  1p IC=0 TC=0,0 
V_U_SAMPLER_V39         U_SAMPLER_N16825269 0 2.5
C_U_SAMPLER_C12         0 U_SAMPLER_N16893982  4p IC=0 TC=0,0 
V_U_SAMPLER_V29         U_SAMPLER_N260427 0 2
X_U_SAMPLER_U14         LOW_PWR U_SAMPLER_N802933 U_SAMPLER_N17006357
+  AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_U_SAMPLER_R17         U_SAMPLER_N16832445 U_SAMPLER_N16852540  150k TC=0,0 
V_U_SAMPLER_V45         U_SAMPLER_N17076682 U_SAMPLER_N3 0.8
X_U_SAMPLER_S11    U_SAMPLER_N16869490 U_SAMPLER_N16874968 U_SAMPLER_N16875431
+  U_SAMPLER_N16874968 Sampler_U_SAMPLER_S11 
V_U_SAMPLER_V43         U_SAMPLER_N17076650 U_SAMPLER_N5 0.8
X_U_SAMPLER_S15    U_SAMPLER_ARMED_N 0 U_SAMPLER_N259041 U_SAMPLER_N457025
+  Sampler_U_SAMPLER_S15 
E_U_SAMPLER_ABM4         U_SAMPLER_M0 0 VALUE { {LIMIT((V(VS_SH) - V(0))*1,
+  3.75,5)}  
+ *1   }
C_U_SAMPLER_C16         U_SAMPLER_N16801608 0  1p  TC=0,0 
X_U_SAMPLER_S17    U_SAMPLER_WE 0 U_SAMPLER_N16874968 U_SAMPLER_N16877262
+  Sampler_U_SAMPLER_S17 
R_U_SAMPLER_R26         U_SAMPLER_N16804396 U_SAMPLER_N16790957  75k TC=0,0 
X_U_SAMPLER_U34         U_SAMPLER_N16804396 U_SAMPLER_V4P0 U_SAMPLER_N16817931
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_SAMPLER_U33         U_SAMPLER_N16801608 U_SAMPLER_V4P0 U_SAMPLER_N16811867
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U_SAMPLER_D84         U_SAMPLER_N2 U_SAMPLER_N17071280 d_d1 PARAMS: 
X_U_SAMPLER_U32         U_SAMPLER_W U_SAMPLER_WZ INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
C_U_SAMPLER_C14         0 NC  5p IC=0 TC=0,0 
X_U_SAMPLER_F1    U_SAMPLER_N16869490 U_SAMPLER_N16869027 U_SAMPLER_N16869490
+  U_SAMPLER_N16875431 Sampler_U_SAMPLER_F1 
X_U_SAMPLER_U64         U_SAMPLER_N16980500 N755552 U_SAMPLER_ENB
+  U_SAMPLER_N16812037 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_S7    U_SAMPLER_ZCURZ 0 U_SAMPLER_N16869490 U_SAMPLER_N16877262
+  Sampler_U_SAMPLER_S7 
R_U_SAMPLER_R25         U_SAMPLER_N16801608 U_SAMPLER_N16795041  75k TC=0,0 
X_U_SAMPLER_U22         N755552 U_SAMPLER_N17015585 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_SAMPLER_S3    U_SAMPLER_ARMED_N 0 U_SAMPLER_N261871 U_SAMPLER_N6
+  Sampler_U_SAMPLER_S3 
X_U_SAMPLER_S5    U_SAMPLER_N263517 0 U_SAMPLER_N263355 0 Sampler_U_SAMPLER_S5 
X_U_SAMPLER_U31         U_SAMPLER_N17022924 WAIT U_SAMPLER_W AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
I_U_SAMPLER_I4         U_SAMPLER_N16902939 U_SAMPLER_N16902945 DC 0.208e-3Adc  
X_U_SAMPLER_U35         VHI N16819089 N755552 U_SAMPLER_N16811867 U_SAMPLER_ENB
+  0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_U23         U_SAMPLER_N6 U_SAMPLER_N5 U_SAMPLER_N259813
+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U_SAMPLER_R14         U_SAMPLER_N16812576 U_SAMPLER_N16809688  100 TC=0,0 
X_U_SAMPLER_U74         U_SAMPLER_N16902945 U_SAMPLER_N16902939 d_d1 PARAMS:
E_U_SAMPLER_ABM1         U_SAMPLER_N0 0 VALUE { {LIMIT((V(VS_SH) - V(0))*1,
+  0.7,5.5)}  
+ *1   }
V_U_SAMPLER_V25         U_SAMPLER_N4 U_SAMPLER_N259989 0.28Vdc
I_U_SAMPLER_I1         0 U_SAMPLER_N263355 DC 1e-5Adc  
V_U_SAMPLER_U_Delay_V39         U_SAMPLER_U_Delay_N00130 0 2.5
X_U_SAMPLER_U_Delay_S4    U_SAMPLER_U_Delay_N16753847 0
+  U_SAMPLER_U_Delay_N00094 0 Delay_Analog_U_SAMPLER_U_Delay_S4 
X_U_SAMPLER_U_Delay_U26         U_SAMPLER_U_Delay_N00094
+  U_SAMPLER_U_Delay_N00130 U_SAMPLER_CCUV_BLANK COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
C_U_SAMPLER_U_Delay_C15         0 U_SAMPLER_U_Delay_N00094  10u IC=0 TC=0,0 
X_U_SAMPLER_U_Delay_U40         U_SAMPLER_N16846437 U_SAMPLER_U_Delay_N16753847
+  INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_U_Delay_S5    U_SAMPLER_N16846437 0 U_SAMPLER_N16902945
+  U_SAMPLER_U_Delay_N00094 Delay_Analog_U_SAMPLER_U_Delay_S5 
X_U_SAMPLER_S13    U_SAMPLER_ARMED_P 0 U_SAMPLER_N260033 U_SAMPLER_N259041
+  Sampler_U_SAMPLER_S13 
E_U_SAMPLER_ABM2         U_SAMPLER_N16825288 0 VALUE { 
+ {LIMIT((V(U_SAMPLER_V4P0) - V(U_SAMPLER_N457025))*62.5, -2.5,2.5)}  
+ *1   }
R_U_SAMPLER_R13         U_SAMPLER_N260033 LEAVE_FLOAT  0.3325k TC=0,0 
C_U_SAMPLER_C6         U_SAMPLER_N3 U_SAMPLER_N5  500f  TC=0,0 
X_U_SAMPLER_D72         U_SAMPLER_N635836 U_SAMPLER_N260427 d_d1 PARAMS: 
C_U_SAMPLER_C17         U_SAMPLER_N16804396 0  1p  TC=0,0 
R_U_SAMPLER_R7         U_SAMPLER_N5 U_SAMPLER_N3  600k TC=0,0 
V_U_SAMPLER_U_op2_V5         U_SAMPLER_U_op2_N16693585 0 4.86Vdc
X_U_SAMPLER_U_op2_D63         U_SAMPLER_N5 U_SAMPLER_U_op2_N16693585 d_d1
+  PARAMS: 
E_U_SAMPLER_U_op2_E2         U_SAMPLER_U_op2_N16693617 0 U_SAMPLER_N4
+  U_SAMPLER_N3 10000
V_U_SAMPLER_U_op2_V6         U_SAMPLER_U_op2_N16693863 0 0.14Vdc
G_U_SAMPLER_U_op2_G1         0 U_SAMPLER_N5 U_SAMPLER_U_op2_N16693617 0 1m
R_U_SAMPLER_U_op2_R1         0 U_SAMPLER_N5  1k TC=0,0 
X_U_SAMPLER_U_op2_D64         U_SAMPLER_U_op2_N16693863 U_SAMPLER_N5 d_d1
+  PARAMS: 
C_U_SAMPLER_C13         0 U_SAMPLER_N457025  20000f IC=0 TC=0,0 
V_U_SAMPLER_V23         U_SAMPLER_N4 0 1.6Vdc
C_U_SAMPLER_C5         U_SAMPLER_N2 U_SAMPLER_N3  1p  TC=0,0 
C_U_SAMPLER_C11         U_SAMPLER_N16869027 U_SAMPLER_N16874968  330f IC=0
+  TC=0,0 
V_U_SAMPLER_V40         U_SAMPLER_N16902939 0 20
C_U_SAMPLER_C7         0 U_SAMPLER_N263355  1p  TC=0,0 
X_U_SAMPLER_U10         U_SAMPLER_ARMED U_SAMPLER_ARMED_P BUF_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U_SAMPLER_U9         U_SAMPLER_ARMED U_SAMPLER_N259813 U_SAMPLER_N264183
+  AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_U30         N755552 U_SAMPLER_N17022924 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
C_U_SAMPLER_C1         U_SAMPLER_N0 U_SAMPLER_N1  1p  TC=0,0 
X_U_SAMPLER_U6         U_SAMPLER_N17008274 U_SAMPLER_N17008274
+  U_SAMPLER_N449859 N755552 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_SAMPLER_D91         U_SAMPLER_N16875431 U_SAMPLER_N16869490 d_d1 PARAMS: 
X_U_SAMPLER_U11         U_SAMPLER_ARMED U_SAMPLER_ARMED_N INV_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
C_U_SAMPLER_C10         U_SAMPLER_N259041 0  400p IC=0 TC=0,0 
R_U_SAMPLER_R11         U_SAMPLER_N16832445 U_SAMPLER_N16834775  7.5k TC=0,0 
X_U_SAMPLER_U25         VOH U_SAMPLER_N16980500 TDM_START_INV U_SAMPLER_N16932844
+  U_SAMPLER_ENB 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3



X_U_SAMPLER_INVERTER TDM_START TDM_START_INV INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3


R_U_SAMPLER_R24         U_SAMPLER_N16790957 0  500k TC=0,0 
R_U_SAMPLER_R27         U_SAMPLER_N16911773 VS_SH  400k TC=0,0 
X_U3         LOWF N16800594 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U1         EN N754980 EN_WZ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_R6         N754888 N754894  0.1m TC=0,0 
V_U_Delay_V39         U_Delay_N00130 0 2.5
X_U_Delay_S4    U_Delay_N16753847 0 U_Delay_N00094 0 Delay_Analog_U_Delay_S4 
X_U_Delay_U26         U_Delay_N00094 U_Delay_N00130 VORH_DLY COMP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
C_U_Delay_C15         0 U_Delay_N00094  10u IC=0 TC=0,0 
X_U_Delay_U40         VORH U_Delay_N16753847 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_Delay_S5    VORH 0 N16778102 U_Delay_N00094 Delay_Analog_U_Delay_S5 
X_U42         VHI VORH_DLY LR OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
R_R3         0 V5  150k TC=0,0 
I_I4         N16778096 N16778102 DC 100e-6Adc  
E_E1         VDD_SH 0 VDD GND 1
X_U74         N16778102 N16778096 d_d1 PARAMS:
X_U2         WAIT N754980 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_V40         N16778096 0 20
X_U30         N16803687 N16800584 N16800594 HI N16806075 0 DFFSR_RHPBASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U_CCT_V6         U_CCT_N16681406 0 0.14Vdc
V_U_CCT_V10         U_CCT_N16717213 0 3.625Vdc
X_U_CCT_U6         U_CCT_N16687813 U_CCT_N16687973 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_CCT_U40         U_CCT_N418491 U_CCT_N16708577 BUF_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
V_U_CCT_V8         U_CCT_N16714918 0 2.375
C_U_CCT_C16         0 U_CCT_N16687813  1p  TC=0,0 
X_U_CCT_S13    U_CCT_VOH_Z 0 U_CCT_N16717213 U_CCT_VLIM Current_CNTL_U_CCT_S13 
C_U_CCT_C1         U_CCT_N383463 N755412  10p IC=3.55 TC=0,0 
X_U_CCT_D63         N755412 U_CCT_N16679329 d_d1 PARAMS: 
X_U_CCT_U44         U_CCT_N00720 N755552 ZCD_FIRST U_CCT_N386967 OR3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_CCT_U12         TDM_START U_CCT_N386967 U_CCT_N00219 U_CCT_N00128
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U_CCT_V9         U_CCT_N16685522 U_CCT_N383463 0.6
X_U_CCT_S11    U_CCT_N16708513 0 N755070 0 Current_CNTL_U_CCT_S11 
R_U_CCT_R16         U_CCT_N383233 U_CCT_N383463  2.75meg TC=0,0 
X_U_CCT_S10    U_CCT_N16708577 0 VCX5 N755070 Current_CNTL_U_CCT_S10 
X_U_CCT_S12    U_CCT_VOH_BUFF 0 U_CCT_N16714918 U_CCT_VLIM
+  Current_CNTL_U_CCT_S12 
X_U_CCT_U46         VOH U_CCT_VOH_Z INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_CCT_D64         U_CCT_N16681406 N755412 d_d1 PARAMS: 
X_U_CCT_U7         U_CCT_N16687973 U_CCT_N418491 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
R_U_CCT_R1         0 N755412  1k TC=0,0 
X_U_CCT_U43         U_CCT_VLIM U_CCT_N16685522 d_d1 PARAMS:
E_U_CCT_E2         U_CCT_N16679519 0 U_CCT_VLIM U_CCT_N383463 10000
X_U_CCT_U45         VOH U_CCT_VOH_BUFF BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
V_U_CCT_V26         U_CCT_N431501 0 3.9
X_U_CCT_U32         N755514 N00102 U_CCT_N00128 U_CCT_N00094 U_CCT_N00564 0
+  DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_CCT_U36         U_CCT_N00094 U_CCT_N00720 U_CCT_N00564 NOR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U_CCT_U37         EN_WZ U_CCT_N00720 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U_CCT_S9    U_CCT_N419295 0 U_CCT_N406220 U_CCT_N383233 Current_CNTL_U_CCT_S9
+  
X_U_CCT_D65         U_CCT_N16687813 U_CCT_N00219 d_d1 PARAMS: 
X_U_CCT_U39         U_CCT_N418491 U_CCT_N404902 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U_CCT_U38         U_CCT_N418491 U_CCT_N419295 BUF_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
X_U_CCT_U41         U_CCT_N431501 N755412 U_CCT_N00094 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U_CCT_S8    U_CCT_N404902 0 U_CCT_N383233 0 Current_CNTL_U_CCT_S8 
V_U_CCT_V5         U_CCT_N16679329 0 4.86Vdc
X_U_CCT_U42         U_CCT_N418491 U_CCT_N16708513 INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
V_U_CCT_V7         U_CCT_N406220 0 5Vdc
R_U_CCT_R4         U_CCT_N16687813 U_CCT_N00219  36.23e3  
G_U_CCT_G1         0 N755412 U_CCT_N16679519 0 1m
E_E2         VS_SH 0 VS GND 1
.ENDS

.subckt WUM_U_WUM_S10 1 2 3 4  
S_U_WUM_S10         3 4 1 2 _U_WUM_S10
RS_U_WUM_S10         1 2 1G
.MODEL         _U_WUM_S10 VSWITCH Roff=1e12 Ron=100 Voff=0.2V Von=0.8V
.ends WUM_U_WUM_S10

.subckt WUM_U_WUM_S9 1 2 3 4  
S_U_WUM_S9         3 4 1 2 _U_WUM_S9
RS_U_WUM_S9         1 2 1G
.MODEL         _U_WUM_S9 VSWITCH Roff=1e12 Ron=100 Voff=0.2V Von=0.8V
.ends WUM_U_WUM_S9

.subckt TOP_UCC28704_S1 1 2 3 4  
S_S1         3 4 1 2 _S1
RS_S1         1 2 1G
.MODEL         _S1 VSWITCH Roff=1e12 Ron=100 Voff=0.0V Von=1.0V
.ends TOP_UCC28704_S1

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_S16 1 2 3 4  
S_CNTLLAW_S16         3 4 1 2 _CNTLLAW_S16
RS_CNTLLAW_S16         1 2 1G
.MODEL         _CNTLLAW_S16 VSWITCH Roff=1e9 Ron=10 Voff=0.1V Von=0.8V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_S16

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_S10 1 2 3 4  
S_CNTLLAW_S10         3 4 1 2 _CNTLLAW_S10
RS_CNTLLAW_S10         1 2 1G
.MODEL         _CNTLLAW_S10 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.9V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_S10

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_F5 1 2 3 4  
F_CNTLLAW_F5         3 4 VF_CNTLLAW_F5 1
VF_CNTLLAW_F5         1 2 0V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_F5

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_S17 1 2 3 4  
S_CNTLLAW_S17         3 4 1 2 _CNTLLAW_S17
RS_CNTLLAW_S17         1 2 1G
.MODEL         _CNTLLAW_S17 VSWITCH Roff=1e9 Ron=10 Voff=0.1V Von=0.8V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_S17

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_S9 1 2 3 4  
S_CNTLLAW_S9         3 4 1 2 _CNTLLAW_S9
RS_CNTLLAW_S9         1 2 1G
.MODEL         _CNTLLAW_S9 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.9V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_S9

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_S8 1 2 3 4  
S_CNTLLAW_S8         3 4 1 2 _CNTLLAW_S8
RS_CNTLLAW_S8         1 2 1G
.MODEL         _CNTLLAW_S8 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.9V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_S8

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_S19 1 2 3 4  
S_CNTLLAW_S19         3 4 1 2 _CNTLLAW_S19
RS_CNTLLAW_S19         1 2 1G
.MODEL         _CNTLLAW_S19 VSWITCH Roff=1e9 Ron=10 Voff=0.1V Von=0.8V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_S19

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_S7 1 2 3 4  
S_CNTLLAW_S7         3 4 1 2 _CNTLLAW_S7
RS_CNTLLAW_S7         1 2 1G
.MODEL         _CNTLLAW_S7 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.9V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_S7

.subckt CNTL_LAW_SIMPLIFIED_CNTLLAW_S20 1 2 3 4  
S_CNTLLAW_S20         3 4 1 2 _CNTLLAW_S20
RS_CNTLLAW_S20         1 2 1G
.MODEL         _CNTLLAW_S20 VSWITCH Roff=1e9 Ron=10 Voff=0.1V Von=0.8V
.ends CNTL_LAW_SIMPLIFIED_CNTLLAW_S20

.subckt Modulator_MODIFIED_U_MOD1_F1 1 2 3 4  
F_U_MOD1_F1         3 4 VF_U_MOD1_F1 100m
VF_U_MOD1_F1         1 2 0V
.ends Modulator_MODIFIED_U_MOD1_F1

.subckt Modulator_MODIFIED_U_MOD1_S8 1 2 3 4  
S_U_MOD1_S8         3 4 1 2 _U_MOD1_S8
RS_U_MOD1_S8         1 2 1G
.MODEL         _U_MOD1_S8 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.9V
.ends Modulator_MODIFIED_U_MOD1_S8

.subckt PCC_CELL8_U_MOD1_UPCC_S8 1 2 3 4  
S_U_MOD1_UPCC_S8         3 4 1 2 _U_MOD1_UPCC_S8
RS_U_MOD1_UPCC_S8         1 2 1G
.MODEL         _U_MOD1_UPCC_S8 VSWITCH Roff=1e12 Ron=6 Voff=0.1V Von=0.8V
.ends PCC_CELL8_U_MOD1_UPCC_S8

.subckt PCC_CELL8_U_MOD1_UPCC_S15 1 2 3 4  
S_U_MOD1_UPCC_S15         3 4 1 2 _U_MOD1_UPCC_S15
RS_U_MOD1_UPCC_S15         1 2 1G
.MODEL         _U_MOD1_UPCC_S15 VSWITCH Roff=1e9 Ron=100 Voff=0.1V Von=0.8V
.ends PCC_CELL8_U_MOD1_UPCC_S15

.subckt PCC_CELL8_U_MOD1_UPCC_F2 1 2 3 4  
F_U_MOD1_UPCC_F2         3 4 VF_U_MOD1_UPCC_F2 1
VF_U_MOD1_UPCC_F2         1 2 0V
.ends PCC_CELL8_U_MOD1_UPCC_F2

.subckt Modulator_MODIFIED_U_MOD1_S7 1 2 3 4  
S_U_MOD1_S7         3 4 1 2 _U_MOD1_S7
RS_U_MOD1_S7         1 2 1G
.MODEL         _U_MOD1_S7 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.9V
.ends Modulator_MODIFIED_U_MOD1_S7

.subckt Timer_Cell_U_MOD1_UZD_u_TIMER_S13 1 2 3 4  
S_U_MOD1_UZD_u_TIMER_S13         3 4 1 2 _U_MOD1_UZD_u_TIMER_S13
RS_U_MOD1_UZD_u_TIMER_S13         1 2 1G
.MODEL         _U_MOD1_UZD_u_TIMER_S13 VSWITCH Roff=100e6 Ron=10 Voff=0.1V
+  Von=0.8V
.ends Timer_Cell_U_MOD1_UZD_u_TIMER_S13

.subckt TDM_U_MOD1_UZD_UTDM_S13 1 2 3 4  
S_U_MOD1_UZD_UTDM_S13         3 4 1 2 _U_MOD1_UZD_UTDM_S13
RS_U_MOD1_UZD_UTDM_S13         1 2 1G
.MODEL         _U_MOD1_UZD_UTDM_S13 VSWITCH Roff=1e9 Ron=10 Voff=0.1V Von=0.8V
.ends TDM_U_MOD1_UZD_UTDM_S13

.subckt ZCD_U_MOD1_UZD_S9 1 2 3 4  
S_U_MOD1_UZD_S9         3 4 1 2 _U_MOD1_UZD_S9
RS_U_MOD1_UZD_S9         1 2 1G
.MODEL         _U_MOD1_UZD_S9 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.9V
.ends ZCD_U_MOD1_UZD_S9

.subckt Modulator_MODIFIED_U_MOD1_F2 1 2 3 4  
F_U_MOD1_F2         3 4 VF_U_MOD1_F2 40m
VF_U_MOD1_F2         1 2 0V
.ends Modulator_MODIFIED_U_MOD1_F2

.subckt MINP_Range_MODIFIED_U_MOD1_U_MINP_S8 1 2 3 4  
S_U_MOD1_U_MINP_S8         3 4 1 2 _U_MOD1_U_MINP_S8
RS_U_MOD1_U_MINP_S8         1 2 1G
.MODEL         _U_MOD1_U_MINP_S8 VSWITCH Roff=10e9 Ron=1m Voff=0.1V Von=0.8V
.ends MINP_Range_MODIFIED_U_MOD1_U_MINP_S8

.subckt PWR_mgnt_U_PM_F3 1 2 3 4  
F_U_PM_F3         3 4 VF_U_PM_F3 1
VF_U_PM_F3         1 2 0V
.ends PWR_mgnt_U_PM_F3

.subckt PWR_mgnt_U_PM_S8 1 2 3 4  
S_U_PM_S8         3 4 1 2 _U_PM_S8
RS_U_PM_S8         1 2 1G
.MODEL         _U_PM_S8 VSWITCH Roff=1e12 Ron=1.0 Voff=0.0V Von=1.0V
.ends PWR_mgnt_U_PM_S8

.subckt PWR_mgnt_U_PM_S9 1 2 3 4  
S_U_PM_S9         3 4 1 2 _U_PM_S9
RS_U_PM_S9         1 2 1G
.MODEL         _U_PM_S9 VSWITCH Roff=1e12 Ron=1.0 Voff=0.0V Von=1.0V
.ends PWR_mgnt_U_PM_S9

.subckt PWR_mgnt_U_PM_S10 1 2 3 4  
S_U_PM_S10         3 4 1 2 _U_PM_S10
RS_U_PM_S10         1 2 1G
.MODEL         _U_PM_S10 VSWITCH Roff=1e12 Ron=1.0 Voff=0.0V Von=1.0V
.ends PWR_mgnt_U_PM_S10

.subckt PWR_mgnt_U_PM_F1 1 2 3 4  
F_U_PM_F1         3 4 VF_U_PM_F1 1
VF_U_PM_F1         1 2 0V
.ends PWR_mgnt_U_PM_F1

.subckt PWR_mgnt_U_PM_F2 1 2 3 4  
F_U_PM_F2         3 4 VF_U_PM_F2 1
VF_U_PM_F2         1 2 0V
.ends PWR_mgnt_U_PM_F2

.subckt Sampler_U_SAMPLER_S12 1 2 3 4  
S_U_SAMPLER_S12         3 4 1 2 _U_SAMPLER_S12
RS_U_SAMPLER_S12         1 2 1G
.MODEL         _U_SAMPLER_S12 VSWITCH Roff=10e9 Ron=2k Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S12

.subckt Sampler_U_SAMPLER_S8 1 2 3 4  
S_U_SAMPLER_S8         3 4 1 2 _U_SAMPLER_S8
RS_U_SAMPLER_S8         1 2 1G
.MODEL         _U_SAMPLER_S8 VSWITCH Roff=100e9 Ron=100 Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S8

.subckt Sampler_U_SAMPLER_S6 1 2 3 4  
S_U_SAMPLER_S6         3 4 1 2 _U_SAMPLER_S6
RS_U_SAMPLER_S6         1 2 1G
.MODEL         _U_SAMPLER_S6 VSWITCH Roff=100e9 Ron=100 Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S6

.subckt Sampler_U_SAMPLER_S16 1 2 3 4  
S_U_SAMPLER_S16         3 4 1 2 _U_SAMPLER_S16
RS_U_SAMPLER_S16         1 2 1G
.MODEL         _U_SAMPLER_S16 VSWITCH Roff=1e12 Ron=2k Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S16

.subckt Sampler_U_SAMPLER_S18 1 2 3 4  
S_U_SAMPLER_S18         3 4 1 2 _U_SAMPLER_S18
RS_U_SAMPLER_S18         1 2 1G
.MODEL         _U_SAMPLER_S18 VSWITCH Roff=10e10 Ron=2k Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S18

.subckt Sampler_U_SAMPLER_S2 1 2 3 4  
S_U_SAMPLER_S2         3 4 1 2 _U_SAMPLER_S2
RS_U_SAMPLER_S2         1 2 1G
.MODEL         _U_SAMPLER_S2 VSWITCH Roff=100e9 Ron=100 Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S2

.subckt Sampler_U_SAMPLER_S14 1 2 3 4  
S_U_SAMPLER_S14         3 4 1 2 _U_SAMPLER_S14
RS_U_SAMPLER_S14         1 2 1G
.MODEL         _U_SAMPLER_S14 VSWITCH Roff=1e12 Ron=200 Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S14

.subckt Sampler_U_SAMPLER_S19 1 2 3 4  
S_U_SAMPLER_S19         3 4 1 2 _U_SAMPLER_S19
RS_U_SAMPLER_S19         1 2 1G
.MODEL         _U_SAMPLER_S19 VSWITCH Roff=1e9 Ron=2k Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S19

.subckt Sampler_U_SAMPLER_S4 1 2 3 4  
S_U_SAMPLER_S4         3 4 1 2 _U_SAMPLER_S4
RS_U_SAMPLER_S4         1 2 1G
.MODEL         _U_SAMPLER_S4 VSWITCH Roff=1000e6 Ron=100 Voff=0.0V Von=1.0V
.ends Sampler_U_SAMPLER_S4

.subckt Sampler_U_SAMPLER_S11 1 2 3 4  
S_U_SAMPLER_S11         3 4 1 2 _U_SAMPLER_S11
RS_U_SAMPLER_S11         1 2 1G
.MODEL         _U_SAMPLER_S11 VSWITCH Roff=1e10 Ron=2k Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S11

.subckt Sampler_U_SAMPLER_S15 1 2 3 4  
S_U_SAMPLER_S15         3 4 1 2 _U_SAMPLER_S15
RS_U_SAMPLER_S15         1 2 1G
.MODEL         _U_SAMPLER_S15 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S15

.subckt Sampler_U_SAMPLER_S17 1 2 3 4  
S_U_SAMPLER_S17         3 4 1 2 _U_SAMPLER_S17
RS_U_SAMPLER_S17         1 2 1G
.MODEL         _U_SAMPLER_S17 VSWITCH Roff=10e10 Ron=2k Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S17

.subckt Sampler_U_SAMPLER_F1 1 2 3 4  
F_U_SAMPLER_F1         3 4 VF_U_SAMPLER_F1 2
VF_U_SAMPLER_F1         1 2 0V
.ends Sampler_U_SAMPLER_F1

.subckt Sampler_U_SAMPLER_S7 1 2 3 4  
S_U_SAMPLER_S7         3 4 1 2 _U_SAMPLER_S7
RS_U_SAMPLER_S7         1 2 1G
.MODEL         _U_SAMPLER_S7 VSWITCH Roff=1e10 Ron=2k Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S7

.subckt Sampler_U_SAMPLER_S3 1 2 3 4  
S_U_SAMPLER_S3         3 4 1 2 _U_SAMPLER_S3
RS_U_SAMPLER_S3         1 2 1G
.MODEL         _U_SAMPLER_S3 VSWITCH Roff=1000e6 Ron=100 Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S3

.subckt Sampler_U_SAMPLER_S5 1 2 3 4  
S_U_SAMPLER_S5         3 4 1 2 _U_SAMPLER_S5
RS_U_SAMPLER_S5         1 2 1G
.MODEL         _U_SAMPLER_S5 VSWITCH Roff=1e9 Ron=100 Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S5

.subckt Delay_Analog_U_SAMPLER_U_Delay_S4 1 2 3 4  
S_U_SAMPLER_U_Delay_S4         3 4 1 2 _U_SAMPLER_U_Delay_S4
RS_U_SAMPLER_U_Delay_S4         1 2 1G
.MODEL         _U_SAMPLER_U_Delay_S4 VSWITCH Roff=1000e6 Ron=1m Voff=0.0V
+  Von=1.0V
.ends Delay_Analog_U_SAMPLER_U_Delay_S4

.subckt Delay_Analog_U_SAMPLER_U_Delay_S5 1 2 3 4  
S_U_SAMPLER_U_Delay_S5         3 4 1 2 _U_SAMPLER_U_Delay_S5
RS_U_SAMPLER_U_Delay_S5         1 2 1G
.MODEL         _U_SAMPLER_U_Delay_S5 VSWITCH Roff=1000e6 Ron=1m Voff=0.0V
+  Von=1.0V
.ends Delay_Analog_U_SAMPLER_U_Delay_S5

.subckt Sampler_U_SAMPLER_S13 1 2 3 4  
S_U_SAMPLER_S13         3 4 1 2 _U_SAMPLER_S13
RS_U_SAMPLER_S13         1 2 1G
.MODEL         _U_SAMPLER_S13 VSWITCH Roff=1e12 Ron=0.01 Voff=0.1V Von=0.8V
.ends Sampler_U_SAMPLER_S13

.subckt Delay_Analog_U_Delay_S4 1 2 3 4  
S_U_Delay_S4         3 4 1 2 _U_Delay_S4
RS_U_Delay_S4         1 2 1G
.MODEL         _U_Delay_S4 VSWITCH Roff=1000e6 Ron=1m Voff=0.0V Von=1.0V
.ends Delay_Analog_U_Delay_S4

.subckt Delay_Analog_U_Delay_S5 1 2 3 4  
S_U_Delay_S5         3 4 1 2 _U_Delay_S5
RS_U_Delay_S5         1 2 1G
.MODEL         _U_Delay_S5 VSWITCH Roff=1000e6 Ron=1m Voff=0.0V Von=1.0V
.ends Delay_Analog_U_Delay_S5

.subckt Current_CNTL_U_CCT_S13 1 2 3 4  
S_U_CCT_S13         3 4 1 2 _U_CCT_S13
RS_U_CCT_S13         1 2 1G
.MODEL         _U_CCT_S13 VSWITCH Roff=1e12 Ron=10 Voff=0.1V Von=0.8V
.ends Current_CNTL_U_CCT_S13

.subckt Current_CNTL_U_CCT_S11 1 2 3 4  
S_U_CCT_S11         3 4 1 2 _U_CCT_S11
RS_U_CCT_S11         1 2 1G
.MODEL         _U_CCT_S11 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.8V
.ends Current_CNTL_U_CCT_S11

.subckt Current_CNTL_U_CCT_S10 1 2 3 4  
S_U_CCT_S10         3 4 1 2 _U_CCT_S10
RS_U_CCT_S10         1 2 1G
.MODEL         _U_CCT_S10 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.8V
.ends Current_CNTL_U_CCT_S10

.subckt Current_CNTL_U_CCT_S12 1 2 3 4  
S_U_CCT_S12         3 4 1 2 _U_CCT_S12
RS_U_CCT_S12         1 2 1G
.MODEL         _U_CCT_S12 VSWITCH Roff=1e12 Ron=10 Voff=0.1V Von=0.8V
.ends Current_CNTL_U_CCT_S12

.subckt Current_CNTL_U_CCT_S9 1 2 3 4  
S_U_CCT_S9         3 4 1 2 _U_CCT_S9
RS_U_CCT_S9         1 2 1G
.MODEL         _U_CCT_S9 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.8V
.ends Current_CNTL_U_CCT_S9

.subckt Current_CNTL_U_CCT_S8 1 2 3 4  
S_U_CCT_S8         3 4 1 2 _U_CCT_S8
RS_U_CCT_S8         1 2 1G
.MODEL         _U_CCT_S8 VSWITCH Roff=1e12 Ron=100 Voff=0.1V Von=0.8V
.ends Current_CNTL_U_CCT_S8


** Wrapper definitions for AA legacy support **

.subckt d_d1 1 2

d1 1 2 dd1

.model dd1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.05
+ n=0.1

.ends d_d1

.subckt one_shot in out
+ params: t=100
s_s1 meas 0 reset2 0 s1
e_abm1 ch 0 value {if( v(in)>0.5 | v(out)>0.5,1,0)}
r_r2 reset2 reset  0.1
e_abm3 out 0 value {if( v(meas)<0.5 & v(ch)>0.5,1,0)}
r_r1 meas ch {t} 
c_c2 0 reset2 1.4427n
c_c1 0 meas 1.4427n
e_abm2 reset 0 value {if(v(ch)<0.5,1,0)}
.model s1 vswitch
+ roff=1e+009
+ ron=1
+ voff=0.25
+ von=0.75
.ends one_shot
.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=0.01 VJ=0.8 )

.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
E_ABM Yint 0 VALUE {IF (V(INP) > 
+ V(INM), {VDD},{VSS})}
R1 Yint Y 1
C1 Y 0 1n
.ENDS COMP_BASIC_GEN
*$
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
EIN INP1 INM1 INP INM 1 
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 5.0n
RINP1 INP1 0 1K
.ENDS COMPHYS_BASIC_GEN
*$
.SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
+ T=10
EIN INP1 INM1 INP INM 1 
EHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) }
EOUT OUT 0 VALUE { IF( V(INP1)>V(INM2), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 10K
RINM2 INM2 0 10K
.ENDS COMPHYS2_BASIC_GEN
*$
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2_BASIC_GEN
*$
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND3_BASIC_GEN
*$
.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND4_BASIC_GEN
*$
.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND2_BASIC_GEN
*$
.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND3_BASIC_GEN
*$
.SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND4_BASIC_GEN
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR2_BASIC_GEN
*$
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR3_BASIC_GEN
*$
.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR4_BASIC_GEN
*$
.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR2_BASIC_GEN
*$
.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR3_BASIC_GEN
*$
.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR4_BASIC_GEN
*$
.SUBCKT NOR5_BASIC_GEN A B C D E Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH} |
+ V(E) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR5_BASIC_GEN
*$
.SUBCKT NOR6_BASIC_GEN A B C D E F Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH} |
+ V(E) > {VTHRESH} |
+ V(F) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR6_BASIC_GEN
*$
.SUBCKT INV_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS INV_BASIC_GEN
*$
.SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XOR2_BASIC_GEN
*$
.SUBCKT XNOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^  
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XNOR2_BASIC_GEN
*$
.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE  YINT 0 VALUE {{IF(V(S) > {VTHRESH},  
+ V(B),V(A))}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS MUX2_BASIC_GEN
*$
.SUBCKT INV_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n 
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , 
+ {VSS},{VDD})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS INV_DELAY_BASIC_GEN
*$
.SUBCKT BUF_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n 
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS BUF_DELAY_BASIC_GEN
*$
.SUBCKT BUF_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS BUF_BASIC_GEN
*$
**Set has higher priority in this latch
.SUBCKT SRLATCHSHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R)>{VTHRESH},-5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1 
Cdummy1 Q 0 1n 
Cdummy2 QB 0 1n 
.IC V(Qint) {VSS}
.ENDS SRLATCHSHP_BASIC_GEN
*$
**Reset has higher priority in this latch
.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1 
Cdummy1 Q 0 1n 
Cdummy2 QB 0 1n
.IC V(Qint) {VSS}
.ENDS SRLATCHRHP_BASIC_GEN
*$
**Reset has higher priority in this latch and active low set and reset - basically NAND based SR latch
.SUBCKT SBRBLATCHRHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB) < {VTHRESH},5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1 
.IC V(Qint) {VSS}
.ENDS SBRBLATCHRHP_BASIC_GEN
*$
**Reset has higher priority in this latch and active low set and reset - basically NAND based SR latch
.SUBCKT SBRBLATCHSHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB) < {VTHRESH},-5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1 
.IC V(Qint) {VSS}
.ENDS SBRBLATCHSHP_BASIC_GEN
*$
.SUBCKT DFFSBRB_SHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
***Set has higher priority in this
** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations
**Faster flip-flops require a a smaller time step to simulate
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB)<{VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.ENDS DFFSBRB_SHPBASIC_GEN
*$
.SUBCKT DFFSR_SHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
***Set has higher priority in this
** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations
**Faster flip-flops require a a smaller time step to simulate
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} 
GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R) > {VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.ENDS DFFSR_SHPBASIC_GEN
*$
.SUBCKT DFFSBRB_RHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
***Set has higher priority in this
** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations
**Faster flip-flops require a a smaller time step to simulate
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} 
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB)< {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 5
D_D11 0 Qint D_D1 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.ENDS DFFSBRB_RHPBASIC_GEN
*$
.SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
***Set has higher priority in this
** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations
**Faster flip-flops require a a smaller time step to simulate
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}  
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.ENDS DFFSR_RHPBASIC_GEN
*$
**** SPM_Mono_POS  ***************************************************************************************
* FUNCTION: SHORT TIME PULSE GENERATOR AT NEG INPUT EDGE
* INPUTS/OUTPUTS: ONE DIGITAL INPUT: A, TWO DIG OUTPUT PINS: Q Qn
* DESCRIPTION: CREATE A PW PULSE WIDTH AT -VE EDGE OF INPUT, PULSE WIDTH OF INPUT NEEDS TO BE GREATER THAN PW PARAMETER VALUE
**********************
.SUBCKT MONOPOS_PS in Q Qn PARAMS: PW=1u 
****buffer*********
*RA in 0 1e11
*CA in 0 0.01pF
*VS VSUP 0 DC 1
**** boolean ************
*EBUF1 Y1 0 VALUE={IF(V(in) > .5 , 1, 0)}
*ROUTpp1 Y1 0 1e11
**** add delay lines ****
*XNSW1 Y2 Y1  0 NSW_PS PARAMS: RONval={(PW+1e-15)/(1e-12*0.693)} VTHval=0.5
*XPSW1 Y2 Y1 VSUP PSW_PS PARAMS: RONval={(PW+1e-15)/(1e-12*0.693)} VTHval=0.5
*CDEL1 Y2 0 1pF
*ETHRESH Y3 0 VALUE={IF(V(Y2) > 0.5, 0, 1)}
*ROUTp Y3 0 1e11
* ************add rise and fall *****
**XNSW2 Y4 Y3 0 NSW_PS PARAMS: RONval=(1e-12/1e-12*2.3) VTHval=0.5
**XPSW2 Y4 Y3 VSUP PSW_PS PARAMS: RONval=(1e-12/1e-12*2.3) VTHval=0.5
**CDEL2 Y4 0 1pF
************XOR2***********
*EXOR2 P 0 VALUE={IF(V(in) > 0.5 ^ V(Y3) > .5, 1, 0)}
*ROUTpp2 P 0 1e11
**********AND************
*EAND2 Y5 0 VALUE={IF(V(in) > 0.5 & V(P) > 0.5 , 0, 1)}
*ROUTpp3 Y5 0 1e11
* add rise and fall *****
*XNSW3 Q Y5 0 NSW_PS PARAMS: RONval=(1e-9/1e-12*2.3) VTHval=0.5
*XPSW3 Q Y5 VSUP PSW_PS PARAMS: RONval=(1e-9/1e-12*2.3) VTHval=0.5
*ROUTq Q 0 1e11
***********end of AND2********************
* add rise and fall + inversion *****
*XNSW4 Qn Q 0 NSW_PS PARAMS: RONval=(1e-9/1e-12*2.3) VTHval=0.5
*XPSW4 Qn Q VSUP PSW_PS PARAMS: RONval=(1e-9/1e-12*2.3) VTHval=0.5
*ROUTqn Qn 0 1e11
*******************************new take on delay*************
VS VSUP 0 DC 1
GIN VSUP YA VALUE={IF(V(IN)>0.5, V(VSUP)/1000K, 0)}
GDIS YA 0 VALUE={IF(V(IN)>0.5,0, V(YA)/1m)}
CIN YA 0 1n IC=0
RIN YA 0 1e11
EABM1 YTD 0 VALUE={IF(V(YA)> {PW*1000}, 1, 0)}
RYTD YTD 0 1e11
EXOR P 0 VALUE={IF(V(YTD) > 0.5 ^ V(IN) > .5, 1, 0)}
ROUTpp2 P 0 1e11
EAND1 Q1 0 VALUE={ IF(V(P)>0.5 & V(IN)>0.5, 1, 0)}
Ro1 Q1 Q 1m
Co1 Q 0 1p
ROUT2 Q 0 1e11
EAND2 Qn1 0 VALUE={ IF(V(Q)>0.5, 0, 1)}
Ro2 Qn1 Qn 1m
Co2 Qn 0 1p
ROUT4 Qn 0 1e11
.ENDS MONOPOS_PS
*$
.SUBCKT LDCR 1 2 PARAMS: L=1u DCR=20m
L1 1 INT1 {L}
R1 INT1 2 {DCR}
.ENDS LDCR
*$
.SUBCKT CESR 1 2 PARAMS: C=10u ESR=2m ESL=1n
C1 1 INT1 {C}
R1 INT1 INT2 {ESR}
L1 INT2 2 {ESL}
.ENDS CESR
*$
.SUBCKT multiplier V1 V2  OUT    
E_MULT    OUT 0 VALUE = { V(V1) *V(V2) }
.ENDS multiplier
*$
.SUBCKT 2to1MUX V1 V2  A  out    PARAMS:  VTHRESH=0.5 
E_MUX    OUT 0 VALUE = {IF (  V(A) > {VTHRESH} ,V(V1),V(V2) ) }
.ENDS 2to1MUX
*$
.SUBCKT VI_HL Vin VDD Vout 
E_out  Vout 0 VALUE = {if ( V(Vin) > V(VDD)*0.7, V(VDD),
+ if ( V(Vin) < V(VDD)*0.3, 0 , V(VDD)/2 ))} 
.ends  
*$
.SUBCKT COMPHYS_BASIC_GEN_NORC INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
EIN INP1 INM1 INP INM 1 
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 1n
*RINP1 INP1 0 1K
RINP1 INP1 0 1000K
.ENDS COMPHYS_BASIC_GEN_NORC
*$
.SUBCKT COMP_HYS IN_POS IN_NEG HYS OUT 
X_U1         IN_POS N00153 OUT COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABM2         N00234 0 VALUE { V(IN_NEG)+  
+ +(-V(OUT)*V(HYS))   }
R_R1         N00234 N00153  1  
C_C1         0 N00153  1n  
.ENDS COMP_HYS
* PSpice Model Editor - Version 16.2.0
*$
.SUBCKT VLC_to_MINP VLC VIAMP  WAKE  PARAMS:  VTHRESH=0.5 
EWAKE    WAKEZ 0 VALUE= {1-V(WAKE)}
*Note: WAKE is gonna be connected to LR at the pin for UCC28704
E_MUX    Vout 0 VALUE = {
+ IF (V(VLC) > = 0.0  & V(VLC) < = 1.586,    (112*V(WAKEZ)+28*V(WAKE)),
+ IF (V(VLC) > 1.586 & V(VLC) < = 2.684 ,    (V(VLC)*535.52-737.33),
+ IF (V(VLC) > 2.684 & V(VLC) < = 3.66,    700,
+ IF (V(VLC) > 3.66 & V(VLC) < = 5.917,    (V(VLC)*744.35-2024.32), 2380  ) ) ) ) }
*R1 Dummy 0 10e6
*C1 Dummy 0 10e-9
E_IOUT   VIAMP 0 VALUE= {V(Vout)*1e-9*1e6}
* Converting  units to nA and then multiplying it by 1e6 so pspice can detect the small pico
* numbers. Will multiply by 1e-6 in the next block (MINP) to cancel 1e6*
* 
.ENDS VLC_to_MINP  
*$
* PSpice Model Editor - Version 16.2.0
*Modified for UCC28704


