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C2 Compliance Test Report

# Power Delivery 3.1 Tests- Result Summary

Sl No | Test ID | Test Name | Test Result
--- | --- | --- | ---
1 | TEST.PD.PROT.SNK.3 | TEST.PD.PROT.SNK.3 SinkWaitCapTimer Deadline | INCOMPLETE

# Power Delivery 3.1 Tests - Detailed Test Result

Test Status | Test Description
--- | ---
INCOMPLETE | 1. TEST.PD.PROT.SNK.3 SinkWaitCapTimer Deadline
PASS | COMMON.PROC.BU.2:
PASS | COMMON.PROC.BU.2 - REVISION_2_0 Rev2Snk:
| SourceCap Packet14
PASS | UUT should respond with request - - COMMON.PROC.BU.2#1:
| Request Packet16
PASS | COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk:
| SourceCap Packet57
PASS | UUT should respond with request - - COMMON.PROC.BU.2#1:
| Request Packet59
INCOMPLETE | Rev2Snk:
INCOMPLETE | Hard_Reset check - TEST.PD.PROT.SNK.3#1:
| Tester sent Hard_Reset message Packet 26 Tester sent SourceCap message Packet 35 Tester intiates Hard_Reset at 2,63896s and SourceCap at 4,21288s.Vbus reached vsafe5v 0s. Tester transmits SourceCap within tTypeCSinkWaitCap min 0s
NA | Request message check - TEST.PD.PROT.SNK.3#2:
INCOMPLETE | Rev3ChkdSnk:
INCOMPLETE | Hard_Reset check - TEST.PD.PROT.SNK.3#1:
| Tester sent Hard_Reset message Packet 73 Tester sent SourceCap message Packet 84 Tester intiates Hard_Reset at 7,66697s and SourceCap at 9,24853s.Vbus reached vsafe5v 0s. Tester transmits SourceCap within tTypeCSinkWaitCap min 0s
NA | Request message check - TEST.PD.PROT.SNK.3#2:

# Packet List (Click to View AMS Summary)

Index | Start time(s.ms.μs.ns) | Stop time(s.ms.μs.ns) | Message Origin | Message |  | Secondary Message | SOP | Port Type | Msg ID | PDO | Header(MSB to LSB) | Payload(LSB to MSB)
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
TEST_PD_PROT_SNK_3_SinkWaitCapTimer_Deadline |
Port A Packet Details
4 | 636.5 mS | 636.5 mS | T-> | Ra_Asserted |  |  | NONE | NONE/NONE/R- | 0 | Ra_CC2 | 0x0000 |
8 | 636.6 mS | 636.6 mS | <-D |  | Rd_Detected |  | NONE | NONE/NONE/R- | 0 | Rd in CC1; | 0x0000 |
10 | 636.6 mS | 636.6 mS | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Disabled -> FSM_State_Unattached_SRC | 0x0000 |
11 | 638.3 mS | 638.3 mS | T-> | Attach |  | Rp_12k_1_5A_Asserted | NONE | NONE/NONE/- | 0 | Rp_12k_1_5A_Asserted | 0x0000 |
12 | 638.3 mS | 638.3 mS | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC | 0x0000 |
13 | 788.4 mS | 788.4 mS | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC | 0x0000 |
14 | 830.0 mS | 830.6 mS | T-> | SourceCap |  |  | SOP | DFP/Source/R2 | 0 | FS: 5V ,1A; | 0x1161 | 0x0A-0x90-0x01-0x28-
15 | 830.6 mS | 831.1 mS | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 0 |  | 0x0041 |
16 | 835.2 mS | 835.9 mS | <-D |  | Request |  | SOP | UFP/Sink/R2 | 0 | PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A | 0x1042 | 0x2C-0x29-0x00-0x15-
17 | 835.9 mS | 836.4 mS | T-> | GoodCRC |  |  | SOP | DFP/Source/R1 | 0 |  | 0x0121 |
18 | 836.5 mS | 836.9 mS | T-> | Accept |  |  | SOP | DFP/Source/R2 | 1 |  | 0x0363 |
19 | 838.9 mS | 839.4 mS | T-> | Accept |  |  | SOP | DFP/Source/R2 | 1 |  | 0x0363 |
20 | 839.4 mS | 839.9 mS | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 1 |  | 0x0241 |
21 | 1,160 S | 1,161 S | T-> | PS_RDY |  |  | SOP | DFP/Source/R2 | 2 |  | 0x0566 |
22 | 1,161 S | 1,161 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 2 |  | 0x0441 |
26 | 2,639 S | 2,639 S | T-> | Hard_Reset |  |  | HARD_RESET | NONE/NONE/R- | 0 |  | 0x0000 |
28 | 2,757 S | 2,757 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Attached_SRC -> FSM_State_Unattached_SRC | 0x0000 |
29 | 2,757 S | 2,757 S | T-> |  | Detach |  | NONE | NONE/NONE/- | 0 | NONE | 0x0000 |
30 | 2,758 S | 2,758 S | <-D |  | NONE | LOAD_CURRENT | NONE | NONE/NONE/R- | 0 | LOAD_CURRENT:0A | 0x0000 |
31 | 3,756 S | 3,756 S | <-D |  | Rd_Detected |  | NONE | NONE/NONE/R- | 0 | Rd in CC1; | 0x0000 |
32 | 3,758 S | 3,758 S | T-> | Attach |  | Rp_12k_1_5A_Asserted | NONE | NONE/NONE/- | 0 | Rp_12k_1_5A_Asserted | 0x0000 |
33 | 3,758 S | 3,758 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC | 0x0000 |
34 | 3,908 S | 3,908 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC | 0x0000 |
35 | 4,212 S | 4,213 S | T-> | SourceCap |  |  | SOP | DFP/Source/R2 | 0 | FS: 5V ,1A; | 0x1161 | 0x0A-0x90-0x01-0x08-
36 | 4,213 S | 4,213 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 0 |  | 0x0041 |
37 | 4,218 S | 4,218 S | <-D |  | Request |  | SOP | UFP/Sink/R2 | 0 | PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A | 0x1042 | 0x2C-0x29-0x00-0x15-
38 | 4,218 S | 4,219 S | T-> | GoodCRC |  |  | SOP | DFP/Source/R1 | 0 |  | 0x0121 |
39 | 4,219 S | 4,219 S | T-> | Accept |  |  | SOP | DFP/Source/R2 | 1 |  | 0x0363 |
40 | 4,219 S | 4,220 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 1 |  | 0x0241 |
41 | 4,540 S | 4,540 S | T-> | PS_RDY |  |  | SOP | DFP/Source/R2 | 2 |  | 0x0566 |
42 | 4,540 S | 4,541 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 2 |  | 0x0441 |
43 | 4,644 S | 4,644 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Attached_SRC -> FSM_State_Disabled | 0x0000 |
44 | 4,644 S | 4,644 S | T-> | Detach |  |  | NONE | NONE/NONE/- | 0 | NONE | 0x0000 |
45 | 4,646 S | 4,646 S | <-D |  | NONE | LOAD_CURRENT | NONE | NONE/NONE/R- | 0 | LOAD_CURRENT:0A | 0x0000 |
46 | 5,646 S | 5,646 S | T-> | Ra_Asserted |  |  | NONE | NONE/NONE/R- | 0 | Ra_CC2 | 0x0000 |
51 | 5,646 S | 5,646 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Disabled -> FSM_State_Unattached_SRC | 0x0000 |
52 | 5,663 S | 5,663 S | <-D |  | Rd_Detected |  | NONE | NONE/NONE/R- | 0 | Rd in CC1; | 0x0000 |
53 | 5,665 S | 5,665 S | T-> | Attach |  | Rp_12k_1_5A_Asserted | NONE | NONE/NONE/- | 0 | Rp_12k_1_5A_Asserted | 0x0000 |
54 | 5,665 S | 5,665 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC | 0x0000 |
55 | 5,815 S | 5,815 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC | 0x0000 |
57 | 5,862 S | 5,863 S | T-> | SourceCap |  |  | SOP | DFP/Source/R3 | 0 | FS: 5V ,1A; | 0x11A1 | 0x0A-0x90-0x01-0x28-
58 | 5,863 S | 5,863 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 0 |  | 0x0041 |
59 | 5,867 S | 5,868 S | <-D |  | Request |  | SOP | UFP/Sink/R3 | 0 | PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A | 0x1082 | 0x2C-0x29-0x80-0x15-
60 | 5,868 S | 5,868 S | T-> | GoodCRC |  |  | SOP | DFP/Source/R1 | 0 |  | 0x0121 |
61 | 5,870 S | 5,870 S | T-> | Accept |  |  | SOP | DFP/Source/R3 | 1 |  | 0x03A3 |
62 | 5,870 S | 5,871 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 1 |  | 0x0241 |
63 | 6,192 S | 6,192 S | T-> | PS_RDY |  |  | SOP | DFP/Source/R3 | 2 |  | 0x05A6 |
64 | 6,192 S | 6,193 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 2 |  | 0x0441 |
66 | 6,193 S | 6,193 S | T-> |  | Rp_Asserted | Rp_4_7k_3A_Asserted | NONE | NONE/NONE/R- | 0 | Rp_4_7k_3A_Asserted | 0x0000 |
68 | 7,647 S | 7,647 S | T-> |  | Rp_Asserted | Rp_12k_1_5A_Asserted | NONE | NONE/NONE/R- | 0 | Rp_12k_1_5A_Asserted | 0x0000 |
69 | 7,647 S | 7,647 S | <-D |  | Rd_Detected |  | NONE | NONE/NONE/R- | 0 | Rd in CC1; | 0x0000 |
73 | 7,667 S | 7,667 S | T-> | Hard_Reset |  |  | HARD_RESET | NONE/NONE/R- | 0 |  | 0x0000 |
76 | 7,787 S | 7,787 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Attached_SRC -> FSM_State_Unattached_SRC | 0x0000 |
77 | 7,787 S | 7,787 S | T-> |  | Detach |  | NONE | NONE/NONE/- | 0 | NONE | 0x0000 |
78 | 7,788 S | 7,788 S | <-D |  | NONE | LOAD_CURRENT | NONE | NONE/NONE/R- | 0 | LOAD_CURRENT:0A | 0x0000 |
79 | 8,787 S | 8,787 S | <-D |  | Rd_Detected |  | NONE | NONE/NONE/R- | 0 | Rd in CC1; | 0x0000 |
80 | 8,788 S | 8,788 S | T-> | Attach |  | Rp_12k_1_5A_Asserted | NONE | NONE/NONE/- | 0 | Rp_12k_1_5A_Asserted | 0x0000 |
81 | 8,788 S | 8,788 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC | 0x0000 |
82 | 8,938 S | 8,938 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC | 0x0000 |
84 | 9,248 S | 9,249 S | T-> | SourceCap |  |  | SOP | DFP/Source/R3 | 0 | FS: 5V ,1A; | 0x11A1 | 0x0A-0x90-0x01-0x08-
85 | 9,249 S | 9,249 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 0 |  | 0x0041 |
86 | 9,253 S | 9,254 S | <-D |  | Request |  | SOP | UFP/Sink/R3 | 0 | PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A | 0x1082 | 0x2C-0x29-0x80-0x15-
87 | 9,254 S | 9,254 S | T-> | GoodCRC |  |  | SOP | DFP/Source/R1 | 0 |  | 0x0121 |
88 | 9,256 S | 9,256 S | T-> | Accept |  |  | SOP | DFP/Source/R3 | 1 |  | 0x03A3 |
89 | 9,256 S | 9,257 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 1 |  | 0x0241 |
90 | 9,579 S | 9,579 S | T-> | PS_RDY |  |  | SOP | DFP/Source/R3 | 2 |  | 0x05A6 |
91 | 9,579 S | 9,580 S | <-D |  | GoodCRC |  | SOP | UFP/Sink/R2 | 2 |  | 0x0441 |
93 | 9,580 S | 9,580 S | T-> |  | Rp_Asserted | Rp_4_7k_3A_Asserted | NONE | NONE/NONE/R- | 0 | Rp_4_7k_3A_Asserted | 0x0000 |
94 | 9,673 S | 9,673 S | <-D |  | Rd_Detected |  | NONE | NONE/NONE/R- | 0 | Rd in CC1; | 0x0000 |
96 | 9,673 S | 9,673 S | T-> |  | Rp_Asserted | Rp_12k_1_5A_Asserted | NONE | NONE/NONE/R- | 0 | Rp_12k_1_5A_Asserted | 0x0000 |
97 | 9,694 S | 9,694 S | T-> | FSM_State_Transition |  |  | NONE | NONE/NONE/R- | 0 | FSM_State_Attached_SRC -> FSM_State_Disabled | 0x0000 |
98 | 9,694 S | 9,694 S | T-> | Detach |  |  | NONE | NONE/NONE/- | 0 | NONE | 0x0000 |
99 | 9,696 S | 9,696 S | <-D |  | NONE | LOAD_CURRENT | NONE | NONE/NONE/R- | 0 | LOAD_CURRENT:0A | 0x0000 |

# AMS Summary

AMS Index | AMS Name | AMS Start | AMS Stop | AMS Status | Child AMS Count
--- | --- | --- | --- | --- | ---
0 | Power_Negotiation | 14 | 22 | COMPLETE | 0
1 | Hard_Reset | 26 | 42 | COMPLETE | 0
2 | Power_Negotiation | 57 | 64 | COMPLETE | 0
3 | Hard_Reset | 73 | 91 | COMPLETE | 0

# DUT Information

Manufacturer | Parrot
Model Number | MPPUA2
Serial Number | 1

# Test Information

Test Lab |
Test_Engineer | Test_Engineer
Remarks | Remarks
Date_and_Time | 14/10/2025 17:33:10

# Controller and Instrument Information

Parameter | Value
--- | ---
GRL_USB_PD_Controller_Serial_No | 397.409.397.077.376.
GRL_USB_PD_Software_Version | 1.6.28.0
GRL_USB_PD_Firmware_Version | 2.2.65
GRL USB-PD Ethernet Buffer Size | 62K
GRL USB-PD Eload Firmware Version | 9.8 / 9.8
Calibration | Calibration Success
RX mask Power selection | Neutral Power
Device_Type | Consumer Only
Cable Type | GRL_SPL_CABLE_1
Impedance (milli ohm) | 0
PD_Merged CTS Version | v.Q4-2024
USB_PD_Spec Version | Rev3.2 Ver1.1RC2
USB_Type_C_Spec Version | v2.3 Oct-2023
VIF_File_Name | Parrot__MPPUA2__1__0_14_10_2025.xml
Noise Pattern Generation: | Two-Tone Noise
Application mode | Informational
Disabled all Pop-up during test execution | False
Pop-up Timer | 0
Rerun Enabled | False
Rerun Count | 1
Rerun Iteration | 0
UI Live Update | False
Execution Time(In Minutes) | 1

# Power Delivery 3.1 Tests Information

Parameter | Value
--- | ---
Connect EPR Test Fixture | False
FR_Swap AUTO Box Connected | False