C2 Compliance Test Report



Power Delivery 3.1 Tests- Result Summary

Sl No

Test ID

Test Name

Test Result

1

TEST.PD.PROT.SNK.4

TEST.PD.PROT.SNK.4 SinkWaitCapTimer Timeout

WARNING

Power Delivery 3.1 Tests - Detailed Test Result

Test Status

Test Description

  WARNING

  1. TEST.PD.PROT.SNK.4 SinkWaitCapTimer Timeout

  PASS

 COMMON.PROC.BU.2:

  PASS

 COMMON.PROC.BU.2 - REVISION_2_0 Rev2Snk:

 

                    SourceCap Packet14

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet16

  PASS

 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk:

 

                    SourceCap Packet65

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet67

  WARNING

 Rev2Snk:

  WARNING

                          SinkWaitCapTimer Timeout - TEST.PD.PROT.SNK.4#1:

 

                                   Measured tTypeCSinkWaitCap value is 641.8 mS which is more than expected limit[310ms ~ 620ms]

  WARNING

 Rev3ChkdSnk:

  WARNING

                          SinkWaitCapTimer Timeout - TEST.PD.PROT.SNK.4#1:

 

                                   Measured tTypeCSinkWaitCap value is 639.2 mS which is more than expected limit[310ms ~ 620ms]

Packet List (Click to View AMS Summary)

Index

   Start time(s.ms.μs.ns)

   Stop time(s.ms.μs.ns)

Message Origin

 Message

 

 Secondary Message

 SOP

 Port Type

 Msg ID

 PDO

 Header(MSB to LSB)

 Payload(LSB to MSB)

TEST_PD_PROT_SNK_4_SinkWaitCapTimer_Timeout

Port A Packet Details

4

636.4 mS

636.4 mS

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

5

636.7 mS

636.7 mS

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

10

636.8 mS

636.8 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

11

638.1 mS

638.1 mS

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

12

638.1 mS

638.1 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

13

788.2 mS

788.2 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

14

839.5 mS

840.1 mS

T->

SourceCap

SOP

DFP/Source/R2

0

 FS: 5V ,1A;

0x1161

0x0A-0x90-0x01-0x28-

15

840.2 mS

840.7 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

16

844.7 mS

845.4 mS

<-D

Request

SOP

UFP/Sink/R2

0

PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A

0x1042

0x2C-0x29-0x00-0x15-

17

845.4 mS

845.9 mS

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

18

846.0 mS

846.4 mS

T->

Accept

SOP

DFP/Source/R2

1

0x0363

19

846.5 mS

847.0 mS

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

20

1,167 S

1,168 S

T->

PS_RDY

SOP

DFP/Source/R2

2

0x0566

21

1,168 S

1,168 S

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

25

2,639 S

2,639 S

T->

Hard_Reset

HARD_RESET

NONE/NONE/R-

0

0x0000

27

2,761 S

2,761 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Unattached_SRC

0x0000

28

2,761 S

2,761 S

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

29

2,761 S

2,761 S

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

30

3,760 S

3,760 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

31

3,762 S

3,762 S

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

32

3,762 S

3,762 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

33

3,912 S

3,912 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

34

4,554 S

4,555 S

<-D

Hard_Reset

HARD_RESET

NONE/NONE/R-

0

0x0000

36

4,672 S

4,672 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Unattached_SRC

0x0000

37

4,672 S

4,672 S

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

38

4,673 S

4,673 S

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

39

5,671 S

5,671 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

40

5,673 S

5,673 S

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

41

5,673 S

5,673 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

42

5,823 S

5,823 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

43

5,865 S

5,865 S

T->

SourceCap

SOP

DFP/Source/R2

0

 FS: 5V ,1A;

0x1161

0x0A-0x90-0x01-0x3A-

44

5,865 S

5,866 S

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

45

5,870 S

5,871 S

<-D

Request

SOP

UFP/Sink/R2

0

PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A

0x1042

0x2C-0x29-0x00-0x15-

46

5,871 S

5,871 S

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

47

5,871 S

5,872 S

T->

Accept

SOP

DFP/Source/R2

1

0x0363

48

5,872 S

5,872 S

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

49

6,192 S

6,193 S

T->

PS_RDY

SOP

DFP/Source/R2

2

0x0566

50

6,193 S

6,193 S

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

51

6,204 S

6,204 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

52

6,204 S

6,204 S

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

53

6,206 S

6,206 S

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

54

7,206 S

7,206 S

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

59

7,206 S

7,206 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

60

7,206 S

7,206 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

61

7,207 S

7,207 S

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

62

7,207 S

7,207 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

63

7,358 S

7,358 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

65

7,405 S

7,406 S

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V ,1A;

0x11A1

0x0A-0x90-0x01-0x28-

66

7,406 S

7,406 S

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

67

7,410 S

7,411 S

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A

0x1082

0x2C-0x29-0x80-0x15-

68

7,411 S

7,411 S

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

69

7,413 S

7,414 S

T->

Accept

SOP

DFP/Source/R3

1

0x03A3

70

7,414 S

7,414 S

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

71

7,735 S

7,736 S

T->

PS_RDY

SOP

DFP/Source/R3

2

0x05A6

72

7,736 S

7,736 S

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

74

7,736 S

7,736 S

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

76

9,207 S

9,207 S

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

77

9,207 S

9,207 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

81

9,227 S

9,227 S

T->

Hard_Reset

HARD_RESET

NONE/NONE/R-

0

0x0000

84

9,352 S

9,352 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Unattached_SRC

0x0000

85

9,352 S

9,352 S

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

86

9,352 S

9,352 S

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

87

10.35 S

10.35 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

88

10.35 S

10.35 S

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

89

10.35 S

10.35 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

90

10.50 S

10.50 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

92

11.14 S

11.15 S

<-D

Hard_Reset

HARD_RESET

NONE/NONE/R-

0

0x0000

95

11.27 S

11.27 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Unattached_SRC

0x0000

96

11.27 S

11.27 S

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

97

11.27 S

11.27 S

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

98

12.27 S

12.27 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

99

12.27 S

12.27 S

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

100

12.27 S

12.27 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

101

12.42 S

12.42 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

103

12.46 S

12.46 S

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V ,1A;

0x11A1

0x0A-0x90-0x01-0x3A-

104

12.46 S

12.46 S

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

105

12.47 S

12.47 S

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A

0x1082

0x2C-0x29-0x80-0x15-

106

12.47 S

12.47 S

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

107

12.47 S

12.47 S

T->

Accept

SOP

DFP/Source/R3

1

0x03A3

108

12.47 S

12.47 S

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

109

12.79 S

12.79 S

T->

PS_RDY

SOP

DFP/Source/R3

2

0x05A6

110

12.79 S

12.79 S

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

112

12.79 S

12.79 S

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

114

12.80 S

12.80 S

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

115

12.80 S

12.80 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

116

12.82 S

12.82 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

117

12.82 S

12.82 S

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

118

12.83 S

12.83 S

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

AMS Summary

AMS Index

AMS Name

AMS Start

AMS Stop

AMS Status

Child AMS Count

0

Power_Negotiation

14

21

COMPLETE

0

1

Hard_Reset

25

25

COMPLETE

0

2

Hard_Reset

34

34

COMPLETE

0

3

Power_Negotiation

43

50

COMPLETE

0

4

Power_Negotiation

65

72

COMPLETE

0

5

Hard_Reset

81

81

COMPLETE

0

6

Hard_Reset

92

92

COMPLETE

0

7

Power_Negotiation

103

110

COMPLETE

0

DUT Information

Manufacturer

Parrot

Model Number

MPPUA2

Serial Number

1

Test Information

Test Lab

Test_Engineer

Test_Engineer

Remarks

Remarks

Date_and_Time

14/10/2025 17:33:32

Controller and Instrument Information

Parameter

Value

GRL_USB_PD_Controller_Serial_No

397.409.397.077.376.

GRL_USB_PD_Software_Version

1.6.28.0

GRL_USB_PD_Firmware_Version

2.2.65

GRL USB-PD Ethernet Buffer Size

62K

GRL USB-PD Eload Firmware Version

9.8 / 9.8

Calibration

Calibration Success

RX mask Power selection

Neutral Power

Device_Type

Consumer Only

Cable Type

GRL_SPL_CABLE_1

Impedance (milli ohm)

0

PD_Merged CTS Version

v.Q4-2024

USB_PD_Spec Version

Rev3.2 Ver1.1RC2

USB_Type_C_Spec Version

v2.3 Oct-2023

VIF_File_Name

Parrot__MPPUA2__1__0_14_10_2025.xml

Noise Pattern Generation:

Two-Tone Noise

Application mode

Informational

Disabled all Pop-up during test execution

False

Pop-up Timer

0

Rerun Enabled

False

Rerun Count

1

Rerun Iteration

0

UI Live Update

False

Execution Time(In Minutes)

1

Power Delivery 3.1 Tests Information

Parameter

Value

Connect EPR Test Fixture

False

FR_Swap AUTO Box Connected

False