C2 Compliance Test Report



Power Delivery 3.1 Tests- Result Summary

Sl No

Test ID

Test Name

Test Result

1

TEST.PD.PROT.SNK.3

TEST.PD.PROT.SNK.3 SinkWaitCapTimer Deadline

PASS

Power Delivery 3.1 Tests - Detailed Test Result

Test Status

Test Description

  PASS

  1. TEST.PD.PROT.SNK.3 SinkWaitCapTimer Deadline

  PASS

 COMMON.PROC.BU.2:

  PASS

 COMMON.PROC.BU.2 - REVISION_2_0 Rev2Snk:

 

                    SourceCap Packet14

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet28

  PASS

 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk:

 

                    SourceCap Packet62

  PASS

                          UUT should respond with request - - COMMON.PROC.BU.2#1:

 

                                   Request Packet73

  PASS

 Rev2Snk:

  PASS

                          Hard_Reset check - TEST.PD.PROT.SNK.3#1:

 

                                   Tester sent Hard_Reset message
                                    Packet 37
                                   Tester sent SourceCap message
                                    Packet 39
                                   Tester transmits SourceCap within tTypeCSinkWaitCap min (0,31) S

  PASS

                          Request message check - TEST.PD.PROT.SNK.3#2:

 

                                   PASS : UUT sent Request message at protocol index 42

  PASS

 Rev3ChkdSnk:

  PASS

                          Hard_Reset check - TEST.PD.PROT.SNK.3#1:

 

                                   Tester sent Hard_Reset message
                                    Packet 87
                                   Tester sent SourceCap message
                                    Packet 90
                                   Tester transmits SourceCap within tTypeCSinkWaitCap min (0,31) S
                                   Tester Rp set to SinkTxNG(1.5A)

  PASS

                          Request message check - TEST.PD.PROT.SNK.3#2:

 

                                   PASS : UUT sent Request message at protocol index 95

Packet List (Click to View AMS Summary)

Index

   Start time(s.ms.μs.ns)

   Stop time(s.ms.μs.ns)

Message Origin

 Message

 

 Secondary Message

 SOP

 Port Type

 Msg ID

 PDO

 Header(MSB to LSB)

 Payload(LSB to MSB)

TEST_PD_PROT_SNK_3_SinkWaitCapTimer_Deadline

Port A Packet Details

4

633.2 mS

633.2 mS

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

9

633.3 mS

633.3 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

10

633.4 mS

633.4 mS

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

11

635.1 mS

635.1 mS

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

12

635.1 mS

635.1 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

13

785.2 mS

785.2 mS

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

14

827.3 mS

827.9 mS

T->

SourceCap

SOP

DFP/Source/R2

0

 FS: 5V ,1A;

0x1161

0x0A-0x90-0x01-0x28-

15

829.9 mS

830.5 mS

T->

SourceCap

SOP

DFP/Source/R2

0

 FS: 5V ,1A;

0x1161

0x0A-0x90-0x01-0x28-

16

832.4 mS

833.0 mS

T->

SourceCap

SOP

DFP/Source/R2

0

 FS: 5V ,1A;

0x1161

0x0A-0x90-0x01-0x28-

17

835.0 mS

835.6 mS

T->

SourceCap

SOP

DFP/Source/R2

0

 FS: 5V ,1A;

0x1161

0x0A-0x90-0x01-0x28-

18

936.7 mS

937.3 mS

T->

SourceCap

SOP

DFP/Source/R2

1

 FS: 5V ,1A;

0x1361

0x0A-0x90-0x01-0x28-

19

939.2 mS

939.8 mS

T->

SourceCap

SOP

DFP/Source/R2

1

 FS: 5V ,1A;

0x1361

0x0A-0x90-0x01-0x28-

20

941.8 mS

942.4 mS

T->

SourceCap

SOP

DFP/Source/R2

1

 FS: 5V ,1A;

0x1361

0x0A-0x90-0x01-0x28-

21

944.3 mS

944.9 mS

T->

SourceCap

SOP

DFP/Source/R2

1

 FS: 5V ,1A;

0x1361

0x0A-0x90-0x01-0x28-

22

1,047 S

1,047 S

T->

SourceCap

SOP

DFP/Source/R2

2

 FS: 5V ,1A;

0x1561

0x0A-0x90-0x01-0x28-

23

1,049 S

1,050 S

T->

SourceCap

SOP

DFP/Source/R2

2

 FS: 5V ,1A;

0x1561

0x0A-0x90-0x01-0x28-

24

1,052 S

1,052 S

T->

SourceCap

SOP

DFP/Source/R2

2

 FS: 5V ,1A;

0x1561

0x0A-0x90-0x01-0x28-

25

1,054 S

1,055 S

T->

SourceCap

SOP

DFP/Source/R2

2

 FS: 5V ,1A;

0x1561

0x0A-0x90-0x01-0x28-

26

1,157 S

1,157 S

T->

SourceCap

SOP

DFP/Source/R2

3

 FS: 5V ,1A;

0x1761

0x0A-0x90-0x01-0x28-

27

1,157 S

1,158 S

<-D

GoodCRC

SOP

UFP/Sink/R2

3

0x0641

28

1,162 S

1,163 S

<-D

Request

SOP

UFP/Sink/R2

0

PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A

0x1042

0x2C-0x29-0x00-0x15-

29

1,163 S

1,163 S

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

30

1,163 S

1,164 S

T->

Accept

SOP

DFP/Source/R2

4

0x0963

31

1,164 S

1,164 S

<-D

GoodCRC

SOP

UFP/Sink/R2

4

0x0841

32

1,484 S

1,485 S

T->

PS_RDY

SOP

DFP/Source/R2

5

0x0B66

33

1,485 S

1,485 S

<-D

GoodCRC

SOP

UFP/Sink/R2

5

0x0A41

37

2,636 S

2,636 S

T->

Hard_Reset

HARD_RESET

NONE/NONE/R-

0

0x0000

40

3,791 S

3,792 S

T->

SourceCap

SOP

DFP/Source/R2

0

 FS: 5V ,1A;

0x1161

0x0A-0x90-0x01-0x08-

40

3,901 S

3,901 S

T->

SourceCap

SOP

DFP/Source/R2

0

 FS: 5V ,1A;

0x1161

0x0A-0x90-0x01-0x08-

41

3,901 S

3,902 S

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

42

3,906 S

3,907 S

<-D

Request

SOP

UFP/Sink/R2

0

PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A

0x1042

0x2C-0x29-0x00-0x15-

43

3,907 S

3,907 S

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

44

3,907 S

3,908 S

T->

Accept

SOP

DFP/Source/R2

1

0x0363

45

3,908 S

3,908 S

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

46

4,228 S

4,228 S

T->

PS_RDY

SOP

DFP/Source/R2

2

0x0566

47

4,228 S

4,229 S

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

48

4,641 S

4,641 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

49

4,641 S

4,641 S

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

50

4,643 S

4,643 S

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

51

5,642 S

5,642 S

T->

Ra_Asserted

NONE

NONE/NONE/R-

0

Ra_CC2

0x0000

56

5,642 S

5,642 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Disabled -> FSM_State_Unattached_SRC

0x0000

57

5,642 S

5,642 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

58

5,644 S

5,644 S

T->

Attach

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/-

0

Rp_12k_1_5A_Asserted

0x0000

59

5,644 S

5,644 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC

0x0000

60

5,794 S

5,794 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC

0x0000

62

5,841 S

5,841 S

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V ,1A;

0x11A1

0x0A-0x90-0x01-0x28-

63

5,843 S

5,844 S

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V ,1A;

0x11A1

0x0A-0x90-0x01-0x28-

64

5,846 S

5,846 S

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V ,1A;

0x11A1

0x0A-0x90-0x01-0x28-

65

5,951 S

5,951 S

T->

SourceCap

SOP

DFP/Source/R3

1

 FS: 5V ,1A;

0x13A1

0x0A-0x90-0x01-0x28-

66

5,953 S

5,954 S

T->

SourceCap

SOP

DFP/Source/R3

1

 FS: 5V ,1A;

0x13A1

0x0A-0x90-0x01-0x28-

67

5,956 S

5,956 S

T->

SourceCap

SOP

DFP/Source/R3

1

 FS: 5V ,1A;

0x13A1

0x0A-0x90-0x01-0x28-

68

6,061 S

6,061 S

T->

SourceCap

SOP

DFP/Source/R3

2

 FS: 5V ,1A;

0x15A1

0x0A-0x90-0x01-0x28-

69

6,063 S

6,064 S

T->

SourceCap

SOP

DFP/Source/R3

2

 FS: 5V ,1A;

0x15A1

0x0A-0x90-0x01-0x28-

70

6,066 S

6,066 S

T->

SourceCap

SOP

DFP/Source/R3

2

 FS: 5V ,1A;

0x15A1

0x0A-0x90-0x01-0x28-

71

6,171 S

6,171 S

T->

SourceCap

SOP

DFP/Source/R3

3

 FS: 5V ,1A;

0x17A1

0x0A-0x90-0x01-0x28-

72

6,171 S

6,172 S

<-D

GoodCRC

SOP

UFP/Sink/R2

3

0x0641

73

6,176 S

6,177 S

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A

0x1082

0x2C-0x29-0x80-0x15-

74

6,177 S

6,177 S

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

75

6,179 S

6,179 S

T->

Accept

SOP

DFP/Source/R3

4

0x09A3

76

6,179 S

6,180 S

<-D

GoodCRC

SOP

UFP/Sink/R2

4

0x0841

77

6,501 S

6,501 S

T->

PS_RDY

SOP

DFP/Source/R3

5

0x0BA6

78

6,501 S

6,502 S

<-D

GoodCRC

SOP

UFP/Sink/R2

5

0x0A41

80

6,502 S

6,502 S

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

82

7,644 S

7,644 S

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

83

7,644 S

7,644 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

87

7,664 S

7,664 S

T->

Hard_Reset

HARD_RESET

NONE/NONE/R-

0

0x0000

91

8,824 S

8,824 S

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V ,1A;

0x11A1

0x0A-0x90-0x01-0x08-

92

8,826 S

8,826 S

T->

Rp_Asserted

Rp_4_7k_3A_Asserted

NONE

NONE/NONE/R-

0

Rp_4_7k_3A_Asserted

0x0000

93

8,934 S

8,934 S

T->

SourceCap

SOP

DFP/Source/R3

0

 FS: 5V ,1A;

0x11A1

0x0A-0x90-0x01-0x08-

94

8,934 S

8,935 S

<-D

GoodCRC

SOP

UFP/Sink/R2

0

0x0041

95

8,939 S

8,940 S

<-D

Request

SOP

UFP/Sink/R3

0

PDO#1 Fixed; OpCurrent = 0,1A; MaxCurrent = 3A

0x1082

0x2C-0x29-0x80-0x15-

96

8,940 S

8,940 S

T->

GoodCRC

SOP

DFP/Source/R1

0

0x0121

97

8,942 S

8,942 S

T->

Accept

SOP

DFP/Source/R3

1

0x03A3

98

8,942 S

8,943 S

<-D

GoodCRC

SOP

UFP/Sink/R2

1

0x0241

99

9,264 S

9,264 S

T->

PS_RDY

SOP

DFP/Source/R3

2

0x05A6

100

9,264 S

9,265 S

<-D

GoodCRC

SOP

UFP/Sink/R2

2

0x0441

102

9,670 S

9,670 S

<-D

Rd_Detected

NONE

NONE/NONE/R-

0

Rd in CC1;

0x0000

104

9,670 S

9,670 S

T->

Rp_Asserted

Rp_12k_1_5A_Asserted

NONE

NONE/NONE/R-

0

Rp_12k_1_5A_Asserted

0x0000

105

9,691 S

9,691 S

T->

FSM_State_Transition

NONE

NONE/NONE/R-

0

FSM_State_Attached_SRC -> FSM_State_Disabled

0x0000

106

9,691 S

9,691 S

T->

Detach

NONE

NONE/NONE/-

0

NONE

0x0000

107

9,693 S

9,693 S

<-D

NONE

LOAD_CURRENT

NONE

NONE/NONE/R-

0

LOAD_CURRENT:0A

0x0000

AMS Summary

AMS Index

AMS Name

AMS Start

AMS Stop

AMS Status

Child AMS Count

0

Power_Negotiation

14

33

COMPLETE

0

1

Hard_Reset

37

47

COMPLETE

0

2

Power_Negotiation

62

78

COMPLETE

0

3

Hard_Reset

87

100

COMPLETE

0

DUT Information

Manufacturer

Parrot

Model Number

MPPUA2

Serial Number

1

Test Information

Test Lab

Test_Engineer

Test_Engineer

Remarks

Remarks

Date_and_Time

14/10/2025 17:20:50

Controller and Instrument Information

Parameter

Value

GRL_USB_PD_Controller_Serial_No

397.409.397.077.376.

GRL_USB_PD_Software_Version

1.6.28.0

GRL_USB_PD_Firmware_Version

2.2.65

GRL USB-PD Ethernet Buffer Size

62K

GRL USB-PD Eload Firmware Version

9.8 / 9.8

Calibration

Calibration Success

RX mask Power selection

Neutral Power

Device_Type

Consumer Only

Cable Type

GRL_SPL_CABLE_1

Impedance (milli ohm)

0

PD_Merged CTS Version

v.Q4-2024

USB_PD_Spec Version

Rev3.2 Ver1.1RC2

USB_Type_C_Spec Version

v2.3 Oct-2023

VIF_File_Name

Parrot__MPPUA2__1__0_14_10_2025.xml

Noise Pattern Generation:

Two-Tone Noise

Application mode

Informational

Disabled all Pop-up during test execution

False

Pop-up Timer

0

Rerun Enabled

False

Rerun Count

1

Rerun Iteration

0

UI Live Update

False

Execution Time(In Minutes)

0

Power Delivery 3.1 Tests Information

Parameter

Value

Connect EPR Test Fixture

False

FR_Swap AUTO Box Connected

False