#======
#Executing .. AFE7950/bringup/setup.py
#Start Time 2023-11-02 11:29:53.817000 
AFE79xxLibraryPG1p0
spi - USB Instrument created.
resetDevice
Purge
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
#Done executing .. AFE7950/bringup/setup.py
#End Time 2023-11-02 11:30:01.380000
#Execution Time = 7.56300020218 s 
#================ ERRORS:0, WARNINGS:0 ================#
#======
#Executing .. AFE7950/bringup/devInit.py
#Start Time 2023-11-02 11:30:16.149000 
Power Card - USB Instrument created.
Reset the FPGA and try again.
Loaded Libraries
Refreshed GUI
#Done executing .. AFE7950/bringup/devInit.py
#End Time 2023-11-02 11:30:46.614000
#Execution Time = 30.4650001526 s 
#================ ERRORS:1, WARNINGS:0 ================#
#======
#Executing .. AFE7950/bringup/S1_OnboardClk_RX_250M_TX_FB_500M.py
#Start Time 2023-11-02 11:50:04.514000 
The External Sysref Frequency should be an integer factor of: 3.84MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 9830.4
laneRateFb: 9830.4
laneRateTx: 9830.4
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 9830.4
laneRateFb: 9830.4
laneRateTx: 9830.4
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
LMK and FPGA Configured.
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x11
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
//Firmware Version = 11000
//PG Version = 1
//Release Date [dd/mm/yy] = 10/7/19
patchSize=11697
//Patch Version = 165
//PG Version = 0
//Release Date [dd/mm/yy] = 27/11/21
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE GPIO configured.
Sysref Read as expected
###########Device DAC JESD-RX 0 Link Status###########
Serdes-FIFO error for lane 0: 1
Serdes-FIFO error for lane 1: 1
Serdes-FIFO error for lane 2: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 0; Alarms: 0xf000
###################################
###########Device DAC JESD-RX 1 Link Status###########
Serdes-FIFO error for lane 0: 1
Serdes-FIFO error for lane 1: 1
Serdes-FIFO error for lane 2: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 1; Alarms: 0xf000
###################################
AFE Configuration Complete
#Done executing .. AFE7950/bringup/S1_OnboardClk_RX_250M_TX_FB_500M.py
#End Time 2023-11-02 11:51:10.207000
#Execution Time = 65.6930000782 s 
#================ ERRORS:18, WARNINGS:1 ================#