//START: Doing AFE Config


//Device Initialization for ChipVersion: 2.0


//**********System Parameters**********


//System Parameters:
//	FRef	=	5000.0
//	FadcFb	=	2500.0
//	FadcRx	=	2500.0
//	Fdac	=	5000.0
//	LMFSHdFb	=	['22210', '22210']
//	LMFSHdRx	=	['14810', '14810', '14810', '14810']
//	LMFSHdTx	=	['14810', '14810', '14810', '14810']
//	RRFMode	=	0
//	adcDataMuxEn	=	1
//	adcSelect0	=	[0, 1, 2]
//	adcSelect1	=	[0, 1, 2]
//	auxAdcEn	=	False
//	broadcastRxNcoSel	=	0
//	broadcastTxNcoSel	=	0
//	chipId	=	1
//	chipType	=	0
//	chipVersion	=	32
//	combineDucMode	=	[0, 0]
//	continuousSysref	=	True
//	dacDataMuxEn	=	1
//	ddcFactorFb	=	[5, 5]
//	ddcFactorRx	=	[20, 20, 20, 20]
//	defaultFbDsa	=	[0, 0]
//	defaultRxDsa	=	[0, 0, 0, 0]
//	defaultTxDsa	=	[0, 0, 0, 0]
//	doSerdesAdaptationSeparately	=	False
//	ducFactorTx	=	[40, 40, 40, 40]
//	enableAdcAveragingMode	=	[False, False]
//	enableDacInterleavedMode	=	False
//	enableReliabilityDetector	=	True
//	enableRxDsaCalibration	=	False
//	enableTxDsaCalibration	=	False
//	enableTxFbLoopbackLowLatencyMode	=	[False, False]
//	executeLinkUpSequenceSeparately	=	False
//	externalClockRx	=	True
//	externalClockTx	=	True
//	fbChainSelForDsaCalib	=	0
//	fbDataMux	=	[0, 1]
//	fbDsaPerTx	=	[0, 0, 0, 0]
//	fbDsaPerTxEn	=	False
//	fbEnable	=	[False, False]
//	fbJesdTxK	=	[4, 4]
//	fbJesdTxScr	=	[True, True]
//	fbJesdTxSyncMux	=	[0, 0]
//	fbNco0	=	[3100, 2800]
//	fbNco1	=	[1800, 1900]
//	fbNco2	=	[1800, 1900]
//	fbNco3	=	[1800, 1900]
//	gpioMapping = {		'K14'	:['FBABTDD', 'FBCDTDD'],
//			'P9'	:'DAC_SYNC3',
//			'H15'	:['TXATDD', 'TXBTDD', 'TXCTDD', 'TXDTDD'],
//			'N8'	:'ADC_SYNC2',
//			'N9'	:'DAC_SYNC2',
//			'N7'	:'ADC_SYNC3',
//			'H8'	:'ADC_SYNC0',
//			'H9'	:'DAC_SYNC0',
//			'H7'	:'ADC_SYNC1',
//			'G9'	:'DAC_SYNC1',
//			'P14'	:'GLOBAL_PDN',
//			'E7'	:['RXATDD', 'RXBTDD', 'RXCTDD', 'RXDTDD'],
//			}
//	gpioOverrideValSet	=	[]
//	gpioPolarityInv	=	[]
//	halfRateModeFb	=	[False, False]
//	halfRateModeRx	=	[False, False]
//	halfRateModeTx	=	[False, False]
//	intPinsParams[0] = {		'SPI'	:True,
//			'TXBPAP'	:True,
//			'TXCPAP'	:True,
//			'JESD'	:True,
//			'TXAPAP'	:True,
//			'PLL'	:True,
//			'TXDPAP'	:True,
//			}
//	
//	intPinsParams[1] = {		'SPI'	:True,
//			'TXBPAP'	:True,
//			'TXCPAP'	:True,
//			'JESD'	:True,
//			'TXAPAP'	:True,
//			'PLL'	:True,
//			'TXDPAP'	:True,
//			}
//	
//	jesdABLvdsSync	=	True
//	jesdCDLvdsSync	=	True
//	jesdLoopbackEn	=	0
//	jesdRxK	=	[4, 4, 4, 4]
//	jesdRxLaneMux	=	[4, 1, 2, 3, 5, 0, 6, 7]
//	jesdRxProtocol	=	[0, 0]
//	jesdRxRbd	=	[3, 3]
//	jesdRxScr	=	[True, True, True, True]
//	jesdRxSyncMux	=	[0, 0, 0, 0]
//	jesdSendZeroesInTddOff	=	False
//	jesdSystemMode	=	[3, 3]
//	jesdTxIlaL	=	[4, 4, 2, 4, 4, 2]
//	jesdTxIlaLid	=	[0, 1, 2, 3, 4, 5, 6, 7]
//	jesdTxIlaM	=	[8, 8, 2, 8, 8, 2]
//	jesdTxLaneMux	=	[0, 1, 2, 3, 7, 5, 6, 4]
//	jesdTxProtocol	=	[0, 0]
//	libVersion	=	'1.11.5'
//	modeTdd	=	0
//	ncoFbMode	=	0
//	ncoFreqMode	=	'FCW'
//	ncoRxMode	=	[0, 0]
//	ncoTxMode	=	[0, 0]
//	numBandsFb	=	[0, 0]
//	numBandsRx	=	[0, 0, 0, 0]
//	numBandsTx	=	[0, 0, 0, 0]
//	numFbNCO	=	1
//	numRxNCO	=	1
//	numRxNCOB0	=	[1, 1, 1, 1]
//	numRxNCOB1	=	[1, 1, 1, 1]
//	numTxNCO	=	1
//	numTxNCOB0	=	[1, 1, 1, 1]
//	numTxNCOB1	=	[1, 1, 1, 1]
//	papParams[0] = {		'hpfWindowCntr'	:0,
//			'triggerToRampDown'	:50,
//			'triggerClearToRampUp'	:50,
//			'hpfNumSample'	:4,
//			'rampDownStartVal'	:128,
//			'enable'	:False,
//			'maNumSample'	:128,
//			'alarmPinDynamicMode'	:1,
//			'waitCounter'	:200,
//			'maWindowCntrTh'	:1,
//			'alarmMask'	:64,
//			'detectInWaitState'	:0,
//			'maThreshB0'	:90.0,
//			'maThreshB1'	:90.0,
//			'hpfWindowCntrTh'	:0,
//			'hpfEnable'	:1,
//			'amplUpdateCycles'	:2,
//			'alarmChannelMask'	:14,
//			'maWindowCntr'	:1,
//			'rampStickyMode'	:0,
//			'gainStepSize'	:5,
//			'multMode'	:0,
//			'alarmPulseGPIO'	:1000,
//			'hpfThreshComb'	:30.0,
//			'maEnable'	:1,
//			'attnStepSize'	:5,
//			'maThreshComb'	:90.0,
//			'hpfThreshB1'	:30.0,
//			'hpfThreshB0'	:30.0,
//			}
//	
//	papParams[1] = {		'hpfWindowCntr'	:0,
//			'triggerToRampDown'	:50,
//			'triggerClearToRampUp'	:50,
//			'hpfNumSample'	:4,
//			'rampDownStartVal'	:128,
//			'enable'	:False,
//			'maNumSample'	:128,
//			'alarmPinDynamicMode'	:1,
//			'waitCounter'	:200,
//			'maWindowCntrTh'	:1,
//			'alarmMask'	:64,
//			'detectInWaitState'	:0,
//			'maThreshB0'	:90.0,
//			'maThreshB1'	:90.0,
//			'hpfWindowCntrTh'	:0,
//			'hpfEnable'	:1,
//			'amplUpdateCycles'	:2,
//			'alarmChannelMask'	:14,
//			'maWindowCntr'	:1,
//			'rampStickyMode'	:0,
//			'gainStepSize'	:5,
//			'multMode'	:0,
//			'alarmPulseGPIO'	:1000,
//			'hpfThreshComb'	:30.0,
//			'maEnable'	:1,
//			'attnStepSize'	:5,
//			'maThreshComb'	:90.0,
//			'hpfThreshB1'	:30.0,
//			'hpfThreshB0'	:30.0,
//			}
//	
//	papParams[2] = {		'hpfWindowCntr'	:0,
//			'triggerToRampDown'	:50,
//			'triggerClearToRampUp'	:50,
//			'hpfNumSample'	:4,
//			'rampDownStartVal'	:128,
//			'enable'	:False,
//			'maNumSample'	:128,
//			'alarmPinDynamicMode'	:1,
//			'waitCounter'	:200,
//			'maWindowCntrTh'	:1,
//			'alarmMask'	:64,
//			'detectInWaitState'	:0,
//			'maThreshB0'	:90.0,
//			'maThreshB1'	:90.0,
//			'hpfWindowCntrTh'	:0,
//			'hpfEnable'	:1,
//			'amplUpdateCycles'	:2,
//			'alarmChannelMask'	:14,
//			'maWindowCntr'	:1,
//			'rampStickyMode'	:0,
//			'gainStepSize'	:5,
//			'multMode'	:0,
//			'alarmPulseGPIO'	:1000,
//			'hpfThreshComb'	:30.0,
//			'maEnable'	:1,
//			'attnStepSize'	:5,
//			'maThreshComb'	:90.0,
//			'hpfThreshB1'	:30.0,
//			'hpfThreshB0'	:30.0,
//			}
//	
//	papParams[3] = {		'hpfWindowCntr'	:0,
//			'triggerToRampDown'	:50,
//			'triggerClearToRampUp'	:50,
//			'hpfNumSample'	:4,
//			'rampDownStartVal'	:128,
//			'enable'	:False,
//			'maNumSample'	:128,
//			'alarmPinDynamicMode'	:1,
//			'waitCounter'	:200,
//			'maWindowCntrTh'	:1,
//			'alarmMask'	:64,
//			'detectInWaitState'	:0,
//			'maThreshB0'	:90.0,
//			'maThreshB1'	:90.0,
//			'hpfWindowCntrTh'	:0,
//			'hpfEnable'	:1,
//			'amplUpdateCycles'	:2,
//			'alarmChannelMask'	:14,
//			'maWindowCntr'	:1,
//			'rampStickyMode'	:0,
//			'gainStepSize'	:5,
//			'multMode'	:0,
//			'alarmPulseGPIO'	:1000,
//			'hpfThreshComb'	:30.0,
//			'maEnable'	:1,
//			'attnStepSize'	:5,
//			'maThreshComb'	:90.0,
//			'hpfThreshB1'	:30.0,
//			'hpfThreshB0'	:30.0,
//			}
//	
//	pllGsmMode	=	False
//	reliabilityDetectorDecayMode	=	2
//	rxChainSelForDsaCalib	=	15
//	rxDataMux	=	[0, 1, 2, 3, 4, 5, 6, 7]
//	rxDsaBandCalibMode	=	0
//	rxDsaCalibMode	=	0
//	rxDsaGainRange	=	[0, 25]
//	rxEnable	=	[True, True, True, True]
//	rxJesdTxK	=	[4, 4, 4, 4]
//	rxJesdTxScr	=	[True, True, True, True]
//	rxJesdTxSyncMux	=	[0, 0, 0, 0]
//	rxNco0	=	[[3100, 2800], [3100, 2800], [3100, 2800], [3100, 2800]]
//	rxNco1	=	[[1800, 2600], [1800, 2600], [1800, 2600], [1800, 2600]]
//	serdesFirmware	=	True
//	serdesManualCTLE	=	[6, 6, 6, 6, 6, 6, 6, 6]
//	serdesManualCTLEEn	=	False
//	serdesRxLanePolarity	=	[False, False, False, False, False, False, False, False]
//	serdesTxLanePolarity	=	[False, False, False, False, False, False, False, False]
//	serdesTxMainCursor	=	[3, 0, 0, 0, 0, 0, 0, 3]
//	serdesTxPostCursor	=	[0, 0, 0, 0, 0, 0, 0, 0]
//	serdesTxPreCursor	=	[0, 0, 0, 0, 0, 0, 0, 0]
//	setIlaParams	=	True
//	spiMode	=	1
//	syncLoopBack	=	True
//	sysrefTermination	=	0
//	txDataMux	=	[0, 1, 2, 3, 4, 5, 6, 7]
//	txDsaBandCalibMode	=	0
//	txDsaCalibMode	=	0
//	txEnable	=	[True, True, True, True]
//	txNco0	=	[[3100, 2800], [3100, 2800], [3100, 2800], [3100, 2800]]
//	txNco1	=	[[1800, 2600], [1800, 2600], [1800, 2600], [1800, 2600]]
//	txToFbMode	=	0
//	txdsaStartStop	=	[0, 29]
//	useSpiSysref	=	False
//	useTxForCalib	=	0
//	


//**********Configuration Starting**********
//	


//EXTERNAL-ACTION: Toggle HW Reset


//STEP: rstDevice/step0 

//START: Device Soft Reset and SPI Check

SPIWrite 0000,30,0,7	//global_soft_reset=0x0; 	Address(0x0[7:7])
SPIWrite 0000,b0,0,7	//global_soft_reset=0x1; 	Address(0x0[7:7])
SPIWrite 0000,30,0,7	//global_soft_reset=0x0; 	Address(0x0[7:7])
SPIWrite 0000,30,0,7	//global_4pin=0x1; 	Address(0x0[7:4])
SPIWrite 0000,30,0,7	//global_ascend=0x1; 	Address(0x0[7:5])
SPIReadCheck 0003,0,7,0a

//Read	chip_type=0xa; 	Address(0x3[7:0],0x4[7:0])

SPIReadCheck 0004,0,7,78
SPIReadCheck 0005,0,7,00

//Read	chip_id=0x78; 	Address(0x4[7:0],0x5[7:0],0x5[7:0],0x6[7:0])

SPIReadCheck 0006,0,7,20

//Read	chip_ver=0x20; 	Address(0x6[7:0],0x7[7:0])

SPIRead 0007,0,7
SPIRead 0008,0,7

//Read	vendor_id=0x451; 	Address(0x7[7:0],0x8[7:0],0x8[7:0],0x9[7:0])


//END: Device Soft Reset and SPI Check


//STEP: rstDevice/step1 

//START: Waking up device

SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 0191,00,0,7	//Property_170h_8_8=0x0; 	Address(0x191[7:0])
SPIWrite 0231,00,0,7	//Property_210h_8_8=0x0; 	Address(0x231[7:0])
SPIWrite 02d1,00,0,7	//Property_2b0h_8_8=0x0; 	Address(0x2d1[7:0])
SPIWrite 0371,00,0,7	//Property_350h_8_8=0x0; 	Address(0x371[7:0])
SPIWrite 042a,00,0,7	//Property_408h_16_16=0x0; 	Address(0x42a[7:0])
SPIWrite 04e2,00,0,7	//Property_4c0h_16_16=0x0; 	Address(0x4e2[7:0])
SPIWrite 059a,00,0,7	//Property_578h_16_16=0x0; 	Address(0x59a[7:0])
SPIWrite 0652,00,0,7	//Property_630h_16_16=0x0; 	Address(0x652[7:0])
SPIWrite 070a,00,0,7	//Property_6e8h_16_16=0x0; 	Address(0x70a[7:0])
SPIWrite 07c2,00,0,7	//Property_7a0h_16_16=0x0; 	Address(0x7c2[7:0])

//START: Setting TDD Pin in override state and setting override values.

SPIWrite 00ec,01,0,7	//Property_cch_0_0=0x1; 	Address(0xec[7:0])
SPIWrite 00f4,01,0,7	//Property_d4h_0_0=0x1; 	Address(0xf4[7:0])
SPIWrite 00e4,01,0,7	//Property_c4h_0_0=0x1; 	Address(0xe4[7:0])
SPIWrite 00ed,00,0,7	//Property_cch_11_8=0x0; 	Address(0xed[7:0])
SPIWrite 00f5,00,0,7	//Property_d4h_9_8=0x0; 	Address(0xf5[7:0])
SPIWrite 00e5,00,0,7	//Property_c4h_11_8=0x0; 	Address(0xe5[7:0])

//END: Setting TDD Pin in override state and setting override values.

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0190,03,0,7	//misc_spi_global_pdn_ctrl=0x1; 	Address(0x190[7:0])
SPIWrite 0190,01,0,7	//misc_spi_global_pdn_sig=0x0; 	Address(0x190[7:1])
SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])

WAIT 0.001

//END: Done waking up device


//START: Setting MCU Clock Div

SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 00c0,04,0,7	//Property_a0h_2_0=0x4; 	Address(0xc0[7:0])

//END: Setting MCU Clock Div


//START: Changing termination to 100 ohm


//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,01,0,7	//pll_reg_spi_req_a=0x1; 	Address(0x170[7:0])
SPIWrite 0540,00,0,7	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

SPIPoll 0171,0,0,01
SPIRead 0171,0,0

//Read	pll_reg_spi_a_ack=0x1(Meaning: );; 	Address(0x171[7:0])


//END: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 0054,81,0,7
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])

//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,00,0,7	//pll_reg_spi_req_a=0x0; 	Address(0x170[7:0])
SPIWrite 0540,00,0,7	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

//END: Requesting/releasing SPI Access to PLL Pages


//END: Changing termination to 100 ohm

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])

//STEP: efuseChain/step0 

//START: Loading Efuse Chain

SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 08a8,02,0,7	//Property_888h_7_0=0x2; 	Address(0x8a8[7:0],0x8a9[7:0])
SPIWrite 0810,01,0,7	//Property_7f0h_0_0=0x1; 	Address(0x810[7:0])
SPIWrite 0830,01,0,7	//Property_810h_0_0=0x1; 	Address(0x830[7:0])
SPIWrite 0200,00,0,7	//Property_1e0h_2_0=0x0; 	Address(0x200[7:0])
SPIWrite 0210,00,0,7	//Property_1f0h_2_0=0x0; 	Address(0x210[7:0])
SPIWrite 0814,00,0,7	//Property_7f4h_1_0=0x0; 	Address(0x814[7:0])
SPIWrite 0834,00,0,7	//Property_814h_1_0=0x0; 	Address(0x834[7:0])
SPIWrite 0814,01,0,7	//Property_7f4h_1_0=0x1; 	Address(0x814[7:0])
SPIWrite 0834,01,0,7	//Property_814h_1_0=0x1; 	Address(0x834[7:0])
SPIWrite 0810,00,0,7	//Property_7f0h_0_0=0x0; 	Address(0x810[7:0])
SPIWrite 0830,00,0,7	//Property_810h_0_0=0x0; 	Address(0x830[7:0])
SPIWrite 0810,01,0,7	//Property_7f0h_0_0=0x1; 	Address(0x810[7:0])
SPIWrite 0830,01,0,7	//Property_810h_0_0=0x1; 	Address(0x830[7:0])
SPIWrite 0200,03,0,7	//Property_1e0h_2_0=0x3; 	Address(0x200[7:0])
SPIWrite 0210,00,0,7	//Property_1f0h_2_0=0x0; 	Address(0x210[7:0])
SPIWrite 0814,03,0,7	//Property_7f4h_1_0=0x3; 	Address(0x814[7:0])
SPIWrite 0834,03,0,7	//Property_814h_1_0=0x3; 	Address(0x834[7:0])
SPIWrite 0814,00,0,7	//Property_7f4h_1_0=0x0; 	Address(0x814[7:0])
SPIWrite 0834,00,0,7	//Property_814h_1_0=0x0; 	Address(0x834[7:0])
SPIWrite 0810,00,0,7	//Property_7f0h_0_0=0x0; 	Address(0x810[7:0])
SPIWrite 0830,00,0,7	//Property_810h_0_0=0x0; 	Address(0x830[7:0])
SPIWrite 0814,00,0,7	//Property_7f4h_5_2=0x0; 	Address(0x814[7:2])
SPIWrite 0834,00,0,7	//Property_814h_5_2=0x0; 	Address(0x834[7:2])
SPIWrite 0814,1c,0,7	//Property_7f4h_5_2=0x7; 	Address(0x814[7:2])
SPIWrite 0834,1c,0,7	//Property_814h_5_2=0x7; 	Address(0x834[7:2])
SPIWrite 0814,00,0,7	//Property_7f4h_5_2=0x0; 	Address(0x814[7:2])
SPIWrite 0834,00,0,7	//Property_814h_5_2=0x0; 	Address(0x834[7:2])

WAIT 0.005

//END: Loading Efuse Chain


//START: Checking for Efuse

SPIReadCheck 0150,0,3,0f

//Read	obs_func_spi_chain_autoload_done=0xf; 	Address(0x150[7:0])

SPIReadCheck 0150,4,7,00

//Read	obs_func_spi_chain_autoload_error=0x0; 	Address(0x150[7:4])

SPIReadCheck 0160,0,3,0f

//Read	obs_func_spi_chain_autoload_done=0xf; 	Address(0x160[7:0])

SPIReadCheck 0160,4,7,00

//Read	obs_func_spi_chain_autoload_error=0x0; 	Address(0x160[7:4])


//END: Checking for Efuse


//START: enabling Efuse Clock

SPIWrite 0830,01,0,7	//Property_810h_0_0=0x1; 	Address(0x830[7:0])
SPIWrite 0810,01,0,7	//Property_7f0h_0_0=0x1; 	Address(0x810[7:0])
SPIWrite 0910,0f,0,7	//Property_8f0h_3_0=0xf; 	Address(0x910[7:0])
SPIWrite 0911,03,0,7	//Property_8f0h_9_8=0x3; 	Address(0x911[7:0])
SPIWrite 0912,0f,0,7	//Property_8f0h_19_16=0xf; 	Address(0x912[7:0])

//END: enabling Efuse Clock

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])

//STEP: mcuWakeUp/step0 
SPIWrite 0016,10,0,7	//jesd_subchip=0x1; 	Address(0x16[7:4])
SPIWrite 00c1,02,0,7	//apb_clk_div_factor=0x2; 	Address(0xc1[7:0])
SPIWrite 00c0,42,0,7	//apb_clk_sysref_sel=0x1; 	Address(0xc0[7:6])
SPIWrite 00c0,42,0,7	//apb_clk_sysref_val=0x0; 	Address(0xc0[7:7])
SPIWrite 00c0,c2,0,7	//apb_clk_sysref_val=0x1; 	Address(0xc0[7:7])
SPIWrite 00c0,42,0,7	//apb_clk_sysref_val=0x0; 	Address(0xc0[7:7])
SPIWrite 0016,00,0,7	//jesd_subchip=0x0; 	Address(0x16[7:4])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIWrite 0140,01,0,7	//Property_120h_0_0=0x1; 	Address(0x140[7:0])
SPIWrite 0140,00,0,7	//Property_120h_0_0=0x0; 	Address(0x140[7:0])

WAIT 0.001
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x2; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,02,0,7
SPIWrite 0193,01,0,7	//MACRO_OPCODE=0x1; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00fb,0,7
SPIRead 00fa,0,7
SPIRead 00f9,0,7
SPIRead 00f8,0,7

//Read	MACRO_RESULT_REG0=0x14020401; 	Address(0xf8[7:0],0xf9[7:0],0xfa[7:0],0xfb[7:0],0xfc[7:0])

SPIRead 00ff,0,7
SPIRead 00fe,0,7
SPIRead 00fd,0,7
SPIRead 00fc,0,7

//Read	MACRO_RESULT_REG1=0x36b1; 	Address(0xfc[7:0],0xfd[7:0],0xfe[7:0],0xff[7:0],0x100[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x0; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,90,0,7	//MACRO_OPCODE=0x90; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 1a28,10,0,7
SPIWrite 1a29,27,0,7
SPIWrite 1a2a,00,0,7
SPIWrite 1a2b,00,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 1a2c,10,0,7
SPIWrite 1a2d,27,0,7
SPIWrite 1a2e,00,0,7
SPIWrite 1a2f,00,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 1a30,10,0,7
SPIWrite 1a31,27,0,7
SPIWrite 1a32,00,0,7
SPIWrite 1a33,00,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 1a34,10,0,7
SPIWrite 1a35,27,0,7
SPIWrite 1a36,00,0,7
SPIWrite 1a37,00,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 03bf,00,0,7
SPIWrite 03be,4c,0,7
SPIWrite 03bd,4b,0,7
SPIWrite 03bc,40,0,7
SPIWrite 03c3,00,0,7
SPIWrite 03c2,03,0,7
SPIWrite 03c1,77,0,7
SPIWrite 03c0,c9,0,7
SPIWrite 03d0,04,0,7
SPIWrite 03ac,1d,0,7
SPIWrite 1abd,03,0,7
SPIWrite 1402,00,0,7
SPIWrite 1403,00,0,7
SPIWrite 1401,00,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,90,0,7	//MACRO_OPCODE=0x90; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])

//STEP: mcuWakeUp/step1 

//STEP: pllEfuse/step0 

//START: Enabling Temp Sense

SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 00c0,84,0,7	//Property_a0h_7_7=0x1; 	Address(0xc0[7:7])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 02a3,00,0,7	//Property_280h_31_0=0x7e; 	Address(0x2a0[7:0],0x2a1[7:0],0x2a2[7:0],0x2a3[7:0],0x2a4[7:0])
SPIWrite 02a2,00,0,7
SPIWrite 02a1,00,0,7
SPIWrite 02a0,7e,0,7
SPIWrite 02a7,01,0,7	//Property_284h_31_0=0x1000000; 	Address(0x2a4[7:0],0x2a5[7:0],0x2a6[7:0],0x2a7[7:0],0x2a8[7:0])
SPIWrite 02a6,00,0,7
SPIWrite 02a5,00,0,7
SPIWrite 02a4,00,0,7

//END: Enabling Temp Sense


//START: Loading PLL EFuse trims

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x30f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,03,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,33,0,7	//MACRO_OPCODE=0x33; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x20f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,02,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,34,0,7	//MACRO_OPCODE=0x34; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,72,0,7	//MACRO_OPCODE=0x72; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0xe0100; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,0e,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,71,0,7	//MACRO_OPCODE=0x71; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//END: Done Loading PLL EFuse trims

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x10101; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,01,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,73,0,7	//MACRO_OPCODE=0x73; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0012,01,0,7	//rxdig=0x1; 	Address(0x12[7:0])
SPIWrite 0761,0a,0,7	//Property_740h_13_12=0x0; 	Address(0x761[7:4])
SPIWrite 0012,02,0,7	//rxdig=0x2; 	Address(0x12[7:0])
SPIWrite 0761,0a,0,7	//Property_740h_13_12=0x0; 	Address(0x761[7:4])
SPIWrite 0012,04,0,7	//rxdig=0x4; 	Address(0x12[7:0])
SPIWrite 0761,0a,0,7	//Property_740h_13_12=0x0; 	Address(0x761[7:4])
SPIWrite 0012,08,0,7	//rxdig=0x8; 	Address(0x12[7:0])
SPIWrite 0761,0a,0,7	//Property_740h_13_12=0x0; 	Address(0x761[7:4])
SPIWrite 0012,00,0,7	//rxdig=0x0; 	Address(0x12[7:0])

//STEP: pllConfig/step0 

//START: Configuring PLL

SPIWrite 0015,08,0,7	//rx=0x2; 	Address(0x15[7:2])
SPIWrite 0043,00,0,7	//Property_20h_31_0=0x0; 	Address(0x40[7:0],0x41[7:0],0x42[7:0],0x43[7:0],0x44[7:0])
SPIWrite 0042,00,0,7
SPIWrite 0041,00,0,7
SPIWrite 0040,00,0,7
SPIWrite 0015,00,0,7	//rx=0x0; 	Address(0x15[7:2])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 00c1,60,0,7	//Property_a0h_15_13=0x3; 	Address(0xc1[7:5])

//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,01,0,7	//pll_reg_spi_req_a=0x1; 	Address(0x170[7:0])
SPIWrite 0540,00,0,7	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

SPIPoll 0171,0,0,01
SPIRead 0171,0,0

//Read	pll_reg_spi_a_ack=0x1(Meaning: );; 	Address(0x171[7:0])


//END: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 003f,00,0,7	//Property_1ch_27_27=0x0; 	Address(0x3f[7:3])
SPIWrite 0028,01,0,7	//Property_8h_0_0=0x1; 	Address(0x28[7:0])
SPIWrite 0035,10,0,7	//Property_14h_12_12=0x1; 	Address(0x35[7:4])
SPIWrite 0036,40,0,7	//Property_14h_22_22=0x1; 	Address(0x36[7:6])
SPIWrite 0038,08,0,7	//Property_18h_3_3=0x1; 	Address(0x38[7:3])
SPIWrite 0039,20,0,7	//Property_18h_13_13=0x1; 	Address(0x39[7:5])
SPIWrite 003b,08,0,7	//Property_18h_27_27=0x1; 	Address(0x3b[7:3])
SPIWrite 0046,40,0,7	//Property_24h_21_21=0x0; 	Address(0x46[7:5])
SPIWrite 0046,00,0,7	//Property_24h_22_22=0x0; 	Address(0x46[7:6])
SPIWrite 0043,08,0,7	//Property_20h_28_28=0x0; 	Address(0x43[7:4])
SPIWrite 0043,00,0,7	//Property_20h_27_27=0x0; 	Address(0x43[7:3])
SPIWrite 004c,00,0,7	//Property_2ch_3_0=0x0; 	Address(0x4c[7:0])
SPIWrite 003c,c0,0,7	//Property_1ch_5_5=0x0; 	Address(0x3c[7:5])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 010c,00,0,7	//EN_REFDIV_DMP=0x0; 	Address(0x10c[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 003c,40,0,7	//Property_1ch_7_7=0x0; 	Address(0x3c[7:7])
SPIWrite 003c,00,0,7	//Property_1ch_6_6=0x0; 	Address(0x3c[7:6])
SPIWrite 003d,00,0,7	//Property_1ch_8_8=0x0; 	Address(0x3d[7:0])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 010d,01,0,7	//CTL_REFDIV_DIV=0x1; 	Address(0x10d[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 0056,43,0,7	//Property_34h_22_22=0x1; 	Address(0x56[7:6])
SPIWrite 0056,c3,0,7	//Property_34h_23_23=0x1; 	Address(0x56[7:7])
SPIWrite 0056,cb,0,7	//Property_34h_19_19=0x1; 	Address(0x56[7:3])
SPIWrite 0056,eb,0,7	//Property_34h_21_20=0x2; 	Address(0x56[7:4])
SPIWrite 0057,02,0,7	//Property_34h_25_25=0x1; 	Address(0x57[7:1])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 07f5,01,0,7	//Property_7d4h_15_0=0x1df; 	Address(0x7f4[7:0],0x7f5[7:0],0x7f6[7:0])
SPIWrite 07f4,df,0,7
SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 006d,01,0,7	//LCMGEN_DIV=0x1df; 	Address(0x6c[7:0],0x6d[7:0],0x6e[7:0])
SPIWrite 006c,df,0,7
SPIWrite 0062,00,0,7	//Property_40h_23_20=0x0; 	Address(0x62[7:4])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 010f,01,0,7	//CTL_FBDIV_DIV=0x1; 	Address(0x10f[7:0])
SPIWrite 010e,00,0,7	//CTL_FBDIV_DIVBY2=0x0; 	Address(0x10e[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 004d,c0,0,7	//Property_2ch_14_14=0x1; 	Address(0x4d[7:6])
SPIWrite 0050,fe,0,7	//Property_30h_2_1=0x3; 	Address(0x50[7:1])
SPIWrite 0050,fe,0,7	//Property_30h_4_3=0x3; 	Address(0x50[7:3])
SPIWrite 0050,fe,0,7	//Property_30h_6_5=0x3; 	Address(0x50[7:5])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 0110,02,0,7	//CTL_OUTDIV_MUX_TX=0x2; 	Address(0x110[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 0051,3d,0,7	//Property_30h_9_9=0x0; 	Address(0x51[7:1])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 0111,00,0,7	//CTL_OUTDIV_DIV_TX=0x0; 	Address(0x111[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 007f,40,0,7	//Property_5ch_30_30=0x1; 	Address(0x7f[7:6])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 0112,03,0,7	//CTL_OUTDIV_MUX_RX=0x3; 	Address(0x112[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 0051,3d,0,7	//Property_30h_10_10=0x1; 	Address(0x51[7:2])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 0113,01,0,7	//CTL_OUTDIV_DIV_RX=0x1; 	Address(0x113[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 007f,c0,0,7	//Property_5ch_31_31=0x1; 	Address(0x7f[7:7])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 0114,01,0,7	//CTL_OUTDIV_MUX_FB=0x1; 	Address(0x114[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 0051,3d,0,7	//Property_30h_11_11=0x1; 	Address(0x51[7:3])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 0115,01,0,7	//CTL_OUTDIV_DIV_FB=0x1; 	Address(0x115[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 0051,2d,0,7	//Property_30h_12_12=0x0; 	Address(0x51[7:4])
SPIWrite 0063,01,0,7	//Property_40h_27_24=0x1; 	Address(0x63[7:0])
SPIWrite 0072,02,0,7	//Property_50h_23_16=0x2; 	Address(0x72[7:0],0x73[7:0])
SPIWrite 006f,04,0,7	//Property_4ch_31_24=0x4; 	Address(0x6f[7:0],0x70[7:0])
SPIWrite 0070,02,0,7	//Property_50h_7_0=0x2; 	Address(0x70[7:0],0x71[7:0])
SPIWrite 0071,02,0,7	//Property_50h_15_8=0x2; 	Address(0x71[7:0],0x72[7:0])
SPIWrite 006d,01,0,7	//LCMGEN_DIV=0x1df; 	Address(0x6c[7:0],0x6d[7:0],0x6e[7:0])
SPIWrite 006c,df,0,7
SPIWrite 007c,04,0,7	//Property_5ch_6_0=0x4; 	Address(0x7c[7:0])
SPIWrite 0055,ff,0,7	//Property_34h_8_8=0x1; 	Address(0x55[7:0])
SPIWrite 0055,ff,0,7	//Property_34h_15_15=0x1; 	Address(0x55[7:7])
SPIWrite 0055,ff,0,7	//Property_34h_9_9=0x1; 	Address(0x55[7:1])
SPIWrite 0055,ff,0,7	//Property_34h_13_10=0xf; 	Address(0x55[7:2])
SPIWrite 0055,ff,0,7	//Property_34h_14_14=0x1; 	Address(0x55[7:6])
SPIWrite 0059,01,0,7	//Property_38h_8_8=0x1; 	Address(0x59[7:0])
SPIWrite 0058,80,0,7	//Property_38h_7_7=0x1; 	Address(0x58[7:7])
SPIWrite 0059,01,0,7	//Property_38h_10_10=0x0; 	Address(0x59[7:2])
SPIWrite 0059,01,0,7	//Property_38h_11_11=0x0; 	Address(0x59[7:3])
SPIWrite 005c,10,0,7	//Property_3ch_7_3=0x2; 	Address(0x5c[7:3])
SPIWrite 005d,00,0,7	//Property_3ch_10_9=0x0; 	Address(0x5d[7:1])
SPIWrite 005d,08,0,7	//Property_3ch_11_11=0x1; 	Address(0x5d[7:3])
SPIWrite 003d,01,0,7	//Property_1ch_8_8=0x1; 	Address(0x3d[7:0])
SPIWrite 0053,03,0,7	//Property_30h_25_24=0x3; 	Address(0x53[7:0])
SPIWrite 0052,00,0,7	//Property_30h_22_21=0x0; 	Address(0x52[7:5])
SPIWrite 0065,22,0,7	//Property_44h_11_10=0x0; 	Address(0x65[7:2])
SPIWrite 0052,00,0,7	//Property_30h_16_16=0x0; 	Address(0x52[7:0])
SPIWrite 0052,00,0,7	//Property_30h_20_20=0x0; 	Address(0x52[7:4])
SPIWrite 0053,03,0,7	//Property_30h_27_26=0x0; 	Address(0x53[7:2])
SPIWrite 005e,00,0,7	//Property_3ch_18_17=0x0; 	Address(0x5e[7:1])
SPIWrite 0052,00,0,7	//Property_30h_19_19=0x0; 	Address(0x52[7:3])
SPIWrite 0052,00,0,7	//Property_30h_23_23=0x0; 	Address(0x52[7:7])
SPIWrite 003e,00,0,7	//Property_1ch_20_20_1ch_25_25=0x0; 	Address(0x3e[7:4],0x3f[7:1])
SPIWrite 003f,00,0,7
SPIWrite 0065,20,0,7	//Property_44h_9_8=0x0; 	Address(0x65[7:0])
SPIWrite 0087,00,0,7	//Property_64h_30_29=0x0; 	Address(0x87[7:5])
SPIWrite 005e,00,0,7	//Property_3ch_20_19=0x0; 	Address(0x5e[7:3])
SPIWrite 0087,00,0,7	//Property_64h_26_25=0x0; 	Address(0x87[7:1])
SPIWrite 0087,00,0,7	//Property_64h_28_27=0x0; 	Address(0x87[7:3])
SPIWrite 003e,00,0,7	//Property_1ch_17_16=0x0; 	Address(0x3e[7:0])
SPIWrite 0051,2d,0,7	//Property_30h_15_14=0x0; 	Address(0x51[7:6])
SPIWrite 0052,00,0,7	//Property_30h_18_17=0x0; 	Address(0x52[7:1])
SPIWrite 0065,00,0,7	//Property_44h_13_12=0x0; 	Address(0x65[7:4])
SPIWrite 0084,10,0,7	//Property_64h_5_4=0x1; 	Address(0x84[7:4])
SPIWrite 0084,90,0,7	//Property_64h_7_6=0x2; 	Address(0x84[7:6])
SPIWrite 0069,47,0,7	//Property_48h_15_8=0x47; 	Address(0x69[7:0],0x6a[7:0])
SPIWrite 0045,20,0,7	//Property_24h_13_13=0x1; 	Address(0x45[7:5])
SPIWrite 0032,00,0,7	//Property_10h_19_18=0x0; 	Address(0x32[7:2])
SPIWrite 0049,38,0,7	//Property_28h_13_11=0x7; 	Address(0x49[7:3])
SPIWrite 0049,3d,0,7	//Property_28h_10_8=0x5; 	Address(0x49[7:0])
SPIWrite 004a,00,0,7	//Property_28h_21_19=0x0; 	Address(0x4a[7:3])
SPIWrite 004b,00,0,7	//Property_28h_30_28=0x0; 	Address(0x4b[7:4])
SPIWrite 004d,c0,0,7	//Property_2ch_9_8=0x0; 	Address(0x4d[7:0])
SPIWrite 004a,06,0,7	//Property_28h_18_16=0x6; 	Address(0x4a[7:0])
SPIWrite 004b,0a,0,7	//Property_28h_27_24=0xa; 	Address(0x4b[7:0])
SPIWrite 0040,20,0,7	//Property_20h_7_5=0x1; 	Address(0x40[7:5])
SPIWrite 0041,00,0,7	//Property_20h_10_9=0x0; 	Address(0x41[7:1])
SPIWrite 0043,e0,0,7	//Property_20h_31_29=0x7; 	Address(0x43[7:5])
SPIWrite 0075,08,0,7	//Property_54h_12_11=0x1; 	Address(0x75[7:3])
SPIWrite 0075,0a,0,7	//Property_54h_10_8=0x2; 	Address(0x75[7:0])
SPIWrite 0045,24,0,7	//Property_24h_11_8=0x4; 	Address(0x45[7:0])
SPIWrite 0031,00,0,7	//Property_10h_15_14=0x0; 	Address(0x31[7:6])
SPIWrite 0046,03,0,7	//Property_24h_17_16=0x3; 	Address(0x46[7:0])
SPIWrite 0045,24,0,7	//Property_24h_15_14=0x0; 	Address(0x45[7:6])
SPIWrite 0064,07,0,7	//Property_44h_4_0=0x7; 	Address(0x64[7:0])
SPIWrite 0065,00,0,7	//Property_44h_14_14=0x0; 	Address(0x65[7:6])
SPIWrite 004e,00,0,7	//Property_2ch_16_16=0x0; 	Address(0x4e[7:0])
SPIWrite 002d,00,0,7	//Property_ch_13_12=0x0; 	Address(0x2d[7:4])
SPIWrite 0035,b0,0,7	//Property_14h_15_13=0x5; 	Address(0x35[7:5])
SPIWrite 003e,00,0,7	//Property_1ch_19_18=0x0; 	Address(0x3e[7:2])
SPIWrite 0073,00,0,7	//Property_50h_29_29=0x0; 	Address(0x73[7:5])
SPIWrite 0056,eb,0,7	//Property_34h_17_17=0x1; 	Address(0x56[7:1])
SPIWrite 0058,84,0,7	//Property_38h_2_2=0x1; 	Address(0x58[7:2])
SPIWrite 0062,00,0,7	//Property_40h_23_20=0x0; 	Address(0x62[7:4])
SPIWrite 0066,00,0,7	//Property_44h_16_16=0x0; 	Address(0x66[7:0])
SPIWrite 0066,01,0,7	//Property_44h_16_16=0x1; 	Address(0x66[7:0])

WAIT 0.001
SPIWrite 0066,03,0,7	//Property_44h_17_17=0x1; 	Address(0x66[7:1])

WAIT 0.005
SPIWrite 0063,41,0,7	//CLR_FLAG_LOCK_LOST=0x1; 	Address(0x63[7:6])
SPIWrite 0063,01,0,7	//CLR_FLAG_LOCK_LOST=0x0; 	Address(0x63[7:6])

WAIT 0.001
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 00bb,00,0,7	//Property_98h_31_0=0x600; 	Address(0xb8[7:0],0xb9[7:0],0xba[7:0],0xbb[7:0],0xbc[7:0])
SPIWrite 00ba,00,0,7
SPIWrite 00b9,06,0,7
SPIWrite 00b8,00,0,7
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 0066,01,0,7	//Property_44h_17_17=0x0; 	Address(0x66[7:1])
SPIWrite 0063,81,0,7	//CLR_FLAG_LOCK_OUT=0x1; 	Address(0x63[7:7])
SPIWrite 0063,c1,0,7	//CLR_FLAG_LOCK_LOST=0x1; 	Address(0x63[7:6])
SPIWrite 0063,c2,0,7	//Property_40h_27_24=0x2; 	Address(0x63[7:0])

//START: Sending Sysref to device


//External-Action: Ensure Sysref is running before this point.

SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 085b,00,0,7	//Property_838h_31_0=0x0; 	Address(0x858[7:0],0x859[7:0],0x85a[7:0],0x85b[7:0],0x85c[7:0])
SPIWrite 085a,00,0,7
SPIWrite 0859,00,0,7
SPIWrite 0858,00,0,7
SPIWrite 085b,00,0,7	//Property_838h_31_0=0x101; 	Address(0x858[7:0],0x859[7:0],0x85a[7:0],0x85b[7:0],0x85c[7:0])
SPIWrite 085a,00,0,7
SPIWrite 0859,01,0,7
SPIWrite 0858,01,0,7
SPIWrite 085b,00,0,7	//Property_838h_31_0=0x0; 	Address(0x858[7:0],0x859[7:0],0x85a[7:0],0x85b[7:0],0x85c[7:0])
SPIWrite 085a,00,0,7
SPIWrite 0859,00,0,7
SPIWrite 0858,00,0,7
SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 006a,00,0,7	//Property_48h_17_17=0x0; 	Address(0x6a[7:1])
SPIWrite 006e,00,0,7	//LCMGEN_USE_SPI_SYSREF=0x0; 	Address(0x6e[7:0])
SPIWrite 006a,00,0,7	//Property_48h_17_17=0x0; 	Address(0x6a[7:1])
SPIWrite 006a,02,0,7	//Property_48h_17_17=0x1; 	Address(0x6a[7:1])
SPIWrite 0058,86,0,7	//Property_38h_1_1=0x1; 	Address(0x58[7:1])

WAIT 0.001
SPIWrite 0058,84,0,7	//Property_38h_1_1=0x0; 	Address(0x58[7:1])

//END: Sending Sysref to device

SPIWrite 0063,c0,0,7	//Property_40h_27_24=0x0; 	Address(0x63[7:0])
SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 00c1,00,0,7	//Property_a0h_15_13=0x0; 	Address(0xc1[7:5])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 0063,40,0,7	//CLR_FLAG_LOCK_OUT=0x0; 	Address(0x63[7:7])
SPIWrite 0063,00,0,7	//CLR_FLAG_LOCK_LOST=0x0; 	Address(0x63[7:6])
SPIWrite 0066,03,0,7	//Property_44h_17_17=0x1; 	Address(0x66[7:1])

//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,00,0,7	//pll_reg_spi_req_a=0x0; 	Address(0x170[7:0])
SPIWrite 0540,00,0,7	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

//END: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 010d,02,0,7	//Property_ech_15_0=0x2ed; 	Address(0x10c[7:0],0x10d[7:0],0x10e[7:0])
SPIWrite 010c,ed,0,7
SPIWrite 01ad,02,0,7	//Property_18ch_15_0=0x2ed; 	Address(0x1ac[7:0],0x1ad[7:0],0x1ae[7:0])
SPIWrite 01ac,ed,0,7
SPIWrite 024d,02,0,7	//Property_22ch_15_0=0x2ed; 	Address(0x24c[7:0],0x24d[7:0],0x24e[7:0])
SPIWrite 024c,ed,0,7
SPIWrite 02ed,02,0,7	//Property_2cch_15_0=0x2ed; 	Address(0x2ec[7:0],0x2ed[7:0],0x2ee[7:0])
SPIWrite 02ec,ed,0,7
SPIWrite 0421,01,0,7	//Property_400h_15_0=0x1f4; 	Address(0x420[7:0],0x421[7:0],0x422[7:0])
SPIWrite 0420,f4,0,7
SPIWrite 04d9,01,0,7	//Property_4b8h_15_0=0x1f4; 	Address(0x4d8[7:0],0x4d9[7:0],0x4da[7:0])
SPIWrite 04d8,f4,0,7
SPIWrite 0591,01,0,7	//Property_570h_15_0=0x1f4; 	Address(0x590[7:0],0x591[7:0],0x592[7:0])
SPIWrite 0590,f4,0,7
SPIWrite 0649,01,0,7	//Property_628h_15_0=0x1f4; 	Address(0x648[7:0],0x649[7:0],0x64a[7:0])
SPIWrite 0648,f4,0,7
SPIWrite 0701,01,0,7	//Property_6e0h_15_0=0x1f4; 	Address(0x700[7:0],0x701[7:0],0x702[7:0])
SPIWrite 0700,f4,0,7
SPIWrite 07b9,01,0,7	//Property_798h_15_0=0x1f4; 	Address(0x7b8[7:0],0x7b9[7:0],0x7ba[7:0])
SPIWrite 07b8,f4,0,7

//END: Configuring PLL

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])

//STEP: serdesConfig/step0 

//START: Enabling access to SERDES

SPIWrite 0016,10,0,7	//jesd_subchip=0x1; 	Address(0x16[7:4])
SPIWrite 00c0,42,0,7	//apb_clk_disable=0x0; 	Address(0xc0[7:0])
SPIWrite 00c0,40,0,7	//apb_clk_dithered_mode_en=0x0; 	Address(0xc0[7:1])
SPIWrite 00c4,01,0,7	//apb_clk_from_MCU_clk_en=0x1; 	Address(0xc4[7:0])
SPIWrite 0020,12,0,7	//serdesab_apb_page_addr_index=0x2; 	Address(0x20[7:0])
SPIWrite 0021,12,0,7	//serdescd_apb_page_addr_index=0x2; 	Address(0x21[7:0])
SPIWrite 0020,12,0,7	//serdesab_apb_mode_16b=0x1; 	Address(0x20[7:4])
SPIWrite 0021,12,0,7	//serdescd_apb_mode_16b=0x1; 	Address(0x21[7:4])
SPIWrite 0020,12,0,7	//serdesab_apb_pin_intf_en=0x0; 	Address(0x20[7:2])
SPIWrite 0021,12,0,7	//serdescd_apb_pin_intf_en=0x0; 	Address(0x21[7:2])
SPIWrite 0016,00,0,7	//jesd_subchip=0x0; 	Address(0x16[7:4])
SPIWrite 0016,20,0,7	//serdes_jesd=0x1; 	Address(0x16[7:5])
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE3=0x0; 	Address(0x9803[7:3])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE2=0x0; 	Address(0x9803[7:2])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE1=0x0; 	Address(0x9803[7:1])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE0=0x0; 	Address(0x9803[7:0])
SPIWrite 7006,00,0,7
SPIWrite 0016,40,0,7	//serdes_jesd=0x2; 	Address(0x16[7:5])
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE3=0x0; 	Address(0x9803[7:3])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE2=0x0; 	Address(0x9803[7:2])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE1=0x0; 	Address(0x9803[7:1])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE0=0x0; 	Address(0x9803[7:0])
SPIWrite 7006,00,0,7

//END: Done enabling access to SERDES


//START: Setting Serdes Reference Clock Divs

SPIWrite 0016,00,0,7	//serdes_jesd=0x0; 	Address(0x16[7:5])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 0107,00,0,7	//Property_e4h_31_0=0x601; 	Address(0x104[7:0],0x105[7:0],0x106[7:0],0x107[7:0],0x108[7:0])
SPIWrite 0106,00,0,7
SPIWrite 0105,06,0,7
SPIWrite 0104,01,0,7

//END: Setting Serdes Reference Clock Divs

SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])

//STEP: serdesConfig/step1 

//START: Resetting Serdes

SPIWrite 0016,20,0,7	//serdes_jesd=0x1; 	Address(0x16[7:5])
SPIWrite 701b,08,0,7	//DOMAIN_RESET=0x888; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,88,0,7
SPIWrite 701b,00,0,7	//DOMAIN_RESET=0x0; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,00,0,7
SPIWrite 701b,07,0,7	//DOMAIN_RESET=0x777; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,77,0,7
SPIWrite 701b,00,0,7	//DOMAIN_RESET=0x0; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,00,0,7

//END: Done resetting Serdes


//START: Resetting Serdes

SPIWrite 0016,40,0,7	//serdes_jesd=0x2; 	Address(0x16[7:5])
SPIWrite 701b,08,0,7	//DOMAIN_RESET=0x888; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,88,0,7
SPIWrite 701b,00,0,7	//DOMAIN_RESET=0x0; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,00,0,7
SPIWrite 701b,07,0,7	//DOMAIN_RESET=0x777; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,77,0,7
SPIWrite 701b,00,0,7	//DOMAIN_RESET=0x0; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,00,0,7

//END: Done resetting Serdes

SPIWrite 0016,00,0,7	//serdes_jesd=0x0; 	Address(0x16[7:5])

//STEP: serdesConfig/step2 

//START: Configuring the SERDES

SPIWrite 0016,10,0,7	//jesd_subchip=0x1; 	Address(0x16[7:4])
SPIWrite 00c0,40,0,7	//apb_clk_disable=0x0; 	Address(0xc0[7:0])
SPIWrite 0020,12,0,7	//serdesab_apb_page_addr_index=0x2; 	Address(0x20[7:0])
SPIWrite 0021,12,0,7	//serdescd_apb_page_addr_index=0x2; 	Address(0x21[7:0])
SPIWrite 0016,00,0,7	//jesd_subchip=0x0; 	Address(0x16[7:4])
SPIWrite 0016,60,0,7	//serdes_jesd=0x3; 	Address(0x16[7:5])
SPIWrite 7029,ff,0,7
SPIWrite 7028,f0,0,7
SPIWrite 701b,0a,0,7
SPIWrite 701a,aa,0,7
SPIWrite 701b,00,0,7
SPIWrite 701a,00,0,7
SPIWrite 7007,00,0,7
SPIWrite 7006,00,0,7
SPIWrite 0016,20,0,7	//serdes_jesd=0x1; 	Address(0x16[7:5])
SPIWrite 49f1,92,0,7
SPIWrite 49f0,00,0,7
SPIWrite 49f3,ea,0,7
SPIWrite 49f2,00,0,7
SPIWrite 49e3,e0,0,7
SPIWrite 49e2,00,0,7
SPIWrite 49b5,47,0,7
SPIWrite 49b4,47,0,7
SPIWrite 49ff,fd,0,7
SPIWrite 49fe,b0,0,7
SPIWrite 49ed,1d,0,7
SPIWrite 49ec,c0,0,7
SPIWrite 49e7,52,0,7
SPIWrite 49e6,36,0,7
SPIWrite 49e5,6e,0,7
SPIWrite 49e4,b6,0,7
SPIWrite 49df,a8,0,7
SPIWrite 49de,28,0,7
SPIWrite 49eb,0c,0,7
SPIWrite 49ea,98,0,7
SPIWrite 49e9,72,0,7
SPIWrite 49e8,44,0,7
SPIWrite 49fd,0c,0,7
SPIWrite 49fc,98,0,7
SPIWrite 49fb,72,0,7
SPIWrite 49fa,48,0,7
SPIWrite 49f9,4a,0,7
SPIWrite 49f8,66,0,7
SPIWrite 49f7,79,0,7
SPIWrite 49f6,b6,0,7
SPIWrite 49d9,6c,0,7
SPIWrite 49d8,06,0,7
SPIWrite 4201,10,0,7
SPIWrite 4200,6b,0,7
SPIWrite 4203,64,0,7
SPIWrite 4202,80,0,7
SPIWrite 4205,62,0,7
SPIWrite 4204,00,0,7
SPIWrite 4207,7b,0,7
SPIWrite 4206,33,0,7
SPIWrite 4209,70,0,7
SPIWrite 4208,0a,0,7
SPIWrite 420b,bd,0,7
SPIWrite 420a,68,0,7
SPIWrite 420d,76,0,7
SPIWrite 420c,2d,0,7
SPIWrite 420f,66,0,7
SPIWrite 420e,ab,0,7
SPIWrite 4211,d0,0,7
SPIWrite 4210,08,0,7
SPIWrite 4213,00,0,7
SPIWrite 4212,18,0,7
SPIWrite 4215,66,0,7
SPIWrite 4214,2c,0,7
SPIWrite 4217,3d,0,7
SPIWrite 4216,15,0,7
SPIWrite 4219,00,0,7
SPIWrite 4218,80,0,7
SPIWrite 421b,00,0,7
SPIWrite 421a,02,0,7
SPIWrite 421d,34,0,7
SPIWrite 421c,00,0,7
SPIWrite 421f,00,0,7
SPIWrite 421e,00,0,7
SPIWrite 4221,10,0,7
SPIWrite 4220,1a,0,7
SPIWrite 4239,03,0,7
SPIWrite 4238,40,0,7
SPIWrite 423b,00,0,7
SPIWrite 423a,60,0,7
SPIWrite 423d,00,0,7
SPIWrite 423c,00,0,7
SPIWrite 423f,00,0,7
SPIWrite 423e,00,0,7
SPIWrite 4277,00,0,7
SPIWrite 4276,00,0,7
SPIWrite 4279,00,0,7
SPIWrite 4278,00,0,7
SPIWrite 427b,00,0,7
SPIWrite 427a,00,0,7
SPIWrite 427d,00,0,7
SPIWrite 427c,00,0,7
SPIWrite 4283,9f,0,7
SPIWrite 4282,df,0,7
SPIWrite 4285,b3,0,7
SPIWrite 4284,c0,0,7
SPIWrite 428f,24,0,7
SPIWrite 428e,a2,0,7
SPIWrite 4291,cc,0,7
SPIWrite 4290,34,0,7
SPIWrite 4293,e3,0,7
SPIWrite 4292,d7,0,7
SPIWrite 4295,76,0,7
SPIWrite 4294,60,0,7
SPIWrite 4297,06,0,7
SPIWrite 4296,db,0,7
SPIWrite 4341,03,0,7
SPIWrite 4340,41,0,7
SPIWrite 43e7,00,0,7
SPIWrite 43e6,80,0,7
SPIWrite 43e9,fc,0,7
SPIWrite 43e8,00,0,7
SPIWrite 43eb,9f,0,7
SPIWrite 43ea,fe,0,7
SPIWrite 43ed,00,0,7
SPIWrite 43ec,60,0,7
SPIWrite 43ef,10,0,7
SPIWrite 43ee,00,0,7
SPIWrite 43f1,68,0,7
SPIWrite 43f0,64,0,7
SPIWrite 43f3,92,0,7
SPIWrite 43f2,30,0,7
SPIWrite 43f5,00,0,7
SPIWrite 43f4,00,0,7
SPIWrite 43f7,6d,0,7
SPIWrite 43f6,83,0,7
SPIWrite 43f9,6d,0,7
SPIWrite 43f8,b6,0,7
SPIWrite 43fb,42,0,7
SPIWrite 43fa,46,0,7
SPIWrite 43fd,62,0,7
SPIWrite 43fc,78,0,7
SPIWrite 43ff,08,0,7
SPIWrite 43fe,c8,0,7
SPIWrite 4001,10,0,7
SPIWrite 4000,6b,0,7
SPIWrite 4003,64,0,7
SPIWrite 4002,80,0,7
SPIWrite 4005,62,0,7
SPIWrite 4004,00,0,7
SPIWrite 4007,7b,0,7
SPIWrite 4006,33,0,7
SPIWrite 4009,70,0,7
SPIWrite 4008,0a,0,7
SPIWrite 400b,bd,0,7
SPIWrite 400a,68,0,7
SPIWrite 400d,76,0,7
SPIWrite 400c,2d,0,7
SPIWrite 400f,66,0,7
SPIWrite 400e,ab,0,7
SPIWrite 4011,d0,0,7
SPIWrite 4010,08,0,7
SPIWrite 4013,00,0,7
SPIWrite 4012,18,0,7
SPIWrite 4015,66,0,7
SPIWrite 4014,2c,0,7
SPIWrite 4017,3d,0,7
SPIWrite 4016,15,0,7
SPIWrite 4019,00,0,7
SPIWrite 4018,80,0,7
SPIWrite 401b,00,0,7
SPIWrite 401a,02,0,7
SPIWrite 401d,34,0,7
SPIWrite 401c,00,0,7
SPIWrite 401f,00,0,7
SPIWrite 401e,00,0,7
SPIWrite 4021,10,0,7
SPIWrite 4020,1a,0,7
SPIWrite 4039,03,0,7
SPIWrite 4038,40,0,7
SPIWrite 403b,00,0,7
SPIWrite 403a,60,0,7
SPIWrite 403d,00,0,7
SPIWrite 403c,00,0,7
SPIWrite 403f,00,0,7
SPIWrite 403e,00,0,7
SPIWrite 4077,00,0,7
SPIWrite 4076,00,0,7
SPIWrite 4079,00,0,7
SPIWrite 4078,00,0,7
SPIWrite 407b,00,0,7
SPIWrite 407a,00,0,7
SPIWrite 407d,00,0,7
SPIWrite 407c,00,0,7
SPIWrite 4083,9f,0,7
SPIWrite 4082,df,0,7
SPIWrite 4085,b3,0,7
SPIWrite 4084,c0,0,7
SPIWrite 408f,24,0,7
SPIWrite 408e,a2,0,7
SPIWrite 4091,cc,0,7
SPIWrite 4090,34,0,7
SPIWrite 4093,e3,0,7
SPIWrite 4092,d7,0,7
SPIWrite 4095,76,0,7
SPIWrite 4094,60,0,7
SPIWrite 4097,06,0,7
SPIWrite 4096,db,0,7
SPIWrite 4141,03,0,7
SPIWrite 4140,41,0,7
SPIWrite 41e7,00,0,7
SPIWrite 41e6,80,0,7
SPIWrite 41e9,fc,0,7
SPIWrite 41e8,00,0,7
SPIWrite 41eb,9f,0,7
SPIWrite 41ea,fe,0,7
SPIWrite 41ed,00,0,7
SPIWrite 41ec,00,0,7
SPIWrite 41ef,10,0,7
SPIWrite 41ee,00,0,7
SPIWrite 41f1,68,0,7
SPIWrite 41f0,64,0,7
SPIWrite 41f3,92,0,7
SPIWrite 41f2,30,0,7
SPIWrite 41f5,00,0,7
SPIWrite 41f4,00,0,7
SPIWrite 41f7,6d,0,7
SPIWrite 41f6,83,0,7
SPIWrite 41f9,6d,0,7
SPIWrite 41f8,b6,0,7
SPIWrite 41fb,42,0,7
SPIWrite 41fa,46,0,7
SPIWrite 41fd,62,0,7
SPIWrite 41fc,78,0,7
SPIWrite 41ff,08,0,7
SPIWrite 41fe,c8,0,7
SPIWrite 4401,10,0,7
SPIWrite 4400,6b,0,7
SPIWrite 4403,64,0,7
SPIWrite 4402,80,0,7
SPIWrite 4405,62,0,7
SPIWrite 4404,00,0,7
SPIWrite 4407,7b,0,7
SPIWrite 4406,33,0,7
SPIWrite 4409,70,0,7
SPIWrite 4408,0a,0,7
SPIWrite 440b,bd,0,7
SPIWrite 440a,68,0,7
SPIWrite 440d,76,0,7
SPIWrite 440c,2d,0,7
SPIWrite 440f,66,0,7
SPIWrite 440e,ab,0,7
SPIWrite 4411,d0,0,7
SPIWrite 4410,08,0,7
SPIWrite 4413,00,0,7
SPIWrite 4412,18,0,7
SPIWrite 4415,66,0,7
SPIWrite 4414,2c,0,7
SPIWrite 4417,3d,0,7
SPIWrite 4416,15,0,7
SPIWrite 4419,00,0,7
SPIWrite 4418,80,0,7
SPIWrite 441b,00,0,7
SPIWrite 441a,02,0,7
SPIWrite 441d,34,0,7
SPIWrite 441c,00,0,7
SPIWrite 441f,00,0,7
SPIWrite 441e,00,0,7
SPIWrite 4421,10,0,7
SPIWrite 4420,1a,0,7
SPIWrite 4439,03,0,7
SPIWrite 4438,40,0,7
SPIWrite 443b,00,0,7
SPIWrite 443a,60,0,7
SPIWrite 443d,00,0,7
SPIWrite 443c,00,0,7
SPIWrite 443f,00,0,7
SPIWrite 443e,00,0,7
SPIWrite 4477,00,0,7
SPIWrite 4476,00,0,7
SPIWrite 4479,00,0,7
SPIWrite 4478,00,0,7
SPIWrite 447b,00,0,7
SPIWrite 447a,00,0,7
SPIWrite 447d,00,0,7
SPIWrite 447c,00,0,7
SPIWrite 4483,9f,0,7
SPIWrite 4482,df,0,7
SPIWrite 4485,b3,0,7
SPIWrite 4484,c0,0,7
SPIWrite 448f,24,0,7
SPIWrite 448e,a2,0,7
SPIWrite 4491,cc,0,7
SPIWrite 4490,34,0,7
SPIWrite 4493,e3,0,7
SPIWrite 4492,d7,0,7
SPIWrite 4495,76,0,7
SPIWrite 4494,60,0,7
SPIWrite 4497,06,0,7
SPIWrite 4496,db,0,7
SPIWrite 4541,03,0,7
SPIWrite 4540,41,0,7
SPIWrite 45e7,00,0,7
SPIWrite 45e6,80,0,7
SPIWrite 45e9,fc,0,7
SPIWrite 45e8,00,0,7
SPIWrite 45eb,1f,0,7
SPIWrite 45ea,fe,0,7
SPIWrite 45ed,00,0,7
SPIWrite 45ec,00,0,7
SPIWrite 45ef,10,0,7
SPIWrite 45ee,00,0,7
SPIWrite 45f1,68,0,7
SPIWrite 45f0,64,0,7
SPIWrite 45f3,92,0,7
SPIWrite 45f2,30,0,7
SPIWrite 45f5,00,0,7
SPIWrite 45f4,00,0,7
SPIWrite 45f7,6d,0,7
SPIWrite 45f6,83,0,7
SPIWrite 45f9,6d,0,7
SPIWrite 45f8,b6,0,7
SPIWrite 45fb,42,0,7
SPIWrite 45fa,46,0,7
SPIWrite 45fd,62,0,7
SPIWrite 45fc,78,0,7
SPIWrite 45ff,08,0,7
SPIWrite 45fe,c8,0,7
SPIWrite 4601,10,0,7
SPIWrite 4600,6b,0,7
SPIWrite 4603,64,0,7
SPIWrite 4602,80,0,7
SPIWrite 4605,62,0,7
SPIWrite 4604,00,0,7
SPIWrite 4607,7b,0,7
SPIWrite 4606,33,0,7
SPIWrite 4609,70,0,7
SPIWrite 4608,0a,0,7
SPIWrite 460b,bd,0,7
SPIWrite 460a,68,0,7
SPIWrite 460d,76,0,7
SPIWrite 460c,2d,0,7
SPIWrite 460f,66,0,7
SPIWrite 460e,ab,0,7
SPIWrite 4611,d0,0,7
SPIWrite 4610,08,0,7
SPIWrite 4613,00,0,7
SPIWrite 4612,18,0,7
SPIWrite 4615,66,0,7
SPIWrite 4614,2c,0,7
SPIWrite 4617,3d,0,7
SPIWrite 4616,15,0,7
SPIWrite 4619,00,0,7
SPIWrite 4618,80,0,7
SPIWrite 461b,00,0,7
SPIWrite 461a,02,0,7
SPIWrite 461d,34,0,7
SPIWrite 461c,00,0,7
SPIWrite 461f,00,0,7
SPIWrite 461e,00,0,7
SPIWrite 4621,10,0,7
SPIWrite 4620,1a,0,7
SPIWrite 4639,03,0,7
SPIWrite 4638,40,0,7
SPIWrite 463b,00,0,7
SPIWrite 463a,60,0,7
SPIWrite 463d,00,0,7
SPIWrite 463c,00,0,7
SPIWrite 463f,00,0,7
SPIWrite 463e,00,0,7
SPIWrite 4677,00,0,7
SPIWrite 4676,00,0,7
SPIWrite 4679,00,0,7
SPIWrite 4678,00,0,7
SPIWrite 467b,00,0,7
SPIWrite 467a,00,0,7
SPIWrite 467d,00,0,7
SPIWrite 467c,00,0,7
SPIWrite 4683,9f,0,7
SPIWrite 4682,df,0,7
SPIWrite 4685,b3,0,7
SPIWrite 4684,c0,0,7
SPIWrite 468f,24,0,7
SPIWrite 468e,a2,0,7
SPIWrite 4691,cc,0,7
SPIWrite 4690,34,0,7
SPIWrite 4693,e3,0,7
SPIWrite 4692,d7,0,7
SPIWrite 4695,76,0,7
SPIWrite 4694,60,0,7
SPIWrite 4697,06,0,7
SPIWrite 4696,db,0,7
SPIWrite 4741,03,0,7
SPIWrite 4740,41,0,7
SPIWrite 47e7,00,0,7
SPIWrite 47e6,80,0,7
SPIWrite 47e9,fc,0,7
SPIWrite 47e8,00,0,7
SPIWrite 47eb,1f,0,7
SPIWrite 47ea,fe,0,7
SPIWrite 47ed,00,0,7
SPIWrite 47ec,00,0,7
SPIWrite 47ef,10,0,7
SPIWrite 47ee,00,0,7
SPIWrite 47f1,68,0,7
SPIWrite 47f0,64,0,7
SPIWrite 47f3,92,0,7
SPIWrite 47f2,30,0,7
SPIWrite 47f5,00,0,7
SPIWrite 47f4,00,0,7
SPIWrite 47f7,6d,0,7
SPIWrite 47f6,83,0,7
SPIWrite 47f9,6d,0,7
SPIWrite 47f8,b6,0,7
SPIWrite 47fb,42,0,7
SPIWrite 47fa,46,0,7
SPIWrite 47fd,62,0,7
SPIWrite 47fc,78,0,7
SPIWrite 47ff,08,0,7
SPIWrite 47fe,c8,0,7
SPIWrite 0016,40,0,7	//serdes_jesd=0x2; 	Address(0x16[7:5])
SPIWrite 49f1,82,0,7
SPIWrite 49f0,40,0,7
SPIWrite 49f3,e2,0,7
SPIWrite 49f2,80,0,7
SPIWrite 49e3,f0,0,7
SPIWrite 49e2,00,0,7
SPIWrite 49b5,47,0,7
SPIWrite 49b4,47,0,7
SPIWrite 49ff,fd,0,7
SPIWrite 49fe,b0,0,7
SPIWrite 49ed,1d,0,7
SPIWrite 49ec,c0,0,7
SPIWrite 49e7,52,0,7
SPIWrite 49e6,36,0,7
SPIWrite 49e5,6e,0,7
SPIWrite 49e4,b6,0,7
SPIWrite 49df,a8,0,7
SPIWrite 49de,28,0,7
SPIWrite 49eb,0c,0,7
SPIWrite 49ea,98,0,7
SPIWrite 49e9,72,0,7
SPIWrite 49e8,44,0,7
SPIWrite 49fd,0c,0,7
SPIWrite 49fc,98,0,7
SPIWrite 49fb,72,0,7
SPIWrite 49fa,48,0,7
SPIWrite 49f9,4a,0,7
SPIWrite 49f8,66,0,7
SPIWrite 49f7,79,0,7
SPIWrite 49f6,b6,0,7
SPIWrite 49d9,6c,0,7
SPIWrite 49d8,06,0,7
SPIWrite 4601,10,0,7
SPIWrite 4600,6b,0,7
SPIWrite 4603,64,0,7
SPIWrite 4602,80,0,7
SPIWrite 4605,62,0,7
SPIWrite 4604,00,0,7
SPIWrite 4607,7b,0,7
SPIWrite 4606,33,0,7
SPIWrite 4609,70,0,7
SPIWrite 4608,0a,0,7
SPIWrite 460b,bd,0,7
SPIWrite 460a,68,0,7
SPIWrite 460d,76,0,7
SPIWrite 460c,2d,0,7
SPIWrite 460f,66,0,7
SPIWrite 460e,ab,0,7
SPIWrite 4611,d0,0,7
SPIWrite 4610,08,0,7
SPIWrite 4613,00,0,7
SPIWrite 4612,18,0,7
SPIWrite 4615,66,0,7
SPIWrite 4614,2c,0,7
SPIWrite 4617,3d,0,7
SPIWrite 4616,15,0,7
SPIWrite 4619,00,0,7
SPIWrite 4618,80,0,7
SPIWrite 461b,00,0,7
SPIWrite 461a,02,0,7
SPIWrite 461d,34,0,7
SPIWrite 461c,00,0,7
SPIWrite 461f,00,0,7
SPIWrite 461e,00,0,7
SPIWrite 4621,10,0,7
SPIWrite 4620,1a,0,7
SPIWrite 4639,03,0,7
SPIWrite 4638,40,0,7
SPIWrite 463b,00,0,7
SPIWrite 463a,60,0,7
SPIWrite 463d,00,0,7
SPIWrite 463c,00,0,7
SPIWrite 463f,00,0,7
SPIWrite 463e,00,0,7
SPIWrite 4677,00,0,7
SPIWrite 4676,00,0,7
SPIWrite 4679,00,0,7
SPIWrite 4678,00,0,7
SPIWrite 467b,00,0,7
SPIWrite 467a,00,0,7
SPIWrite 467d,00,0,7
SPIWrite 467c,00,0,7
SPIWrite 4683,9f,0,7
SPIWrite 4682,df,0,7
SPIWrite 4685,b3,0,7
SPIWrite 4684,c0,0,7
SPIWrite 468f,24,0,7
SPIWrite 468e,a2,0,7
SPIWrite 4691,cc,0,7
SPIWrite 4690,34,0,7
SPIWrite 4693,e3,0,7
SPIWrite 4692,d7,0,7
SPIWrite 4695,76,0,7
SPIWrite 4694,60,0,7
SPIWrite 4697,06,0,7
SPIWrite 4696,db,0,7
SPIWrite 4741,03,0,7
SPIWrite 4740,41,0,7
SPIWrite 47e7,00,0,7
SPIWrite 47e6,80,0,7
SPIWrite 47e9,fc,0,7
SPIWrite 47e8,00,0,7
SPIWrite 47eb,1f,0,7
SPIWrite 47ea,fe,0,7
SPIWrite 47ed,00,0,7
SPIWrite 47ec,00,0,7
SPIWrite 47ef,10,0,7
SPIWrite 47ee,00,0,7
SPIWrite 47f1,68,0,7
SPIWrite 47f0,64,0,7
SPIWrite 47f3,92,0,7
SPIWrite 47f2,30,0,7
SPIWrite 47f5,00,0,7
SPIWrite 47f4,00,0,7
SPIWrite 47f7,6d,0,7
SPIWrite 47f6,87,0,7
SPIWrite 47f9,6d,0,7
SPIWrite 47f8,b6,0,7
SPIWrite 47fb,42,0,7
SPIWrite 47fa,46,0,7
SPIWrite 47fd,62,0,7
SPIWrite 47fc,7c,0,7
SPIWrite 47ff,88,0,7
SPIWrite 47fe,c8,0,7
SPIWrite 4401,10,0,7
SPIWrite 4400,6b,0,7
SPIWrite 4403,64,0,7
SPIWrite 4402,80,0,7
SPIWrite 4405,62,0,7
SPIWrite 4404,00,0,7
SPIWrite 4407,7b,0,7
SPIWrite 4406,33,0,7
SPIWrite 4409,70,0,7
SPIWrite 4408,0a,0,7
SPIWrite 440b,bd,0,7
SPIWrite 440a,68,0,7
SPIWrite 440d,76,0,7
SPIWrite 440c,2d,0,7
SPIWrite 440f,66,0,7
SPIWrite 440e,ab,0,7
SPIWrite 4411,d0,0,7
SPIWrite 4410,08,0,7
SPIWrite 4413,00,0,7
SPIWrite 4412,18,0,7
SPIWrite 4415,66,0,7
SPIWrite 4414,2c,0,7
SPIWrite 4417,3d,0,7
SPIWrite 4416,15,0,7
SPIWrite 4419,00,0,7
SPIWrite 4418,80,0,7
SPIWrite 441b,00,0,7
SPIWrite 441a,02,0,7
SPIWrite 441d,34,0,7
SPIWrite 441c,00,0,7
SPIWrite 441f,00,0,7
SPIWrite 441e,00,0,7
SPIWrite 4421,10,0,7
SPIWrite 4420,1a,0,7
SPIWrite 4439,03,0,7
SPIWrite 4438,40,0,7
SPIWrite 443b,00,0,7
SPIWrite 443a,60,0,7
SPIWrite 443d,00,0,7
SPIWrite 443c,00,0,7
SPIWrite 443f,00,0,7
SPIWrite 443e,00,0,7
SPIWrite 4477,00,0,7
SPIWrite 4476,00,0,7
SPIWrite 4479,00,0,7
SPIWrite 4478,00,0,7
SPIWrite 447b,00,0,7
SPIWrite 447a,00,0,7
SPIWrite 447d,00,0,7
SPIWrite 447c,00,0,7
SPIWrite 4483,9f,0,7
SPIWrite 4482,df,0,7
SPIWrite 4485,b3,0,7
SPIWrite 4484,c0,0,7
SPIWrite 448f,24,0,7
SPIWrite 448e,a2,0,7
SPIWrite 4491,cc,0,7
SPIWrite 4490,34,0,7
SPIWrite 4493,e3,0,7
SPIWrite 4492,d7,0,7
SPIWrite 4495,76,0,7
SPIWrite 4494,60,0,7
SPIWrite 4497,06,0,7
SPIWrite 4496,db,0,7
SPIWrite 4541,03,0,7
SPIWrite 4540,41,0,7
SPIWrite 45e7,00,0,7
SPIWrite 45e6,80,0,7
SPIWrite 45e9,fc,0,7
SPIWrite 45e8,00,0,7
SPIWrite 45eb,1f,0,7
SPIWrite 45ea,fe,0,7
SPIWrite 45ed,00,0,7
SPIWrite 45ec,00,0,7
SPIWrite 45ef,10,0,7
SPIWrite 45ee,00,0,7
SPIWrite 45f1,68,0,7
SPIWrite 45f0,64,0,7
SPIWrite 45f3,92,0,7
SPIWrite 45f2,30,0,7
SPIWrite 45f5,00,0,7
SPIWrite 45f4,00,0,7
SPIWrite 45f7,6d,0,7
SPIWrite 45f6,87,0,7
SPIWrite 45f9,6d,0,7
SPIWrite 45f8,b6,0,7
SPIWrite 45fb,42,0,7
SPIWrite 45fa,46,0,7
SPIWrite 45fd,62,0,7
SPIWrite 45fc,7c,0,7
SPIWrite 45ff,88,0,7
SPIWrite 45fe,c8,0,7
SPIWrite 4001,10,0,7
SPIWrite 4000,6b,0,7
SPIWrite 4003,64,0,7
SPIWrite 4002,80,0,7
SPIWrite 4005,62,0,7
SPIWrite 4004,00,0,7
SPIWrite 4007,7b,0,7
SPIWrite 4006,33,0,7
SPIWrite 4009,70,0,7
SPIWrite 4008,0a,0,7
SPIWrite 400b,bd,0,7
SPIWrite 400a,68,0,7
SPIWrite 400d,76,0,7
SPIWrite 400c,2d,0,7
SPIWrite 400f,66,0,7
SPIWrite 400e,ab,0,7
SPIWrite 4011,d0,0,7
SPIWrite 4010,08,0,7
SPIWrite 4013,00,0,7
SPIWrite 4012,18,0,7
SPIWrite 4015,66,0,7
SPIWrite 4014,2c,0,7
SPIWrite 4017,3d,0,7
SPIWrite 4016,15,0,7
SPIWrite 4019,00,0,7
SPIWrite 4018,80,0,7
SPIWrite 401b,00,0,7
SPIWrite 401a,02,0,7
SPIWrite 401d,34,0,7
SPIWrite 401c,00,0,7
SPIWrite 401f,00,0,7
SPIWrite 401e,00,0,7
SPIWrite 4021,10,0,7
SPIWrite 4020,1a,0,7
SPIWrite 4039,03,0,7
SPIWrite 4038,40,0,7
SPIWrite 403b,00,0,7
SPIWrite 403a,60,0,7
SPIWrite 403d,00,0,7
SPIWrite 403c,00,0,7
SPIWrite 403f,00,0,7
SPIWrite 403e,00,0,7
SPIWrite 4077,00,0,7
SPIWrite 4076,00,0,7
SPIWrite 4079,00,0,7
SPIWrite 4078,00,0,7
SPIWrite 407b,00,0,7
SPIWrite 407a,00,0,7
SPIWrite 407d,00,0,7
SPIWrite 407c,00,0,7
SPIWrite 4083,9f,0,7
SPIWrite 4082,df,0,7
SPIWrite 4085,b3,0,7
SPIWrite 4084,c0,0,7
SPIWrite 408f,24,0,7
SPIWrite 408e,a2,0,7
SPIWrite 4091,cc,0,7
SPIWrite 4090,34,0,7
SPIWrite 4093,e3,0,7
SPIWrite 4092,d7,0,7
SPIWrite 4095,76,0,7
SPIWrite 4094,60,0,7
SPIWrite 4097,06,0,7
SPIWrite 4096,db,0,7
SPIWrite 4141,03,0,7
SPIWrite 4140,41,0,7
SPIWrite 41e7,00,0,7
SPIWrite 41e6,80,0,7
SPIWrite 41e9,fc,0,7
SPIWrite 41e8,00,0,7
SPIWrite 41eb,9f,0,7
SPIWrite 41ea,fe,0,7
SPIWrite 41ed,00,0,7
SPIWrite 41ec,00,0,7
SPIWrite 41ef,10,0,7
SPIWrite 41ee,00,0,7
SPIWrite 41f1,68,0,7
SPIWrite 41f0,64,0,7
SPIWrite 41f3,92,0,7
SPIWrite 41f2,30,0,7
SPIWrite 41f5,00,0,7
SPIWrite 41f4,00,0,7
SPIWrite 41f7,6d,0,7
SPIWrite 41f6,83,0,7
SPIWrite 41f9,6d,0,7
SPIWrite 41f8,b6,0,7
SPIWrite 41fb,42,0,7
SPIWrite 41fa,46,0,7
SPIWrite 41fd,62,0,7
SPIWrite 41fc,78,0,7
SPIWrite 41ff,08,0,7
SPIWrite 41fe,c8,0,7
SPIWrite 4201,10,0,7
SPIWrite 4200,6b,0,7
SPIWrite 4203,64,0,7
SPIWrite 4202,80,0,7
SPIWrite 4205,62,0,7
SPIWrite 4204,00,0,7
SPIWrite 4207,7b,0,7
SPIWrite 4206,33,0,7
SPIWrite 4209,70,0,7
SPIWrite 4208,0a,0,7
SPIWrite 420b,bd,0,7
SPIWrite 420a,68,0,7
SPIWrite 420d,76,0,7
SPIWrite 420c,2d,0,7
SPIWrite 420f,66,0,7
SPIWrite 420e,ab,0,7
SPIWrite 4211,d0,0,7
SPIWrite 4210,08,0,7
SPIWrite 4213,00,0,7
SPIWrite 4212,18,0,7
SPIWrite 4215,66,0,7
SPIWrite 4214,2c,0,7
SPIWrite 4217,3d,0,7
SPIWrite 4216,15,0,7
SPIWrite 4219,00,0,7
SPIWrite 4218,80,0,7
SPIWrite 421b,00,0,7
SPIWrite 421a,02,0,7
SPIWrite 421d,34,0,7
SPIWrite 421c,00,0,7
SPIWrite 421f,00,0,7
SPIWrite 421e,00,0,7
SPIWrite 4221,10,0,7
SPIWrite 4220,1a,0,7
SPIWrite 4239,03,0,7
SPIWrite 4238,40,0,7
SPIWrite 423b,00,0,7
SPIWrite 423a,60,0,7
SPIWrite 423d,00,0,7
SPIWrite 423c,00,0,7
SPIWrite 423f,00,0,7
SPIWrite 423e,00,0,7
SPIWrite 4277,00,0,7
SPIWrite 4276,00,0,7
SPIWrite 4279,00,0,7
SPIWrite 4278,00,0,7
SPIWrite 427b,00,0,7
SPIWrite 427a,00,0,7
SPIWrite 427d,00,0,7
SPIWrite 427c,00,0,7
SPIWrite 4283,9f,0,7
SPIWrite 4282,df,0,7
SPIWrite 4285,b3,0,7
SPIWrite 4284,c0,0,7
SPIWrite 428f,24,0,7
SPIWrite 428e,a2,0,7
SPIWrite 4291,cc,0,7
SPIWrite 4290,34,0,7
SPIWrite 4293,e3,0,7
SPIWrite 4292,d7,0,7
SPIWrite 4295,76,0,7
SPIWrite 4294,60,0,7
SPIWrite 4297,06,0,7
SPIWrite 4296,db,0,7
SPIWrite 4341,03,0,7
SPIWrite 4340,41,0,7
SPIWrite 43e7,00,0,7
SPIWrite 43e6,80,0,7
SPIWrite 43e9,fc,0,7
SPIWrite 43e8,00,0,7
SPIWrite 43eb,9f,0,7
SPIWrite 43ea,fe,0,7
SPIWrite 43ed,00,0,7
SPIWrite 43ec,60,0,7
SPIWrite 43ef,10,0,7
SPIWrite 43ee,00,0,7
SPIWrite 43f1,68,0,7
SPIWrite 43f0,64,0,7
SPIWrite 43f3,92,0,7
SPIWrite 43f2,30,0,7
SPIWrite 43f5,00,0,7
SPIWrite 43f4,00,0,7
SPIWrite 43f7,6d,0,7
SPIWrite 43f6,83,0,7
SPIWrite 43f9,6d,0,7
SPIWrite 43f8,b6,0,7
SPIWrite 43fb,42,0,7
SPIWrite 43fa,46,0,7
SPIWrite 43fd,62,0,7
SPIWrite 43fc,78,0,7
SPIWrite 43ff,08,0,7
SPIWrite 43fe,c8,0,7
SPIWrite 0016,60,0,7	//serdes_jesd=0x3; 	Address(0x16[7:5])
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE0=0x0; 	Address(0x9803[7:0])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE1=0x0; 	Address(0x9803[7:1])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE2=0x0; 	Address(0x9803[7:2])
SPIWrite 7006,00,0,7
SPIWrite 7007,00,0,7	//BUS_WIDTH_LANE3=0x0; 	Address(0x9803[7:3])
SPIWrite 7006,00,0,7
SPIWrite 0016,00,0,7	//serdes_jesd=0x0; 	Address(0x16[7:5])

//END: Done configuring the SERDES


//STEP: serdesConfig/step3 

//START: Loading Serdes Firmware.

SPIWrite 0018,20,5,5	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x10300; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,01,0,7
SPIWrite 00a1,03,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,79,0,7	//MACRO_OPCODE=0x79; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x10301; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,01,0,7
SPIWrite 00a1,03,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,79,0,7	//MACRO_OPCODE=0x79; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0016,60,0,7	//serdes_jesd=0x3; 	Address(0x16[7:5])
SPIWrite 702d,00,0,7
SPIWrite 702c,05,0,7
SPIWrite 7025,00,0,7
SPIWrite 7024,08,0,7
SPIWrite 702b,e0,0,7
SPIWrite 702a,20,0,7
SPIWrite 702d,00,0,7
SPIWrite 702c,02,0,7
SPIWrite 7025,00,0,7
SPIWrite 7024,50,0,7
SPIWrite 702b,e0,0,7
SPIWrite 702a,20,0,7
SPIWrite 701b,07,0,7	//DOMAIN_RESET=0x777; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,77,0,7
SPIWrite 701b,00,0,7	//DOMAIN_RESET=0x0; 	Address(0x980d[3:0],0x980e[7:0])
SPIWrite 701a,00,0,7

WAIT 5
SPIWrite 0016,00,0,7	//serdes_jesd=0x0; 	Address(0x16[7:5])

//END: Done loading Serdes Firmware.


//STEP: topConfig/step0 

//START: Setting Top Control Modes

SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 0081,00,0,7	//fdd_mode=0x0; 	Address(0x81[7:0])
SPIWrite 0080,01,0,7	//mode_2t2r=0x1; 	Address(0x80[7:0])
SPIWrite 008c,01,0,7	//use_per_ch_txab_tdd=0x1; 	Address(0x8c[7:0])
SPIWrite 008d,01,0,7	//use_per_ch_txcd_tdd=0x1; 	Address(0x8d[7:0])
SPIWrite 00a0,01,0,7	//use_per_ch_rxab_tdd=0x1; 	Address(0xa0[7:0])
SPIWrite 00a1,01,0,7	//use_per_ch_rxcd_tdd=0x1; 	Address(0xa1[7:0])
SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 0129,00,0,7	//Property_108h_11_8=0x0; 	Address(0x129[7:0])
SPIWrite 012a,00,0,7	//Property_108h_19_16=0x0; 	Address(0x12a[7:0])
SPIWrite 012b,00,0,7	//Property_108h_25_24=0x0; 	Address(0x12b[7:0])
SPIWrite 00dc,00,0,7	//Property_bch_1_0=0x0; 	Address(0xdc[7:0])
SPIWrite 00df,00,0,7	//Property_bch_25_24=0x0; 	Address(0xdf[7:0])
SPIWrite 00c4,00,0,7	//Property_a4h_1_0=0x0; 	Address(0xc4[7:0])
SPIWrite 00c7,00,0,7	//Property_a4h_25_24=0x0; 	Address(0xc7[7:0])
SPIWrite 00cc,00,0,7	//Property_ach_1_0=0x0; 	Address(0xcc[7:0])
SPIWrite 00cf,00,0,7	//Property_ach_25_24=0x0; 	Address(0xcf[7:0])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 0399,00,0,7	//Property_378h_15_0=0x0; 	Address(0x398[7:0],0x399[7:0],0x39a[7:0])
SPIWrite 0398,00,0,7
SPIWrite 039b,00,0,7	//Property_378h_31_16=0xe1; 	Address(0x39a[7:0],0x39b[7:0],0x39c[7:0])
SPIWrite 039a,e1,0,7
SPIWrite 0451,00,0,7	//Property_430h_15_0=0x0; 	Address(0x450[7:0],0x451[7:0],0x452[7:0])
SPIWrite 0450,00,0,7
SPIWrite 0453,00,0,7	//Property_430h_31_16=0xe1; 	Address(0x452[7:0],0x453[7:0],0x454[7:0])
SPIWrite 0452,e1,0,7
SPIWrite 0509,00,0,7	//Property_4e8h_15_0=0x0; 	Address(0x508[7:0],0x509[7:0],0x50a[7:0])
SPIWrite 0508,00,0,7
SPIWrite 050b,00,0,7	//Property_4e8h_31_16=0xe1; 	Address(0x50a[7:0],0x50b[7:0],0x50c[7:0])
SPIWrite 050a,e1,0,7
SPIWrite 05c1,00,0,7	//Property_5a0h_15_0=0x0; 	Address(0x5c0[7:0],0x5c1[7:0],0x5c2[7:0])
SPIWrite 05c0,00,0,7
SPIWrite 05c3,00,0,7	//Property_5a0h_31_16=0xe1; 	Address(0x5c2[7:0],0x5c3[7:0],0x5c4[7:0])
SPIWrite 05c2,e1,0,7
SPIWrite 0679,00,0,7	//Property_658h_15_0=0x0; 	Address(0x678[7:0],0x679[7:0],0x67a[7:0])
SPIWrite 0678,00,0,7
SPIWrite 067b,00,0,7	//Property_658h_31_16=0xe1; 	Address(0x67a[7:0],0x67b[7:0],0x67c[7:0])
SPIWrite 067a,e1,0,7
SPIWrite 0731,00,0,7	//Property_710h_15_0=0x0; 	Address(0x730[7:0],0x731[7:0],0x732[7:0])
SPIWrite 0730,00,0,7
SPIWrite 0733,00,0,7	//Property_710h_31_16=0xe1; 	Address(0x732[7:0],0x733[7:0],0x734[7:0])
SPIWrite 0732,e1,0,7

//END: Setting Top Control Modes

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0180,00,0,7	//Property_160h_3_0=0x0; 	Address(0x180[7:0])
SPIWrite 0181,00,0,7	//Property_160h_11_8=0x0; 	Address(0x181[7:0])
SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])

//STEP: topConfig/step1 
SPIWrite 0013,40,6,7	//dsa_page1=0x1; 	Address(0x13[7:6])
SPIWrite 054e,00,0,0	//Property_52ch_16_16=0x0; 	Address(0x54e[7:0])
SPIWrite 0013,80,6,7	//dsa_page1=0x2; 	Address(0x13[7:6])
SPIWrite 054e,00,0,0	//Property_52ch_16_16=0x0; 	Address(0x54e[7:0])
SPIWrite 0013,c0,0,7	//dsa_page1=0x3; 	Address(0x13[7:6])
SPIWrite 0744,03,0,7
SPIWrite 0745,00,0,7
SPIWrite 0746,00,0,7
SPIWrite 0747,00,0,7
SPIWrite 0748,0f,0,7
SPIWrite 0749,08,0,7
SPIWrite 074a,00,0,7
SPIWrite 074b,00,0,7
SPIWrite 074c,13,0,7
SPIWrite 074d,04,0,7
SPIWrite 074e,01,0,7
SPIWrite 074f,00,0,7
SPIWrite 0750,27,0,7
SPIWrite 0751,88,0,7
SPIWrite 0752,01,0,7
SPIWrite 0753,00,0,7
SPIWrite 0754,37,0,7
SPIWrite 0755,08,0,7
SPIWrite 0756,02,0,7
SPIWrite 0757,00,0,7
SPIWrite 0758,47,0,7
SPIWrite 0759,8c,0,7
SPIWrite 075a,02,0,7
SPIWrite 075b,00,0,7
SPIWrite 075c,57,0,7
SPIWrite 075d,10,0,7
SPIWrite 075e,03,0,7
SPIWrite 075f,01,0,7
SPIWrite 0760,67,0,7
SPIWrite 0761,94,0,7
SPIWrite 0762,03,0,7
SPIWrite 0763,01,0,7
SPIWrite 0764,7b,0,7
SPIWrite 0765,18,0,7
SPIWrite 0766,04,0,7
SPIWrite 0767,01,0,7
SPIWrite 0768,8b,0,7
SPIWrite 0769,9c,0,7
SPIWrite 076a,04,0,7
SPIWrite 076b,01,0,7
SPIWrite 076c,9f,0,7
SPIWrite 076d,20,0,7
SPIWrite 076e,05,0,7
SPIWrite 076f,02,0,7
SPIWrite 0770,b3,0,7
SPIWrite 0771,a4,0,7
SPIWrite 0772,05,0,7
SPIWrite 0773,02,0,7
SPIWrite 0774,c7,0,7
SPIWrite 0775,28,0,7
SPIWrite 0776,06,0,7
SPIWrite 0777,02,0,7
SPIWrite 0778,db,0,7
SPIWrite 0779,2c,0,7
SPIWrite 077a,07,0,7
SPIWrite 077b,03,0,7
SPIWrite 077c,ef,0,7
SPIWrite 077d,b0,0,7
SPIWrite 077e,07,0,7
SPIWrite 077f,03,0,7
SPIWrite 0780,03,0,7
SPIWrite 0781,b5,0,7
SPIWrite 0782,08,0,7
SPIWrite 0783,04,0,7
SPIWrite 0784,17,0,7
SPIWrite 0785,b9,0,7
SPIWrite 0786,09,0,7
SPIWrite 0787,04,0,7
SPIWrite 0788,2b,0,7
SPIWrite 0789,bd,0,7
SPIWrite 078a,0a,0,7
SPIWrite 078b,05,0,7
SPIWrite 078c,3f,0,7
SPIWrite 078d,c1,0,7
SPIWrite 078e,0b,0,7
SPIWrite 078f,05,0,7
SPIWrite 0790,53,0,7
SPIWrite 0791,45,0,7
SPIWrite 0792,0c,0,7
SPIWrite 0793,05,0,7
SPIWrite 0794,6b,0,7
SPIWrite 0795,49,0,7
SPIWrite 0796,0d,0,7
SPIWrite 0797,06,0,7
SPIWrite 0798,7f,0,7
SPIWrite 0799,4d,0,7
SPIWrite 079a,0e,0,7
SPIWrite 079b,07,0,7
SPIWrite 079c,93,0,7
SPIWrite 079d,51,0,7
SPIWrite 079e,0f,0,7
SPIWrite 079f,07,0,7
SPIWrite 07a0,a7,0,7
SPIWrite 07a1,d5,0,7
SPIWrite 07a2,0f,0,7
SPIWrite 07a3,08,0,7
SPIWrite 07a4,b3,0,7
SPIWrite 07a5,55,0,7
SPIWrite 07a6,10,0,7
SPIWrite 07a7,08,0,7
SPIWrite 07a8,c7,0,7
SPIWrite 07a9,59,0,7
SPIWrite 07aa,11,0,7
SPIWrite 07ab,09,0,7
SPIWrite 07ac,db,0,7
SPIWrite 07ad,5d,0,7
SPIWrite 07ae,12,0,7
SPIWrite 07af,0a,0,7
SPIWrite 07b0,f3,0,7
SPIWrite 07b1,61,0,7
SPIWrite 07b2,13,0,7
SPIWrite 07b3,0b,0,7
SPIWrite 07b4,13,0,7
SPIWrite 07b5,e6,0,7
SPIWrite 07b6,14,0,7
SPIWrite 07b7,0c,0,7
SPIWrite 07b8,27,0,7
SPIWrite 07b9,ea,0,7
SPIWrite 07ba,15,0,7
SPIWrite 07bb,0d,0,7
SPIWrite 07bc,3b,0,7
SPIWrite 07bd,ee,0,7
SPIWrite 07be,16,0,7
SPIWrite 07bf,0e,0,7
SPIWrite 07c0,4f,0,7
SPIWrite 07c1,72,0,7
SPIWrite 07c2,17,0,7
SPIWrite 07c3,11,0,7
SPIWrite 07c4,63,0,7
SPIWrite 07c5,f6,0,7
SPIWrite 07c6,17,0,7
SPIWrite 07c7,11,0,7
SPIWrite 07c8,77,0,7
SPIWrite 07c9,7a,0,7
SPIWrite 07ca,18,0,7
SPIWrite 07cb,13,0,7
SPIWrite 07cc,8b,0,7
SPIWrite 07cd,fa,0,7
SPIWrite 07ce,18,0,7
SPIWrite 07cf,15,0,7
SPIWrite 07d0,9f,0,7
SPIWrite 07d1,fe,0,7
SPIWrite 07d2,19,0,7
SPIWrite 07d3,18,0,7
SPIWrite 07d4,b3,0,7
SPIWrite 07d5,7e,0,7
SPIWrite 07d6,1a,0,7
SPIWrite 07d7,18,0,7
SPIWrite 07d8,c7,0,7
SPIWrite 07d9,fe,0,7
SPIWrite 07da,1a,0,7
SPIWrite 07db,19,0,7
SPIWrite 07dc,db,0,7
SPIWrite 07dd,7e,0,7
SPIWrite 07de,1b,0,7
SPIWrite 07df,1d,0,7
SPIWrite 07e0,ef,0,7
SPIWrite 07e1,fe,0,7
SPIWrite 07e2,1b,0,7
SPIWrite 07e3,1d,0,7
SPIWrite 07e4,ff,0,7
SPIWrite 07e5,7e,0,7
SPIWrite 07e6,1c,0,7
SPIWrite 07e7,1f,0,7
SPIWrite 07e8,13,0,7
SPIWrite 07e9,ff,0,7
SPIWrite 07ea,1c,0,7
SPIWrite 07eb,1f,0,7
SPIWrite 07ec,23,0,7
SPIWrite 07ed,7f,0,7
SPIWrite 07ee,1d,0,7
SPIWrite 07ef,1f,0,7
SPIWrite 07f0,33,0,7
SPIWrite 07f1,ff,0,7
SPIWrite 07f2,1d,0,7
SPIWrite 07f3,1f,0,7
SPIWrite 07f4,3f,0,7
SPIWrite 07f5,7f,0,7
SPIWrite 07f6,1e,0,7
SPIWrite 07f7,1f,0,7
SPIWrite 07f8,4b,0,7
SPIWrite 07f9,ff,0,7
SPIWrite 07fa,1e,0,7
SPIWrite 07fb,1f,0,7
SPIWrite 07fc,53,0,7
SPIWrite 07fd,7f,0,7
SPIWrite 07fe,1f,0,7
SPIWrite 07ff,1f,0,7
SPIWrite 0800,5f,0,7
SPIWrite 0801,ff,0,7
SPIWrite 0802,1f,0,7
SPIWrite 0803,1f,0,7
SPIWrite 0804,67,0,7
SPIWrite 0805,ff,0,7
SPIWrite 0806,1f,0,7
SPIWrite 0807,1f,0,7
SPIWrite 0808,73,0,7
SPIWrite 0809,ff,0,7
SPIWrite 080a,1f,0,7
SPIWrite 080b,1f,0,7
SPIWrite 0844,03,0,7
SPIWrite 0845,00,0,7
SPIWrite 0846,00,0,7
SPIWrite 0847,00,0,7
SPIWrite 0848,0f,0,7
SPIWrite 0849,08,0,7
SPIWrite 084a,00,0,7
SPIWrite 084b,00,0,7
SPIWrite 084c,13,0,7
SPIWrite 084d,04,0,7
SPIWrite 084e,01,0,7
SPIWrite 084f,00,0,7
SPIWrite 0850,27,0,7
SPIWrite 0851,88,0,7
SPIWrite 0852,01,0,7
SPIWrite 0853,00,0,7
SPIWrite 0854,37,0,7
SPIWrite 0855,08,0,7
SPIWrite 0856,02,0,7
SPIWrite 0857,00,0,7
SPIWrite 0858,47,0,7
SPIWrite 0859,8c,0,7
SPIWrite 085a,02,0,7
SPIWrite 085b,00,0,7
SPIWrite 085c,57,0,7
SPIWrite 085d,10,0,7
SPIWrite 085e,03,0,7
SPIWrite 085f,01,0,7
SPIWrite 0860,67,0,7
SPIWrite 0861,94,0,7
SPIWrite 0862,03,0,7
SPIWrite 0863,01,0,7
SPIWrite 0864,7b,0,7
SPIWrite 0865,18,0,7
SPIWrite 0866,04,0,7
SPIWrite 0867,01,0,7
SPIWrite 0868,8b,0,7
SPIWrite 0869,9c,0,7
SPIWrite 086a,04,0,7
SPIWrite 086b,01,0,7
SPIWrite 086c,9f,0,7
SPIWrite 086d,20,0,7
SPIWrite 086e,05,0,7
SPIWrite 086f,02,0,7
SPIWrite 0870,b3,0,7
SPIWrite 0871,a4,0,7
SPIWrite 0872,05,0,7
SPIWrite 0873,02,0,7
SPIWrite 0874,c7,0,7
SPIWrite 0875,28,0,7
SPIWrite 0876,06,0,7
SPIWrite 0877,02,0,7
SPIWrite 0878,db,0,7
SPIWrite 0879,2c,0,7
SPIWrite 087a,07,0,7
SPIWrite 087b,03,0,7
SPIWrite 087c,ef,0,7
SPIWrite 087d,b0,0,7
SPIWrite 087e,07,0,7
SPIWrite 087f,03,0,7
SPIWrite 0880,03,0,7
SPIWrite 0881,b5,0,7
SPIWrite 0882,08,0,7
SPIWrite 0883,04,0,7
SPIWrite 0884,17,0,7
SPIWrite 0885,b9,0,7
SPIWrite 0886,09,0,7
SPIWrite 0887,04,0,7
SPIWrite 0888,2b,0,7
SPIWrite 0889,bd,0,7
SPIWrite 088a,0a,0,7
SPIWrite 088b,05,0,7
SPIWrite 088c,3f,0,7
SPIWrite 088d,c1,0,7
SPIWrite 088e,0b,0,7
SPIWrite 088f,05,0,7
SPIWrite 0890,53,0,7
SPIWrite 0891,45,0,7
SPIWrite 0892,0c,0,7
SPIWrite 0893,05,0,7
SPIWrite 0894,6b,0,7
SPIWrite 0895,49,0,7
SPIWrite 0896,0d,0,7
SPIWrite 0897,06,0,7
SPIWrite 0898,7f,0,7
SPIWrite 0899,4d,0,7
SPIWrite 089a,0e,0,7
SPIWrite 089b,07,0,7
SPIWrite 089c,93,0,7
SPIWrite 089d,51,0,7
SPIWrite 089e,0f,0,7
SPIWrite 089f,07,0,7
SPIWrite 08a0,a7,0,7
SPIWrite 08a1,d5,0,7
SPIWrite 08a2,0f,0,7
SPIWrite 08a3,08,0,7
SPIWrite 08a4,b3,0,7
SPIWrite 08a5,55,0,7
SPIWrite 08a6,10,0,7
SPIWrite 08a7,08,0,7
SPIWrite 08a8,c7,0,7
SPIWrite 08a9,59,0,7
SPIWrite 08aa,11,0,7
SPIWrite 08ab,09,0,7
SPIWrite 08ac,db,0,7
SPIWrite 08ad,5d,0,7
SPIWrite 08ae,12,0,7
SPIWrite 08af,0a,0,7
SPIWrite 08b0,f3,0,7
SPIWrite 08b1,61,0,7
SPIWrite 08b2,13,0,7
SPIWrite 08b3,0b,0,7
SPIWrite 08b4,13,0,7
SPIWrite 08b5,e6,0,7
SPIWrite 08b6,14,0,7
SPIWrite 08b7,0c,0,7
SPIWrite 08b8,27,0,7
SPIWrite 08b9,ea,0,7
SPIWrite 08ba,15,0,7
SPIWrite 08bb,0d,0,7
SPIWrite 08bc,3b,0,7
SPIWrite 08bd,ee,0,7
SPIWrite 08be,16,0,7
SPIWrite 08bf,0e,0,7
SPIWrite 08c0,4f,0,7
SPIWrite 08c1,72,0,7
SPIWrite 08c2,17,0,7
SPIWrite 08c3,11,0,7
SPIWrite 08c4,63,0,7
SPIWrite 08c5,f6,0,7
SPIWrite 08c6,17,0,7
SPIWrite 08c7,11,0,7
SPIWrite 08c8,77,0,7
SPIWrite 08c9,7a,0,7
SPIWrite 08ca,18,0,7
SPIWrite 08cb,13,0,7
SPIWrite 08cc,8b,0,7
SPIWrite 08cd,fa,0,7
SPIWrite 08ce,18,0,7
SPIWrite 08cf,15,0,7
SPIWrite 08d0,9f,0,7
SPIWrite 08d1,fe,0,7
SPIWrite 08d2,19,0,7
SPIWrite 08d3,18,0,7
SPIWrite 08d4,b3,0,7
SPIWrite 08d5,7e,0,7
SPIWrite 08d6,1a,0,7
SPIWrite 08d7,18,0,7
SPIWrite 08d8,c7,0,7
SPIWrite 08d9,fe,0,7
SPIWrite 08da,1a,0,7
SPIWrite 08db,19,0,7
SPIWrite 08dc,db,0,7
SPIWrite 08dd,7e,0,7
SPIWrite 08de,1b,0,7
SPIWrite 08df,1d,0,7
SPIWrite 08e0,ef,0,7
SPIWrite 08e1,fe,0,7
SPIWrite 08e2,1b,0,7
SPIWrite 08e3,1d,0,7
SPIWrite 08e4,ff,0,7
SPIWrite 08e5,7e,0,7
SPIWrite 08e6,1c,0,7
SPIWrite 08e7,1f,0,7
SPIWrite 08e8,13,0,7
SPIWrite 08e9,ff,0,7
SPIWrite 08ea,1c,0,7
SPIWrite 08eb,1f,0,7
SPIWrite 08ec,23,0,7
SPIWrite 08ed,7f,0,7
SPIWrite 08ee,1d,0,7
SPIWrite 08ef,1f,0,7
SPIWrite 08f0,33,0,7
SPIWrite 08f1,ff,0,7
SPIWrite 08f2,1d,0,7
SPIWrite 08f3,1f,0,7
SPIWrite 08f4,3f,0,7
SPIWrite 08f5,7f,0,7
SPIWrite 08f6,1e,0,7
SPIWrite 08f7,1f,0,7
SPIWrite 08f8,4b,0,7
SPIWrite 08f9,ff,0,7
SPIWrite 08fa,1e,0,7
SPIWrite 08fb,1f,0,7
SPIWrite 08fc,53,0,7
SPIWrite 08fd,7f,0,7
SPIWrite 08fe,1f,0,7
SPIWrite 08ff,1f,0,7
SPIWrite 0900,5f,0,7
SPIWrite 0901,ff,0,7
SPIWrite 0902,1f,0,7
SPIWrite 0903,1f,0,7
SPIWrite 0904,67,0,7
SPIWrite 0905,ff,0,7
SPIWrite 0906,1f,0,7
SPIWrite 0907,1f,0,7
SPIWrite 0908,73,0,7
SPIWrite 0909,ff,0,7
SPIWrite 090a,1f,0,7
SPIWrite 090b,1f,0,7
SPIWrite 00d1,06,0,7	//dig_gain_range=0x6; 	Address(0xd1[7:0])
SPIWrite 0124,01,0,7	//spi_agc_dsa_A=0x1; 	Address(0x124[7:0])
SPIWrite 0124,00,0,7	//spi_agc_dsa_A=0x0; 	Address(0x124[7:0])
SPIWrite 0174,01,0,7	//spi_agc_dsa_B=0x1; 	Address(0x174[7:0])
SPIWrite 0174,00,0,7	//spi_agc_dsa_B=0x0; 	Address(0x174[7:0])
SPIWrite 0013,00,0,7	//dsa_page1=0x0; 	Address(0x13[7:6])
SPIWrite 0013,10,0,7	//dsa_page0=0x1; 	Address(0x13[7:4])
SPIWrite 006c,01,0,7	//spi_agc_dsa_fb=0x1; 	Address(0x6c[7:0])
SPIWrite 006c,00,0,7	//spi_agc_dsa_fb=0x0; 	Address(0x6c[7:0])
SPIWrite 0013,00,0,7	//dsa_page0=0x0; 	Address(0x13[7:4])
SPIWrite 0013,80,0,7	//dsa_page1=0x2; 	Address(0x13[7:6])
SPIWrite 00d1,06,0,7	//dig_gain_range=0x6; 	Address(0xd1[7:0])
SPIWrite 0124,01,0,7	//spi_agc_dsa_A=0x1; 	Address(0x124[7:0])
SPIWrite 0124,00,0,7	//spi_agc_dsa_A=0x0; 	Address(0x124[7:0])
SPIWrite 0174,01,0,7	//spi_agc_dsa_B=0x1; 	Address(0x174[7:0])
SPIWrite 0174,00,0,7	//spi_agc_dsa_B=0x0; 	Address(0x174[7:0])
SPIWrite 0013,00,0,7	//dsa_page1=0x0; 	Address(0x13[7:6])
SPIWrite 0013,20,0,7	//dsa_page0=0x2; 	Address(0x13[7:4])
SPIWrite 006c,01,0,7	//spi_agc_dsa_fb=0x1; 	Address(0x6c[7:0])
SPIWrite 006c,00,0,7	//spi_agc_dsa_fb=0x0; 	Address(0x6c[7:0])
SPIWrite 0013,00,0,7	//dsa_page0=0x0; 	Address(0x13[7:4])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0940,00,0,7	//Property_920h_2_0=0x0; 	Address(0x940[7:0])
SPIWrite 0941,00,0,7	//Property_920h_10_8=0x0; 	Address(0x941[7:0])
SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0013,c0,0,7	//dsa_page1=0x3; 	Address(0x13[7:6])
SPIWrite 0545,06,0,7	//Property_524h_13_8=0x6; 	Address(0x545[7:0])
SPIWrite 054a,06,0,7	//Property_528h_21_16=0x6; 	Address(0x54a[7:0])
SPIWrite 05a4,2c,0,7	//Property_584h_5_0=0x2c; 	Address(0x5a4[7:0])
SPIWrite 05a5,18,0,7	//Property_584h_13_8=0x18; 	Address(0x5a5[7:0])
SPIWrite 056e,00,0,7	//Property_54ch_17_0=0x12; 	Address(0x56c[1:0],0x56d[1:0],0x56e[7:0])
SPIWrite 056d,00,0,7
SPIWrite 056c,12,0,7
SPIWrite 0572,00,0,7	//Property_550h_22_0=0x7; 	Address(0x570[6:0],0x571[6:0],0x572[7:0])
SPIWrite 0571,00,0,7
SPIWrite 0570,07,0,7
SPIWrite 0576,00,0,7	//Property_554h_17_0=0x0; 	Address(0x574[1:0],0x575[1:0],0x576[7:0])
SPIWrite 0575,00,0,7
SPIWrite 0574,00,0,7
SPIWrite 057e,00,0,7	//Property_55ch_21_0=0x5c; 	Address(0x57c[5:0],0x57d[5:0],0x57e[7:0])
SPIWrite 057d,00,0,7
SPIWrite 057c,5c,0,7
SPIWrite 057a,00,0,7	//Property_558h_22_0=0x1; 	Address(0x578[6:0],0x579[6:0],0x57a[7:0])
SPIWrite 0579,00,0,7
SPIWrite 0578,01,0,7
SPIWrite 0596,00,0,7	//Property_574h_22_0=0x7; 	Address(0x594[6:0],0x595[6:0],0x596[7:0])
SPIWrite 0595,00,0,7
SPIWrite 0594,07,0,7
SPIWrite 059a,00,0,7	//Property_578h_22_0=0x7; 	Address(0x598[6:0],0x599[6:0],0x59a[7:0])
SPIWrite 0599,00,0,7
SPIWrite 0598,07,0,7
SPIWrite 0556,00,0,7	//Property_534h_17_0=0x12; 	Address(0x554[1:0],0x555[1:0],0x556[7:0])
SPIWrite 0555,00,0,7
SPIWrite 0554,12,0,7
SPIWrite 055a,00,0,7	//Property_538h_22_0=0x7; 	Address(0x558[6:0],0x559[6:0],0x55a[7:0])
SPIWrite 0559,00,0,7
SPIWrite 0558,07,0,7
SPIWrite 055e,00,0,7	//Property_53ch_17_0=0x0; 	Address(0x55c[1:0],0x55d[1:0],0x55e[7:0])
SPIWrite 055d,00,0,7
SPIWrite 055c,00,0,7
SPIWrite 0566,00,0,7	//Property_544h_21_0=0x5c; 	Address(0x564[5:0],0x565[5:0],0x566[7:0])
SPIWrite 0565,00,0,7
SPIWrite 0564,5c,0,7
SPIWrite 0562,00,0,7	//Property_540h_22_0=0x1; 	Address(0x560[6:0],0x561[6:0],0x562[7:0])
SPIWrite 0561,00,0,7
SPIWrite 0560,01,0,7
SPIWrite 058e,00,0,7	//Property_56ch_22_0=0x7; 	Address(0x58c[6:0],0x58d[6:0],0x58e[7:0])
SPIWrite 058d,00,0,7
SPIWrite 058c,07,0,7
SPIWrite 0592,00,0,7	//Property_570h_22_0=0x7; 	Address(0x590[6:0],0x591[6:0],0x592[7:0])
SPIWrite 0591,00,0,7
SPIWrite 0590,07,0,7
SPIWrite 0577,01,0,7	//Property_554h_24_24=0x1; 	Address(0x577[7:0])
SPIWrite 056f,00,0,7	//Property_54ch_24_24=0x0; 	Address(0x56f[7:0])
SPIWrite 05a1,00,0,7	//Property_580h_8_8=0x0; 	Address(0x5a1[7:0])
SPIWrite 055f,01,0,7	//Property_53ch_24_24=0x1; 	Address(0x55f[7:0])
SPIWrite 0557,00,0,7	//Property_534h_24_24=0x0; 	Address(0x557[7:0])
SPIWrite 05a0,00,0,7	//Property_580h_0_0=0x0; 	Address(0x5a0[7:0])
SPIWrite 0013,00,0,7	//dsa_page1=0x0; 	Address(0x13[7:6])

//STEP: topConfig/step2 
SPIWrite 0013,10,0,7	//dsa_page0=0x1; 	Address(0x13[7:4])
SPIWrite 00d0,18,0,7	//txa_dsa_dig0_gain=0x18; 	Address(0xd0[7:0],0xd1[7:0])
SPIWrite 00d4,18,0,7	//txb_dsa_dig0_gain=0x18; 	Address(0xd4[7:0],0xd5[7:0])
SPIWrite 0013,20,0,7	//dsa_page0=0x2; 	Address(0x13[7:4])
SPIWrite 00d0,18,0,7	//txa_dsa_dig0_gain=0x18; 	Address(0xd0[7:0],0xd1[7:0])
SPIWrite 00d4,18,0,7	//txb_dsa_dig0_gain=0x18; 	Address(0xd4[7:0],0xd5[7:0])
SPIWrite 0013,00,0,7	//dsa_page0=0x0; 	Address(0x13[7:4])
SPIWrite 0013,c0,0,7	//dsa_page1=0x3; 	Address(0x13[7:6])
SPIWrite 0a37,40,0,7
SPIWrite 0a3f,40,0,7
SPIWrite 0a4f,40,0,7
SPIWrite 0a5f,40,0,7
SPIWrite 0a77,40,0,7
SPIWrite 0a7f,40,0,7
SPIWrite 0a97,40,0,7
SPIWrite 0a9f,40,0,7
SPIWrite 0aa7,40,0,7
SPIWrite 0aaf,40,0,7
SPIWrite 0c37,40,0,7
SPIWrite 0c3f,40,0,7
SPIWrite 0c4f,40,0,7
SPIWrite 0c5f,40,0,7
SPIWrite 0c77,40,0,7
SPIWrite 0c7f,40,0,7
SPIWrite 0c97,40,0,7
SPIWrite 0c9f,40,0,7
SPIWrite 0ca7,40,0,7
SPIWrite 0caf,40,0,7
SPIWrite 0013,00,0,7	//dsa_page1=0x0; 	Address(0x13[7:6])

//STEP: sysConfig/step0 

//START: Configuring RRF Mode to TOP MCU

SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x3; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,03,0,7
SPIWrite 0193,22,0,7	//MACRO_OPCODE=0x22; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0xf000f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,0f,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,21,0,7	//MACRO_OPCODE=0x21; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,2f,0,7	//MACRO_OPCODE=0x2f; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//END: Configuring RRF Mode to TOP MCU

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])

//STEP: sysConfig/step1 

//START: Configuring RX Chain Parameters to TOP MCU

SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x603; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,06,0,7
SPIWrite 00a0,03,0,7
SPIWrite 0193,2c,0,7	//MACRO_OPCODE=0x2c; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x201; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,02,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,29,0,7	//MACRO_OPCODE=0x29; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x101; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,23,0,7	//MACRO_OPCODE=0x23; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,a3,0,7	//MACRO_OPERAND_REG0=0xa3d70001; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,d7,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 00a7,51,0,7	//MACRO_OPERAND_REG1=0x51ec3d70; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,ec,0,7
SPIWrite 00a5,3d,0,7
SPIWrite 00a4,70,0,7
SPIWrite 00ab,eb,0,7	//MACRO_OPERAND_REG2=0xeb851eb8; 	Address(0xa8[7:0],0xa9[7:0],0xaa[7:0],0xab[7:0],0xac[7:0])
SPIWrite 00aa,85,0,7
SPIWrite 00a9,1e,0,7
SPIWrite 00a8,b8,0,7
SPIWrite 00af,70,0,7	//MACRO_OPERAND_REG3=0x70a4b851; 	Address(0xac[7:0],0xad[7:0],0xae[7:0],0xaf[7:0],0xb0[7:0])
SPIWrite 00ae,a4,0,7
SPIWrite 00ad,b8,0,7
SPIWrite 00ac,51,0,7
SPIWrite 00b3,00,0,7	//MACRO_OPERAND_REG4=0xa3d; 	Address(0xb0[7:0],0xb1[7:0],0xb2[7:0],0xb3[7:0],0xb4[7:0])
SPIWrite 00b2,00,0,7
SPIWrite 00b1,0a,0,7
SPIWrite 00b0,3d,0,7
SPIWrite 0193,31,0,7	//MACRO_OPCODE=0x31; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x202; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,02,0,7
SPIWrite 00a0,02,0,7
SPIWrite 0193,29,0,7	//MACRO_OPCODE=0x29; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x102; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,02,0,7
SPIWrite 0193,23,0,7	//MACRO_OPCODE=0x23; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,a3,0,7	//MACRO_OPERAND_REG0=0xa3d70002; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,d7,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,02,0,7
SPIWrite 00a7,51,0,7	//MACRO_OPERAND_REG1=0x51ec3d70; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,ec,0,7
SPIWrite 00a5,3d,0,7
SPIWrite 00a4,70,0,7
SPIWrite 00ab,eb,0,7	//MACRO_OPERAND_REG2=0xeb851eb8; 	Address(0xa8[7:0],0xa9[7:0],0xaa[7:0],0xab[7:0],0xac[7:0])
SPIWrite 00aa,85,0,7
SPIWrite 00a9,1e,0,7
SPIWrite 00a8,b8,0,7
SPIWrite 00af,70,0,7	//MACRO_OPERAND_REG3=0x70a4b851; 	Address(0xac[7:0],0xad[7:0],0xae[7:0],0xaf[7:0],0xb0[7:0])
SPIWrite 00ae,a4,0,7
SPIWrite 00ad,b8,0,7
SPIWrite 00ac,51,0,7
SPIWrite 00b3,00,0,7	//MACRO_OPERAND_REG4=0xa3d; 	Address(0xb0[7:0],0xb1[7:0],0xb2[7:0],0xb3[7:0],0xb4[7:0])
SPIWrite 00b2,00,0,7
SPIWrite 00b1,0a,0,7
SPIWrite 00b0,3d,0,7
SPIWrite 0193,31,0,7	//MACRO_OPCODE=0x31; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x204; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,02,0,7
SPIWrite 00a0,04,0,7
SPIWrite 0193,29,0,7	//MACRO_OPCODE=0x29; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x104; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,04,0,7
SPIWrite 0193,23,0,7	//MACRO_OPCODE=0x23; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,a3,0,7	//MACRO_OPERAND_REG0=0xa3d70004; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,d7,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,04,0,7
SPIWrite 00a7,51,0,7	//MACRO_OPERAND_REG1=0x51ec3d70; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,ec,0,7
SPIWrite 00a5,3d,0,7
SPIWrite 00a4,70,0,7
SPIWrite 00ab,eb,0,7	//MACRO_OPERAND_REG2=0xeb851eb8; 	Address(0xa8[7:0],0xa9[7:0],0xaa[7:0],0xab[7:0],0xac[7:0])
SPIWrite 00aa,85,0,7
SPIWrite 00a9,1e,0,7
SPIWrite 00a8,b8,0,7
SPIWrite 00af,70,0,7	//MACRO_OPERAND_REG3=0x70a4b851; 	Address(0xac[7:0],0xad[7:0],0xae[7:0],0xaf[7:0],0xb0[7:0])
SPIWrite 00ae,a4,0,7
SPIWrite 00ad,b8,0,7
SPIWrite 00ac,51,0,7
SPIWrite 00b3,00,0,7	//MACRO_OPERAND_REG4=0xa3d; 	Address(0xb0[7:0],0xb1[7:0],0xb2[7:0],0xb3[7:0],0xb4[7:0])
SPIWrite 00b2,00,0,7
SPIWrite 00b1,0a,0,7
SPIWrite 00b0,3d,0,7
SPIWrite 0193,31,0,7	//MACRO_OPCODE=0x31; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x208; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,02,0,7
SPIWrite 00a0,08,0,7
SPIWrite 0193,29,0,7	//MACRO_OPCODE=0x29; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x108; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,08,0,7
SPIWrite 0193,23,0,7	//MACRO_OPCODE=0x23; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,a3,0,7	//MACRO_OPERAND_REG0=0xa3d70008; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,d7,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,08,0,7
SPIWrite 00a7,51,0,7	//MACRO_OPERAND_REG1=0x51ec3d70; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,ec,0,7
SPIWrite 00a5,3d,0,7
SPIWrite 00a4,70,0,7
SPIWrite 00ab,eb,0,7	//MACRO_OPERAND_REG2=0xeb851eb8; 	Address(0xa8[7:0],0xa9[7:0],0xaa[7:0],0xab[7:0],0xac[7:0])
SPIWrite 00aa,85,0,7
SPIWrite 00a9,1e,0,7
SPIWrite 00a8,b8,0,7
SPIWrite 00af,70,0,7	//MACRO_OPERAND_REG3=0x70a4b851; 	Address(0xac[7:0],0xad[7:0],0xae[7:0],0xaf[7:0],0xb0[7:0])
SPIWrite 00ae,a4,0,7
SPIWrite 00ad,b8,0,7
SPIWrite 00ac,51,0,7
SPIWrite 00b3,00,0,7	//MACRO_OPERAND_REG4=0xa3d; 	Address(0xb0[7:0],0xb1[7:0],0xb2[7:0],0xb3[7:0],0xb4[7:0])
SPIWrite 00b2,00,0,7
SPIWrite 00b1,0a,0,7
SPIWrite 00b0,3d,0,7
SPIWrite 0193,31,0,7	//MACRO_OPCODE=0x31; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//END: Configuring RX Chain Parameters to TOP MCU

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])

//STEP: sysConfig/step2 

//START: Configuring FB Chain Parameters to TOP MCU

SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x600; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,06,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,2d,0,7	//MACRO_OPCODE=0x2d; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//END: Configuring FB Chain Parameters to TOP MCU

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])

//STEP: sysConfig/step3 

//START: Configuring TX Chain Parameters to TOP MCU

SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,8d,0,7	//MACRO_OPCODE=0x8d; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0xb03; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,0b,0,7
SPIWrite 00a0,03,0,7
SPIWrite 0193,2e,0,7	//MACRO_OPCODE=0x2e; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x20f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,02,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,2b,0,7	//MACRO_OPCODE=0x2b; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1f0; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,f0,0,7
SPIWrite 0193,23,0,7	//MACRO_OPCODE=0x23; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,51,0,7	//MACRO_OPERAND_REG0=0x51ec000f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,ec,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 00a7,28,0,7	//MACRO_OPERAND_REG1=0x28f69eb8; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,f6,0,7
SPIWrite 00a5,9e,0,7
SPIWrite 00a4,b8,0,7
SPIWrite 00ab,f5,0,7	//MACRO_OPERAND_REG2=0xf5c38f5c; 	Address(0xa8[7:0],0xa9[7:0],0xaa[7:0],0xab[7:0],0xac[7:0])
SPIWrite 00aa,c3,0,7
SPIWrite 00a9,8f,0,7
SPIWrite 00a8,5c,0,7
SPIWrite 00af,b8,0,7	//MACRO_OPERAND_REG3=0xb8525c28; 	Address(0xac[7:0],0xad[7:0],0xae[7:0],0xaf[7:0],0xb0[7:0])
SPIWrite 00ae,52,0,7
SPIWrite 00ad,5c,0,7
SPIWrite 00ac,28,0,7
SPIWrite 00b3,00,0,7	//MACRO_OPERAND_REG4=0x851e; 	Address(0xb0[7:0],0xb1[7:0],0xb2[7:0],0xb3[7:0],0xb4[7:0])
SPIWrite 00b2,00,0,7
SPIWrite 00b1,85,0,7
SPIWrite 00b0,1e,0,7
SPIWrite 0193,30,0,7	//MACRO_OPCODE=0x30; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//END: Configuring TX Chain Parameters to TOP MCU

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])

//STEP: configTune/step0 

//START: Configuring Digital Chain

SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x606; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,06,0,7
SPIWrite 00a0,06,0,7
SPIWrite 0193,3a,0,7	//MACRO_OPCODE=0x3a; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x0; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,90,0,7	//MACRO_OPCODE=0x90; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 0309,04,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,90,0,7	//MACRO_OPCODE=0x90; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0xf0f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,0f,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,36,0,7	//MACRO_OPCODE=0x36; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//END: Configuring Digital Chain

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])

//STEP: configTune/step1 

//START: Setting FIFO Pointers

SPIWrite 0012,01,0,3	//rxdig=0x1; 	Address(0x12[7:0])
SPIWrite 0060,47,0,3	//Property_40h_3_0=0x7; 	Address(0x60[7:0])
SPIWrite 0060,77,4,7	//Property_40h_7_4=0x7; 	Address(0x60[7:4])
SPIWrite 0061,47,0,3	//Property_40h_11_8=0x7; 	Address(0x61[7:0])
SPIWrite 0061,77,4,7	//Property_40h_15_12=0x7; 	Address(0x61[7:4])
SPIWrite 0012,02,0,3	//rxdig=0x2; 	Address(0x12[7:0])
SPIWrite 0060,47,0,3	//Property_40h_3_0=0x7; 	Address(0x60[7:0])
SPIWrite 0060,77,4,7	//Property_40h_7_4=0x7; 	Address(0x60[7:4])
SPIWrite 0061,47,0,3	//Property_40h_11_8=0x7; 	Address(0x61[7:0])
SPIWrite 0061,77,4,7	//Property_40h_15_12=0x7; 	Address(0x61[7:4])
SPIWrite 0012,04,0,3	//rxdig=0x4; 	Address(0x12[7:0])
SPIWrite 0060,47,0,3	//Property_40h_3_0=0x7; 	Address(0x60[7:0])
SPIWrite 0060,77,4,7	//Property_40h_7_4=0x7; 	Address(0x60[7:4])
SPIWrite 0061,47,0,3	//Property_40h_11_8=0x7; 	Address(0x61[7:0])
SPIWrite 0061,77,4,7	//Property_40h_15_12=0x7; 	Address(0x61[7:4])
SPIWrite 0012,08,0,3	//rxdig=0x8; 	Address(0x12[7:0])
SPIWrite 0060,47,0,3	//Property_40h_3_0=0x7; 	Address(0x60[7:0])
SPIWrite 0060,77,4,7	//Property_40h_7_4=0x7; 	Address(0x60[7:4])
SPIWrite 0061,47,0,3	//Property_40h_11_8=0x7; 	Address(0x61[7:0])
SPIWrite 0061,77,4,7	//Property_40h_15_12=0x7; 	Address(0x61[7:4])
SPIWrite 0012,00,0,3	//rxdig=0x0; 	Address(0x12[7:0])
SPIWrite 0012,10,4,5	//fbdig=0x1; 	Address(0x12[7:4])
SPIWrite 0060,47,0,3	//Property_40h_3_0=0x7; 	Address(0x60[7:0])
SPIWrite 0060,77,4,7	//Property_40h_7_4=0x7; 	Address(0x60[7:4])
SPIWrite 0061,47,0,3	//Property_40h_11_8=0x7; 	Address(0x61[7:0])
SPIWrite 0061,77,4,7	//Property_40h_15_12=0x7; 	Address(0x61[7:4])
SPIWrite 0012,20,4,5	//fbdig=0x2; 	Address(0x12[7:4])
SPIWrite 0060,47,0,3	//Property_40h_3_0=0x7; 	Address(0x60[7:0])
SPIWrite 0060,77,4,7	//Property_40h_7_4=0x7; 	Address(0x60[7:4])
SPIWrite 0061,47,0,3	//Property_40h_11_8=0x7; 	Address(0x61[7:0])
SPIWrite 0061,77,4,7	//Property_40h_15_12=0x7; 	Address(0x61[7:4])
SPIWrite 0012,00,4,5	//fbdig=0x0; 	Address(0x12[7:4])
SPIWrite 0019,10,4,7	//txdig=0x1; 	Address(0x19[7:4])
SPIWrite 0062,05,0,3	//Property_40h_19_16=0x5; 	Address(0x62[7:0])
SPIWrite 0019,20,4,7	//txdig=0x2; 	Address(0x19[7:4])
SPIWrite 0062,05,0,3	//Property_40h_19_16=0x5; 	Address(0x62[7:0])
SPIWrite 0019,40,4,7	//txdig=0x4; 	Address(0x19[7:4])
SPIWrite 0062,05,0,3	//Property_40h_19_16=0x5; 	Address(0x62[7:0])
SPIWrite 0019,80,4,7	//txdig=0x8; 	Address(0x19[7:4])
SPIWrite 0062,05,0,3	//Property_40h_19_16=0x5; 	Address(0x62[7:0])
SPIWrite 0019,10,4,7	//txdig=0x1; 	Address(0x19[7:4])
SPIWrite 0060,00,0,3	//Property_40h_3_0=0x0; 	Address(0x60[7:0])
SPIWrite 0019,20,4,7	//txdig=0x2; 	Address(0x19[7:4])
SPIWrite 0060,00,0,3	//Property_40h_3_0=0x0; 	Address(0x60[7:0])
SPIWrite 0019,40,4,7	//txdig=0x4; 	Address(0x19[7:4])
SPIWrite 0060,00,0,3	//Property_40h_3_0=0x0; 	Address(0x60[7:0])
SPIWrite 0019,80,4,7	//txdig=0x8; 	Address(0x19[7:4])
SPIWrite 0060,00,0,3	//Property_40h_3_0=0x0; 	Address(0x60[7:0])
SPIWrite 0019,00,4,7	//txdig=0x0; 	Address(0x19[7:4])
SPIWrite 0016,10,4,4	//jesd_subchip=0x1; 	Address(0x16[7:4])
SPIWrite 0030,8d,0,3	//rxa_afifo_offset=0xd; 	Address(0x30[7:0])
SPIWrite 0030,dd,4,7	//rxb_afifo_offset=0xd; 	Address(0x30[7:4])
SPIWrite 0031,8d,0,3	//rxc_afifo_offset=0xd; 	Address(0x31[7:0])
SPIWrite 0031,dd,4,7	//rxd_afifo_offset=0xd; 	Address(0x31[7:4])
SPIWrite 0032,80,0,3	//fba_afifo_offset=0x0; 	Address(0x32[7:0])
SPIWrite 0032,00,4,7	//fbc_afifo_offset=0x0; 	Address(0x32[7:4])

//END: Setting FIFO Pointers

SPIWrite 0016,00,0,7	//jesd_subchip=0x0; 	Address(0x16[7:4])

//STEP: analogWrites/step0 
SPIWrite 0011,3f,0,7	//ec_ana=0x3f; 	Address(0x11[7:0])
SPIWrite 0075,00,0,7	//Property_75h_7_7_76h_3_0=0x6; 	Address(0x75[7:7],0x76[7:0])
SPIWrite 0076,03,0,7
SPIWrite 0071,04,0,7	//Property_71h_2_1=0x2; 	Address(0x71[7:1])
SPIWrite 0071,14,0,7	//Property_71h_4_4=0x1; 	Address(0x71[7:4])
SPIWrite 0084,80,0,7	//Property_84h_7_6_85h_1_0=0xe; 	Address(0x84[7:6],0x85[7:0])
SPIWrite 0085,03,0,7
SPIWrite 00e7,80,0,7	//Property_e7h_7_7_e8h_1_0=0x7; 	Address(0xe7[7:7],0xe8[7:0])
SPIWrite 00e8,03,0,7
SPIWrite 00e9,38,0,7	//Property_e9h_5_3=0x7; 	Address(0xe9[7:3])
SPIWrite 00da,00,0,7	//Property_dah_7_6=0x0; 	Address(0xda[7:6])
SPIWrite 0066,08,0,7	//Property_66h_3_3=0x1; 	Address(0x66[7:3])
SPIWrite 0011,00,0,7	//ec_ana=0x0; 	Address(0x11[7:0])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIRead 086b,0,7
SPIRead 086a,0,7
SPIRead 0869,0,7
SPIRead 0868,0,7

//Read	Property_848h_31_0=0xc400b00; 	Address(0x868[7:0],0x869[7:0],0x86a[7:0],0x86b[7:0],0x86c[7:0])

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x100; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,71,0,7	//MACRO_OPCODE=0x71; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x124; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,01,0,7
SPIWrite 00a0,24,0,7
SPIWrite 0193,72,0,7	//MACRO_OPCODE=0x72; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,06,0,7	//MACRO_OPERAND_REG0=0x6010600; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,01,0,7
SPIWrite 00a1,06,0,7
SPIWrite 00a0,00,0,7
SPIWrite 00a7,13,0,7	//MACRO_OPERAND_REG1=0x13090807; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,09,0,7
SPIWrite 00a5,08,0,7
SPIWrite 00a4,07,0,7
SPIWrite 0193,71,0,7	//MACRO_OPCODE=0x71; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0011,3f,0,7	//ec_ana=0x3f; 	Address(0x11[7:0])
SPIWrite 0060,01,0,7	//Property_60h_0_0=0x1; 	Address(0x60[7:0])
SPIWrite 0060,00,0,7	//Property_60h_0_0=0x0; 	Address(0x60[7:0])
SPIWrite 0011,00,0,7	//ec_ana=0x0; 	Address(0x11[7:0])

//STEP: analogWrites/step1 
SPIWrite 0013,0f,0,7	//txdh=0xf; 	Address(0x13[7:0])
SPIWrite 015a,02,0,7	//Property_138h_17_17=0x1; 	Address(0x15a[7:1])
SPIWrite 0013,00,0,7	//txdh=0x0; 	Address(0x13[7:0])

//START: Removing TDD Pin Overrides.

SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 00ed,00,0,7	//Property_cch_11_8=0x0; 	Address(0xed[7:0])
SPIWrite 00f5,00,0,7	//Property_d4h_9_8=0x0; 	Address(0xf5[7:0])
SPIWrite 00e5,0f,0,7	//Property_c4h_11_8=0xf; 	Address(0xe5[7:0])

//END: Removing TDD Pin Overrides.


//START: DAC Analog Writes

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0013,0f,0,7	//txdh=0xf; 	Address(0x13[7:0])
SPIWrite 015a,22,0,7	//Property_138h_21_21=0x1; 	Address(0x15a[7:5])
SPIWrite 01bd,00,0,7	//Property_19ch_15_0=0x1; 	Address(0x1bc[7:0],0x1bd[7:0],0x1be[7:0])
SPIWrite 01bc,01,0,7
SPIWrite 0070,27,0,7	//Property_50h_5_0=0x27; 	Address(0x70[7:0])
SPIWrite 0071,27,0,7	//Property_50h_13_8=0x27; 	Address(0x71[7:0])
SPIWrite 0072,27,0,7	//Property_50h_21_16=0x27; 	Address(0x72[7:0])
SPIWrite 0074,27,0,7	//Property_54h_5_0=0x27; 	Address(0x74[7:0])
SPIWrite 0075,27,0,7	//Property_54h_13_8=0x27; 	Address(0x75[7:0])
SPIWrite 0076,27,0,7	//Property_54h_21_16=0x27; 	Address(0x76[7:0])
SPIWrite 0078,27,0,7	//Property_58h_5_0=0x27; 	Address(0x78[7:0])
SPIWrite 0079,27,0,7	//Property_58h_13_8=0x27; 	Address(0x79[7:0])
SPIWrite 007a,27,0,7	//Property_58h_21_16=0x27; 	Address(0x7a[7:0])
SPIWrite 015a,26,0,7	//Property_138h_18_18=0x1; 	Address(0x15a[7:2])
SPIWrite 015a,26,0,7	//Property_138h_18_18=0x1; 	Address(0x15a[7:2])
SPIWrite 0025,00,0,7	//Property_4h_8_8=0x0; 	Address(0x25[7:0])
SPIWrite 0168,01,0,7	//Property_148h_0_0=0x1; 	Address(0x168[7:0])
SPIWrite 017c,01,0,7	//Property_15ch_0_0=0x1; 	Address(0x17c[7:0])
SPIWrite 01b1,00,0,7	//Property_190h_15_0=0x10; 	Address(0x1b0[7:0],0x1b1[7:0],0x1b2[7:0])
SPIWrite 01b0,10,0,7
SPIWrite 0158,01,0,7	//Property_138h_0_0=0x1; 	Address(0x158[7:0])
SPIWrite 0159,01,0,7	//Property_138h_8_8=0x1; 	Address(0x159[7:0])
SPIWrite 0177,00,0,7	//Property_154h_31_0_158h_3_0=0x800000001; 	Address(0x174[7:0],0x175[7:0],0x176[7:0],0x177[7:0],0x178[7:0],0x178[7:0])
SPIWrite 0176,00,0,7
SPIWrite 0175,00,0,7
SPIWrite 0174,01,0,7
SPIWrite 0178,08,0,7
SPIWrite 018b,00,0,7	//Property_168h_31_0_16ch_3_0=0x800000001; 	Address(0x188[7:0],0x189[7:0],0x18a[7:0],0x18b[7:0],0x18c[7:0],0x18c[7:0])
SPIWrite 018a,00,0,7
SPIWrite 0189,00,0,7
SPIWrite 0188,01,0,7
SPIWrite 018c,08,0,7
SPIWrite 011a,00,0,7	//Property_f8h_20_0=0x0; 	Address(0x118[4:0],0x119[4:0],0x11a[7:0])
SPIWrite 0119,00,0,7
SPIWrite 0118,00,0,7
SPIWrite 0126,00,0,7	//Property_104h_20_0=0x0; 	Address(0x124[4:0],0x125[4:0],0x126[7:0])
SPIWrite 0125,00,0,7
SPIWrite 0124,00,0,7
SPIWrite 01c5,3d,0,7	//Property_1a4h_15_0=0x3de0; 	Address(0x1c4[7:0],0x1c5[7:0],0x1c6[7:0])
SPIWrite 01c4,e0,0,7
SPIWrite 0029,00,0,7	//Property_8h_8_8=0x0; 	Address(0x29[7:0])
SPIWrite 018e,01,0,7	//Property_16ch_16_16=0x1; 	Address(0x18e[7:0])
SPIWrite 0112,00,0,7	//Property_f0h_18_0=0x0; 	Address(0x110[2:0],0x111[2:0],0x112[7:0])
SPIWrite 0111,00,0,7
SPIWrite 0110,00,0,7
SPIWrite 0151,0e,0,7	//Property_130h_15_0=0xed3; 	Address(0x150[7:0],0x151[7:0],0x152[7:0])
SPIWrite 0150,d3,0,7
SPIWrite 01ad,00,0,7	//Property_18ch_15_0=0xff; 	Address(0x1ac[7:0],0x1ad[7:0],0x1ae[7:0])
SPIWrite 01ac,ff,0,7
SPIWrite 0162,00,0,7	//Property_140h_19_16=0x0; 	Address(0x162[7:0])
SPIWrite 0163,00,0,7	//Property_140h_27_24=0x0; 	Address(0x163[7:0])
SPIWrite 0013,00,0,7	//txdh=0x0; 	Address(0x13[7:0])
SPIWrite 0013,0f,0,7	//txdh=0xf; 	Address(0x13[7:0])
SPIWrite 0133,00,0,7	//Property_110h_31_0_114h_14_0=0x1fe0; 	Address(0x130[7:0],0x131[7:0],0x132[7:0],0x133[7:0],0x134[7:0],0x134[6:0],0x135[7:0])
SPIWrite 0132,00,0,7
SPIWrite 0131,1f,0,7
SPIWrite 0130,e0,0,7
SPIWrite 0135,00,0,7
SPIWrite 0134,00,0,7
SPIWrite 0013,00,0,7	//txdh=0x0; 	Address(0x13[7:0])

//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,01,0,7	//pll_reg_spi_req_a=0x1; 	Address(0x170[7:0])
SPIWrite 0540,00,0,7	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

SPIPoll 0171,0,0,01
SPIRead 0171,0,0

//Read	pll_reg_spi_a_ack=0x1(Meaning: );; 	Address(0x171[7:0])


//END: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0014,ff,0,7	//txcalib=0xff; 	Address(0x14[7:0],0x15[7:0])
SPIWrite 0119,00,0,7	//Property_f8h_15_0=0x1; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0])
SPIWrite 0118,01,0,7
SPIWrite 0119,00,0,7	//Property_f8h_15_0=0x0; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0])
SPIWrite 0118,00,0,7

//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0014,00,0,7	//txcalib=0x0; 	Address(0x14[7:0],0x15[7:0])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,00,0,7	//pll_reg_spi_req_a=0x0; 	Address(0x170[7:0])
SPIWrite 0540,00,0,7	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

//END: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0019,f0,0,7	//txdig=0xf; 	Address(0x19[7:4])
SPIWrite 07d3,01,0,7	//EnDacDataRandomization=0x1; 	Address(0x7d3[7:0])
SPIWrite 0019,00,0,7	//txdig=0x0; 	Address(0x19[7:4])
SPIWrite 0019,f0,0,7	//txdig=0xf; 	Address(0x19[7:4])
SPIWrite 0320,00,0,7	//Property_300h_3_0=0x0; 	Address(0x320[7:0])
SPIWrite 0019,00,0,7	//txdig=0x0; 	Address(0x19[7:4])
SPIWrite 0013,0f,0,7	//txdh=0xf; 	Address(0x13[7:0])
SPIWrite 0024,01,0,7	//Property_4h_1_0=0x1; 	Address(0x24[7:0])
SPIWrite 0013,00,0,7	//txdh=0x0; 	Address(0x13[7:0])
SPIWrite 0019,f0,0,7	//txdig=0xf; 	Address(0x19[7:4])
SPIWrite 030c,00,0,7	//Property_2ech_0_0=0x0; 	Address(0x30c[7:0])
SPIWrite 0019,00,0,7	//txdig=0x0; 	Address(0x19[7:4])
SPIWrite 0013,0f,0,7	//txdh=0xf; 	Address(0x13[7:0])
SPIWrite 011a,00,0,7	//Property_f8h_20_0=0x2000; 	Address(0x118[4:0],0x119[4:0],0x11a[7:0])
SPIWrite 0119,20,0,7
SPIWrite 0118,00,0,7
SPIWrite 0126,00,0,7	//Property_104h_20_0=0x2000; 	Address(0x124[4:0],0x125[4:0],0x126[7:0])
SPIWrite 0125,20,0,7
SPIWrite 0124,00,0,7
SPIWrite 0013,00,0,7	//txdh=0x0; 	Address(0x13[7:0])
SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 00fd,01,0,7	//Property_dch_15_0=0x180; 	Address(0xfc[7:0],0xfd[7:0],0xfe[7:0])
SPIWrite 00fc,80,0,7
SPIWrite 0101,01,0,7	//Property_e0h_15_0=0x180; 	Address(0x100[7:0],0x101[7:0],0x102[7:0])
SPIWrite 0100,80,0,7
SPIWrite 019d,01,0,7	//Property_17ch_15_0=0x180; 	Address(0x19c[7:0],0x19d[7:0],0x19e[7:0])
SPIWrite 019c,80,0,7
SPIWrite 01a1,01,0,7	//Property_180h_15_0=0x180; 	Address(0x1a0[7:0],0x1a1[7:0],0x1a2[7:0])
SPIWrite 01a0,80,0,7
SPIWrite 023d,01,0,7	//Property_21ch_15_0=0x180; 	Address(0x23c[7:0],0x23d[7:0],0x23e[7:0])
SPIWrite 023c,80,0,7
SPIWrite 0241,01,0,7	//Property_220h_15_0=0x180; 	Address(0x240[7:0],0x241[7:0],0x242[7:0])
SPIWrite 0240,80,0,7
SPIWrite 02dd,01,0,7	//Property_2bch_15_0=0x180; 	Address(0x2dc[7:0],0x2dd[7:0],0x2de[7:0])
SPIWrite 02dc,80,0,7
SPIWrite 02e1,01,0,7	//Property_2c0h_15_0=0x180; 	Address(0x2e0[7:0],0x2e1[7:0],0x2e2[7:0])
SPIWrite 02e0,80,0,7
SPIWrite 0135,0c,0,7	//Property_114h_15_0=0xc00; 	Address(0x134[7:0],0x135[7:0],0x136[7:0])
SPIWrite 0134,00,0,7
SPIWrite 01d5,0c,0,7	//Property_1b4h_15_0=0xc00; 	Address(0x1d4[7:0],0x1d5[7:0],0x1d6[7:0])
SPIWrite 01d4,00,0,7
SPIWrite 0275,0c,0,7	//Property_254h_15_0=0xc00; 	Address(0x274[7:0],0x275[7:0],0x276[7:0])
SPIWrite 0274,00,0,7
SPIWrite 0315,0c,0,7	//Property_2f4h_15_0=0xc00; 	Address(0x314[7:0],0x315[7:0],0x316[7:0])
SPIWrite 0314,00,0,7
SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0013,0f,0,7	//txdh=0xf; 	Address(0x13[7:0])
SPIWrite 0167,02,0,7	//Property_144h_27_0=0x2000000; 	Address(0x164[3:0],0x165[3:0],0x166[3:0],0x167[7:0])
SPIWrite 0166,00,0,7
SPIWrite 0165,00,0,7
SPIWrite 0164,00,0,7
SPIWrite 01b1,00,0,7	//Property_190h_15_0=0x30; 	Address(0x1b0[7:0],0x1b1[7:0],0x1b2[7:0])
SPIWrite 01b0,30,0,7
SPIWrite 0112,01,0,7	//Property_f0h_18_0=0x10000; 	Address(0x110[2:0],0x111[2:0],0x112[7:0])
SPIWrite 0111,00,0,7
SPIWrite 0110,00,0,7
SPIWrite 0013,00,0,7	//txdh=0x0; 	Address(0x13[7:0])
SPIWrite 0019,f0,0,7	//txdig=0xf; 	Address(0x19[7:4])
SPIWrite 07b2,00,0,7	//rf_droop_comp_bypass=0x0; 	Address(0x7b2[7:0])
SPIWrite 07b0,1c,0,7	//rf_headroom_band0=0x1c; 	Address(0x7b0[7:0])
SPIWrite 07b1,1c,0,7	//rf_headroom_band1=0x1c; 	Address(0x7b1[7:0])
SPIWrite 0019,00,0,7	//txdig=0x0; 	Address(0x19[7:4])
SPIWrite 0013,0f,0,7	//txdh=0xf; 	Address(0x13[7:0])
SPIWrite 0107,40,0,7	//Property_e4h_31_0_e8h_19_0=0x800240000000; 	Address(0x104[7:0],0x105[7:0],0x106[7:0],0x107[7:0],0x108[7:0],0x108[3:0],0x109[3:0],0x10a[7:0])
SPIWrite 0106,00,0,7
SPIWrite 0105,00,0,7
SPIWrite 0104,00,0,7
SPIWrite 010a,00,0,7
SPIWrite 0109,80,0,7
SPIWrite 0108,02,0,7
SPIWrite 0107,40,0,7	//Property_e4h_31_0_e8h_19_0=0x800a40000000; 	Address(0x104[7:0],0x105[7:0],0x106[7:0],0x107[7:0],0x108[7:0],0x108[3:0],0x109[3:0],0x10a[7:0])
SPIWrite 0106,00,0,7
SPIWrite 0105,00,0,7
SPIWrite 0104,00,0,7
SPIWrite 010a,00,0,7
SPIWrite 0109,80,0,7
SPIWrite 0108,0a,0,7
SPIWrite 0107,60,0,7	//Property_e4h_31_0_e8h_19_0=0x800a60000000; 	Address(0x104[7:0],0x105[7:0],0x106[7:0],0x107[7:0],0x108[7:0],0x108[3:0],0x109[3:0],0x10a[7:0])
SPIWrite 0106,00,0,7
SPIWrite 0105,00,0,7
SPIWrite 0104,00,0,7
SPIWrite 010a,00,0,7
SPIWrite 0109,80,0,7
SPIWrite 0108,0a,0,7
SPIWrite 0107,40,0,7	//Property_e4h_31_0_e8h_19_0=0x800a40000000; 	Address(0x104[7:0],0x105[7:0],0x106[7:0],0x107[7:0],0x108[7:0],0x108[3:0],0x109[3:0],0x10a[7:0])
SPIWrite 0106,00,0,7
SPIWrite 0105,00,0,7
SPIWrite 0104,00,0,7
SPIWrite 010a,00,0,7
SPIWrite 0109,80,0,7
SPIWrite 0108,0a,0,7
SPIWrite 0195,02,0,7	//Property_174h_9_0=0x200; 	Address(0x194[1:0],0x195[7:0])
SPIWrite 0194,00,0,7
SPIWrite 0197,02,0,7	//Property_174h_25_16=0x200; 	Address(0x196[1:0],0x197[7:0])
SPIWrite 0196,00,0,7
SPIWrite 01b5,03,0,7
SPIWrite 01b4,ff,0,7
SPIWrite 0013,00,0,7	//txdh=0x0; 	Address(0x13[7:0])
SPIWrite 0019,f0,0,7	//txdig=0xf; 	Address(0x19[7:4])
SPIWrite 07b0,1c,0,7	//rf_headroom_band0=0x1c; 	Address(0x7b0[7:0])
SPIWrite 07b1,1c,0,7	//rf_headroom_band1=0x1c; 	Address(0x7b1[7:0])
SPIWrite 0019,00,0,7	//txdig=0x0; 	Address(0x19[7:4])

//END: DAC Analog Writes

SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,0a,0,7	//MACRO_OPERAND_REG0=0xa101014; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,10,0,7
SPIWrite 00a1,10,0,7
SPIWrite 00a0,14,0,7
SPIWrite 00a7,1f,0,7	//MACRO_OPERAND_REG1=0x1f010100; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,01,0,7
SPIWrite 00a5,01,0,7
SPIWrite 00a4,00,0,7
SPIWrite 00ab,03,0,7	//MACRO_OPERAND_REG2=0x303041f; 	Address(0xa8[7:0],0xa9[7:0],0xaa[7:0],0xab[7:0],0xac[7:0])
SPIWrite 00aa,03,0,7
SPIWrite 00a9,04,0,7
SPIWrite 00a8,1f,0,7
SPIWrite 00af,00,0,7	//MACRO_OPERAND_REG3=0x101; 	Address(0xac[7:0],0xad[7:0],0xae[7:0],0xaf[7:0],0xb0[7:0])
SPIWrite 00ae,00,0,7
SPIWrite 00ad,01,0,7
SPIWrite 00ac,01,0,7
SPIWrite 0193,88,0,7	//MACRO_OPCODE=0x88; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x0; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,90,0,7	//MACRO_OPCODE=0x90; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 1f96,00,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 1bd4,10,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,90,0,7	//MACRO_OPCODE=0x90; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//START: Configuring AUX ADC

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 00c0,c4,0,7	//Property_a0h_6_6=0x1; 	Address(0xc0[7:6])
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0500,01,0,7	//Property_4e0h_0_0=0x1; 	Address(0x500[7:0])
SPIWrite 0500,01,0,7	//Property_4e0h_1_1=0x0; 	Address(0x500[7:1])
SPIWrite 0500,09,0,7	//Property_4e0h_3_3=0x1; 	Address(0x500[7:3])
SPIWrite 0506,01,0,7	//Property_4e4h_16_16=0x1; 	Address(0x506[7:0])
SPIWrite 0502,00,0,7	//Property_4e0h_23_21=0x0; 	Address(0x502[7:5])
SPIWrite 0502,00,0,7	//Property_4e0h_20_18=0x0; 	Address(0x502[7:2])
SPIWrite 0501,08,0,7	//Property_4e0h_12_11=0x1; 	Address(0x501[7:3])
SPIWrite 0501,0a,0,7	//Property_4e0h_10_8=0x2; 	Address(0x501[7:0])
SPIWrite 0508,00,0,7	//Property_4e8h_5_5=0x0; 	Address(0x508[7:5])
SPIWrite 0505,a0,0,7	//Property_4e4h_15_13=0x5; 	Address(0x505[7:5])
SPIWrite 0505,a1,0,7	//Property_4e4h_9_8=0x1; 	Address(0x505[7:0])
SPIWrite 0506,05,0,7	//Property_4e4h_18_17=0x2; 	Address(0x506[7:1])
SPIWrite 0506,15,0,7	//Property_4e4h_20_19=0x2; 	Address(0x506[7:3])
SPIWrite 0506,15,0,7	//Property_4e4h_23_21=0x0; 	Address(0x506[7:5])
SPIWrite 0505,a1,0,7	//Property_4e4h_12_10=0x0; 	Address(0x505[7:2])
SPIWrite 0508,00,0,7	//Property_4e8h_6_6=0x0; 	Address(0x508[7:6])
SPIWrite 0508,00,0,7	//Property_4e8h_4_4=0x0; 	Address(0x508[7:4])
SPIWrite 0503,00,0,7	//Property_4e0h_31_30=0x0; 	Address(0x503[7:6])
SPIWrite 0502,00,0,7	//Property_4e0h_17_16=0x0; 	Address(0x502[7:0])
SPIWrite 0500,01,0,7	//Property_4e0h_3_3=0x0; 	Address(0x500[7:3])
SPIWrite 0500,03,0,7	//Property_4e0h_1_1=0x1; 	Address(0x500[7:1])

//END: Configuring AUX ADC

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])

//STEP: analogWrites/step2 

//START: Removing TDD Pin Overrides.

SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 00ed,0f,0,7	//Property_cch_11_8=0xf; 	Address(0xed[7:0])
SPIWrite 00f5,00,0,7	//Property_d4h_9_8=0x0; 	Address(0xf5[7:0])
SPIWrite 00e5,00,0,7	//Property_c4h_11_8=0x0; 	Address(0xe5[7:0])

//END: Removing TDD Pin Overrides.

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0011,3f,0,7	//ec_ana=0x3f; 	Address(0x11[7:0])
SPIWrite 0063,80,0,7	//Property_63h_7_7=0x1; 	Address(0x63[7:7])
SPIWrite 0067,10,0,7	//Property_67h_4_4=0x1; 	Address(0x67[7:4])
SPIWrite 0077,0c,0,7	//Property_77h_5_1=0x6; 	Address(0x77[7:1])
SPIWrite 0076,53,0,7	//Property_76h_6_4=0x5; 	Address(0x76[7:4])
SPIWrite 0082,80,0,7	//Property_82h_7_6=0x2; 	Address(0x82[7:6])
SPIWrite 0082,a0,0,7	//Property_82h_5_3=0x4; 	Address(0x82[7:3])
SPIWrite 0081,30,0,7	//Property_81h_5_4=0x3; 	Address(0x81[7:4])
SPIWrite 0086,c0,0,7	//Property_86h_7_5_87h_0_0=0xe; 	Address(0x86[7:5],0x87[7:0])
SPIWrite 0087,01,0,7
SPIWrite 0084,85,0,7	//Property_84h_2_0=0x5; 	Address(0x84[7:0])
SPIWrite 0087,05,0,7	//Property_87h_2_1=0x2; 	Address(0x87[7:1])
SPIWrite 00f9,00,0,7	//Property_f9h_7_7_fah_2_0=0xc; 	Address(0xf9[7:7],0xfa[7:0])
SPIWrite 00fa,06,0,7
SPIWrite 00e8,83,0,7	//Property_e8h_7_5=0x4; 	Address(0xe8[7:5])
SPIWrite 014e,01,0,7	//Property_14eh_2_0=0x1; 	Address(0x14e[7:0])
SPIWrite 014d,1c,0,7	//Property_14dh_4_2=0x7; 	Address(0x14d[7:2])
SPIWrite 014c,20,0,7	//Property_14ch_5_3=0x4; 	Address(0x14c[7:3])
SPIWrite 0138,18,0,7	//Property_138h_5_3=0x3; 	Address(0x138[7:3])
SPIWrite 013e,40,0,7	//Property_13eh_6_6=0x1; 	Address(0x13e[7:6])
SPIWrite 004a,60,0,7	//Property_4ah_6_4=0x6; 	Address(0x4a[7:4])
SPIWrite 0049,80,0,7	//Property_49h_7_6_4ah_0_0=0x6; 	Address(0x49[7:6],0x4a[7:0])
SPIWrite 004a,61,0,7
SPIWrite 00c2,c0,0,7	//Property_c2h_7_5=0x6; 	Address(0xc2[7:5])
SPIWrite 00c1,60,0,7	//Property_c1h_6_4=0x6; 	Address(0xc1[7:4])
SPIWrite 00b6,0c,0,7	//Property_b6h_3_2=0x3; 	Address(0xb6[7:2])
SPIWrite 004f,0c,0,7	//Property_4fh_3_2=0x3; 	Address(0x4f[7:2])
SPIWrite 012e,80,0,7	//Property_12eh_7_7_12fh_1_0=0x7; 	Address(0x12e[7:7],0x12f[7:0])
SPIWrite 012f,03,0,7
SPIWrite 012e,f0,0,7	//Property_12eh_6_4=0x7; 	Address(0x12e[7:4])
SPIWrite 012f,03,0,7	//Property_12fh_3_2=0x0; 	Address(0x12f[7:2])
SPIWrite 0011,00,0,7	//ec_ana=0x0; 	Address(0x11[7:0])
SPIWrite 0010,3f,0,7	//ec_dig=0x3f; 	Address(0x10[7:0])
SPIWrite 00c1,5a,0,7	//Property_c1h_6_0=0x5a; 	Address(0xc1[7:0])
SPIWrite 0078,60,0,7	//Property_78h_7_7=0x0; 	Address(0x78[7:7])
SPIWrite 00c0,17,0,7	//Property_c0h_3_3=0x0; 	Address(0xc0[7:3])
SPIWrite 00d5,00,0,7	//Property_d5h_1_0=0x0; 	Address(0xd5[7:0])
SPIWrite 00d5,08,0,7	//Property_d5h_3_2=0x2; 	Address(0xd5[7:2])
SPIWrite 0150,30,0,7	//Property_150h_3_3=0x0; 	Address(0x150[7:3])
SPIWrite 00f8,51,0,7	//Property_f8h_7_0_f9h_7_0_fah_7_0_fbh_7_0_fch_7_0=0xa8c0c5051; 	Address(0xf8[7:0],0xf9[7:0],0xf9[7:0],0xfa[7:0],0xfa[7:0],0xfb[7:0],0xfb[7:0],0xfc[7:0],0xfc[7:0],0xfd[7:0])
SPIWrite 00f9,50,0,7
SPIWrite 00fa,0c,0,7
SPIWrite 00fb,8c,0,7
SPIWrite 00fc,0a,0,7
SPIWrite 0168,02,0,7	//Property_168h_1_1=0x1; 	Address(0x168[7:1])
SPIWrite 00ef,08,0,7	//Property_efh_6_6=0x0; 	Address(0xef[7:6])
SPIWrite 0178,71,0,7	//Property_178h_4_4=0x1; 	Address(0x178[7:4])
SPIWrite 0075,b5,0,7	//Property_75h_4_4=0x1; 	Address(0x75[7:4])
SPIWrite 0168,06,0,7	//Property_168h_2_2=0x1; 	Address(0x168[7:2])
SPIWrite 0168,02,0,7	//Property_168h_2_2=0x0; 	Address(0x168[7:2])
SPIWrite 0169,bb,0,7	//Property_169h_3_0=0xb; 	Address(0x169[7:0])
SPIWrite 0074,7a,0,7	//Property_74h_7_7=0x0; 	Address(0x74[7:7])
SPIWrite 013c,fe,0,7	//Property_13ch_7_0_13dh_7_0_13eh_7_0=0x6bfffe; 	Address(0x13c[7:0],0x13d[7:0],0x13d[7:0],0x13e[7:0],0x13e[7:0],0x13f[7:0])
SPIWrite 013d,ff,0,7
SPIWrite 013e,6b,0,7
SPIWrite 0124,fe,0,7	//Property_124h_7_0_125h_7_0_126h_7_0=0x6bfffe; 	Address(0x124[7:0],0x125[7:0],0x125[7:0],0x126[7:0],0x126[7:0],0x127[7:0])
SPIWrite 0125,ff,0,7
SPIWrite 0126,6b,0,7
SPIWrite 0129,24,0,7	//Property_129h_2_0=0x4; 	Address(0x129[7:0])
SPIWrite 0130,76,0,7	//Property_130h_2_2=0x1; 	Address(0x130[7:2])
SPIWrite 0130,7e,0,7	//Property_130h_3_3=0x1; 	Address(0x130[7:3])
SPIWrite 0044,01,0,7	//Property_44h_0_0=0x1; 	Address(0x44[7:0])
SPIWrite 003c,01,0,7	//Property_3ch_0_0=0x1; 	Address(0x3c[7:0])
SPIWrite 003c,00,0,7	//Property_3ch_0_0=0x0; 	Address(0x3c[7:0])
SPIWrite 0044,00,0,7	//Property_44h_0_0=0x0; 	Address(0x44[7:0])
SPIWrite 00e8,00,0,7	//Property_e8h_0_0=0x0; 	Address(0xe8[7:0])
SPIWrite 00e8,01,0,7	//Property_e8h_0_0=0x1; 	Address(0xe8[7:0])
SPIWrite 0010,00,0,7	//ec_dig=0x0; 	Address(0x10[7:0])
SPIWrite 0015,04,0,7	//rx=0x1; 	Address(0x15[7:2])
SPIWrite 0063,00,0,7	//Property_40h_31_0=0x40000; 	Address(0x60[7:0],0x61[7:0],0x62[7:0],0x63[7:0],0x64[7:0])
SPIWrite 0062,04,0,7
SPIWrite 0061,00,0,7
SPIWrite 0060,00,0,7
SPIWrite 0038,b0,0,7
SPIWrite 0028,04,0,7
SPIWrite 0015,08,0,7	//rx=0x2; 	Address(0x15[7:2])
SPIWrite 0063,00,0,7	//Property_40h_31_0=0x40000; 	Address(0x60[7:0],0x61[7:0],0x62[7:0],0x63[7:0],0x64[7:0])
SPIWrite 0062,04,0,7
SPIWrite 0061,00,0,7
SPIWrite 0060,00,0,7
SPIWrite 0038,b0,0,7
SPIWrite 0028,04,0,7
SPIWrite 0015,00,0,7	//rx=0x0; 	Address(0x15[7:2])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 006b,00,0,7	//Property_48h_31_0=0x8; 	Address(0x68[7:0],0x69[7:0],0x6a[7:0],0x6b[7:0],0x6c[7:0])
SPIWrite 006a,00,0,7
SPIWrite 0069,00,0,7
SPIWrite 0068,08,0,7
SPIWrite 0067,00,0,7	//Property_44h_31_0=0x4000; 	Address(0x64[7:0],0x65[7:0],0x66[7:0],0x67[7:0],0x68[7:0])
SPIWrite 0066,00,0,7
SPIWrite 0065,40,0,7
SPIWrite 0064,00,0,7
SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])
SPIWrite 0012,0f,0,7	//rxdig=0xf; 	Address(0x12[7:0])
SPIWrite 20f4,32,0,7	//DSAGainRange0=0x32; 	Address(0x20f4[7:0])
SPIWrite 20f5,32,0,7	//DSAGainRange1=0x32; 	Address(0x20f5[7:0])
SPIWrite 20f6,32,0,7	//DSAGainRange2=0x32; 	Address(0x20f6[7:0])
SPIWrite 20f7,32,0,7	//DSAGainRange3=0x32; 	Address(0x20f7[7:0])
SPIWrite 20f8,32,0,7	//DSAGainRange4=0x32; 	Address(0x20f8[7:0])
SPIWrite 20f9,32,0,7	//DSAGainRange5=0x32; 	Address(0x20f9[7:0])
SPIWrite 0012,00,0,7	//rxdig=0x0; 	Address(0x12[7:0])
SPIWrite 0012,30,0,7	//fbdig=0x3; 	Address(0x12[7:4])
SPIWrite 20f4,32,0,7	//DSAGainRange0=0x32; 	Address(0x20f4[7:0])
SPIWrite 20f5,32,0,7	//DSAGainRange1=0x32; 	Address(0x20f5[7:0])
SPIWrite 20f6,32,0,7	//DSAGainRange2=0x32; 	Address(0x20f6[7:0])
SPIWrite 20f7,32,0,7	//DSAGainRange3=0x32; 	Address(0x20f7[7:0])
SPIWrite 20f8,32,0,7	//DSAGainRange4=0x32; 	Address(0x20f8[7:0])
SPIWrite 20f9,32,0,7	//DSAGainRange5=0x32; 	Address(0x20f9[7:0])
SPIWrite 0012,00,0,7	//fbdig=0x0; 	Address(0x12[7:4])

//STEP: analogWrites/step3 

//START: PLL Ana Trims


//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,40,6,6	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,01,0,0	//pll_reg_spi_req_a=0x1; 	Address(0x170[7:0])
SPIWrite 0540,00,0,0	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

SPIPoll 0171,0,0,01
SPIRead 0171,0,0

//Read	pll_reg_spi_a_ack=0x1(Meaning: );; 	Address(0x171[7:0])


//END: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,6,6	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0015,01,0,0	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 005e,01,0,0	//Property_3ch_16_16=0x1; 	Address(0x5e[7:0])
SPIWrite 005d,e8,5,7	//Property_3ch_15_13=0x7; 	Address(0x5d[7:5])

//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,0	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,40,6,6	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,00,0,0	//pll_reg_spi_req_a=0x0; 	Address(0x170[7:0])
SPIWrite 0540,00,0,0	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

//END: Requesting/releasing SPI Access to PLL Pages

SPIWrite 050f,00,0,7	//Property_4ech_31_0=0xc0000; 	Address(0x50c[7:0],0x50d[7:0],0x50e[7:0],0x50f[7:0],0x510[7:0])
SPIWrite 050e,0c,0,7
SPIWrite 050d,00,0,7
SPIWrite 050c,00,0,7
SPIWrite 0015,00,6,6	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0015,02,1,1	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 00bb,00,0,7	//Property_98h_31_0=0x600; 	Address(0xb8[7:0],0xb9[7:0],0xba[7:0],0xbb[7:0],0xbc[7:0])
SPIWrite 00ba,00,0,7
SPIWrite 00b9,06,0,7
SPIWrite 00b8,00,0,7
SPIWrite 00bb,03,0,7	//Property_98h_31_0=0x3008000; 	Address(0xb8[7:0],0xb9[7:0],0xba[7:0],0xbb[7:0],0xbc[7:0])
SPIWrite 00ba,00,0,7
SPIWrite 00b9,80,0,7
SPIWrite 00b8,00,0,7
SPIWrite 00bb,00,0,7	//Property_98h_31_0=0x600; 	Address(0xb8[7:0],0xb9[7:0],0xba[7:0],0xbb[7:0],0xbc[7:0])
SPIWrite 00ba,00,0,7
SPIWrite 00b9,06,0,7
SPIWrite 00b8,00,0,7

//END: PLL Ana Trims

SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])

//STEP: jesdConfig/step0 

//START: Configuring JESD Muxes and Pointers


//START: Configuring JESD TX Lane Mux

SPIWrite 0016,10,0,7	//jesd_subchip=0x1; 	Address(0x16[7:4])
SPIWrite 0048,10,0,7	//txoctetpath0_sel=0x0; 	Address(0x48[7:0])
SPIWrite 0048,10,0,7	//txoctetpath1_sel=0x1; 	Address(0x48[7:4])
SPIWrite 0049,32,0,7	//txoctetpath2_sel=0x2; 	Address(0x49[7:0])
SPIWrite 0049,32,0,7	//txoctetpath3_sel=0x3; 	Address(0x49[7:4])
SPIWrite 004a,57,0,7	//txoctetpath4_sel=0x7; 	Address(0x4a[7:0])
SPIWrite 004a,57,0,7	//txoctetpath5_sel=0x5; 	Address(0x4a[7:4])
SPIWrite 004b,76,0,7	//txoctetpath6_sel=0x6; 	Address(0x4b[7:0])
SPIWrite 004b,46,0,7	//txoctetpath7_sel=0x4; 	Address(0x4b[7:4])
SPIWrite 004c,10,0,7	//txoctetpath0_clk_sel=0x0; 	Address(0x4c[7:0])
SPIWrite 004c,10,0,7	//txoctetpath1_clk_sel=0x1; 	Address(0x4c[7:4])
SPIWrite 004d,32,0,7	//txoctetpath2_clk_sel=0x2; 	Address(0x4d[7:0])
SPIWrite 004d,32,0,7	//txoctetpath3_clk_sel=0x3; 	Address(0x4d[7:4])
SPIWrite 004e,57,0,7	//txoctetpath4_clk_sel=0x7; 	Address(0x4e[7:0])
SPIWrite 004e,57,0,7	//txoctetpath5_clk_sel=0x5; 	Address(0x4e[7:4])
SPIWrite 004f,76,0,7	//txoctetpath6_clk_sel=0x6; 	Address(0x4f[7:0])
SPIWrite 004f,46,0,7	//txoctetpath7_clk_sel=0x4; 	Address(0x4f[7:4])

//END: Configuring JESD TX Lane Mux


//START: Configuring JESD RX Lane Mux

SPIWrite 0068,14,0,7	//rxoctetpath0_sel=0x4; 	Address(0x68[7:0])
SPIWrite 0068,14,0,7	//rxoctetpath1_sel=0x1; 	Address(0x68[7:4])
SPIWrite 0069,32,0,7	//rxoctetpath2_sel=0x2; 	Address(0x69[7:0])
SPIWrite 0069,32,0,7	//rxoctetpath3_sel=0x3; 	Address(0x69[7:4])
SPIWrite 006a,55,0,7	//rxoctetpath4_sel=0x5; 	Address(0x6a[7:0])
SPIWrite 006a,05,0,7	//rxoctetpath5_sel=0x0; 	Address(0x6a[7:4])
SPIWrite 006b,76,0,7	//rxoctetpath6_sel=0x6; 	Address(0x6b[7:0])
SPIWrite 006b,76,0,7	//rxoctetpath7_sel=0x7; 	Address(0x6b[7:4])
SPIWrite 006c,15,0,7	//rxoctetpath0_clk_sel=0x5; 	Address(0x6c[7:0])
SPIWrite 006c,15,0,7	//rxoctetpath1_clk_sel=0x1; 	Address(0x6c[7:4])
SPIWrite 006d,32,0,7	//rxoctetpath2_clk_sel=0x2; 	Address(0x6d[7:0])
SPIWrite 006d,32,0,7	//rxoctetpath3_clk_sel=0x3; 	Address(0x6d[7:4])
SPIWrite 006e,50,0,7	//rxoctetpath4_clk_sel=0x0; 	Address(0x6e[7:0])
SPIWrite 006e,40,0,7	//rxoctetpath5_clk_sel=0x4; 	Address(0x6e[7:4])
SPIWrite 006f,76,0,7	//rxoctetpath6_clk_sel=0x6; 	Address(0x6f[7:0])
SPIWrite 006f,76,0,7	//rxoctetpath7_clk_sel=0x7; 	Address(0x6f[7:4])

//END: Configuring JESD RX Lane Mux


//START: Configuring the DDC-JESD Data Muxes

SPIWrite 0034,00,0,7	//mux_sel_rxa_b1_i_for_2r1f_ab=0x0; 	Address(0x34[7:0])
SPIWrite 0034,00,0,7	//mux_sel_rxa_b1_q_for_2r1f_ab=0x0; 	Address(0x34[7:4])
SPIWrite 0035,22,0,7	//mux_sel_rxa_b2_i_for_2r1f_ab=0x2; 	Address(0x35[7:0])
SPIWrite 0035,22,0,7	//mux_sel_rxa_b2_q_for_2r1f_ab=0x2; 	Address(0x35[7:4])
SPIWrite 0036,44,0,7	//mux_sel_rxb_b1_i_for_2r1f_ab=0x4; 	Address(0x36[7:0])
SPIWrite 0036,44,0,7	//mux_sel_rxb_b1_q_for_2r1f_ab=0x4; 	Address(0x36[7:4])
SPIWrite 0037,66,0,7	//mux_sel_rxb_b2_i_for_2r1f_ab=0x6; 	Address(0x37[7:0])
SPIWrite 0037,66,0,7	//mux_sel_rxb_b2_q_for_2r1f_ab=0x6; 	Address(0x37[7:4])
SPIWrite 0038,40,0,7	//mux_sel_rxc_b1_i_for_2r1f_ab=0x0; 	Address(0x38[7:0])
SPIWrite 0038,00,0,7	//mux_sel_rxc_b1_q_for_2r1f_ab=0x0; 	Address(0x38[7:4])
SPIWrite 0039,52,0,7	//mux_sel_rxc_b2_i_for_2r1f_ab=0x2; 	Address(0x39[7:0])
SPIWrite 0039,22,0,7	//mux_sel_rxc_b2_q_for_2r1f_ab=0x2; 	Address(0x39[7:4])
SPIWrite 003a,64,0,7	//mux_sel_rxd_b1_i_for_2r1f_ab=0x4; 	Address(0x3a[7:0])
SPIWrite 003a,44,0,7	//mux_sel_rxd_b1_q_for_2r1f_ab=0x4; 	Address(0x3a[7:4])
SPIWrite 003b,76,0,7	//mux_sel_rxd_b2_i_for_2r1f_ab=0x6; 	Address(0x3b[7:0])
SPIWrite 003b,66,0,7	//mux_sel_rxd_b2_q_for_2r1f_ab=0x6; 	Address(0x3b[7:4])
SPIWrite 0040,00,0,7	//mux_sel_rxc_b1_i_for_2r1f_cd=0x0; 	Address(0x40[7:0])
SPIWrite 0040,00,0,7	//mux_sel_rxc_b1_q_for_2r1f_cd=0x0; 	Address(0x40[7:4])
SPIWrite 0041,22,0,7	//mux_sel_rxc_b2_i_for_2r1f_cd=0x2; 	Address(0x41[7:0])
SPIWrite 0041,22,0,7	//mux_sel_rxc_b2_q_for_2r1f_cd=0x2; 	Address(0x41[7:4])
SPIWrite 0042,24,0,7	//mux_sel_rxd_b1_i_for_2r1f_cd=0x4; 	Address(0x42[7:0])
SPIWrite 0042,44,0,7	//mux_sel_rxd_b1_q_for_2r1f_cd=0x4; 	Address(0x42[7:4])
SPIWrite 0043,36,0,7	//mux_sel_rxd_b2_i_for_2r1f_cd=0x6; 	Address(0x43[7:0])
SPIWrite 0043,66,0,7	//mux_sel_rxd_b2_q_for_2r1f_cd=0x6; 	Address(0x43[7:4])
SPIWrite 0044,50,0,7	//mux_sel_fba_i0_for_2r1f_ab=0x0; 	Address(0x44[7:0])
SPIWrite 0044,50,0,7	//mux_sel_fba_q0_for_2r1f_ab=0x0; 	Address(0x44[7:2])
SPIWrite 0044,50,0,7	//mux_sel_fba_i1_for_2r1f_ab=0x1; 	Address(0x44[7:4])
SPIWrite 0044,50,0,7	//mux_sel_fba_q1_for_2r1f_ab=0x1; 	Address(0x44[7:6])
SPIWrite 0045,fa,0,7	//mux_sel_fbc_i0_for_2r1f_ab=0x2; 	Address(0x45[7:0])
SPIWrite 0045,fa,0,7	//mux_sel_fbc_q0_for_2r1f_ab=0x2; 	Address(0x45[7:2])
SPIWrite 0045,fa,0,7	//mux_sel_fbc_i1_for_2r1f_ab=0x3; 	Address(0x45[7:4])
SPIWrite 0045,fa,0,7	//mux_sel_fbc_q1_for_2r1f_ab=0x3; 	Address(0x45[7:6])
SPIWrite 0046,fa,0,7	//mux_sel_fba_i0_for_2r1f_cd=0x2; 	Address(0x46[7:0])
SPIWrite 0046,fa,0,7	//mux_sel_fba_q0_for_2r1f_cd=0x2; 	Address(0x46[7:2])
SPIWrite 0046,fa,0,7	//mux_sel_fba_i1_for_2r1f_cd=0x3; 	Address(0x46[7:4])
SPIWrite 0046,fa,0,7	//mux_sel_fba_q1_for_2r1f_cd=0x3; 	Address(0x46[7:6])
SPIWrite 0047,50,0,7	//mux_sel_fbc_i0_for_2r1f_cd=0x0; 	Address(0x47[7:0])
SPIWrite 0047,50,0,7	//mux_sel_fbc_q0_for_2r1f_cd=0x0; 	Address(0x47[7:2])
SPIWrite 0047,50,0,7	//mux_sel_fbc_i1_for_2r1f_cd=0x1; 	Address(0x47[7:4])
SPIWrite 0047,50,0,7	//mux_sel_fbc_q1_for_2r1f_cd=0x1; 	Address(0x47[7:6])

//END: Configuring the DDC-JESD Data Muxes


//START: Configuring the JESD-DUC Data Muxes

SPIWrite 00cc,00,0,7	//mux_sel_for_txa_b0_i=0x0; 	Address(0xcc[7:0])
SPIWrite 00cc,00,0,7	//mux_sel_for_txa_b0_q=0x0; 	Address(0xcc[7:4])
SPIWrite 00cd,11,0,7	//mux_sel_for_txa_b1_i=0x1; 	Address(0xcd[7:0])
SPIWrite 00cd,11,0,7	//mux_sel_for_txa_b1_q=0x1; 	Address(0xcd[7:4])
SPIWrite 00ce,22,0,7	//mux_sel_for_txb_b0_i=0x2; 	Address(0xce[7:0])
SPIWrite 00ce,22,0,7	//mux_sel_for_txb_b0_q=0x2; 	Address(0xce[7:4])
SPIWrite 00cf,33,0,7	//mux_sel_for_txb_b1_i=0x3; 	Address(0xcf[7:0])
SPIWrite 00cf,33,0,7	//mux_sel_for_txb_b1_q=0x3; 	Address(0xcf[7:4])
SPIWrite 00d0,48,0,7	//mux_sel_for_txc_b0_i=0x8; 	Address(0xd0[7:0])
SPIWrite 00d0,88,0,7	//mux_sel_for_txc_b0_q=0x8; 	Address(0xd0[7:4])
SPIWrite 00d1,59,0,7	//mux_sel_for_txc_b1_i=0x9; 	Address(0xd1[7:0])
SPIWrite 00d1,99,0,7	//mux_sel_for_txc_b1_q=0x9; 	Address(0xd1[7:4])
SPIWrite 00d2,6a,0,7	//mux_sel_for_txd_b0_i=0xa; 	Address(0xd2[7:0])
SPIWrite 00d2,aa,0,7	//mux_sel_for_txd_b0_q=0xa; 	Address(0xd2[7:4])
SPIWrite 00d3,7b,0,7	//mux_sel_for_txd_b1_i=0xb; 	Address(0xd3[7:0])
SPIWrite 00d3,bb,0,7	//mux_sel_for_txd_b1_q=0xb; 	Address(0xd3[7:4])
SPIWrite 0060,10,0,7	//mux_sel_for_txa_ctrl=0x0; 	Address(0x60[7:0])
SPIWrite 0060,10,0,7	//mux_sel_for_txb_ctrl=0x1; 	Address(0x60[7:4])
SPIWrite 0061,34,0,7	//mux_sel_for_txc_ctrl=0x4; 	Address(0x61[7:0])
SPIWrite 0061,54,0,7	//mux_sel_for_txd_ctrl=0x5; 	Address(0x61[7:4])
SPIWrite 00bc,e4,0,7	//tdd_tx_on_a_2t_ab_mux_sel=0x0; 	Address(0xbc[7:0])
SPIWrite 00bc,e4,0,7	//tdd_tx_on_b_2t_ab_mux_sel=0x1; 	Address(0xbc[7:2])
SPIWrite 00bc,e4,0,7	//tdd_tx_on_c_2t_ab_mux_sel=0x2; 	Address(0xbc[7:4])
SPIWrite 00bc,e4,0,7	//tdd_tx_on_d_2t_ab_mux_sel=0x3; 	Address(0xbc[7:6])
SPIWrite 00be,4e,0,7	//tdd_tx_on_a_2t_cd_mux_sel=0x2; 	Address(0xbe[7:0])
SPIWrite 00be,4e,0,7	//tdd_tx_on_b_2t_cd_mux_sel=0x3; 	Address(0xbe[7:2])
SPIWrite 00be,6e,0,7	//tdd_tx_on_c_2t_cd_mux_sel=0x2; 	Address(0xbe[7:4])
SPIWrite 00be,ee,0,7	//tdd_tx_on_d_2t_cd_mux_sel=0x3; 	Address(0xbe[7:6])

//END: Configuring the JESD-DUC Data Muxes


//START: Configuring JESD TX Sync Mux

SPIWrite 0054,00,0,7	//adc_jesd_sync_n0_mux_sel=0x0; 	Address(0x54[7:0])
SPIWrite 0054,00,0,7	//adc_jesd_sync_n1_mux_sel=0x0; 	Address(0x54[7:4])
SPIWrite 0055,30,0,7	//adc_jesd_sync_n2_mux_sel=0x0; 	Address(0x55[7:0])
SPIWrite 0055,00,0,7	//adc_jesd_sync_n3_mux_sel=0x0; 	Address(0x55[7:4])
SPIWrite 0056,50,0,7	//adc_jesd_sync_n4_mux_sel=0x0; 	Address(0x56[7:0])
SPIWrite 0056,00,0,7	//adc_jesd_sync_n5_mux_sel=0x0; 	Address(0x56[7:4])

//END: Configuring JESD TX Sync Mux


//START: Configuring JESD RX Sync Mux

SPIWrite 00ca,e4,0,7	//dac_jesd_sync_n0_mux_sel=0x0; 	Address(0xca[7:0])
SPIWrite 00ca,e0,0,7	//dac_jesd_sync_n1_mux_sel=0x0; 	Address(0xca[7:2])
SPIWrite 00ca,c0,0,7	//dac_jesd_sync_n2_mux_sel=0x0; 	Address(0xca[7:4])
SPIWrite 00ca,00,0,7	//dac_jesd_sync_n3_mux_sel=0x0; 	Address(0xca[7:6])

//END: Configuring JESD RX Sync Mux

SPIWrite 009c,03,0,7	//rx_clk_dithered_mode_en=0x1; 	Address(0x9c[7:1])
SPIWrite 009e,03,0,7	//fb_clk_dithered_mode_en=0x1; 	Address(0x9e[7:1])
SPIWrite 009c,03,0,7	//rx_clk_disable=0x1; 	Address(0x9c[7:0])
SPIWrite 00a0,02,0,7	//tx_clk_disable=0x0; 	Address(0xa0[7:0])
SPIWrite 00a0,02,0,7	//tx_clk_dithered_mode_en=0x1; 	Address(0xa0[7:1])

//END: Configuring JESD Muxes and Pointers


//START: Setting JESD SyncB Pin Mode

SPIWrite 0016,00,0,7	//jesd_subchip=0x0; 	Address(0x16[7:4])
SPIWrite 0015,04,0,7	//rx=0x1; 	Address(0x15[7:2])
SPIWrite 0067,18,0,7	//Property_44h_31_0=0x18000000; 	Address(0x64[7:0],0x65[7:0],0x66[7:0],0x67[7:0],0x68[7:0])
SPIWrite 0066,00,0,7
SPIWrite 0065,00,0,7
SPIWrite 0064,00,0,7
SPIWrite 0015,08,0,7	//rx=0x2; 	Address(0x15[7:2])
SPIWrite 0067,18,0,7	//Property_44h_31_0=0x18000000; 	Address(0x64[7:0],0x65[7:0],0x66[7:0],0x67[7:0],0x68[7:0])
SPIWrite 0066,00,0,7
SPIWrite 0065,00,0,7
SPIWrite 0064,00,0,7

//END: Setting JESD SyncB Pin Mode

SPIWrite 0015,00,0,7	//rx=0x0; 	Address(0x15[7:2])

//STEP: jesdConfig/step1 

//START: Configuring ADC JESD TX

SPIWrite 0016,01,0,7	//adc_jesd=0x1; 	Address(0x16[7:0])
SPIWrite 006d,07,0,7	//link0_init_state=0x1; 	Address(0x6d[7:0])
SPIWrite 006d,07,0,7	//link1_init_state=0x1; 	Address(0x6d[7:1])
SPIWrite 006d,07,0,7	//link2_init_state=0x1; 	Address(0x6d[7:2])
SPIWrite 006f,02,0,7	//init_state_gearbox_spi_ovr=0x1; 	Address(0x6f[7:1])
SPIWrite 006c,0f,0,7	//lane0_gearbox_init_state=0x1; 	Address(0x6c[7:0])
SPIWrite 006c,0f,0,7	//lane1_gearbox_init_state=0x1; 	Address(0x6c[7:1])
SPIWrite 006c,0f,0,7	//lane2_gearbox_init_state=0x1; 	Address(0x6c[7:2])
SPIWrite 006c,0f,0,7	//lane3_gearbox_init_state=0x1; 	Address(0x6c[7:3])
SPIWrite 006c,0e,0,7	//lane0_gearbox_init_state=0x0; 	Address(0x6c[7:0])
SPIWrite 006c,0c,0,7	//lane1_gearbox_init_state=0x0; 	Address(0x6c[7:1])
SPIWrite 006c,08,0,7	//lane2_gearbox_init_state=0x0; 	Address(0x6c[7:2])
SPIWrite 006c,00,0,7	//lane3_gearbox_init_state=0x0; 	Address(0x6c[7:3])
SPIWrite 006e,0f,0,7	//lane0_serdes_fifo_init_state=0x1; 	Address(0x6e[7:0])
SPIWrite 006e,0f,0,7	//lane1_serdes_fifo_init_state=0x1; 	Address(0x6e[7:1])
SPIWrite 006e,0f,0,7	//lane2_serdes_fifo_init_state=0x1; 	Address(0x6e[7:2])
SPIWrite 006e,0f,0,7	//lane3_serdes_fifo_init_state=0x1; 	Address(0x6e[7:3])
SPIWrite 005c,1f,0,7	//rx_root_clk_dither_en=0x1; 	Address(0x5c[7:0])
SPIWrite 005c,1f,0,7	//fb_root_clk_dither_en=0x1; 	Address(0x5c[7:1])
SPIWrite 005c,1b,0,7	//ddc_rd_clk_dither_en=0x0; 	Address(0x5c[7:2])
SPIWrite 005c,13,0,7	//jesd_clk_dither_en=0x0; 	Address(0x5c[7:3])
SPIWrite 005c,03,0,7	//jesd_clk_div2_dither_en=0x0; 	Address(0x5c[7:4])
SPIWrite 0021,03,0,7	//jesd_system_mode=0x3; 	Address(0x21[7:0])
SPIWrite 005d,01,0,7	//rx_adc_clk_sysref_mux=0x1; 	Address(0x5d[7:0])
SPIWrite 005d,01,0,7	//fb_adc_clk_sysref_mux=0x0; 	Address(0x5d[7:1])
SPIWrite 0024,0f,0,7	//jesd_clear_data=0xf; 	Address(0x24[7:0])
SPIWrite 0069,8c,0,7	//serdes_fifo_read_dly_lane0=0xc; 	Address(0x69[7:0])
SPIWrite 0069,cc,0,7	//serdes_fifo_read_dly_lane1=0xc; 	Address(0x69[7:4])
SPIWrite 006a,8c,0,7	//serdes_fifo_read_dly_lane2=0xc; 	Address(0x6a[7:0])
SPIWrite 006a,cc,0,7	//serdes_fifo_read_dly_lane3=0xc; 	Address(0x6a[7:4])
SPIWrite 0040,02,0,7	//rx1_root_clk_div_m=0x2; 	Address(0x40[7:0])
SPIWrite 0041,04,0,7	//rx1_root_clk_div_n_m1=0x4; 	Address(0x41[7:0])
SPIWrite 0046,01,0,7	//ddc_rd_clk_rx1_div_m=0x1; 	Address(0x46[7:0])
SPIWrite 0047,01,0,7	//ddc_rd_clk_rx1_div_n_m1=0x1; 	Address(0x47[7:0])
SPIWrite 004c,01,0,7	//jesd_clk_rx1_div_m=0x1; 	Address(0x4c[7:0])
SPIWrite 004d,00,0,7	//jesd_clk_rx1_div_n_m1=0x0; 	Address(0x4d[7:0])
SPIWrite 0034,01,0,7	//rx1_jesd_mode=0x1; 	Address(0x34[7:0])
SPIWrite 0084,03,0,7	//link0_k_m1=0x3; 	Address(0x84[7:0],0x85[7:0])
SPIWrite 0079,03,0,7	//link0_ila_k_m1=0x3; 	Address(0x79[7:0],0x7a[7:0])
SPIWrite 0042,02,0,7	//rx2_root_clk_div_m=0x2; 	Address(0x42[7:0])
SPIWrite 0043,04,0,7	//rx2_root_clk_div_n_m1=0x4; 	Address(0x43[7:0])
SPIWrite 0048,01,0,7	//ddc_rd_clk_rx2_div_m=0x1; 	Address(0x48[7:0])
SPIWrite 0049,01,0,7	//ddc_rd_clk_rx2_div_n_m1=0x1; 	Address(0x49[7:0])
SPIWrite 004e,01,0,7	//jesd_clk_rx2_div_m=0x1; 	Address(0x4e[7:0])
SPIWrite 004f,00,0,7	//jesd_clk_rx2_div_n_m1=0x0; 	Address(0x4f[7:0])
SPIWrite 0035,01,0,7	//rx2_jesd_mode=0x1; 	Address(0x35[7:0])
SPIWrite 009c,03,0,7	//link1_k_m1=0x3; 	Address(0x9c[7:0],0x9d[7:0])
SPIWrite 0091,03,0,7	//link1_ila_k_m1=0x3; 	Address(0x91[7:0],0x92[7:0])
SPIWrite 0044,02,0,7	//fb_root_clk_div_m=0x2; 	Address(0x44[7:0])
SPIWrite 0045,04,0,7	//fb_root_clk_div_n_m1=0x4; 	Address(0x45[7:0])
SPIWrite 004a,01,0,7	//ddc_rd_clk_fb_div_m=0x1; 	Address(0x4a[7:0])
SPIWrite 004b,01,0,7	//ddc_rd_clk_fb_div_n_m1=0x1; 	Address(0x4b[7:0])
SPIWrite 0050,01,0,7	//jesd_clk_fb_div_m=0x1; 	Address(0x50[7:0])
SPIWrite 0051,00,0,7	//jesd_clk_fb_div_n_m1=0x0; 	Address(0x51[7:0])
SPIWrite 0036,18,0,7	//fb_jesd_mode=0x18; 	Address(0x36[7:0])
SPIWrite 00b4,03,0,7	//link2_k_m1=0x3; 	Address(0xb4[7:0],0xb5[7:0])
SPIWrite 00a9,03,0,7	//link2_ila_k_m1=0x3; 	Address(0xa9[7:0],0xaa[7:0])
SPIWrite 0020,00,0,7	//jesd_std_sel=0x0; 	Address(0x20[7:0])
SPIWrite 0077,81,0,7	//link0_scr=0x1; 	Address(0x77[7:7])
SPIWrite 008f,81,0,7	//link1_scr=0x1; 	Address(0x8f[7:7])
SPIWrite 00a7,81,0,7	//link2_scr=0x1; 	Address(0xa7[7:7])
SPIWrite 0023,01,0,7	//lane_ena=0x1; 	Address(0x23[7:0])
SPIWrite 003c,02,0,7	//sel_rx1_jesd_mode_1s_2s_ovr=0x1; 	Address(0x3c[7:1])
SPIWrite 003c,02,0,7	//sel_rx1_jesd_mode_1s_2s_val=0x0; 	Address(0x3c[7:0])
SPIWrite 003c,0a,0,7	//sel_rx2_jesd_mode_1s_2s_ovr=0x1; 	Address(0x3c[7:3])
SPIWrite 003c,0a,0,7	//sel_rx2_jesd_mode_1s_2s_val=0x0; 	Address(0x3c[7:2])
SPIWrite 003c,2a,0,7	//sel_fb_jesd_mode_1s_2s_ovr=0x1; 	Address(0x3c[7:5])
SPIWrite 003c,3a,0,7	//sel_fb_jesd_mode_1s_2s_val=0x1; 	Address(0x3c[7:4])
SPIWrite 0083,01,0,7	//link0_jesd_ila_config_override=0x1; 	Address(0x83[7:0])
SPIWrite 009b,01,0,7	//link1_jesd_ila_config_override=0x1; 	Address(0x9b[7:0])
SPIWrite 00b2,80,0,7	//link2_jesd_ila_config_override=0x1; 	Address(0xb2[7:7])
SPIWrite 0078,07,0,7	//link0_ila_f_m1=0x7; 	Address(0x78[7:0],0x79[7:0])
SPIWrite 0090,07,0,7	//link1_ila_f_m1=0x7; 	Address(0x90[7:0],0x91[7:0])
SPIWrite 00a8,07,0,7	//link2_ila_f_m1=0x7; 	Address(0xa8[7:0],0xa9[7:0])
SPIWrite 007a,07,0,7	//link0_ila_m_m1=0x7; 	Address(0x7a[7:0],0x7b[7:0])
SPIWrite 0092,07,0,7	//link1_ila_m_m1=0x7; 	Address(0x92[7:0],0x93[7:0])
SPIWrite 00aa,07,0,7	//link2_ila_m_m1=0x7; 	Address(0xaa[7:0],0xab[7:0])
SPIWrite 0077,83,0,7	//link0_ila_l_m1=0x3; 	Address(0x77[7:0])
SPIWrite 008f,83,0,7	//link1_ila_l_m1=0x3; 	Address(0x8f[7:0])
SPIWrite 00a7,83,0,7	//link2_ila_l_m1=0x3; 	Address(0xa7[7:0])
SPIWrite 007b,0f,0,7	//link0_ila_n_m1=0xf; 	Address(0x7b[7:0])
SPIWrite 0093,0f,0,7	//link1_ila_n_m1=0xf; 	Address(0x93[7:0])
SPIWrite 00ab,0f,0,7	//link2_ila_n_m1=0xf; 	Address(0xab[7:0])
SPIWrite 00bc,00,0,7	//lid0=0x0; 	Address(0xbc[7:0])
SPIWrite 00bd,01,0,7	//lid1=0x1; 	Address(0xbd[7:0])
SPIWrite 00be,02,0,7	//lid2=0x2; 	Address(0xbe[7:0])
SPIWrite 00bf,03,0,7	//lid3=0x3; 	Address(0xbf[7:0])
SPIWrite 00e4,42,0,7	//msf_rx1_offset_default_mode0=0x2; 	Address(0xe4[7:0])
SPIWrite 00e4,22,0,7	//msf_rx1_offset_default_mode1=0x2; 	Address(0xe4[7:4])
SPIWrite 00e5,83,0,7	//msf_rx1_offset_default_mode2=0x3; 	Address(0xe5[7:0])
SPIWrite 00e5,43,0,7	//msf_rx1_offset_default_mode3=0x4; 	Address(0xe5[7:4])
SPIWrite 00e6,42,0,7	//msf_rx2_offset_default_mode0=0x2; 	Address(0xe6[7:0])
SPIWrite 00e6,22,0,7	//msf_rx2_offset_default_mode1=0x2; 	Address(0xe6[7:4])
SPIWrite 00e7,83,0,7	//msf_rx2_offset_default_mode2=0x3; 	Address(0xe7[7:0])
SPIWrite 00e7,43,0,7	//msf_rx2_offset_default_mode3=0x4; 	Address(0xe7[7:4])
SPIWrite 00e8,42,0,7	//msf_fb_offset_default_mode0=0x2; 	Address(0xe8[7:0])
SPIWrite 00e8,22,0,7	//msf_fb_offset_default_mode1=0x2; 	Address(0xe8[7:4])
SPIWrite 00e9,83,0,7	//msf_fb_offset_default_mode2=0x3; 	Address(0xe9[7:0])
SPIWrite 00e9,43,0,7	//msf_fb_offset_default_mode3=0x4; 	Address(0xe9[7:4])
SPIWrite 0037,06,0,7	//rx1_ctrlmode_12b_trunc_en=0x0; 	Address(0x37[7:0])
SPIWrite 0037,04,0,7	//rx2_ctrlmode_12b_trunc_en=0x0; 	Address(0x37[7:1])
SPIWrite 0037,00,0,7	//fb_ctrlmode_12b_trunc_en=0x0; 	Address(0x37[7:2])

//END: Done Configuring ADC JESD TX


//START: Configuring ADC JESD TX

SPIWrite 0016,02,0,7	//adc_jesd=0x2; 	Address(0x16[7:0])
SPIWrite 006d,07,0,7	//link0_init_state=0x1; 	Address(0x6d[7:0])
SPIWrite 006d,07,0,7	//link1_init_state=0x1; 	Address(0x6d[7:1])
SPIWrite 006d,07,0,7	//link2_init_state=0x1; 	Address(0x6d[7:2])
SPIWrite 006f,02,0,7	//init_state_gearbox_spi_ovr=0x1; 	Address(0x6f[7:1])
SPIWrite 006c,0f,0,7	//lane0_gearbox_init_state=0x1; 	Address(0x6c[7:0])
SPIWrite 006c,0f,0,7	//lane1_gearbox_init_state=0x1; 	Address(0x6c[7:1])
SPIWrite 006c,0f,0,7	//lane2_gearbox_init_state=0x1; 	Address(0x6c[7:2])
SPIWrite 006c,0f,0,7	//lane3_gearbox_init_state=0x1; 	Address(0x6c[7:3])
SPIWrite 006c,0e,0,7	//lane0_gearbox_init_state=0x0; 	Address(0x6c[7:0])
SPIWrite 006c,0c,0,7	//lane1_gearbox_init_state=0x0; 	Address(0x6c[7:1])
SPIWrite 006c,08,0,7	//lane2_gearbox_init_state=0x0; 	Address(0x6c[7:2])
SPIWrite 006c,00,0,7	//lane3_gearbox_init_state=0x0; 	Address(0x6c[7:3])
SPIWrite 006e,0f,0,7	//lane0_serdes_fifo_init_state=0x1; 	Address(0x6e[7:0])
SPIWrite 006e,0f,0,7	//lane1_serdes_fifo_init_state=0x1; 	Address(0x6e[7:1])
SPIWrite 006e,0f,0,7	//lane2_serdes_fifo_init_state=0x1; 	Address(0x6e[7:2])
SPIWrite 006e,0f,0,7	//lane3_serdes_fifo_init_state=0x1; 	Address(0x6e[7:3])
SPIWrite 005c,1f,0,7	//rx_root_clk_dither_en=0x1; 	Address(0x5c[7:0])
SPIWrite 005c,1f,0,7	//fb_root_clk_dither_en=0x1; 	Address(0x5c[7:1])
SPIWrite 005c,1b,0,7	//ddc_rd_clk_dither_en=0x0; 	Address(0x5c[7:2])
SPIWrite 005c,13,0,7	//jesd_clk_dither_en=0x0; 	Address(0x5c[7:3])
SPIWrite 005c,03,0,7	//jesd_clk_div2_dither_en=0x0; 	Address(0x5c[7:4])
SPIWrite 0021,03,0,7	//jesd_system_mode=0x3; 	Address(0x21[7:0])
SPIWrite 005d,01,0,7	//rx_adc_clk_sysref_mux=0x1; 	Address(0x5d[7:0])
SPIWrite 005d,01,0,7	//fb_adc_clk_sysref_mux=0x0; 	Address(0x5d[7:1])
SPIWrite 0024,0f,0,7	//jesd_clear_data=0xf; 	Address(0x24[7:0])
SPIWrite 0069,8c,0,7	//serdes_fifo_read_dly_lane0=0xc; 	Address(0x69[7:0])
SPIWrite 0069,cc,0,7	//serdes_fifo_read_dly_lane1=0xc; 	Address(0x69[7:4])
SPIWrite 006a,8c,0,7	//serdes_fifo_read_dly_lane2=0xc; 	Address(0x6a[7:0])
SPIWrite 006a,cc,0,7	//serdes_fifo_read_dly_lane3=0xc; 	Address(0x6a[7:4])
SPIWrite 0040,02,0,7	//rx1_root_clk_div_m=0x2; 	Address(0x40[7:0])
SPIWrite 0041,04,0,7	//rx1_root_clk_div_n_m1=0x4; 	Address(0x41[7:0])
SPIWrite 0046,01,0,7	//ddc_rd_clk_rx1_div_m=0x1; 	Address(0x46[7:0])
SPIWrite 0047,01,0,7	//ddc_rd_clk_rx1_div_n_m1=0x1; 	Address(0x47[7:0])
SPIWrite 004c,01,0,7	//jesd_clk_rx1_div_m=0x1; 	Address(0x4c[7:0])
SPIWrite 004d,00,0,7	//jesd_clk_rx1_div_n_m1=0x0; 	Address(0x4d[7:0])
SPIWrite 0034,01,0,7	//rx1_jesd_mode=0x1; 	Address(0x34[7:0])
SPIWrite 0084,03,0,7	//link0_k_m1=0x3; 	Address(0x84[7:0],0x85[7:0])
SPIWrite 0079,03,0,7	//link0_ila_k_m1=0x3; 	Address(0x79[7:0],0x7a[7:0])
SPIWrite 0042,02,0,7	//rx2_root_clk_div_m=0x2; 	Address(0x42[7:0])
SPIWrite 0043,04,0,7	//rx2_root_clk_div_n_m1=0x4; 	Address(0x43[7:0])
SPIWrite 0048,01,0,7	//ddc_rd_clk_rx2_div_m=0x1; 	Address(0x48[7:0])
SPIWrite 0049,01,0,7	//ddc_rd_clk_rx2_div_n_m1=0x1; 	Address(0x49[7:0])
SPIWrite 004e,01,0,7	//jesd_clk_rx2_div_m=0x1; 	Address(0x4e[7:0])
SPIWrite 004f,00,0,7	//jesd_clk_rx2_div_n_m1=0x0; 	Address(0x4f[7:0])
SPIWrite 0035,01,0,7	//rx2_jesd_mode=0x1; 	Address(0x35[7:0])
SPIWrite 009c,03,0,7	//link1_k_m1=0x3; 	Address(0x9c[7:0],0x9d[7:0])
SPIWrite 0091,03,0,7	//link1_ila_k_m1=0x3; 	Address(0x91[7:0],0x92[7:0])
SPIWrite 0044,02,0,7	//fb_root_clk_div_m=0x2; 	Address(0x44[7:0])
SPIWrite 0045,04,0,7	//fb_root_clk_div_n_m1=0x4; 	Address(0x45[7:0])
SPIWrite 004a,01,0,7	//ddc_rd_clk_fb_div_m=0x1; 	Address(0x4a[7:0])
SPIWrite 004b,01,0,7	//ddc_rd_clk_fb_div_n_m1=0x1; 	Address(0x4b[7:0])
SPIWrite 0050,01,0,7	//jesd_clk_fb_div_m=0x1; 	Address(0x50[7:0])
SPIWrite 0051,00,0,7	//jesd_clk_fb_div_n_m1=0x0; 	Address(0x51[7:0])
SPIWrite 0036,18,0,7	//fb_jesd_mode=0x18; 	Address(0x36[7:0])
SPIWrite 00b4,03,0,7	//link2_k_m1=0x3; 	Address(0xb4[7:0],0xb5[7:0])
SPIWrite 00a9,03,0,7	//link2_ila_k_m1=0x3; 	Address(0xa9[7:0],0xaa[7:0])
SPIWrite 0020,00,0,7	//jesd_std_sel=0x0; 	Address(0x20[7:0])
SPIWrite 0077,81,0,7	//link0_scr=0x1; 	Address(0x77[7:7])
SPIWrite 008f,81,0,7	//link1_scr=0x1; 	Address(0x8f[7:7])
SPIWrite 00a7,81,0,7	//link2_scr=0x1; 	Address(0xa7[7:7])
SPIWrite 0023,01,0,7	//lane_ena=0x1; 	Address(0x23[7:0])
SPIWrite 003c,02,0,7	//sel_rx1_jesd_mode_1s_2s_ovr=0x1; 	Address(0x3c[7:1])
SPIWrite 003c,02,0,7	//sel_rx1_jesd_mode_1s_2s_val=0x0; 	Address(0x3c[7:0])
SPIWrite 003c,0a,0,7	//sel_rx2_jesd_mode_1s_2s_ovr=0x1; 	Address(0x3c[7:3])
SPIWrite 003c,0a,0,7	//sel_rx2_jesd_mode_1s_2s_val=0x0; 	Address(0x3c[7:2])
SPIWrite 003c,2a,0,7	//sel_fb_jesd_mode_1s_2s_ovr=0x1; 	Address(0x3c[7:5])
SPIWrite 003c,3a,0,7	//sel_fb_jesd_mode_1s_2s_val=0x1; 	Address(0x3c[7:4])
SPIWrite 0083,01,0,7	//link0_jesd_ila_config_override=0x1; 	Address(0x83[7:0])
SPIWrite 009b,01,0,7	//link1_jesd_ila_config_override=0x1; 	Address(0x9b[7:0])
SPIWrite 00b2,80,0,7	//link2_jesd_ila_config_override=0x1; 	Address(0xb2[7:7])
SPIWrite 0078,07,0,7	//link0_ila_f_m1=0x7; 	Address(0x78[7:0],0x79[7:0])
SPIWrite 0090,07,0,7	//link1_ila_f_m1=0x7; 	Address(0x90[7:0],0x91[7:0])
SPIWrite 00a8,07,0,7	//link2_ila_f_m1=0x7; 	Address(0xa8[7:0],0xa9[7:0])
SPIWrite 007a,07,0,7	//link0_ila_m_m1=0x7; 	Address(0x7a[7:0],0x7b[7:0])
SPIWrite 0092,07,0,7	//link1_ila_m_m1=0x7; 	Address(0x92[7:0],0x93[7:0])
SPIWrite 00aa,07,0,7	//link2_ila_m_m1=0x7; 	Address(0xaa[7:0],0xab[7:0])
SPIWrite 0077,83,0,7	//link0_ila_l_m1=0x3; 	Address(0x77[7:0])
SPIWrite 008f,83,0,7	//link1_ila_l_m1=0x3; 	Address(0x8f[7:0])
SPIWrite 00a7,83,0,7	//link2_ila_l_m1=0x3; 	Address(0xa7[7:0])
SPIWrite 007b,0f,0,7	//link0_ila_n_m1=0xf; 	Address(0x7b[7:0])
SPIWrite 0093,0f,0,7	//link1_ila_n_m1=0xf; 	Address(0x93[7:0])
SPIWrite 00ab,0f,0,7	//link2_ila_n_m1=0xf; 	Address(0xab[7:0])
SPIWrite 00bc,04,0,7	//lid0=0x4; 	Address(0xbc[7:0])
SPIWrite 00bd,05,0,7	//lid1=0x5; 	Address(0xbd[7:0])
SPIWrite 00be,06,0,7	//lid2=0x6; 	Address(0xbe[7:0])
SPIWrite 00bf,07,0,7	//lid3=0x7; 	Address(0xbf[7:0])
SPIWrite 00e4,42,0,7	//msf_rx1_offset_default_mode0=0x2; 	Address(0xe4[7:0])
SPIWrite 00e4,22,0,7	//msf_rx1_offset_default_mode1=0x2; 	Address(0xe4[7:4])
SPIWrite 00e5,83,0,7	//msf_rx1_offset_default_mode2=0x3; 	Address(0xe5[7:0])
SPIWrite 00e5,43,0,7	//msf_rx1_offset_default_mode3=0x4; 	Address(0xe5[7:4])
SPIWrite 00e6,42,0,7	//msf_rx2_offset_default_mode0=0x2; 	Address(0xe6[7:0])
SPIWrite 00e6,22,0,7	//msf_rx2_offset_default_mode1=0x2; 	Address(0xe6[7:4])
SPIWrite 00e7,83,0,7	//msf_rx2_offset_default_mode2=0x3; 	Address(0xe7[7:0])
SPIWrite 00e7,43,0,7	//msf_rx2_offset_default_mode3=0x4; 	Address(0xe7[7:4])
SPIWrite 00e8,42,0,7	//msf_fb_offset_default_mode0=0x2; 	Address(0xe8[7:0])
SPIWrite 00e8,22,0,7	//msf_fb_offset_default_mode1=0x2; 	Address(0xe8[7:4])
SPIWrite 00e9,83,0,7	//msf_fb_offset_default_mode2=0x3; 	Address(0xe9[7:0])
SPIWrite 00e9,43,0,7	//msf_fb_offset_default_mode3=0x4; 	Address(0xe9[7:4])
SPIWrite 0037,06,0,7	//rx1_ctrlmode_12b_trunc_en=0x0; 	Address(0x37[7:0])
SPIWrite 0037,04,0,7	//rx2_ctrlmode_12b_trunc_en=0x0; 	Address(0x37[7:1])
SPIWrite 0037,00,0,7	//fb_ctrlmode_12b_trunc_en=0x0; 	Address(0x37[7:2])

//END: Done Configuring ADC JESD TX

SPIWrite 0016,00,0,7	//adc_jesd=0x0; 	Address(0x16[7:0])

//STEP: jesdConfig/step2 

//START: Configuring DAC JESD RX

SPIWrite 0016,04,0,7	//dac_jesd=0x1; 	Address(0x16[7:2])
SPIWrite 006c,03,0,7	//link0_k_m1=0x3; 	Address(0x6c[7:0],0x6d[7:0])
SPIWrite 006d,03,0,7	//link1_k_m1=0x3; 	Address(0x6d[7:0],0x6e[7:0])
SPIWrite 0057,03,0,7	//link1_ila_k_m1=0x3; 	Address(0x57[7:0],0x58[7:0])
SPIWrite 0049,03,0,7	//link0_ila_k_m1=0x3; 	Address(0x49[7:0],0x4a[7:0])
SPIWrite 0069,00,0,7	//link0_rbd_m1=0x2; 	Address(0x68[7:0],0x69[7:0],0x6a[7:0])
SPIWrite 0068,02,0,7
SPIWrite 006b,00,0,7	//link1_rbd_m1=0x2; 	Address(0x6a[7:0],0x6b[7:0],0x6c[7:0])
SPIWrite 006a,02,0,7
SPIWrite 0024,5e,0,7	//gearbox_init_state_ovr=0x1; 	Address(0x24[7:6])
SPIWrite 0025,ff,0,7	//gearbox_init_state_lane0_val=0x1; 	Address(0x25[7:0])
SPIWrite 0025,ff,0,7	//gearbox_init_state_lane1_val=0x1; 	Address(0x25[7:1])
SPIWrite 0025,ff,0,7	//gearbox_init_state_lane2_val=0x1; 	Address(0x25[7:2])
SPIWrite 0025,ff,0,7	//gearbox_init_state_lane3_val=0x1; 	Address(0x25[7:3])
SPIWrite 0025,fe,0,7	//gearbox_init_state_lane0_val=0x0; 	Address(0x25[7:0])
SPIWrite 0025,fc,0,7	//gearbox_init_state_lane1_val=0x0; 	Address(0x25[7:1])
SPIWrite 0025,f8,0,7	//gearbox_init_state_lane2_val=0x0; 	Address(0x25[7:2])
SPIWrite 0025,f0,0,7	//gearbox_init_state_lane3_val=0x0; 	Address(0x25[7:3])
SPIWrite 0020,03,0,7	//link0_init_state=0x1; 	Address(0x20[7:0])
SPIWrite 0020,03,0,7	//link1_init_state=0x1; 	Address(0x20[7:1])
SPIWrite 0064,ff,0,7	//jesd_clear_data=0xf; 	Address(0x64[7:4])
SPIWrite 0040,04,0,7	//link0_comma_align_lock_reset_disable=0x1; 	Address(0x40[7:2])
SPIWrite 0040,0c,0,7	//link1_comma_align_lock_reset_disable=0x1; 	Address(0x40[7:3])
SPIWrite 00ac,04,0,7	//link0_emb_align_lock_reset_disable=0x1; 	Address(0xac[7:2])
SPIWrite 00ac,0c,0,7	//link1_emb_align_lock_reset_disable=0x1; 	Address(0xac[7:3])
SPIWrite 002c,02,0,7	//root_clk_tx1_div_m=0x2; 	Address(0x2c[7:0])
SPIWrite 002d,04,0,7	//root_clk_tx1_div_n_m1=0x4; 	Address(0x2d[7:0])
SPIWrite 002e,02,0,7	//root_clk_tx2_div_m=0x2; 	Address(0x2e[7:0])
SPIWrite 002f,04,0,7	//root_clk_tx2_div_n_m1=0x4; 	Address(0x2f[7:0])
SPIWrite 0030,01,0,7	//duc_clk_tx1_div_m=0x1; 	Address(0x30[7:0])
SPIWrite 0031,01,0,7	//duc_clk_tx1_div_n_m1=0x1; 	Address(0x31[7:0])
SPIWrite 0032,01,0,7	//duc_clk_tx2_div_m=0x1; 	Address(0x32[7:0])
SPIWrite 0033,01,0,7	//duc_clk_tx2_div_n_m1=0x1; 	Address(0x33[7:0])
SPIWrite 0034,01,0,7	//jesd_clk_tx1_div_m=0x1; 	Address(0x34[7:0])
SPIWrite 0035,00,0,7	//jesd_clk_tx1_div_n_m1=0x0; 	Address(0x35[7:0])
SPIWrite 0036,01,0,7	//jesd_clk_tx2_div_m=0x1; 	Address(0x36[7:0])
SPIWrite 0037,00,0,7	//jesd_clk_tx2_div_n_m1=0x0; 	Address(0x37[7:0])
SPIWrite 0022,41,0,7	//link0_jesd_mode=0x1; 	Address(0x22[7:0])
SPIWrite 0023,41,0,7	//link1_jesd_mode=0x1; 	Address(0x23[7:0])
SPIWrite 0022,41,0,7	//link0_jesd_sample_mode=0x1; 	Address(0x22[7:6])
SPIWrite 0023,41,0,7	//link1_jesd_sample_mode=0x1; 	Address(0x23[7:6])
SPIWrite 0038,1f,0,7	//tx_root_clk_div_dither_en=0x1; 	Address(0x38[7:0])
SPIWrite 0038,1d,0,7	//duc_clk_io_div_dither_en=0x0; 	Address(0x38[7:1])
SPIWrite 0038,19,0,7	//duc_clk_div_dither_en=0x0; 	Address(0x38[7:2])
SPIWrite 0038,11,0,7	//jesd_clk_div_dither_en=0x0; 	Address(0x38[7:3])
SPIWrite 0038,01,0,7	//jesd_clk_div2_div_dither_en=0x0; 	Address(0x38[7:4])
SPIWrite 0026,00,0,7	//num_links=0x0; 	Address(0x26[7:2])
SPIWrite 0042,7f,0,7	//comma_align_valid_thresh=0x7f; 	Address(0x42[7:0])
SPIWrite 0078,df,0,7	//link0_sync_request_ena=0xdf; 	Address(0x78[7:0],0x79[7:0])
SPIWrite 0079,df,0,7	//link1_sync_request_ena=0xdf; 	Address(0x79[7:0],0x7a[7:0])
SPIWrite 007a,00,0,7	//link0_error_ena=0x0; 	Address(0x7a[7:0],0x7b[7:0])
SPIWrite 007b,00,0,7	//link1_error_ena=0x0; 	Address(0x7b[7:0],0x7c[7:0])
SPIWrite 0103,00,0,7	//alarms_clear=0x202020200000003f; 	Address(0x100[7:0],0x101[7:0],0x102[7:0],0x103[7:0],0x104[7:0],0x104[7:0],0x105[7:0],0x106[7:0],0x107[7:0],0x108[7:0])
SPIWrite 0102,00,0,7
SPIWrite 0101,00,0,7
SPIWrite 0100,3f,0,7
SPIWrite 0107,20,0,7
SPIWrite 0106,20,0,7
SPIWrite 0105,20,0,7
SPIWrite 0104,20,0,7
SPIWrite 00fb,00,0,7	//alarms_mask=0x202020200000003f; 	Address(0xf8[7:0],0xf9[7:0],0xfa[7:0],0xfb[7:0],0xfc[7:0],0xfc[7:0],0xfd[7:0],0xfe[7:0],0xff[7:0],0x100[7:0])
SPIWrite 00fa,00,0,7
SPIWrite 00f9,00,0,7
SPIWrite 00f8,3f,0,7
SPIWrite 00ff,20,0,7
SPIWrite 00fe,20,0,7
SPIWrite 00fd,20,0,7
SPIWrite 00fc,20,0,7
SPIWrite 0113,00,0,7	//alarms_to_pap_clear=0x202020200000003f; 	Address(0x110[7:0],0x111[7:0],0x112[7:0],0x113[7:0],0x114[7:0],0x114[7:0],0x115[7:0],0x116[7:0],0x117[7:0],0x118[7:0])
SPIWrite 0112,00,0,7
SPIWrite 0111,00,0,7
SPIWrite 0110,3f,0,7
SPIWrite 0117,20,0,7
SPIWrite 0116,20,0,7
SPIWrite 0115,20,0,7
SPIWrite 0114,20,0,7
SPIWrite 010b,00,0,7	//alarms_to_pap_mask=0x202020200000003f; 	Address(0x108[7:0],0x109[7:0],0x10a[7:0],0x10b[7:0],0x10c[7:0],0x10c[7:0],0x10d[7:0],0x10e[7:0],0x10f[7:0],0x110[7:0])
SPIWrite 010a,00,0,7
SPIWrite 0109,00,0,7
SPIWrite 0108,3f,0,7
SPIWrite 010f,20,0,7
SPIWrite 010e,20,0,7
SPIWrite 010d,20,0,7
SPIWrite 010c,20,0,7
SPIWrite 0024,5c,0,7	//alarm_zeros_jesd_data_ena=0x0; 	Address(0x24[7:1])
SPIWrite 003c,84,0,7	//serdes_fifo_offset_lane0=0x4; 	Address(0x3c[7:0])
SPIWrite 003c,44,0,7	//serdes_fifo_offset_lane1=0x4; 	Address(0x3c[7:4])
SPIWrite 003d,84,0,7	//serdes_fifo_offset_lane2=0x4; 	Address(0x3d[7:0])
SPIWrite 003d,44,0,7	//serdes_fifo_offset_lane3=0x4; 	Address(0x3d[7:4])
SPIWrite 0026,00,0,7	//jesd_std_sel=0x0; 	Address(0x26[7:0])
SPIWrite 0047,81,0,7	//link0_scr=0x1; 	Address(0x47[7:7])
SPIWrite 0055,81,0,7	//link1_scr=0x1; 	Address(0x55[7:7])
SPIWrite 0064,f1,0,7	//lane_ena=0x1; 	Address(0x64[7:0])
SPIWrite 0081,f1,0,7	//rbd_buf_overflow_err_cnt_thresh=0xf; 	Address(0x81[7:4])
SPIWrite 0083,1f,0,7	//dec_8b10b_code_err_cnt_thresh=0xf; 	Address(0x83[7:0])
SPIWrite 0083,ff,0,7	//dec_8b10b_disp_err_cnt_thresh=0xf; 	Address(0x83[7:4])
SPIWrite 0081,ff,0,7	//link_config_err_cnt_thresh=0xf; 	Address(0x81[7:0])
SPIWrite 0080,1f,0,7	//multiframe_align_err_cnt_thresh=0xf; 	Address(0x80[7:0])
SPIWrite 0080,ff,0,7	//frame_align_err_cnt_thresh=0xf; 	Address(0x80[7:4])
SPIWrite 00a8,02,0,7	//Property_88h_1_1=0x1; 	Address(0xa8[7:1])
SPIWrite 0024,58,0,7	//zero_invalid_data=0x0; 	Address(0x24[7:2])
SPIWrite 0024,50,0,7	//fifo_error_zeros_data_ena=0x0; 	Address(0x24[7:3])

//END: Done Configuring DAC JESD RX


//START: Configuring DAC JESD RX

SPIWrite 0016,08,0,7	//dac_jesd=0x2; 	Address(0x16[7:2])
SPIWrite 006c,03,0,7	//link0_k_m1=0x3; 	Address(0x6c[7:0],0x6d[7:0])
SPIWrite 006d,03,0,7	//link1_k_m1=0x3; 	Address(0x6d[7:0],0x6e[7:0])
SPIWrite 0057,03,0,7	//link1_ila_k_m1=0x3; 	Address(0x57[7:0],0x58[7:0])
SPIWrite 0049,03,0,7	//link0_ila_k_m1=0x3; 	Address(0x49[7:0],0x4a[7:0])
SPIWrite 0069,00,0,7	//link0_rbd_m1=0x2; 	Address(0x68[7:0],0x69[7:0],0x6a[7:0])
SPIWrite 0068,02,0,7
SPIWrite 006b,00,0,7	//link1_rbd_m1=0x2; 	Address(0x6a[7:0],0x6b[7:0],0x6c[7:0])
SPIWrite 006a,02,0,7
SPIWrite 0024,5e,0,7	//gearbox_init_state_ovr=0x1; 	Address(0x24[7:6])
SPIWrite 0025,ff,0,7	//gearbox_init_state_lane0_val=0x1; 	Address(0x25[7:0])
SPIWrite 0025,ff,0,7	//gearbox_init_state_lane1_val=0x1; 	Address(0x25[7:1])
SPIWrite 0025,ff,0,7	//gearbox_init_state_lane2_val=0x1; 	Address(0x25[7:2])
SPIWrite 0025,ff,0,7	//gearbox_init_state_lane3_val=0x1; 	Address(0x25[7:3])
SPIWrite 0025,fe,0,7	//gearbox_init_state_lane0_val=0x0; 	Address(0x25[7:0])
SPIWrite 0025,fc,0,7	//gearbox_init_state_lane1_val=0x0; 	Address(0x25[7:1])
SPIWrite 0025,f8,0,7	//gearbox_init_state_lane2_val=0x0; 	Address(0x25[7:2])
SPIWrite 0025,f0,0,7	//gearbox_init_state_lane3_val=0x0; 	Address(0x25[7:3])
SPIWrite 0020,03,0,7	//link0_init_state=0x1; 	Address(0x20[7:0])
SPIWrite 0020,03,0,7	//link1_init_state=0x1; 	Address(0x20[7:1])
SPIWrite 0064,ff,0,7	//jesd_clear_data=0xf; 	Address(0x64[7:4])
SPIWrite 0040,04,0,7	//link0_comma_align_lock_reset_disable=0x1; 	Address(0x40[7:2])
SPIWrite 0040,0c,0,7	//link1_comma_align_lock_reset_disable=0x1; 	Address(0x40[7:3])
SPIWrite 00ac,04,0,7	//link0_emb_align_lock_reset_disable=0x1; 	Address(0xac[7:2])
SPIWrite 00ac,0c,0,7	//link1_emb_align_lock_reset_disable=0x1; 	Address(0xac[7:3])
SPIWrite 002c,02,0,7	//root_clk_tx1_div_m=0x2; 	Address(0x2c[7:0])
SPIWrite 002d,04,0,7	//root_clk_tx1_div_n_m1=0x4; 	Address(0x2d[7:0])
SPIWrite 002e,02,0,7	//root_clk_tx2_div_m=0x2; 	Address(0x2e[7:0])
SPIWrite 002f,04,0,7	//root_clk_tx2_div_n_m1=0x4; 	Address(0x2f[7:0])
SPIWrite 0030,01,0,7	//duc_clk_tx1_div_m=0x1; 	Address(0x30[7:0])
SPIWrite 0031,01,0,7	//duc_clk_tx1_div_n_m1=0x1; 	Address(0x31[7:0])
SPIWrite 0032,01,0,7	//duc_clk_tx2_div_m=0x1; 	Address(0x32[7:0])
SPIWrite 0033,01,0,7	//duc_clk_tx2_div_n_m1=0x1; 	Address(0x33[7:0])
SPIWrite 0034,01,0,7	//jesd_clk_tx1_div_m=0x1; 	Address(0x34[7:0])
SPIWrite 0035,00,0,7	//jesd_clk_tx1_div_n_m1=0x0; 	Address(0x35[7:0])
SPIWrite 0036,01,0,7	//jesd_clk_tx2_div_m=0x1; 	Address(0x36[7:0])
SPIWrite 0037,00,0,7	//jesd_clk_tx2_div_n_m1=0x0; 	Address(0x37[7:0])
SPIWrite 0022,41,0,7	//link0_jesd_mode=0x1; 	Address(0x22[7:0])
SPIWrite 0023,41,0,7	//link1_jesd_mode=0x1; 	Address(0x23[7:0])
SPIWrite 0022,41,0,7	//link0_jesd_sample_mode=0x1; 	Address(0x22[7:6])
SPIWrite 0023,41,0,7	//link1_jesd_sample_mode=0x1; 	Address(0x23[7:6])
SPIWrite 0038,1f,0,7	//tx_root_clk_div_dither_en=0x1; 	Address(0x38[7:0])
SPIWrite 0038,1d,0,7	//duc_clk_io_div_dither_en=0x0; 	Address(0x38[7:1])
SPIWrite 0038,19,0,7	//duc_clk_div_dither_en=0x0; 	Address(0x38[7:2])
SPIWrite 0038,11,0,7	//jesd_clk_div_dither_en=0x0; 	Address(0x38[7:3])
SPIWrite 0038,01,0,7	//jesd_clk_div2_div_dither_en=0x0; 	Address(0x38[7:4])
SPIWrite 0026,00,0,7	//num_links=0x0; 	Address(0x26[7:2])
SPIWrite 0042,7f,0,7	//comma_align_valid_thresh=0x7f; 	Address(0x42[7:0])
SPIWrite 0078,df,0,7	//link0_sync_request_ena=0xdf; 	Address(0x78[7:0],0x79[7:0])
SPIWrite 0079,df,0,7	//link1_sync_request_ena=0xdf; 	Address(0x79[7:0],0x7a[7:0])
SPIWrite 007a,00,0,7	//link0_error_ena=0x0; 	Address(0x7a[7:0],0x7b[7:0])
SPIWrite 007b,00,0,7	//link1_error_ena=0x0; 	Address(0x7b[7:0],0x7c[7:0])
SPIWrite 0103,00,0,7	//alarms_clear=0x202020200000003f; 	Address(0x100[7:0],0x101[7:0],0x102[7:0],0x103[7:0],0x104[7:0],0x104[7:0],0x105[7:0],0x106[7:0],0x107[7:0],0x108[7:0])
SPIWrite 0102,00,0,7
SPIWrite 0101,00,0,7
SPIWrite 0100,3f,0,7
SPIWrite 0107,20,0,7
SPIWrite 0106,20,0,7
SPIWrite 0105,20,0,7
SPIWrite 0104,20,0,7
SPIWrite 00fb,00,0,7	//alarms_mask=0x202020200000003f; 	Address(0xf8[7:0],0xf9[7:0],0xfa[7:0],0xfb[7:0],0xfc[7:0],0xfc[7:0],0xfd[7:0],0xfe[7:0],0xff[7:0],0x100[7:0])
SPIWrite 00fa,00,0,7
SPIWrite 00f9,00,0,7
SPIWrite 00f8,3f,0,7
SPIWrite 00ff,20,0,7
SPIWrite 00fe,20,0,7
SPIWrite 00fd,20,0,7
SPIWrite 00fc,20,0,7
SPIWrite 0113,00,0,7	//alarms_to_pap_clear=0x202020200000003f; 	Address(0x110[7:0],0x111[7:0],0x112[7:0],0x113[7:0],0x114[7:0],0x114[7:0],0x115[7:0],0x116[7:0],0x117[7:0],0x118[7:0])
SPIWrite 0112,00,0,7
SPIWrite 0111,00,0,7
SPIWrite 0110,3f,0,7
SPIWrite 0117,20,0,7
SPIWrite 0116,20,0,7
SPIWrite 0115,20,0,7
SPIWrite 0114,20,0,7
SPIWrite 010b,00,0,7	//alarms_to_pap_mask=0x202020200000003f; 	Address(0x108[7:0],0x109[7:0],0x10a[7:0],0x10b[7:0],0x10c[7:0],0x10c[7:0],0x10d[7:0],0x10e[7:0],0x10f[7:0],0x110[7:0])
SPIWrite 010a,00,0,7
SPIWrite 0109,00,0,7
SPIWrite 0108,3f,0,7
SPIWrite 010f,20,0,7
SPIWrite 010e,20,0,7
SPIWrite 010d,20,0,7
SPIWrite 010c,20,0,7
SPIWrite 0024,5c,0,7	//alarm_zeros_jesd_data_ena=0x0; 	Address(0x24[7:1])
SPIWrite 003c,84,0,7	//serdes_fifo_offset_lane0=0x4; 	Address(0x3c[7:0])
SPIWrite 003c,44,0,7	//serdes_fifo_offset_lane1=0x4; 	Address(0x3c[7:4])
SPIWrite 003d,84,0,7	//serdes_fifo_offset_lane2=0x4; 	Address(0x3d[7:0])
SPIWrite 003d,44,0,7	//serdes_fifo_offset_lane3=0x4; 	Address(0x3d[7:4])
SPIWrite 0026,00,0,7	//jesd_std_sel=0x0; 	Address(0x26[7:0])
SPIWrite 0047,81,0,7	//link0_scr=0x1; 	Address(0x47[7:7])
SPIWrite 0055,81,0,7	//link1_scr=0x1; 	Address(0x55[7:7])
SPIWrite 0064,f1,0,7	//lane_ena=0x1; 	Address(0x64[7:0])
SPIWrite 0081,f1,0,7	//rbd_buf_overflow_err_cnt_thresh=0xf; 	Address(0x81[7:4])
SPIWrite 0083,1f,0,7	//dec_8b10b_code_err_cnt_thresh=0xf; 	Address(0x83[7:0])
SPIWrite 0083,ff,0,7	//dec_8b10b_disp_err_cnt_thresh=0xf; 	Address(0x83[7:4])
SPIWrite 0081,ff,0,7	//link_config_err_cnt_thresh=0xf; 	Address(0x81[7:0])
SPIWrite 0080,1f,0,7	//multiframe_align_err_cnt_thresh=0xf; 	Address(0x80[7:0])
SPIWrite 0080,ff,0,7	//frame_align_err_cnt_thresh=0xf; 	Address(0x80[7:4])
SPIWrite 00a8,02,0,7	//Property_88h_1_1=0x1; 	Address(0xa8[7:1])
SPIWrite 0024,58,0,7	//zero_invalid_data=0x0; 	Address(0x24[7:2])
SPIWrite 0024,50,0,7	//fifo_error_zeros_data_ena=0x0; 	Address(0x24[7:3])

//END: Done Configuring DAC JESD RX

SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])

//STEP: jesdConfig/step3 
SPIWrite 0016,10,0,7	//jesd_subchip=0x1; 	Address(0x16[7:4])
SPIWrite 007c,c3,0,7	//lp_rx_on_a_sel_2r1f_ab_mask=0x3; 	Address(0x7c[7:0])
SPIWrite 007c,c3,0,7	//lp_rx_on_b_sel_2r1f_ab_mask=0xc; 	Address(0x7c[7:4])
SPIWrite 007d,03,0,7	//lp_rx_on_c_sel_2r1f_ab_mask=0x3; 	Address(0x7d[7:0])
SPIWrite 007d,c3,0,7	//lp_rx_on_d_sel_2r1f_ab_mask=0xc; 	Address(0x7d[7:4])
SPIWrite 007e,09,0,7	//lp_fb_on_a_sel_2r1f_ab_mask=0x1; 	Address(0x7e[7:0])
SPIWrite 007e,09,0,7	//lp_fb_on_c_sel_2r1f_ab_mask=0x2; 	Address(0x7e[7:2])
SPIWrite 0016,00,0,7	//jesd_subchip=0x0; 	Address(0x16[7:4])
SPIWrite 0016,01,0,7	//adc_jesd=0x1; 	Address(0x16[7:0])
SPIWrite 0120,00,0,7	//ctrl_rx1_msf_sig_invalid=0x0; 	Address(0x120[7:0])
SPIWrite 0120,0c,0,7	//ctrl_rx2_msf_sig_invalid=0x3; 	Address(0x120[7:2])
SPIWrite 0120,3c,0,7	//ctrl_rx3_rx4_msf_sig_invalid=0x3; 	Address(0x120[7:4])
SPIWrite 0121,03,0,7	//ctrl_fb1_msf_sig_invalid=0x3; 	Address(0x121[7:0])
SPIWrite 0121,0f,0,7	//ctrl_fb2_msf_sig_invalid=0x3; 	Address(0x121[7:2])
SPIWrite 0016,00,0,7	//adc_jesd=0x0; 	Address(0x16[7:0])
SPIWrite 0016,10,0,7	//jesd_subchip=0x1; 	Address(0x16[7:4])
SPIWrite 0029,03,0,7	//dual_2t2r1f_mode_ab=0x1; 	Address(0x29[7:0])
SPIWrite 0029,03,0,7	//dual_2t2r1f_mode_cd=0x1; 	Address(0x29[7:1])
SPIWrite 0081,03,0,7	//lp_rx_on_c_sel_2r1f_cd_mask=0x3; 	Address(0x81[7:0])
SPIWrite 0081,c3,0,7	//lp_rx_on_d_sel_2r1f_cd_mask=0xc; 	Address(0x81[7:4])
SPIWrite 0082,04,0,7	//lp_fb_on_c_sel_2r1f_cd_mask=0x1; 	Address(0x82[7:2])
SPIWrite 0082,06,0,7	//lp_fb_on_a_sel_2r1f_cd_mask=0x2; 	Address(0x82[7:0])
SPIWrite 0016,00,0,7	//jesd_subchip=0x0; 	Address(0x16[7:4])
SPIWrite 0016,02,0,7	//adc_jesd=0x2; 	Address(0x16[7:0])
SPIWrite 0120,00,0,7	//ctrl_rx1_msf_sig_invalid=0x0; 	Address(0x120[7:0])
SPIWrite 0120,0c,0,7	//ctrl_rx2_msf_sig_invalid=0x3; 	Address(0x120[7:2])
SPIWrite 0120,3c,0,7	//ctrl_rx3_rx4_msf_sig_invalid=0x3; 	Address(0x120[7:4])
SPIWrite 0121,03,0,7	//ctrl_fb1_msf_sig_invalid=0x3; 	Address(0x121[7:0])
SPIWrite 0121,0f,0,7	//ctrl_fb2_msf_sig_invalid=0x3; 	Address(0x121[7:2])
SPIWrite 0016,00,0,7	//adc_jesd=0x0; 	Address(0x16[7:0])
SPIWrite 0016,10,0,7	//jesd_subchip=0x1; 	Address(0x16[7:4])
SPIWrite 0029,03,0,7	//dual_2t2r1f_mode_ab=0x1; 	Address(0x29[7:0])
SPIWrite 0029,03,0,7	//dual_2t2r1f_mode_cd=0x1; 	Address(0x29[7:1])
SPIWrite 0016,00,0,7	//jesd_subchip=0x0; 	Address(0x16[7:4])

//STEP: agcConfig/step0 
SPIWrite 0013,40,0,7	//dsa_page1=0x1; 	Address(0x13[7:6])
SPIWrite 00d0,03,0,7	//gain_ctrl=0x3; 	Address(0xd0[7:0])
SPIWrite 0013,80,0,7	//dsa_page1=0x2; 	Address(0x13[7:6])
SPIWrite 00d0,03,0,7	//gain_ctrl=0x3; 	Address(0xd0[7:0])
SPIWrite 0013,00,0,7	//dsa_page1=0x0; 	Address(0x13[7:6])
SPIWrite 0012,01,0,7	//rxdig=0x1; 	Address(0x12[7:0])
SPIWrite 0773,01,0,7	//Property_750h_24_24=0x1; 	Address(0x773[7:0])
SPIWrite 0773,01,0,7	//Property_750h_24_24=0x1; 	Address(0x773[7:0])
SPIWrite 0012,08,0,7	//rxdig=0x8; 	Address(0x12[7:0])
SPIWrite 0773,01,0,7	//Property_750h_24_24=0x1; 	Address(0x773[7:0])
SPIWrite 0773,01,0,7	//Property_750h_24_24=0x1; 	Address(0x773[7:0])
SPIWrite 0012,00,0,7	//rxdig=0x0; 	Address(0x12[7:0])

//STEP: miscConfig/step0 

//START: Configuring Interrupt Pins

SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0101,02,0,7	//alarm_mask_lsb_for_alarm0=0x23f; 	Address(0x100[7:0],0x101[7:0],0x102[7:0])
SPIWrite 0100,3f,0,7
SPIWrite 0103,00,0,7	//alarm_mask_msb_for_alarm0=0x0; 	Address(0x102[7:0],0x103[7:0],0x104[7:0])
SPIWrite 0102,00,0,7
SPIWrite 0105,02,0,7	//alarm_mask_lsb_for_alarm1=0x23f; 	Address(0x104[7:0],0x105[7:0],0x106[7:0])
SPIWrite 0104,3f,0,7
SPIWrite 0107,00,0,7	//alarm_mask_msb_for_alarm1=0x0; 	Address(0x106[7:0],0x107[7:0],0x108[7:0])
SPIWrite 0106,00,0,7

//END: Done configuring Interrupt Pins


//START: Power Saving Options

SPIWrite 0931,01,0,7	//Property_910h_8_8=0x1; 	Address(0x931[7:0])
SPIWrite 0931,03,0,7	//Property_910h_9_9=0x1; 	Address(0x931[7:1])
SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0011,3f,0,7	//ec_ana=0x3f; 	Address(0x11[7:0])
SPIWrite 00ce,20,0,7	//Property_ceh_5_5=0x1; 	Address(0xce[7:5])
SPIWrite 00cb,04,0,7	//Property_cbh_2_2=0x1; 	Address(0xcb[7:2])
SPIWrite 00ca,20,0,7	//Property_cah_5_5=0x1; 	Address(0xca[7:5])
SPIWrite 00ce,30,0,7	//Property_ceh_4_4=0x1; 	Address(0xce[7:4])
SPIWrite 00c3,40,0,7	//Property_c3h_6_6=0x1; 	Address(0xc3[7:6])
SPIWrite 00c0,01,0,7	//Property_c0h_0_0=0x1; 	Address(0xc0[7:0])
SPIWrite 00b9,40,0,7	//Property_b9h_6_6=0x1; 	Address(0xb9[7:6])
SPIWrite 00b9,50,0,7	//Property_b9h_4_4=0x1; 	Address(0xb9[7:4])
SPIWrite 00b9,70,0,7	//Property_b9h_5_5=0x1; 	Address(0xb9[7:5])
SPIWrite 00b9,78,0,7	//Property_b9h_3_3=0x1; 	Address(0xb9[7:3])
SPIWrite 0011,00,0,7	//ec_ana=0x0; 	Address(0x11[7:0])
SPIWrite 0010,3f,0,7	//ec_dig=0x3f; 	Address(0x10[7:0])
SPIWrite 00b0,30,0,7	//Property_b0h_5_5=0x1; 	Address(0xb0[7:5])
SPIWrite 00b4,30,0,7	//Property_b4h_5_5=0x1; 	Address(0xb4[7:5])
SPIWrite 0010,00,0,7	//ec_dig=0x0; 	Address(0x10[7:0])
SPIWrite 0019,01,0,7	//Property_19h_0_0=0x1; 	Address(0x19[7:0])
SPIWrite 039c,01,0,7	//Property_37ch_0_0=0x1; 	Address(0x39c[7:0])
SPIWrite 039d,01,0,7	//Property_37ch_8_8=0x1; 	Address(0x39d[7:0])
SPIWrite 039e,01,0,7	//Property_37ch_16_16=0x1; 	Address(0x39e[7:0])
SPIWrite 039f,01,0,7	//Property_37ch_24_24=0x1; 	Address(0x39f[7:0])
SPIWrite 03a0,01,0,7	//Property_380h_0_0=0x1; 	Address(0x3a0[7:0])
SPIWrite 03a1,01,0,7	//Property_380h_8_8=0x1; 	Address(0x3a1[7:0])

//END: Power Saving Options

SPIWrite 0019,00,0,7	//Property_19h_0_0=0x0; 	Address(0x19[7:0])

//STEP: miscConfig/step1 
SPIWrite 0013,40,0,7	//dsa_page1=0x1; 	Address(0x13[7:6])
SPIWrite 0124,00,0,7	//spi_agc_dsa_A=0x0; 	Address(0x124[7:0])
SPIWrite 0174,00,0,7	//spi_agc_dsa_B=0x0; 	Address(0x174[7:0])
SPIWrite 0013,80,0,7	//dsa_page1=0x2; 	Address(0x13[7:6])
SPIWrite 0124,00,0,7	//spi_agc_dsa_A=0x0; 	Address(0x124[7:0])
SPIWrite 0174,00,0,7	//spi_agc_dsa_B=0x0; 	Address(0x174[7:0])
SPIWrite 0013,00,0,7	//dsa_page1=0x0; 	Address(0x13[7:6])
SPIWrite 0013,10,0,7	//dsa_page0=0x1; 	Address(0x13[7:4])
SPIWrite 00c8,00,0,7	//txa_dsa_index=0x0; 	Address(0xc8[7:0])
SPIWrite 00cc,00,0,7	//txb_dsa_index=0x0; 	Address(0xcc[7:0])
SPIWrite 0013,20,0,7	//dsa_page0=0x2; 	Address(0x13[7:4])
SPIWrite 00c8,00,0,7	//txa_dsa_index=0x0; 	Address(0xc8[7:0])
SPIWrite 00cc,00,0,7	//txb_dsa_index=0x0; 	Address(0xcc[7:0])
SPIWrite 0013,10,0,7	//dsa_page0=0x1; 	Address(0x13[7:4])
SPIWrite 006c,00,0,7	//spi_agc_dsa_fb=0x0; 	Address(0x6c[7:0])
SPIWrite 0013,20,0,7	//dsa_page0=0x2; 	Address(0x13[7:4])
SPIWrite 006c,00,0,7	//spi_agc_dsa_fb=0x0; 	Address(0x6c[7:0])
SPIWrite 0013,00,0,7	//dsa_page0=0x0; 	Address(0x13[7:4])

//STEP: gpioConfig/step0 
SPIWrite 0015,10,0,7	//io_wrap=0x1; 	Address(0x15[7:4])
SPIWrite 0420,01,0,7	//preferred_input_sel_gpio_8=0x0; 	Address(0x420[7:2])
SPIWrite 0420,01,0,7	//buf_dir_ctrl_gpio_8=0x1; 	Address(0x420[7:0])
SPIWrite 08c9,00,0,7	//ovr_sel_intpi_tdd_en_fbab=0x0; 	Address(0x8c9[7:1])
SPIWrite 08ca,09,0,7	//crossbar_sel_intpi_tdd_en_fbab=0x9; 	Address(0x8ca[7:0],0x8cb[7:0])
SPIWrite 0420,01,0,7	//preferred_input_sel_gpio_8=0x0; 	Address(0x420[7:2])
SPIWrite 0420,01,0,7	//buf_dir_ctrl_gpio_8=0x1; 	Address(0x420[7:0])
SPIWrite 08cd,00,0,7	//ovr_sel_intpi_tdd_en_fbcd=0x0; 	Address(0x8cd[7:1])
SPIWrite 08ce,09,0,7	//crossbar_sel_intpi_tdd_en_fbcd=0x9; 	Address(0x8ce[7:0],0x8cf[7:0])
SPIWrite 0514,21,0,7	//preferred_output_sel_gpio_69=0x1; 	Address(0x514[7:5])
SPIWrite 0514,22,0,7	//buf_dir_ctrl_gpio_69=0x2; 	Address(0x514[7:0])
SPIWrite 10f5,00,0,7	//ovr_sel_intpo_dac_sync_n_cd_1=0x0; 	Address(0x10f5[7:1])
SPIWrite 040c,01,0,7	//preferred_input_sel_gpio_3=0x0; 	Address(0x40c[7:2])
SPIWrite 040c,01,0,7	//buf_dir_ctrl_gpio_3=0x1; 	Address(0x40c[7:0])
SPIWrite 08b9,00,0,7	//ovr_sel_intpi_tdd_en_txa=0x0; 	Address(0x8b9[7:1])
SPIWrite 08ba,04,0,7	//crossbar_sel_intpi_tdd_en_txa=0x4; 	Address(0x8ba[7:0],0x8bb[7:0])
SPIWrite 040c,01,0,7	//preferred_input_sel_gpio_3=0x0; 	Address(0x40c[7:2])
SPIWrite 040c,01,0,7	//buf_dir_ctrl_gpio_3=0x1; 	Address(0x40c[7:0])
SPIWrite 08bd,00,0,7	//ovr_sel_intpi_tdd_en_txb=0x0; 	Address(0x8bd[7:1])
SPIWrite 08be,04,0,7	//crossbar_sel_intpi_tdd_en_txb=0x4; 	Address(0x8be[7:0],0x8bf[7:0])
SPIWrite 040c,01,0,7	//preferred_input_sel_gpio_3=0x0; 	Address(0x40c[7:2])
SPIWrite 040c,01,0,7	//buf_dir_ctrl_gpio_3=0x1; 	Address(0x40c[7:0])
SPIWrite 08c1,00,0,7	//ovr_sel_intpi_tdd_en_txc=0x0; 	Address(0x8c1[7:1])
SPIWrite 08c2,04,0,7	//crossbar_sel_intpi_tdd_en_txc=0x4; 	Address(0x8c2[7:0],0x8c3[7:0])
SPIWrite 040c,01,0,7	//preferred_input_sel_gpio_3=0x0; 	Address(0x40c[7:2])
SPIWrite 040c,01,0,7	//buf_dir_ctrl_gpio_3=0x1; 	Address(0x40c[7:0])
SPIWrite 08c5,00,0,7	//ovr_sel_intpi_tdd_en_txd=0x0; 	Address(0x8c5[7:1])
SPIWrite 08c6,04,0,7	//crossbar_sel_intpi_tdd_en_txd=0x4; 	Address(0x8c6[7:0],0x8c7[7:0])
SPIWrite 0510,01,0,7	//preferred_input_sel_gpio_68=0x0; 	Address(0x510[7:2])
SPIWrite 0510,01,0,7	//buf_dir_ctrl_gpio_68=0x1; 	Address(0x510[7:0])
SPIWrite 08ad,00,0,7	//ovr_sel_intpi_adc_sync_n_cd_0=0x0; 	Address(0x8ad[7:1])
SPIWrite 08ae,3e,0,7	//crossbar_sel_intpi_adc_sync_n_cd_0=0x3e; 	Address(0x8ae[7:0],0x8af[7:0])
SPIWrite 050c,21,0,7	//preferred_output_sel_gpio_67=0x1; 	Address(0x50c[7:5])
SPIWrite 050c,22,0,7	//buf_dir_ctrl_gpio_67=0x2; 	Address(0x50c[7:0])
SPIWrite 10f1,00,0,7	//ovr_sel_intpo_dac_sync_n_cd_0=0x0; 	Address(0x10f1[7:1])
SPIWrite 0534,05,0,7	//preferred_input_sel_gpio_77=0x1; 	Address(0x534[7:2])
SPIWrite 0534,05,0,7	//buf_dir_ctrl_gpio_77=0x1; 	Address(0x534[7:0])
SPIWrite 08b1,00,0,7	//ovr_sel_intpi_adc_sync_n_cd_1=0x0; 	Address(0x8b1[7:1])
SPIWrite 04c0,05,0,7	//preferred_input_sel_gpio_48=0x1; 	Address(0x4c0[7:2])
SPIWrite 04c0,05,0,7	//buf_dir_ctrl_gpio_48=0x1; 	Address(0x4c0[7:0])
SPIWrite 08a1,00,0,7	//ovr_sel_intpi_adc_sync_n_ab_0=0x0; 	Address(0x8a1[7:1])
SPIWrite 04bc,21,0,7	//preferred_output_sel_gpio_47=0x1; 	Address(0x4bc[7:5])
SPIWrite 04bc,22,0,7	//buf_dir_ctrl_gpio_47=0x2; 	Address(0x4bc[7:0])
SPIWrite 10c5,00,0,7	//ovr_sel_intpo_dac_sync_n_ab_0=0x0; 	Address(0x10c5[7:1])
SPIWrite 04e4,05,0,7	//preferred_input_sel_gpio_57=0x1; 	Address(0x4e4[7:2])
SPIWrite 04e4,05,0,7	//buf_dir_ctrl_gpio_57=0x1; 	Address(0x4e4[7:0])
SPIWrite 08a5,00,0,7	//ovr_sel_intpi_adc_sync_n_ab_1=0x0; 	Address(0x8a5[7:1])
SPIWrite 04c4,21,0,7	//preferred_output_sel_gpio_49=0x1; 	Address(0x4c4[7:5])
SPIWrite 04c4,22,0,7	//buf_dir_ctrl_gpio_49=0x2; 	Address(0x4c4[7:0])
SPIWrite 10c9,00,0,7	//ovr_sel_intpo_dac_sync_n_ab_1=0x0; 	Address(0x10c9[7:1])
SPIWrite 0454,05,0,7	//preferred_input_sel_gpio_21=0x1; 	Address(0x454[7:2])
SPIWrite 0454,05,0,7	//buf_dir_ctrl_gpio_21=0x1; 	Address(0x454[7:0])
SPIWrite 0905,00,0,7	//ovr_sel_intpi_global_pdn=0x0; 	Address(0x905[7:1])
SPIWrite 04cc,01,0,7	//preferred_input_sel_gpio_51=0x0; 	Address(0x4cc[7:2])
SPIWrite 04cc,01,0,7	//buf_dir_ctrl_gpio_51=0x1; 	Address(0x4cc[7:0])
SPIWrite 09d5,00,0,7	//ovr_sel_intpi_tdd_en_rxa=0x0; 	Address(0x9d5[7:1])
SPIWrite 09d6,2d,0,7	//crossbar_sel_intpi_tdd_en_rxa=0x2d; 	Address(0x9d6[7:0],0x9d7[7:0])
SPIWrite 04cc,01,0,7	//preferred_input_sel_gpio_51=0x0; 	Address(0x4cc[7:2])
SPIWrite 04cc,01,0,7	//buf_dir_ctrl_gpio_51=0x1; 	Address(0x4cc[7:0])
SPIWrite 09d9,00,0,7	//ovr_sel_intpi_tdd_en_rxb=0x0; 	Address(0x9d9[7:1])
SPIWrite 09da,2d,0,7	//crossbar_sel_intpi_tdd_en_rxb=0x2d; 	Address(0x9da[7:0],0x9db[7:0])
SPIWrite 04cc,01,0,7	//preferred_input_sel_gpio_51=0x0; 	Address(0x4cc[7:2])
SPIWrite 04cc,01,0,7	//buf_dir_ctrl_gpio_51=0x1; 	Address(0x4cc[7:0])
SPIWrite 09dd,00,0,7	//ovr_sel_intpi_tdd_en_rxc=0x0; 	Address(0x9dd[7:1])
SPIWrite 09de,2d,0,7	//crossbar_sel_intpi_tdd_en_rxc=0x2d; 	Address(0x9de[7:0],0x9df[7:0])
SPIWrite 04cc,01,0,7	//preferred_input_sel_gpio_51=0x0; 	Address(0x4cc[7:2])
SPIWrite 04cc,01,0,7	//buf_dir_ctrl_gpio_51=0x1; 	Address(0x4cc[7:0])
SPIWrite 09e1,00,0,7	//ovr_sel_intpi_tdd_en_rxd=0x0; 	Address(0x9e1[7:1])
SPIWrite 09e2,2d,0,7	//crossbar_sel_intpi_tdd_en_rxd=0x2d; 	Address(0x9e2[7:0],0x9e3[7:0])
SPIWrite 02bc,00,0,7	//pull_ctrl_gpio_47=0x0; 	Address(0x2bc[7:0])
SPIWrite 02c4,00,0,7	//pull_ctrl_gpio_49=0x0; 	Address(0x2c4[7:0])
SPIWrite 030c,00,0,7	//pull_ctrl_gpio_67=0x0; 	Address(0x30c[7:0])
SPIWrite 0314,00,0,7	//pull_ctrl_gpio_69=0x0; 	Address(0x314[7:0])
SPIWrite 02c0,00,0,7	//pull_ctrl_gpio_48=0x0; 	Address(0x2c0[7:0])
SPIWrite 02e4,00,0,7	//pull_ctrl_gpio_57=0x0; 	Address(0x2e4[7:0])
SPIWrite 0334,00,0,7	//pull_ctrl_gpio_77=0x0; 	Address(0x334[7:0])
SPIWrite 0310,00,0,7	//pull_ctrl_gpio_68=0x0; 	Address(0x310[7:0])
SPIWrite 0015,00,0,7	//io_wrap=0x0; 	Address(0x15[7:4])

//STEP: sysrefJesdLinkup/step0 
SPIWrite 0016,03,0,7	//adc_jesd=0x3; 	Address(0x16[7:0])
SPIWrite 006d,06,0,7	//link0_init_state=0x0; 	Address(0x6d[7:0])
SPIWrite 006d,02,0,7	//link2_init_state=0x0; 	Address(0x6d[7:2])
SPIWrite 006d,00,0,7	//link1_init_state=0x0; 	Address(0x6d[7:1])
SPIWrite 006e,0e,0,7	//lane0_serdes_fifo_init_state=0x0; 	Address(0x6e[7:0])
SPIWrite 006e,0c,0,7	//lane1_serdes_fifo_init_state=0x0; 	Address(0x6e[7:1])
SPIWrite 006e,08,0,7	//lane2_serdes_fifo_init_state=0x0; 	Address(0x6e[7:2])
SPIWrite 006e,00,0,7	//lane3_serdes_fifo_init_state=0x0; 	Address(0x6e[7:3])
SPIWrite 0016,00,0,7	//adc_jesd=0x0; 	Address(0x16[7:0])
SPIWrite 0016,0c,0,7	//dac_jesd=0x3; 	Address(0x16[7:2])
SPIWrite 0020,02,0,7	//link0_init_state=0x0; 	Address(0x20[7:0])
SPIWrite 0020,00,0,7	//link1_init_state=0x0; 	Address(0x20[7:1])
SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])

//STEP: sysrefJesdLinkup/step1 

//START: Clearing Sysref Flags

SPIWrite 0016,03,0,7	//adc_jesd=0x3; 	Address(0x16[7:0])
SPIWrite 0124,08,0,7	//clear_jesd_clk_rx1_p0=0x1; 	Address(0x124[7:3])
SPIWrite 0128,08,0,7	//clear_jesd_sysref_rx1_p0=0x1; 	Address(0x128[7:3])
SPIWrite 0124,00,0,7	//clear_jesd_clk_rx1_p0=0x0; 	Address(0x124[7:3])
SPIWrite 0128,00,0,7	//clear_jesd_sysref_rx1_p0=0x0; 	Address(0x128[7:3])
SPIWrite 0016,00,0,7	//adc_jesd=0x0; 	Address(0x16[7:0])
SPIWrite 0016,04,0,7	//dac_jesd=0x1; 	Address(0x16[7:2])
SPIWrite 00eb,f0,0,7	//clear_jesd_sysref_flag=0xf; 	Address(0xeb[7:4])
SPIWrite 00eb,ff,0,7	//clear_jesd_clk_flag=0xf; 	Address(0xeb[7:0])
SPIWrite 00eb,0f,0,7	//clear_jesd_sysref_flag=0x0; 	Address(0xeb[7:4])
SPIWrite 00eb,00,0,7	//clear_jesd_clk_flag=0x0; 	Address(0xeb[7:0])
SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])
SPIWrite 0015,02,0,7	//ana_4t4r=0x1; 	Address(0x15[7:1])
SPIWrite 00dc,10,0,7	//Property_bch_4_4=0x1; 	Address(0xdc[7:4])
SPIWrite 00df,10,0,7	//Property_bch_28_28=0x1; 	Address(0xdf[7:4])
SPIWrite 0100,10,0,7	//Property_e0h_4_4=0x1; 	Address(0x100[7:4])
SPIWrite 00c4,10,0,7	//Property_a4h_4_4=0x1; 	Address(0xc4[7:4])
SPIWrite 00c7,10,0,7	//Property_a4h_28_28=0x1; 	Address(0xc7[7:4])
SPIWrite 00cc,10,0,7	//Property_ach_4_4=0x1; 	Address(0xcc[7:4])
SPIWrite 00cf,10,0,7	//Property_ach_28_28=0x1; 	Address(0xcf[7:4])
SPIWrite 00d8,10,0,7	//Property_b8h_4_4=0x1; 	Address(0xd8[7:4])
SPIWrite 00d4,10,0,7	//Property_b4h_4_4=0x1; 	Address(0xd4[7:4])
SPIWrite 00dc,00,0,7	//Property_bch_4_4=0x0; 	Address(0xdc[7:4])
SPIWrite 00df,00,0,7	//Property_bch_28_28=0x0; 	Address(0xdf[7:4])
SPIWrite 0100,00,0,7	//Property_e0h_4_4=0x0; 	Address(0x100[7:4])
SPIWrite 00c4,00,0,7	//Property_a4h_4_4=0x0; 	Address(0xc4[7:4])
SPIWrite 00c7,00,0,7	//Property_a4h_28_28=0x0; 	Address(0xc7[7:4])
SPIWrite 00cc,00,0,7	//Property_ach_4_4=0x0; 	Address(0xcc[7:4])
SPIWrite 00cf,00,0,7	//Property_ach_28_28=0x0; 	Address(0xcf[7:4])
SPIWrite 00d8,00,0,7	//Property_b8h_4_4=0x0; 	Address(0xd8[7:4])
SPIWrite 00d4,00,0,7	//Property_b4h_4_4=0x0; 	Address(0xd4[7:4])

//END: Done clearing Sysref Flags

SPIWrite 0015,00,0,7	//ana_4t4r=0x0; 	Address(0x15[7:1])

//STEP: sysrefJesdLinkup/step2 

//START: Sending Sysref to device


//External-Action: Ensure Sysref is running before this point.


//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,01,0,7	//pll_reg_spi_req_a=0x1; 	Address(0x170[7:0])
SPIWrite 0540,00,0,7	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

SPIPoll 0171,0,0,01
SPIRead 0171,0,0

//Read	pll_reg_spi_a_ack=0x1(Meaning: );; 	Address(0x171[7:0])


//END: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])
SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 085b,00,0,7	//Property_838h_31_0=0x0; 	Address(0x858[7:0],0x859[7:0],0x85a[7:0],0x85b[7:0],0x85c[7:0])
SPIWrite 085a,00,0,7
SPIWrite 0859,00,0,7
SPIWrite 0858,00,0,7
SPIWrite 085b,00,0,7	//Property_838h_31_0=0x101; 	Address(0x858[7:0],0x859[7:0],0x85a[7:0],0x85b[7:0],0x85c[7:0])
SPIWrite 085a,00,0,7
SPIWrite 0859,01,0,7
SPIWrite 0858,01,0,7
SPIWrite 085b,00,0,7	//Property_838h_31_0=0x0; 	Address(0x858[7:0],0x859[7:0],0x85a[7:0],0x85b[7:0],0x85c[7:0])
SPIWrite 085a,00,0,7
SPIWrite 0859,00,0,7
SPIWrite 0858,00,0,7
SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0015,01,0,7	//pll=0x1; 	Address(0x15[7:0])
SPIWrite 006a,00,0,7	//Property_48h_17_17=0x0; 	Address(0x6a[7:1])
SPIWrite 006e,00,0,7	//LCMGEN_USE_SPI_SYSREF=0x0; 	Address(0x6e[7:0])
SPIWrite 006a,00,0,7	//Property_48h_17_17=0x0; 	Address(0x6a[7:1])
SPIWrite 006a,02,0,7	//Property_48h_17_17=0x1; 	Address(0x6a[7:1])
SPIWrite 0058,86,0,7	//Property_38h_1_1=0x1; 	Address(0x58[7:1])

WAIT 0.001
SPIWrite 0058,84,0,7	//Property_38h_1_1=0x0; 	Address(0x58[7:1])

//START: Requesting/releasing SPI Access to PLL Pages

SPIWrite 0015,00,0,7	//pll=0x0; 	Address(0x15[7:0])
SPIWrite 0015,40,0,7	//digtop=0x1; 	Address(0x15[7:6])
SPIWrite 0170,00,0,7	//pll_reg_spi_req_a=0x0; 	Address(0x170[7:0])
SPIWrite 0540,00,0,7	//Property_520h_0_0=0x0; 	Address(0x540[7:0])

//END: Requesting/releasing SPI Access to PLL Pages


//END: Sending Sysref to device

SPIWrite 0015,00,0,7	//digtop=0x0; 	Address(0x15[7:6])

//STEP: sysrefJesdLinkup/step3 

//START: Checking Sysref Flags

SPIWrite 0016,01,0,7	//adc_jesd=0x1; 	Address(0x16[7:0])
SPIReadCheck 012c,3,3,08

//Read	monitor_jesd_clk_rx1_p0=0x1; 	Address(0x12c[7:3])

SPIReadCheck 0130,3,3,08

//Read	monitor_jesd_sysref_rx1_p0=0x1; 	Address(0x130[7:3])


//END: Done checking Sysref Flags

SPIWrite 0016,00,0,7	//adc_jesd=0x0; 	Address(0x16[7:0])

//STEP: sysrefJesdLinkup/step4 
SPIWrite 0016,03,0,7	//adc_jesd=0x3; 	Address(0x16[7:0])
SPIWrite 0024,00,0,7	//jesd_clear_data=0x0; 	Address(0x24[7:0])
SPIWrite 00f0,0f,0,7	//alarms_serdes_fifo_errors_clear=0xf; 	Address(0xf0[7:0])
SPIWrite 00f0,00,0,7	//alarms_serdes_fifo_errors_clear=0x0; 	Address(0xf0[7:0])
SPIWrite 0016,00,0,7	//adc_jesd=0x0; 	Address(0x16[7:0])
SPIWrite 0016,0c,0,7	//dac_jesd=0x3; 	Address(0x16[7:2])
SPIWrite 0064,01,0,7	//jesd_clear_data=0x0; 	Address(0x64[7:4])
SPIWrite 0128,01,0,7	//clear_all_alarms=0x1; 	Address(0x128[7:0])
SPIWrite 0128,00,0,7	//clear_all_alarms=0x0; 	Address(0x128[7:0])
SPIWrite 0128,04,0,7	//clear_all_alarms_to_pap=0x1; 	Address(0x128[7:2])
SPIWrite 0128,00,0,7	//clear_all_alarms_to_pap=0x0; 	Address(0x128[7:2])
SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])

//STEP: postLinkUp/step0 

//START: Writing Post Link up SERDES writes

SPIWrite 0016,60,0,7	//serdes_jesd=0x3; 	Address(0x16[7:5])
SPIWrite 0016,20,0,7	//serdes_jesd=0x1; 	Address(0x16[7:5])
SPIWrite 0016,60,0,7	//serdes_jesd=0x3; 	Address(0x16[7:5])
SPIWrite 41fb,02,0,7
SPIWrite 41fa,46,0,7
SPIWrite 43fb,02,0,7
SPIWrite 43fa,46,0,7
SPIWrite 45fb,02,0,7
SPIWrite 45fa,46,0,7
SPIWrite 47fb,02,0,7
SPIWrite 47fa,46,0,7

//END: Done writing Post Link up SERDES writes

SPIWrite 0016,00,0,7	//serdes_jesd=0x0; 	Address(0x16[7:5])
SPIWrite 0013,0f,0,7	//txdh=0xf; 	Address(0x13[7:0])
SPIWrite 015a,24,0,7	//Property_138h_17_17=0x0; 	Address(0x15a[7:1])
SPIWrite 0013,00,0,7	//txdh=0x0; 	Address(0x13[7:0])

//STEP: postLinkUp/step1 

//START: Removing TDD Pin Overrides.

SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 00ed,00,0,7	//Property_cch_11_8=0x0; 	Address(0xed[7:0])
SPIWrite 00f5,00,0,7	//Property_d4h_9_8=0x0; 	Address(0xf5[7:0])
SPIWrite 00e5,0f,0,7	//Property_c4h_11_8=0xf; 	Address(0xe5[7:0])

//END: Removing TDD Pin Overrides.

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0xf; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 00a7,00,0,7	//MACRO_OPERAND_REG1=0x1; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,00,0,7
SPIWrite 00a5,00,0,7
SPIWrite 00a4,01,0,7
SPIWrite 0193,52,0,7	//MACRO_OPCODE=0x52; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x30f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,03,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,53,0,7	//MACRO_OPCODE=0x53; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0019,f0,0,7	//txdig=0xf; 	Address(0x19[7:4])
SPIWrite 0320,00,0,7	//Property_300h_3_0=0x0; 	Address(0x320[7:0])
SPIWrite 0019,00,0,7	//txdig=0x0; 	Address(0x19[7:4])

//START: Removing TDD Pin Overrides.

SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 00ed,0f,0,7	//Property_cch_11_8=0xf; 	Address(0xed[7:0])
SPIWrite 00f5,00,0,7	//Property_d4h_9_8=0x0; 	Address(0xf5[7:0])
SPIWrite 00e5,00,0,7	//Property_c4h_11_8=0x0; 	Address(0xe5[7:0])

//END: Removing TDD Pin Overrides.

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0010,0f,0,7	//ec_dig=0xf; 	Address(0x10[7:0])
SPIWrite 003c,01,0,7	//Property_3ch_0_0=0x1; 	Address(0x3c[7:0])
SPIWrite 003c,00,0,7	//Property_3ch_0_0=0x0; 	Address(0x3c[7:0])
SPIWrite 0010,00,0,7	//ec_dig=0x0; 	Address(0x10[7:0])

//START: Removing TDD Pin Overrides.

SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 00ed,00,0,7	//Property_cch_11_8=0x0; 	Address(0xed[7:0])
SPIWrite 00f5,03,0,7	//Property_d4h_9_8=0x3; 	Address(0xf5[7:0])
SPIWrite 00e5,00,0,7	//Property_c4h_11_8=0x0; 	Address(0xe5[7:0])

//END: Removing TDD Pin Overrides.

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0010,30,0,7	//ec_dig=0x30; 	Address(0x10[7:0])
SPIWrite 003c,01,0,7	//Property_3ch_0_0=0x1; 	Address(0x3c[7:0])
SPIWrite 003c,00,0,7	//Property_3ch_0_0=0x0; 	Address(0x3c[7:0])
SPIWrite 0010,00,0,7	//ec_dig=0x0; 	Address(0x10[7:0])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x0; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,90,0,7	//MACRO_OPCODE=0x90; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0144,08,0,7	//Property_124h_4_2=0x2; 	Address(0x144[7:2])
SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0018,08,0,7	//Property_18h_3_3=0x1; 	Address(0x18[7:3])
SPIWrite 1f8f,05,0,7
SPIWrite 0018,00,0,7	//Property_18h_3_3=0x0; 	Address(0x18[7:3])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,90,0,7	//MACRO_OPCODE=0x90; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,01,0,7	//MACRO_OPERAND_REG0=0x101000f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,01,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,9f,0,7	//MACRO_OPCODE=0x9f; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0xb000f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,0b,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,49,0,7	//MACRO_OPCODE=0x49; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x1000f; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,01,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,0f,0,7
SPIWrite 0193,4b,0,7	//MACRO_OPCODE=0x4b; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0xff; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,ff,0,7
SPIWrite 00a7,00,0,7	//MACRO_OPERAND_REG1=0x0; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,00,0,7
SPIWrite 00a5,00,0,7
SPIWrite 00a4,00,0,7
SPIWrite 0193,13,0,7	//MACRO_OPCODE=0x13; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.3
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x0; 	Address(0xf0[7:2])

SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0018,00,5,5	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0012,01,0,3	//rxdig=0x1; 	Address(0x12[7:0])
SPIWrite 14c4,00,0,0	//dc_corr_fw_pause=0x0; 	Address(0x14c4[7:0])
SPIWrite 0012,02,0,3	//rxdig=0x2; 	Address(0x12[7:0])
SPIWrite 14c4,00,0,0	//dc_corr_fw_pause=0x0; 	Address(0x14c4[7:0])
SPIWrite 0012,04,0,3	//rxdig=0x4; 	Address(0x12[7:0])
SPIWrite 14c4,00,0,0	//dc_corr_fw_pause=0x0; 	Address(0x14c4[7:0])
SPIWrite 0012,08,0,3	//rxdig=0x8; 	Address(0x12[7:0])
SPIWrite 14c4,00,0,0	//dc_corr_fw_pause=0x0; 	Address(0x14c4[7:0])
SPIWrite 0012,00,0,3	//rxdig=0x0; 	Address(0x12[7:0])
SPIWrite 0012,10,4,5	//fbdig=0x1; 	Address(0x12[7:4])
SPIWrite 14c4,00,0,0	//dc_corr_fw_pause=0x0; 	Address(0x14c4[7:0])
SPIWrite 0012,20,4,5	//fbdig=0x2; 	Address(0x12[7:4])
SPIWrite 14c4,00,0,0	//dc_corr_fw_pause=0x0; 	Address(0x14c4[7:0])
SPIWrite 0012,00,0,7	//fbdig=0x0; 	Address(0x12[7:4])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 0193,3d,0,7	//MACRO_OPCODE=0x3d; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//START: Removing TDD Pin Overrides.

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])
SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 00ed,00,0,7	//Property_cch_11_8=0x0; 	Address(0xed[7:0])
SPIWrite 00f5,03,0,7	//Property_d4h_9_8=0x3; 	Address(0xf5[7:0])
SPIWrite 00e5,00,0,7	//Property_c4h_11_8=0x0; 	Address(0xe5[7:0])

//END: Removing TDD Pin Overrides.


//START: Removing TDD Pin Overrides.

SPIWrite 00ed,0f,0,7	//Property_cch_11_8=0xf; 	Address(0xed[7:0])
SPIWrite 00f5,00,0,7	//Property_d4h_9_8=0x0; 	Address(0xf5[7:0])
SPIWrite 00e5,00,0,7	//Property_c4h_11_8=0x0; 	Address(0xe5[7:0])

//END: Removing TDD Pin Overrides.


//START: Removing TDD Pin Overrides.

SPIWrite 00ec,00,0,7	//Property_cch_0_0=0x0; 	Address(0xec[7:0])
SPIWrite 00f4,00,0,7	//Property_d4h_0_0=0x0; 	Address(0xf4[7:0])
SPIWrite 00e4,00,0,7	//Property_c4h_0_0=0x0; 	Address(0xe4[7:0])

//END: Removing TDD Pin Overrides.

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[7:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7	//MACRO_OPERAND_REG0=0x0; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,00,0,7
SPIWrite 0193,15,0,7	//MACRO_OPCODE=0x15; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[7:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[7:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[7:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[7:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])

SPIWrite 0018,00,0,7	//macro=0x0; 	Address(0x18[7:5])

//STEP: postLinkUp/step2 
SPIWrite 0016,03,0,7	//adc_jesd=0x3; 	Address(0x16[7:0])
SPIWrite 0024,00,0,7	//jesd_clear_data=0x0; 	Address(0x24[7:0])
SPIWrite 00f0,0f,0,7	//alarms_serdes_fifo_errors_clear=0xf; 	Address(0xf0[7:0])
SPIWrite 00f0,00,0,7	//alarms_serdes_fifo_errors_clear=0x0; 	Address(0xf0[7:0])
SPIWrite 0016,00,0,7	//adc_jesd=0x0; 	Address(0x16[7:0])
SPIWrite 0016,0c,0,7	//dac_jesd=0x3; 	Address(0x16[7:2])
SPIWrite 0064,01,0,7	//jesd_clear_data=0x0; 	Address(0x64[7:4])
SPIWrite 0128,01,0,7	//clear_all_alarms=0x1; 	Address(0x128[7:0])
SPIWrite 0128,00,0,7	//clear_all_alarms=0x0; 	Address(0x128[7:0])
SPIWrite 0128,04,0,7	//clear_all_alarms_to_pap=0x1; 	Address(0x128[7:2])
SPIWrite 0128,00,0,7	//clear_all_alarms_to_pap=0x0; 	Address(0x128[7:2])
SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])
SPIWrite 0019,f0,0,7	//txdig=0xf; 	Address(0x19[7:4])
SPIWrite 0a40,0f,0,7	//HBF59OvrClr=0xf; 	Address(0xa40[7:0])
SPIWrite 0a41,0f,0,7	//HBF23HROvrClr=0xf; 	Address(0xa41[7:0])
SPIWrite 0a44,0f,0,7	//mixerOvrClr=0xf; 	Address(0xa44[7:0])
SPIWrite 0a45,0f,0,7	//isincOvrClr=0xf; 	Address(0xa45[7:0])
SPIWrite 0a46,0f,0,7	//dacDitherOvrClr=0xf; 	Address(0xa46[7:0])
SPIWrite 0a40,00,0,7	//HBF59OvrClr=0x0; 	Address(0xa40[7:0])
SPIWrite 0a41,00,0,7	//HBF23HROvrClr=0x0; 	Address(0xa41[7:0])
SPIWrite 0a44,00,0,7	//mixerOvrClr=0x0; 	Address(0xa44[7:0])
SPIWrite 0a45,00,0,7	//isincOvrClr=0x0; 	Address(0xa45[7:0])
SPIWrite 0a46,00,0,7	//dacDitherOvrClr=0x0; 	Address(0xa46[7:0])
SPIWrite 054d,07,0,7	//Property_52ch_10_0=0x7ff; 	Address(0x54c[2:0],0x54d[7:0])
SPIWrite 054c,ff,0,7
SPIWrite 0580,07,0,7	//Property_560h_2_0=0x7; 	Address(0x580[7:0])
SPIWrite 0589,07,0,7	//Property_568h_10_8=0x7; 	Address(0x589[7:0])
SPIWrite 06b4,01,0,7	//pap_hw_alarm_act_alc_clr=0x1; 	Address(0x6b4[7:0])
SPIWrite 06b4,03,0,7	//pap_hw_alarm_act_lmt_clr=0x1; 	Address(0x6b4[7:1])
SPIWrite 054d,00,0,7	//Property_52ch_10_0=0x0; 	Address(0x54c[2:0],0x54d[7:0])
SPIWrite 054c,00,0,7
SPIWrite 0580,00,0,7	//Property_560h_2_0=0x0; 	Address(0x580[7:0])
SPIWrite 0589,00,0,7	//Property_568h_10_8=0x0; 	Address(0x589[7:0])
SPIWrite 06b4,02,0,7	//pap_hw_alarm_act_alc_clr=0x0; 	Address(0x6b4[7:0])
SPIWrite 06b4,00,0,7	//pap_hw_alarm_act_lmt_clr=0x0; 	Address(0x6b4[7:1])
SPIWrite 052c,1f,0,7	//Property_50ch_4_0=0x1f; 	Address(0x52c[7:0])
SPIWrite 052c,00,0,7	//Property_50ch_4_0=0x0; 	Address(0x52c[7:0])
SPIWrite 0019,00,0,7	//txdig=0x0; 	Address(0x19[7:4])

//STEP: dlJesdLinkupCheck/step0 

//START: Reading the JESD RX states to check if link is established


WAIT 0.001
SPIWrite 0016,04,0,7	//dac_jesd=0x1; 	Address(0x16[7:2])
SPIReadCheck 011b,0,7,00
SPIReadCheck 011a,0,7,00
SPIReadCheck 0119,0,7,00
SPIReadCheck 0118,0,7,00
SPIReadCheck 011f,0,7,00
SPIReadCheck 011e,0,7,00
SPIReadCheck 011d,0,7,00
SPIReadCheck 011c,0,7,00

//Read	alarms=0x0; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0],0x11b[7:0],0x11c[7:0],0x11c[7:0],0x11d[7:0],0x11e[7:0],0x11f[7:0],0x120[7:0])

SPIReadCheck 00ee,0,3,01

//Read	comma_align_lock_flag=0x1; 	Address(0xee[7:0])

SPIReadCheck 00a2,0,7,02

//Read	jesd_cs_state=0x2; 	Address(0xa2[7:0],0xa3[7:0])

SPIReadCheck 00a4,0,7,01

//Read	jesd_fs_state=0x1; 	Address(0xa4[7:0],0xa5[7:0])


//END: Done reading the JESD RX states to check if link is established


//START: Reading the JESD RX states to check if link is established


WAIT 0.001
SPIWrite 0016,08,0,7	//dac_jesd=0x2; 	Address(0x16[7:2])
SPIReadCheck 011b,0,7,00
SPIReadCheck 011a,0,7,00
SPIReadCheck 0119,0,7,00
SPIReadCheck 0118,0,7,00
SPIReadCheck 011f,0,7,00
SPIReadCheck 011e,0,7,00
SPIReadCheck 011d,0,7,00
SPIReadCheck 011c,0,7,00

//Read	alarms=0x0; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0],0x11b[7:0],0x11c[7:0],0x11c[7:0],0x11d[7:0],0x11e[7:0],0x11f[7:0],0x120[7:0])

SPIReadCheck 00ee,0,3,01

//Read	comma_align_lock_flag=0x1; 	Address(0xee[7:0])

SPIReadCheck 00a2,0,7,02

//Read	jesd_cs_state=0x2; 	Address(0xa2[7:0],0xa3[7:0])

SPIReadCheck 00a4,0,7,01

//Read	jesd_fs_state=0x1; 	Address(0xa4[7:0],0xa5[7:0])


//END: Done reading the JESD RX states to check if link is established

SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])

//END: Device Config Complete


//START: Setting TDD Pin in override state and setting override values.

SPIWrite 0015,80,0,7	//timing_controller=0x1; 	Address(0x15[7:7])
SPIWrite 00ec,01,0,7	//Property_cch_0_0=0x1; 	Address(0xec[7:0])
SPIWrite 00f4,01,0,7	//Property_d4h_0_0=0x1; 	Address(0xf4[7:0])
SPIWrite 00e4,01,0,7	//Property_c4h_0_0=0x1; 	Address(0xe4[7:0])
SPIWrite 00ed,0f,0,7	//Property_cch_11_8=0xf; 	Address(0xed[7:0])
SPIWrite 00f5,03,0,7	//Property_d4h_9_8=0x3; 	Address(0xf5[7:0])
SPIWrite 00e5,0f,0,7	//Property_c4h_11_8=0xf; 	Address(0xe5[7:0])

//END: Setting TDD Pin in override state and setting override values.


//START: Setting TDD Pin in override state and setting override values.

SPIWrite 00ec,01,0,7	//Property_cch_0_0=0x1; 	Address(0xec[7:0])
SPIWrite 00f4,01,0,7	//Property_d4h_0_0=0x1; 	Address(0xf4[7:0])
SPIWrite 00e4,01,0,7	//Property_c4h_0_0=0x1; 	Address(0xe4[7:0])
SPIWrite 00ed,0f,0,7	//Property_cch_11_8=0xf; 	Address(0xed[7:0])
SPIWrite 00f5,03,0,7	//Property_d4h_9_8=0x3; 	Address(0xf5[7:0])
SPIWrite 00e5,00,0,7	//Property_c4h_11_8=0x0; 	Address(0xe5[7:0])

//END: Setting TDD Pin in override state and setting override values.