// The following parameter defines if the 
// IP is in 8b/10b mode or 64b/66b mode
// Leave the second line commented if it is
// in 64b/66b, else uncomment it to enable 8b/10b
`undef IP_8B10B
`undef IP_64B66B
//`define IP_8B10B
`define IP_64B66B

`undef IP_TYPE
`define IP_TYPE "RXTX"

`undef ADC_RESOLUTION
`define ADC_RESOLUTION 16

`undef DAC_RESOLUTION
`define DAC_RESOLUTION 16
/////////////////////////////////////////////////
// The following parameters configure the JESD IP
// to interact with the transceiver created using
// the Vivado Transceiver wizard.
// Please ensure that the settings/parameters match
// that of the transceiver
/////////////////////////////////////////////////

// Set the number of lanes in the link
// This is equal to the number of lanes/channels
// in the transceiver IP
`undef NUMBER_OF_RX_LANES
`undef NUMBER_OF_TX_LANES

`define NUMBER_OF_RX_LANES 8
`define NUMBER_OF_TX_LANES 8

// Set the number of quads used in the transceiver
// IP. This is based on the transceiver Quad/Lane
// mapping. In this case, the 8 lanes are spread over
// 2 Quads
`undef NUMBER_OF_QUADS
`define NUMBER_OF_QUADS 2

// Select the type of Transceiver used in the IP
// Options are: GTH, GTP, GTX and GTY. Refer to
// the IP user guide for more details
// GTH : Ultrascale GTH
// GTHP : Ultrascale+ GTH
// GTY : Ultrascale GTY
// GTYP : Ultrascale+ GTY
// GTX : GTX in Zynq/Virtex/Kintex 7000 series
// GTP : GTP in Artix 7000 series
`undef MGT_TYPE
`define MGT_TYPE "GTHP"

// Set the number of Reference Clock
// Buffers used by the Transceiver
// In most cases, there is one clock per
// link, and the clock is internally routed
// to the individual Quad/Channel clocking logic
`undef NUMBER_OF_REFCLK_BUFFERS
`define NUMBER_OF_REFCLK_BUFFERS 1

// The following parameter controls the mapping
// of the ADC lanes to the transceiver lanes
// This helps account for any lane mapping mismatches
// on account of the board routing
// This parameter is from the perspective of the ADC
// and is ordered as {LANE_N,...,LANE2,LANE1,LANE0}
// For example a value of {3,1,0,2} will mean the 
// following:
//   1> Lane 0 of ADC is mapped to Lane 2 of the transceiver
//   2> Lane 1 of ADC is mapped to Lane 0 of the transceiver
//   3> Lane 2 of ADC is mapped to Lane 1 of the transceiver
//   4> Lane 3 of ADC is mapped to Lane 3 of the transceiver
// NOTE: Ensure that the parameter below has as many bits
// as the number of lanes on the transceiver
`undef LANE_ADC_TO_GT_MAP
`define LANE_ADC_TO_GT_MAP {3'd7,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0}

`undef LANE_DAC_TO_GT_MAP
`define LANE_DAC_TO_GT_MAP {3'd7,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0}

// The following parameter controls the polarity
// of the transceiver lanes. If the P and N differential
// pins are inverted between the transmitter and receiver,
// set the corresponding bit to '1'. If there is no inversion
// set the corresponding bit to 0.
// This parameter is from the perspective of the ADC
// and is ordered as {LANE_N,...,LANE2,LANE1,LANE0}
// NOTE: Ensure that the parameter below has as many bits
// as the number of lanes on the transceiver
`undef RX_LANE_POLARITY
`define RX_LANE_POLARITY 8'b00000000

`undef TX_LANE_POLARITY
`define TX_LANE_POLARITY 8'b00000000

// Set the width of the final lane data bus exported
// by each lane of the Rx IP.
`undef RX_LANE_DATA_WIDTH
`define RX_LANE_DATA_WIDTH 64

// Set the width of the final lane data bus exported
// by each lane of the Tx IP.
`undef TX_LANE_DATA_WIDTH
`define TX_LANE_DATA_WIDTH 64

// End of parameters related to the transceiver
//////////////////////////////////////////////

//////////////////////////////////////////////
// The rest of the parameters configure the IP
// for the correct operation of the 8b/10b data
// link protocol
// PLEASE NOTE: The parameters MUST be set based
// on those of the transmitting device, without
// which the link will not work or may display
// intermittent failures
//////////////////////////////////////////////

///////////////////////////////////////////////////////////
// Parameters related to 8b/10b encoding
// These parameters are ignored if 8b/10b is chosen

// The following parameter sets the value
// of the F (octets per frame) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
`undef RX_F_VAL
`define RX_F_VAL 2

`undef TX_F_VAL
`define TX_F_VAL 2

// The following parameter sets the value
// of the K (frames per multiframe) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
`undef RX_K_VAL
`define RX_K_VAL 32

`undef TX_K_VAL
`define TX_K_VAL 32

// End of parameters related to 8b/10b 
///////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////
// Parameter related to 64b/66b Encoding
// The following parameter sets the value
// of the E (multiblocks per extended multiblock) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
// This parameter is ignored if 8b/10b is chosen
`undef RX_E_VAL
`define RX_E_VAL 3

`undef TX_E_VAL
`define TX_E_VAL 3
///////////////////////////////////////////////////////////

`undef RBD_COUNT_WIDTH
`define RBD_COUNT_WIDTH 10

// End of parameters related to deterministic latency
///////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////
// The following parameters are for the RX and TX BUFFERs
///////////////////////////////////////////////////////////
`undef RX_BUFFER
`define RX_BUFFER "NORM"

`undef BUFFER_RATIO
`define BUFFER_RATIO 1

`undef TX_BUFFER
`define TX_BUFFER "NORM"

///////////////////////////////////////////////////////////
// Define if the Clock Chip is emulated on the FPGA
///////////////////////////////////////////////////////////
`undef SYSREF_GEN
`define SYSREF_GEN

`undef SYSREF_TARGET_COUNT
`define SYSREF_TARGET_COUNT 96