#======
#Executing .. AFE79xx/bringup/setup.py
#Start Time 2022-08-09 17:27:56.355000 
AFE79xxLibraryPG1p0
spi - USB Instrument created.
resetDevice
Purge
MPSSE mode set
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
#Done executing .. AFE79xx/bringup/setup.py
#End Time 2022-08-09 17:28:03.402000
#Execution Time = 7.04699993134 s 
#================ ERRORS:0, WARNINGS:0 ================#
#======
#Executing .. AFE79xx/bringup/devInit.py
#Start Time 2022-08-09 17:28:11.648000 
Power Card - USB Instrument created.
Reset the FPGA and try again.
Loaded Libraries
#Done executing .. AFE79xx/bringup/devInit.py
#End Time 2022-08-09 17:28:37.593000
#Execution Time = 25.9449999332 s 
#================ ERRORS:1, WARNINGS:0 ================#
#======
#Executing .. AFE79xx/bringup/AFE79xx_EVM_Mode2.py
#Start Time 2022-08-09 17:28:59.159000 
The External Sysref Frequency should be an integer factor of: 3.84MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 9830.4
laneRateFb: 9830.4
laneRateTx: 9830.4
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 9830.4
laneRateFb: 9830.4
laneRateTx: 9830.4
Device Initialization for ChipVersion: 2.0
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x20
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Fuse farm load autoload done successful
No autload error
Waiting for MACRO_DONE bit to go high, Count: 1
Waiting for MACRO_DONE bit to go high, Count: 2
Waiting for MACRO_DONE bit to go high failed
Execution stopped
#Done executing .. AFE79xx/bringup/AFE79xx_EVM_Mode2.py
# End Time 2022-08-09 17:29:50.503000
# Execution Time = 51.3440001011 s 
#=======================================