// This reference design implements a
// TX/RX link of parameters LMFS = 4841
// L (number of lanes) = 4
// M (number of converters) = 8
// F (octets per frame) = 4
// S (samples per converter per frame) = 1

// Encoding protocol = 8b/10b
// K (frames per multi-frame) = 16

`default_nettype none
`timescale 1ps/1ps

`include "jesd_link_params.vh"

module TI_204c_IP_ref
#(
	parameter NUM_REFCLK_BUFFERS = `NUMBER_OF_REFCLK_BUFFERS,
	parameter NUM_RX_LANES = `NUMBER_OF_RX_LANES,
	parameter NUM_TX_LANES = `NUMBER_OF_TX_LANES
)
(
	// Signals related to the clock chip
	// Implemented if the FPGA is emulating the
	// clock chip (used with loopback cards)
	//`ifdef SYSREF_GEN
	//output wire	cc_sysref_out_p,
	//output wire	cc_sysref_out_n,
	//`endif

	// Signals related to the JESD IPs
	input wire	sys_clk_p,
	input wire	sys_clk_n,

	// Reference clock for the FPGA transceivers
	input wire	[NUM_REFCLK_BUFFERS-1:0] refclk_p,
	input wire	[NUM_REFCLK_BUFFERS-1:0] refclk_n,
	
	// Sysref for the JESD IP
	input wire	sysref_p,
	input wire	sysref_n,
	
	// SYNCn signals for 8b/10b link
	// initialization
	// These are defined only in 8b/10b mode
	`ifdef IP_8B10B
	output wire	adc_rx_sync_n,
	input wire	dac_tx_sync_n,
	`endif

	input wire	[NUM_RX_LANES-1:0] adc_lane_rxp,
	input wire	[NUM_RX_LANES-1:0] adc_lane_rxn,
	output wire	[NUM_TX_LANES-1:0] dac_lane_txp,
	output wire	[NUM_TX_LANES-1:0] dac_lane_txn
);

localparam IP_TYPE = `IP_TYPE;

`ifdef IP_8B10B
  localparam IP_PROTOCOL = 810;
`elsif IP_64B66B
  localparam IP_PROTOCOL = 6466;
`endif


// Resolutions of the converter
localparam ADC_RES = `ADC_RESOLUTION;
localparam DAC_RES = `DAC_RESOLUTION;

`ifdef IP_8B10B
// 8B/10B protocol related parameters
// for receiver
// Note: The value of F*K must be equal to or 
// an integral multiple of GT_RX_DATA_WIDTH
localparam PARAM_RX_F = `RX_F_VAL;
localparam PARAM_RX_K = `RX_K_VAL;
localparam PARAM_RX_HD = 0;

// 8B/10B protocol related PARAMeters
// for transmitter. These are left at default
// values if the IP is in 64b/66b mode
localparam PARAM_TX_N = `DAC_RESOLUTION;
localparam PARAM_TX_NPR = `DAC_RESOLUTION;
localparam PARAM_TX_CS = 0;
localparam PARAM_TX_F = `TX_F_VAL;
localparam PARAM_TX_K = `TX_K_VAL;
localparam PARAM_TX_DEVID = 0;
localparam PARAM_TX_BANKID = 0;
localparam PARAM_TX_HD = 0;
localparam PARAM_TX_M = 4;
localparam PARAM_TX_S = 1;
`endif

`ifdef IP_64B66B
// 64b/66b protocol related parameters
// for receiver
localparam PARAM_RX_E = `RX_E_VAL;

// 64b/66b protocol related parameters
// for transmitter
localparam PARAM_TX_E = `TX_E_VAL;
`endif

// MGT Transcevier related parameters
localparam GT_TYPE = `MGT_TYPE;
localparam NUM_QUADS = `NUMBER_OF_QUADS;

// Infer the lane index width from the number of lanes
localparam RX_LN_IDX_WIDTH = 
  (NUM_RX_LANES <= 2)? 1 :
  (NUM_RX_LANES <= 4)? 2 :
  (NUM_RX_LANES <= 8)? 3 :
  4;

localparam RX_LN_DATA_WIDTH = `RX_LANE_DATA_WIDTH;

localparam TX_LN_IDX_WIDTH = 
  (NUM_TX_LANES <= 2)? 1 :
  (NUM_TX_LANES <= 4)? 2 :
  (NUM_TX_LANES <= 8)? 3 :
  4;

localparam TX_LN_DATA_WIDTH = `TX_LANE_DATA_WIDTH;

localparam GT_USERIO_IN_WIDTH = 16;
localparam GT_USERIO_OUT_WIDTH = 16;

// Deterministic latency related parameters
// These are left at default (auto-computed by
// the RX IP)
localparam RX_RBD_COUNT_WIDTH = 10;
/*
localparam RX_SYSREF_OFFSET = 0;
localparam TX_SYSREF_OFFSET = 0;
localparam RX_LMFC_TARGET_COUNT = `LMFC_COUNT_VAL;
localparam RX_LEMC_TARGET_COUNT = `LEMC_COUNT_VAL;
*/

// Rx/Tx Buffer type control
localparam RX_BUFFER_TYPE = `RX_BUFFER;
localparam TX_BUFFER_TYPE = `TX_BUFFER;
localparam RX_BUFFER_RATIO = `BUFFER_RATIO;

///////////////////////////////////////
// Common reset and MGT related ports for the IP
////////////////////////////////////////////
// Async master reset
wire	master_reset_n;

// Free running clock required by the transceiver
wire	mgt_freerun_clock;

// Pad inputs for the Transceiver reference clock
wire	[NUM_REFCLK_BUFFERS-1:0] mgt_refclk_p;
wire	[NUM_REFCLK_BUFFERS-1:0] mgt_refclk_n;

// User GP input to the transceiver
wire	[GT_USERIO_IN_WIDTH-1:0] mgt_gpio_in;
// User GP output from the transceiver
wire	[GT_USERIO_OUT_WIDTH-1:0] mgt_gpio_out;

// PLL locked status signals
wire	[NUM_QUADS-1:0] qpll0_locked;
wire	[NUM_QUADS-1:0] qpll1_locked;
wire	[NUM_QUADS-1:0] cpll_locked;

////////////////////////////////////////////
// Primary Receiver related ports. These are
// independent of the 8B10b / 64B66B protocol
////////////////////////////////////////////

// Pad inputs for the Transceiver Rx lanes
wire	[NUM_RX_LANES-1:0] mgt_lane_rxp;
wire	[NUM_RX_LANES-1:0] mgt_lane_rxn;
wire	[NUM_RX_LANES-1:0] cfg_rx_lane_polarity;

// RXUSRCLK2 extracted by the transceiver
(* dont_touch = "TRUE" *) wire	mgt_rx_usrclk2;

// Lane Mapping between ADC and Transceiver
// Note: This is defined with respect to the 
// ADC lanes
wire	[RX_LN_IDX_WIDTH-1:0] cfg_rx_lane_map [NUM_RX_LANES-1:0]; 

// Application/System Clock for the Rx
wire	rx_sys_clock;

// Application/System Synchronous Reset for the Rx
wire	rx_sync_reset;

// lane enable signals (usually tied to all 1's; 
// but can be used for individual lane checks)
wire	[NUM_RX_LANES-1:0] cfg_rx_lane_enable;

wire rx_all_lanes_locked;
wire rx_release_all_lanes;

// Lane data outputs. There is one output data
// bus per lane
wire	[RX_LN_DATA_WIDTH-1:0] rx_lane_data [NUM_RX_LANES-1:0];

// Data valid signal. This applies simultaneously
// to all lanes
wire	rx_lane_data_valid;

// Rx Lane Buffer overflow indicator
wire	[NUM_RX_LANES-1:0] rx_lane_buffer_overflow;

// The following are the lane sideband signals
// in 8B/10B mode

// SYNCn signal
wire	rx_sync_n;
// Control signal for RX de-scrambling.
wire	cfg_rx_scrambling_enabled;

wire	[111:0] rx_lane_configuration_data [NUM_RX_LANES-1:0];
wire	[RX_LN_DATA_WIDTH/8-1:0] rx_lane_start_of_frame [NUM_RX_LANES-1:0];
wire	[RX_LN_DATA_WIDTH/8-1:0] rx_lane_start_of_multiframe [NUM_RX_LANES-1:0];

// The following are the lane sideband signals
// in 64b/66b mode

wire	[NUM_RX_LANES-1:0] rx_lane_start_of_mblock;
wire	[NUM_RX_LANES-1:0] rx_lane_start_of_emblock;
wire	[NUM_RX_LANES-1:0] rx_lane_crc_error;

// This is the master clear signal for all
// the error counts exported by the IP
wire	[NUM_RX_LANES-1:0] rx_clr_all_err_count;

// The following signals are the error related
// counts for the 8b/10b protocol
wire	[3:0] rx_lane_invalid_somf_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_somf_err_count;
wire	[3:0] rx_lane_invalid_eomf_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_eomf_err_count;
wire	[3:0] rx_lane_invalid_eof_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_eof_err_count;
wire	[3:0] rx_lane_notintable_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_notintable_err_count;
wire	[3:0] rx_lane_disp_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_disp_err_count;

// The following signals are the error related
// counts for the 64b/66b protocol
wire	[3:0] rx_lane_invalid_header_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_header_err_count;
wire	[3:0] rx_lane_invalid_eomb_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_eomb_err_count;
wire	[3:0] rx_lane_invalid_eoemb_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_eoemb_err_count;
wire	[3:0] rx_lane_crc_mismatch_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_crc_mismatch_err_count;

// Rx Sysref control and status signals
wire	rx_sysref;
wire	[3:0] rx_sysref_realign_count;
wire	rx_clr_sysref_realign_count;
wire	rx_lmfc_pulse;
wire	rx_lemc_pulse;

wire	cfg_rx_det_latency_en;
wire	[RX_RBD_COUNT_WIDTH-1:0] cfg_rx_buffer_release_delay;
wire	[RX_RBD_COUNT_WIDTH-1:0] rx_lmfc_to_buffer_release_delay;
wire	[RX_RBD_COUNT_WIDTH-1:0] rx_lemc_to_buffer_release_delay;

////////////////////////////////////////////
// Primary Transmitter related ports. These are
// independent of the 8B10b / 64B66B protocol
////////////////////////////////////////////

// Pad inputs for the Transceiver Rx lanes
wire	[NUM_TX_LANES-1:0] mgt_lane_txp;
wire	[NUM_TX_LANES-1:0] mgt_lane_txn;
wire	[NUM_TX_LANES-1:0] cfg_tx_lane_polarity;

// TXUSRCLK2 extracted by the transceiver
wire	mgt_tx_usrclk2;

// Lane Mapping between ADC and Transceiver
// Note: This is defined with respect to the 
// ADC lanes
wire	[TX_LN_IDX_WIDTH-1:0] cfg_tx_lane_map [NUM_TX_LANES-1:0]; 

// Application/System Clock for the Rx
wire	tx_sys_clock;

// Application/System Synchronous Reset for the Rx
wire	tx_sync_reset;

// lane enable signals (usually tied to all 1's; 
// but can be used for individual lane checks)
wire	[NUM_TX_LANES-1:0] cfg_tx_lane_enable;

// Lane data inputs. There is one input data
// bus per lane
wire	[TX_LN_DATA_WIDTH-1:0] tx_lane_data [NUM_TX_LANES-1:0];

// Data ready signal. This applies simultaneously
// to all lanes
wire	tx_lane_data_ready;

// The following are the lane sideband signals
// in 8B/10B mode

// SYNCn signal
wire	tx_sync_n;

// Control signal for TX scrambling.
wire	cfg_tx_scrambling_enabled;

// Control signal for forcing Tx to ILAS mode
wire	cfg_tx_ilas_test_mode;

wire	[TX_LN_DATA_WIDTH/8-1:0] tx_lane_start_of_frame;
wire	[TX_LN_DATA_WIDTH/8-1:0] tx_lane_start_of_multiframe;

// The following are the lane sideband signals
// in 64b/66b mode

wire	tx_lane_start_of_mblock;
wire	tx_lane_start_of_emblock;

// Rx Sysref control and status signals
wire	tx_sysref;
wire	tx_lmfc_pulse;
wire	tx_lemc_pulse;

wire	[3:0] tx_sysref_realign_count;
wire	tx_clr_sysref_realign_count;

wire	[255:0] testport1_in;
wire	[255:0] testport1_out;
wire	[255:0] testport2_in;
wire	[255:0] testport2_out;
wire	[1049:0] testport3_in;
wire	[1049:0] testport3_out;

////////////////////////////////////////////////////
// System PLL for generating the free-run clock
// This also generates the sys_clock for the Rx
// and Tx IPs
////////////////////////////////////////////////////

wire sys_clock;

sys_pll pll_inst (
    .clk_in1_p (sys_clk_p),
    .clk_in1_n (sys_clk_n),
    .locked (),
    .reset (0),
    .sys_clk (sys_clock),
    .freerun_clk (mgt_freerun_clock));

/////////////////////////////////////////////
// IP related wire assignments
/////////////////////////////////////////////
assign rx_sys_clock = sys_clock;
assign tx_sys_clock = sys_clock;

assign mgt_refclk_p = refclk_p;
assign mgt_refclk_n = refclk_n;

//assign mgt_gpio_in[0] = rx_sync_reset;
//assign mgt_gpio_in[1] = tx_sync_reset;

//assign mgt_gpio_in[15:2] = 14'd0;
assign mgt_gpio_in = 16'd0;

assign mgt_lane_rxp = adc_lane_rxp;
assign mgt_lane_rxn = adc_lane_rxn;

assign cfg_rx_lane_polarity = `RX_LANE_POLARITY;

assign cfg_rx_lane_map = `LANE_ADC_TO_GT_MAP;

assign cfg_rx_lane_enable = {NUM_RX_LANES{1'b1}};
assign cfg_tx_lane_enable = {NUM_TX_LANES{1'b1}};

assign cfg_rx_scrambling_enabled = 1'b1;
assign cfg_tx_scrambling_enabled = 1'b1;

assign rx_release_all_lanes = 1'b1;

assign rx_clr_all_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_somf_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_eomf_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_eof_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_notintable_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_disp_err_count = {NUM_RX_LANES{1'b0}};

assign rx_lane_clr_invalid_header_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_eomb_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_eoemb_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_crc_mismatch_err_count = {NUM_RX_LANES{1'b0}};

// Derive sysref from top level

wire sysref;
IBUFDS sysref_ibuf (.I(sysref_p), .IB(sysref_n), .O(sysref));

assign rx_sysref = sysref;
assign tx_sysref = sysref;

// Enable deterministic latency
assign cfg_rx_det_latency_en = 1'b1;

assign rx_clr_sysref_realign_count = 1'b0;
assign tx_clr_sysref_realign_count = 1'b0;

assign dac_lane_txp = mgt_lane_txp;
assign dac_lane_txn = mgt_lane_txn;

assign cfg_tx_lane_polarity = `TX_LANE_POLARITY;
assign cfg_tx_lane_map = `LANE_DAC_TO_GT_MAP;

assign	cfg_tx_ilas_test_mode = 1'b0;

`ifdef IP_8B10B
assign adc_rx_sync_n = rx_sync_n;
assign tx_sync_n = dac_tx_sync_n;
`else
assign tx_sync_n = 1'b0;
`endif

assign testport1_in = 'd0;
assign testport2_in = 'd0;
assign testport3_in = 'd0;

/////////////////////////////////////////////
// Instantiate the IP
/////////////////////////////////////////////

TI_204c_IP
	#(
	// IP type and protocol
	// Allowed values are RX / TX / RXTX
	.IP_TYPE (IP_TYPE),
	.IP_PROTOCOL (IP_PROTOCOL),

	// Resolutions of the converter
	.ADC_RES (ADC_RES),
	.DAC_RES (DAC_RES),

	`ifdef IP_8B10B
	// 8B/10B protocol related parameters
	// for receiver
	// Note: The value of F*K must be equal to or 
	// an integral multiple of GT_RX_DATA_WIDTH
	.PARAM_RX_F (PARAM_RX_F),
	.PARAM_RX_K (PARAM_RX_K),
	.PARAM_RX_HD (PARAM_RX_HD),

	// 8B/10B protocol related PARAMeters
	// for transmitter
	.PARAM_TX_N (PARAM_TX_N),
	.PARAM_TX_NPR (PARAM_TX_NPR),
	.PARAM_TX_CS (PARAM_TX_CS),
	// Note: The value of F*K must be equal to or 
	// an integral multiple of GT_TX_DATA_WIDTH
	.PARAM_TX_F (PARAM_TX_F),
	.PARAM_TX_K (PARAM_TX_K),
	.PARAM_TX_DEVID (PARAM_TX_DEVID),
	.PARAM_TX_BANKID (PARAM_TX_BANKID),
	.PARAM_TX_HD (PARAM_TX_HD),
	.PARAM_TX_M (PARAM_TX_M),
	.PARAM_TX_S (PARAM_TX_S),
	`endif

	`ifdef IP_64B66B
	// 64b/66b protocol related parameters
	// for receiver
	.PARAM_RX_E (PARAM_RX_E),

	// 64b/66b protocol related parameters
	// for transmitter
	.PARAM_TX_E (PARAM_TX_E),
	`endif

	// MGT Transcevier related parameters
	.GT_TYPE (GT_TYPE),
	.NUM_REFCLK_BUFFERS (NUM_REFCLK_BUFFERS),
	.NUM_QUADS (NUM_QUADS),
	.NUM_RX_LANES (NUM_RX_LANES),
	.RX_LN_IDX_WIDTH (RX_LN_IDX_WIDTH),
	.RX_LN_DATA_WIDTH (RX_LN_DATA_WIDTH),
	.NUM_TX_LANES (NUM_TX_LANES),
	.TX_LN_IDX_WIDTH (TX_LN_IDX_WIDTH),
	.TX_LN_DATA_WIDTH (TX_LN_DATA_WIDTH),
	.GT_USERIO_IN_WIDTH (GT_USERIO_IN_WIDTH),
	.GT_USERIO_OUT_WIDTH (GT_USERIO_OUT_WIDTH),

	/*
	// Deterministic latency related parameters
	.RX_SYSREF_OFFSET (RX_SYSREF_OFFSET),
	.TX_SYSREF_OFFSET (TX_SYSREF_OFFSET),
	.RX_RBD_COUNT_WIDTH (RX_RBD_COUNT_WIDTH),
	.RX_LMFC_TARGET_COUNT (RX_LMFC_TARGET_COUNT),
	.RX_LEMC_TARGET_COUNT (RX_LEMC_TARGET_COUNT),
	*/

	// Rx/Tx Buffer type control
	.RX_BUFFER_TYPE (RX_BUFFER_TYPE),
	.TX_BUFFER_TYPE (TX_BUFFER_TYPE),
	.RX_BUFFER_RATIO (RX_BUFFER_RATIO)

	/*
	// Rx Transport layer related parameters
	.RX_TL_ENABLED (RX_TL_ENABLED),
	.TL_PARAM1 (TL_PARAM1),
	.TL_PARAM2 (TL_PARAM2),
	.TL_PARAM3 (TL_PARAM3),
	.SAMPLES_PER_CYCLE_PER_LANE (SAMPLES_PER_CYCLE_PER_LANE),
	.TL_TYPE (TL_TYPE)
	*/

)
TI_IP_inst	(
	////////////////////////////////////////////
	// Common reset and MGT related ports for the IP
	////////////////////////////////////////////
	// Async master reset
	.master_reset_n (master_reset_n),

	// Free running clock required by the transceiver
	.mgt_freerun_clock (mgt_freerun_clock),

	// Pad inputs for the Transceiver reference clock
	.mgt_refclk_p (mgt_refclk_p),
	.mgt_refclk_n (mgt_refclk_n),

	// User GP input to the transceiver
	.mgt_gpio_in (mgt_gpio_in),
	// User GP output from the transceiver
	.mgt_gpio_out (mgt_gpio_out),

	// PLL locked status signals
	.qpll0_locked (qpll0_locked),
	.qpll1_locked (qpll1_locked),
	.cpll_locked (cpll_locked),

	////////////////////////////////////////////
	// Primary Receiver related ports. These are
	// independent of the 8B10b / 64B66B protocol
	////////////////////////////////////////////

	// Pad inputs for the Transceiver Rx lanes
	.mgt_lane_rxp (mgt_lane_rxp),
	.mgt_lane_rxn (mgt_lane_rxn),
	.cfg_rx_lane_polarity (cfg_rx_lane_polarity),

	// RXUSRCLK2 extracted by the transceiver
	.mgt_rx_usrclk2 (mgt_rx_usrclk2),

	// Lane Mapping between ADC and Transceiver
	// Note: This is defined with respect to the 
	// ADC lanes
	.cfg_rx_lane_map (cfg_rx_lane_map), 

	// Application/System Clock for the Rx
	.rx_sys_clock (rx_sys_clock),

	// Application/System Synchronous Reset for the Rx
	.rx_sync_reset (rx_sync_reset),

	// lane enable signals (usually tied to all 1's, 
	// but can be used for individual lane checks)
	.cfg_rx_lane_enable (cfg_rx_lane_enable),

	// Lane release status and control
	.rx_all_lanes_locked (rx_all_lanes_locked),
	.rx_release_all_lanes (rx_release_all_lanes),

	// Lane data outputs. There is one output data
	// bus per lane
	.rx_lane_data (rx_lane_data),

	// Data valid signal. This applies simultaneously
	// to all lanes
	.rx_lane_data_valid (rx_lane_data_valid),

	// Rx Lane Buffer overflow indicator
	.rx_lane_buffer_overflow (rx_lane_buffer_overflow),

	// The following signals comprise the lane data
	// directly packed and sorted as samples. These are 
	// generated only if the transport layer is included 
	// inside the IP
	.rx_lane_samples (),
	.rx_lane_samples_valid (),

	// The following are the lane sideband signals
	// in 8B/10B mode

	// SYNCn signal
	.rx_sync_n (rx_sync_n),
	// Control signal for RX de-scrambling.
	.cfg_rx_scrambling_enabled (cfg_rx_scrambling_enabled),

	.rx_lane_configuration_data (rx_lane_configuration_data),
	.rx_lane_start_of_frame (rx_lane_start_of_frame),
	.rx_lane_start_of_multiframe (rx_lane_start_of_multiframe),

	// The following are the lane sideband signals
	// in 64b/66b mode

	.rx_lane_start_of_mblock (rx_lane_start_of_mblock),
	.rx_lane_start_of_emblock (rx_lane_start_of_emblock),
	.rx_lane_crc_error (rx_lane_crc_error),

	// This is the master clear signal for all
	// the error counts exported by the IP
	.rx_clr_all_err_count (rx_clr_all_err_count),

	// The following signals are the error related
	// counts for the 8b/10b protocol
	.rx_lane_invalid_somf_err_count (rx_lane_invalid_somf_err_count),
	.rx_lane_clr_invalid_somf_err_count (rx_lane_clr_invalid_somf_err_count),
	.rx_lane_invalid_eomf_err_count (rx_lane_invalid_eomf_err_count),
	.rx_lane_clr_invalid_eomf_err_count (rx_lane_clr_invalid_eomf_err_count),
	.rx_lane_invalid_eof_err_count (rx_lane_invalid_eof_err_count),
	.rx_lane_clr_invalid_eof_err_count (rx_lane_clr_invalid_eof_err_count),
	.rx_lane_notintable_err_count (rx_lane_notintable_err_count),
	.rx_lane_clr_notintable_err_count (rx_lane_clr_notintable_err_count),
	.rx_lane_disp_err_count (rx_lane_disp_err_count),
	.rx_lane_clr_disp_err_count (rx_lane_clr_disp_err_count),

	// The following signals are the error related
	// counts for the 64b/66b protocol
	.rx_lane_invalid_header_err_count (rx_lane_invalid_header_err_count),
	.rx_lane_clr_invalid_header_err_count (rx_lane_clr_invalid_header_err_count),
	.rx_lane_invalid_eomb_err_count (rx_lane_invalid_eomb_err_count),
	.rx_lane_clr_invalid_eomb_err_count (rx_lane_clr_invalid_eomb_err_count),
	.rx_lane_invalid_eoemb_err_count (rx_lane_invalid_eoemb_err_count),
	.rx_lane_clr_invalid_eoemb_err_count (rx_lane_clr_invalid_eoemb_err_count),
	.rx_lane_crc_mismatch_err_count (rx_lane_crc_mismatch_err_count),
	.rx_lane_clr_crc_mismatch_err_count (rx_lane_clr_crc_mismatch_err_count),

	// Rx Sysref control and status signals
	.rx_sysref (rx_sysref),
	.rx_sysref_realign_count (rx_sysref_realign_count),
	.rx_clr_sysref_realign_count (rx_clr_sysref_realign_count),
	.rx_lmfc_pulse (rx_lmfc_pulse),
	.rx_lemc_pulse (rx_lemc_pulse),

	.cfg_rx_det_latency_en (cfg_rx_det_latency_en),
	.cfg_rx_buffer_release_delay (cfg_rx_buffer_release_delay),
	.rx_lmfc_to_buffer_release_delay (rx_lmfc_to_buffer_release_delay),
	.rx_lemc_to_buffer_release_delay (rx_lemc_to_buffer_release_delay),

	////////////////////////////////////////////
	// Primary Transmitter related ports. These are
	// independent of the 8B10b / 64B66B protocol
	////////////////////////////////////////////

	// Pad inputs for the Transceiver Rx lanes
	.mgt_lane_txp (mgt_lane_txp),
	.mgt_lane_txn (mgt_lane_txn),
	.cfg_tx_lane_polarity (cfg_tx_lane_polarity),

	// TXUSRCLK2 extracted by the transceiver
	.mgt_tx_usrclk2 (mgt_tx_usrclk2),

	// Lane Mapping between ADC and Transceiver
	// Note: This is defined with respect to the 
	// ADC lanes
	.cfg_tx_lane_map (cfg_tx_lane_map), 

	// Application/System Clock for the Rx
	.tx_sys_clock (tx_sys_clock),

	// Application/System Synchronous Reset for the Rx
	.tx_sync_reset (tx_sync_reset),

	// lane enable signals (usually tied to all 1's, 
	// but can be used for individual lane checks)
	.cfg_tx_lane_enable (cfg_tx_lane_enable),

	// Lane data inputs. There is one input data
	// bus per lane
	.tx_lane_data (tx_lane_data),

	// Data ready signal. This applies simultaneously
	// to all lanes
	.tx_lane_data_ready (tx_lane_data_ready),

	// The following are the lane sideband signals
	// in 8B/10B mode

	// SYNCn signal
	.tx_sync_n (tx_sync_n),

	// Control signal for TX scrambling.
	.cfg_tx_scrambling_enabled (cfg_tx_scrambling_enabled),

	// Control signal for forcing Tx to ILAS mode
	.cfg_tx_ilas_test_mode (cfg_tx_ilas_test_mode),

	.tx_lane_start_of_frame (tx_lane_start_of_frame),
	.tx_lane_start_of_multiframe (tx_lane_start_of_multiframe),

	// The following are the lane sideband signals
	// in 64b/66b mode

	.tx_lane_start_of_mblock (tx_lane_start_of_mblock),
	.tx_lane_start_of_emblock (tx_lane_start_of_emblock),


	// Rx Sysref control and status signals
	.tx_sysref (tx_sysref),
	.tx_lmfc_pulse (tx_lmfc_pulse),
	.tx_lemc_pulse (tx_lemc_pulse),

	.tx_sysref_realign_count (tx_sysref_realign_count),
	.tx_clr_sysref_realign_count (tx_clr_sysref_realign_count),
	.testport1_in (testport1_in),
	.testport1_out (testport1_out),
	.testport2_in (testport2_in),
	.testport2_out (testport2_out),
	.testport3_in (testport3_in),
	.testport3_out (testport3_out)

);

////////////////////////////////////////////////////
// Instantiate the VIO module that will control
// the JESD IP's reset and misc signals
////////////////////////////////////////////////////
wire rx_sync_reset_vio;
wire tx_sync_reset_vio;
wire [1:0] sine_attenuation_factor;

vio vio_inst (
	.clk (mgt_freerun_clock),
	`ifdef IP_8B10B
	.probe_in0 (rx_lmfc_to_buffer_release_delay),
	`else
	.probe_in0 (rx_lemc_to_buffer_release_delay),
	`endif
	.probe_in1 (qpll0_locked),
	.probe_in2 (qpll1_locked),
	.probe_in3 (cpll_locked),
	.probe_out0 (master_reset_n),
	.probe_out1 (rx_sync_reset_vio),
	.probe_out2 (tx_sync_reset_vio),
	.probe_out3 (cfg_rx_buffer_release_delay)
	);

// Synchronize the Rx sync reset from VIO clock to rx_sys_clock
// Synchronize the Tx sync reset from VIO clock to tx_sys_clock
//
(* ASYNC_REG="true" *) reg [1:0] rx_sync_reset_sync;
(* ASYNC_REG="true" *) reg [1:0] tx_sync_reset_sync;

////////////////////////////////////////////////////
// Logic related to the Tx
// Instantiated only if the Tx mode exists
////////////////////////////////////////////////////

genvar i;
generate
begin : tx_refdesign_gen

if (IP_TYPE == "RXTX" || IP_TYPE == "TX")
begin

always @(posedge tx_sys_clock or negedge master_reset_n)
begin
	if (!master_reset_n)
	 begin
	  tx_sync_reset_sync <= 2'b11;
	 end
	else
	 begin
	  tx_sync_reset_sync[0] <= tx_sync_reset_vio;
	  tx_sync_reset_sync[1] <= tx_sync_reset_sync[0];
	 end
end

assign tx_sync_reset = tx_sync_reset_sync[1];

refdesign_tx
#(
	.IP_PROTOCOL (IP_PROTOCOL),
	.NUM_TX_LANES (NUM_TX_LANES),
	.TX_LN_DATA_WIDTH (TX_LN_DATA_WIDTH)
)
refdesign_tx_inst (
	.master_reset_n (master_reset_n),
	.mgt_freerun_clock (mgt_freerun_clock),
	.tx_sys_clock (tx_sys_clock),
	.tx_sync_reset (tx_sync_reset),
	.tx_lane_data (tx_lane_data),
	.tx_lane_data_ready (tx_lane_data_ready),
	.tx_sync_n (tx_sync_n),
	.tx_lane_start_of_frame (tx_lane_start_of_frame),
	.tx_lane_start_of_multiframe (tx_lane_start_of_multiframe),
	.tx_lane_start_of_mblock (tx_lane_start_of_mblock),
	.tx_lane_start_of_emblock (tx_lane_start_of_emblock),
	.tx_sysref (tx_sysref),
	.tx_lmfc_pulse (tx_lmfc_pulse),
	.tx_lemc_pulse (tx_lemc_pulse),
	.tx_sysref_realign_count (tx_sysref_realign_count),
	.tx_clr_sysref_realign_count (tx_clr_sysref_realign_count),
	.sine_att_factor (sine_attenuation_factor)
);

end
else
begin : tx_default_gen

// If Tx IP doesn't exist, drive tx_lane_data to 0's
for (i=0; i<NUM_TX_LANES; i=i+1)
  assign tx_lane_data[i] = {TX_LN_DATA_WIDTH{1'b0}};

assign tx_sync_reset = 1'b1;

end

end
endgenerate

////////////////////////////////////////////////////
// END Logic related to the Tx
////////////////////////////////////////////////////

////////////////////////////////////////////////////
// Logic related to the Rx
// Instantiated only if the Rx mode exists
////////////////////////////////////////////////////

if (IP_TYPE == "RXTX" || IP_TYPE == "RX")
begin : rx_refdesign_gen

always @(posedge rx_sys_clock or negedge master_reset_n)
begin
	if (!master_reset_n)
	 begin
	  rx_sync_reset_sync <= 2'b11;
	 end
	else
	 begin
	  rx_sync_reset_sync[0] <= rx_sync_reset_vio;
	  rx_sync_reset_sync[1] <= rx_sync_reset_sync[0];
	 end
end

assign rx_sync_reset = rx_sync_reset_sync[1];

refdesign_rx
#(
	.IP_PROTOCOL (IP_PROTOCOL),
	.NUM_RX_LANES (NUM_TX_LANES),
	.RX_LN_DATA_WIDTH (RX_LN_DATA_WIDTH),
	.ADC_RES (ADC_RES)
	)
refdesign_rx_inst (
	.mgt_freerun_clock (mgt_freerun_clock),
	.rx_sys_clock (rx_sys_clock),
	.rx_sync_reset (rx_sync_reset),
	.rx_all_lanes_locked (rx_all_lanes_locked),
	.rx_release_all_lanes (rx_release_all_lanes),
	.rx_lane_data (rx_lane_data),
	.rx_lane_data_valid (rx_lane_data_valid),
	.rx_lane_buffer_overflow (rx_lane_buffer_overflow),
	.rx_sync_n (rx_sync_n),
	.rx_lane_configuration_data (rx_lane_configuration_data),
	.rx_lane_start_of_frame (rx_lane_start_of_frame),
	.rx_lane_start_of_multiframe (rx_lane_start_of_multiframe),
	.rx_lane_start_of_mblock (rx_lane_start_of_mblock),
	.rx_lane_start_of_emblock (rx_lane_start_of_emblock),
	.rx_lane_crc_error (rx_lane_crc_error),
	.rx_lane_invalid_somf_err_count (rx_lane_invalid_somf_err_count),
	.rx_lane_invalid_eomf_err_count (rx_lane_invalid_eomf_err_count),
	.rx_lane_invalid_eof_err_count (rx_lane_invalid_eof_err_count),
	.rx_lane_notintable_err_count (rx_lane_notintable_err_count),
	.rx_lane_disp_err_count (rx_lane_disp_err_count),
	.rx_lane_invalid_header_err_count (rx_lane_invalid_header_err_count),
	.rx_lane_invalid_eomb_err_count (rx_lane_invalid_eomb_err_count),
	.rx_lane_invalid_eoemb_err_count (rx_lane_invalid_eoemb_err_count),
	.rx_lane_crc_mismatch_err_count (rx_lane_crc_mismatch_err_count),
	.rx_sysref (rx_sysref),
	.rx_sysref_realign_count (rx_sysref_realign_count),
	.rx_clr_sysref_realign_count (rx_clr_sysref_realign_count),
	.rx_lmfc_pulse (rx_lmfc_pulse),
	.rx_lemc_pulse (rx_lemc_pulse)
);

end
else
begin : rx_default_gen

assign rx_sync_reset = 1'b1;

end

////////////////////////////////////////////////////
// END Logic related to the Rx
////////////////////////////////////////////////////

////////////////////////////////////////////////////
// Instantiate the Emulated Clock Chip
////////////////////////////////////////////////////

`ifdef SYSREF_GEN

// Instantiate the SYSREF generation logic 
// The period is based on the SYSREF_TARGET_COUNT
// parameter

reg [7:0] sysref_count;
reg sysref_toggle;

always @(posedge sys_clock or negedge master_reset_n)
begin
	if (!master_reset_n)
	 begin
	  sysref_count = 'd0;
	  sysref_toggle <= 1'b0;
	 end
	else
	if (sysref_count == `SYSREF_TARGET_COUNT)
	 begin
	  sysref_count = 'd1;
	  sysref_toggle <= ~sysref_toggle;
	 end
	else
	 sysref_count <= sysref_count+1;
end

(* IOB_REG="true" *) reg sysref_final;

always @(posedge sys_clock)
  sysref_final <= sysref_toggle;

OBUFDS sysref_obuf (.I(sysref_final), 
  .O(cc_sysref_out_p), 
  .OB(cc_sysref_out_n));

`endif

endmodule
`default_nettype wire