AFE79xxLibraryPG1p0
True
spi - USB Instrument created.
resetDevice
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Power Card - USB Instrument created.
Version : 0x104204b
Connected to Capture Card
Loaded Libraries
#================ ERRORS:0, WARNINGS:0 ================#
#================ ERRORS:0, WARNINGS:0 ================#
Version : 0x104204b
Connected to Capture Card
For bandwidth greater than 600MHz, Feedback Channels cannot be supported
Switching to 204B JESD Mode
Lane rate exceeded the max supported value in 204B mode for J58 FPGA board or Maximum Lane Rate (Mbps) parameter set incorrectly. Calculated lane rate: 30000.0Msps
Switching to 204C JESD Mode
For bandwidth greater than 600MHz, Feedback Channels cannot be supported
Switching to 204B JESD Mode
Lane rate exceeded the max supported value in 204B mode for J58 FPGA board or Maximum Lane Rate (Mbps) parameter set incorrectly. Calculated lane rate: 30000.0Msps
Switching to 204C JESD Mode
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For bandwidth greater than 600MHz, Feedback Channels cannot be supported
For these rates, 1KHz raster mode is not supported. Changing to 32-bit NCO mode.
The External Sysref Frequency should be an integer factor of: 3.90625MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 24750.0
laneRateFb: 24750.0
laneRateTx: 24750.0
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 24750.0
laneRateFb: 24750.0
laneRateTx: 24750.0
Matched for 204C mode:477
Connect 1500.0MHz reference clock at LMK_CLK_IN (J14) connector
Generated system parameters successfully
Refreshed GUI
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The External Sysref Frequency should be an integer factor of: 3.90625MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 24750.0
laneRateFb: 24750.0
laneRateTx: 24750.0
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 24750.0
laneRateFb: 24750.0
laneRateTx: 24750.0
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
FPGA Reset device not found
Resetting FPGA.
Version : 0x104204b
Connected to Capture Card
Mismatch in the FPGA bit file version. AFE JESD Protocol is 204C but the FPGA bit file is 0x204b
LMK and FPGA Configured.
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x11
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE GPIO configured.
Sysref Read as expected
Setting RBD to: 15
Setting RBD to: 15
###########Device DAC JESD-RX 0 Link Status###########
Serdes-FIFO error for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Serdes-FIFO error for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0; Alarms: 0xfe00
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###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Serdes-FIFO error for lane 0: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Serdes-FIFO error for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1; Alarms: 0x7d00
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AFE Configuration Complete
Function Execution Failed: setGoodRbd
Function Execution Failed: setGoodRbd
###########Device DAC JESD-RX 0 Link Status###########
Serdes-FIFO error for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Serdes-FIFO error for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0; Alarms: 0xfe00
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###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Serdes-FIFO error for lane 0: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Serdes-FIFO error for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1; Alarms: 0xfd00
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