`default_nettype none
`timescale 1ps/1ps

// This is the top level module that contains the control
// and data path for each lane
//
module mgt_8b10b_wrap
#(
	parameter IP_ID = 0,
	parameter GT_TYPE = "GTHP",
	parameter NUM_LANES = 4,
	parameter NUM_QUADS = 1,
	parameter NUM_REFCLK_BUFFERS = 1,
	parameter TX_BYTES_PER_LANE = 8,
	parameter RX_BYTES_PER_LANE = 8,
	parameter GT_USERIO_IN_WIDTH = 16,
	parameter GT_USERIO_OUT_WIDTH = 16
)
(
	// Reference and free-run clock signals
	input wire	[NUM_REFCLK_BUFFERS-1:0] gt_refclk_p,
	input wire	[NUM_REFCLK_BUFFERS-1:0] gt_refclk_n,
	input wire	gt_reset_clk_freerun,

	// xcvr IP ports. Each Lane has one Tx and one
	// Rx data port. Leave unused ports unconnected
	// or tied off 
	input wire	[NUM_LANES-1:0] gt_rxp,
	input wire	[NUM_LANES-1:0] gt_rxn,
	input wire	[NUM_LANES-1:0] gt_rxpolarity,
	output wire	[NUM_LANES-1:0] gt_txp,
	output wire	[NUM_LANES-1:0] gt_txn,
	input wire	[NUM_LANES-1:0] gt_txpolarity,

	// Clock and CDR related output wires
	output wire	[NUM_QUADS-1:0] qpll0_locked,
	output wire	[NUM_QUADS-1:0] qpll1_locked,
	output wire	[NUM_LANES-1:0] cpll_locked,
	output wire	[NUM_LANES-1:0] cdr_locked,

	// Datapath related signals
	// These are controlled/used by the JESD Rx IP
	output wire	xcvr_rx_usrclk,
	output wire	xcvr_rx_usrclk2,
	output wire	xcvr_tx_usrclk,
	output wire	xcvr_tx_usrclk2,
	input wire	xcvr_reset_all,
	input wire	xcvr_reset_tx,
	input wire	xcvr_reset_rx,
	output wire	xcvr_reset_rx_done,
	output wire	xcvr_reset_tx_done,

	output wire [RX_BYTES_PER_LANE*8-1:0] xcvr_rx_data [NUM_LANES-1:0],
	output wire [RX_BYTES_PER_LANE-1:0] xcvr_rx_is_comma [NUM_LANES-1:0],
	output wire [RX_BYTES_PER_LANE-1:0] xcvr_rx_is_char [NUM_LANES-1:0],
	output wire [RX_BYTES_PER_LANE-1:0] xcvr_rx_notintable [NUM_LANES-1:0],
	output wire [RX_BYTES_PER_LANE-1:0] xcvr_rx_disperror [NUM_LANES-1:0],
	input wire [NUM_LANES-1:0] xcvr_comma_det_align_en,
	output wire [NUM_LANES-1:0] xcvr_rx_byte_aligned,
	output wire [NUM_LANES-1:0] xcvr_rx_byte_realigned,

	input wire [TX_BYTES_PER_LANE*8-1:0] xcvr_tx_data [NUM_LANES-1:0],
	input wire [TX_BYTES_PER_LANE-1:0] xcvr_tx_data_is_char [NUM_LANES-1:0],
	input wire [GT_USERIO_IN_WIDTH-1:0] mgt_gpio_in,
	output wire [GT_USERIO_OUT_WIDTH-1:0] mgt_gpio_out

);

	wire [NUM_REFCLK_BUFFERS-1:0] gt_refclk0_buf;

genvar j;
generate for (j=0; j<NUM_REFCLK_BUFFERS; j=j+1)
begin

 if (GT_TYPE == "GTHP")
 begin

  IBUFDS_GTE4 #(
    .REFCLK_EN_TX_PATH  (1'b0),
    .REFCLK_HROW_CK_SEL (2'b00),
    .REFCLK_ICNTL_RX    (2'b00)
  ) IBUFDS_GTE4_INST (
    .I     (gt_refclk_p[j]),
    .IB     (gt_refclk_n[j]),
    .CEB   (1'b0),
    .O     (gt_refclk0_buf[j]),
    .ODIV2 ()
  );

 end

 else
 begin

  IBUFDS_GTE3 #(
    .REFCLK_EN_TX_PATH  (1'b0),
    .REFCLK_HROW_CK_SEL (2'b00),
    .REFCLK_ICNTL_RX    (2'b00)
  ) IBUFDS_GTE3_INST (
    .I     (gt_refclk_p[j]),
    .IB     (gt_refclk_n[j]),
    .CEB   (1'b0),
    .O     (gt_refclk0_buf[j]),
    .ODIV2 ()
  );

 end

end
endgenerate

	wire xcvr_userclk_rx_reset;
	wire xcvr_userclk_tx_reset;
	wire xcvr_userclk_rx_usrclk2;
	wire xcvr_userclk_rx_active;
	wire [NUM_LANES*RX_BYTES_PER_LANE*8-1:0] xcvr_userdata_rx;
	wire [NUM_LANES*16-1:0] xcvr_rxctrl0;
	wire [NUM_LANES*16-1:0] xcvr_rxctrl1;
	wire [NUM_LANES*8-1:0] xcvr_rxctrl2;
	wire [NUM_LANES*TX_BYTES_PER_LANE*8-1:0] xcvr_userdata_tx;
	wire [NUM_LANES*16-1:0] xcvr_txctrl0;
	wire [NUM_LANES*16-1:0] xcvr_txctrl1;
	wire [NUM_LANES*8-1:0] xcvr_txctrl2;
	wire [NUM_LANES*8-1:0] xcvr_rxctrl3;
	wire [NUM_LANES-1:0] xcvr_txpmaresetdone;
	wire [NUM_LANES-1:0] xcvr_rxpmaresetdone;

assign xcvr_userclk_rx_reset =
	~(&xcvr_rxpmaresetdone);

assign xcvr_userclk_tx_reset =
	~(&xcvr_txpmaresetdone);

genvar i;
generate for (i = 0; i < NUM_LANES; i=i+1)
begin : lane_gen

  assign xcvr_rx_data[i] = 
           xcvr_userdata_rx[RX_BYTES_PER_LANE*8*i +: RX_BYTES_PER_LANE*8];

  assign xcvr_rx_is_comma[i] = 
           xcvr_rxctrl2[8*i +: RX_BYTES_PER_LANE];

  assign xcvr_rx_is_char[i] = 
           xcvr_rxctrl0[16*i +: RX_BYTES_PER_LANE];

  assign xcvr_rx_notintable[i] = 
           xcvr_rxctrl3[8*i +: RX_BYTES_PER_LANE];

  assign xcvr_rx_disperror[i] = 
           xcvr_rxctrl1[16*i +: RX_BYTES_PER_LANE];

  assign xcvr_userdata_tx[TX_BYTES_PER_LANE*8*i +: TX_BYTES_PER_LANE*8] = 
     xcvr_tx_data[i];
           

  assign xcvr_txctrl2[8*i +: TX_BYTES_PER_LANE] = xcvr_tx_data_is_char[i];
           
end
endgenerate

  assign xcvr_txctrl1 = 'd0;
  assign xcvr_txctrl0 = 'd0;


generate
begin : xcvr_gen

if (TX_BYTES_PER_LANE == 8 && RX_BYTES_PER_LANE == 8)
gth_8b10b_xcvr xcvr_inst
(
	.gtwiz_userclk_tx_reset_in (xcvr_userclk_tx_reset),
	.gtwiz_userclk_tx_srcclk_out (),
	.gtwiz_userclk_tx_usrclk_out (xcvr_tx_usrclk),
	.gtwiz_userclk_tx_usrclk2_out (xcvr_tx_usrclk2),
	.gtwiz_userclk_tx_active_out (),
	.gtwiz_userclk_rx_reset_in (xcvr_userclk_rx_reset),
	.gtwiz_userclk_rx_srcclk_out (),
	.gtwiz_userclk_rx_usrclk_out (xcvr_rx_usrclk),
	.gtwiz_userclk_rx_usrclk2_out (xcvr_rx_usrclk2),
	.gtwiz_userclk_rx_active_out (),
	.gtwiz_reset_clk_freerun_in (gt_reset_clk_freerun),
	.gtwiz_reset_all_in (xcvr_reset_all),
	.gtwiz_reset_tx_pll_and_datapath_in (1'b0),
	.gtwiz_reset_tx_datapath_in (xcvr_reset_tx),
	//.gtwiz_reset_tx_datapath_in (mgt_gpio_in[1]),
	.gtwiz_reset_rx_pll_and_datapath_in (1'b0),
	.gtwiz_reset_rx_datapath_in (xcvr_reset_rx),
	//.gtwiz_reset_rx_datapath_in (mgt_gpio_in[1'b0]),
	.gtwiz_reset_rx_cdr_stable_out (),
	.gtwiz_reset_tx_done_out (xcvr_reset_tx_done),
	.gtwiz_reset_rx_done_out (xcvr_reset_rx_done),
	.gtwiz_userdata_tx_in (xcvr_userdata_tx),
	.gtwiz_userdata_rx_out (xcvr_userdata_rx),
	// MGTREFCLK0 of Quad 130 connected to REFCLK
	// inputs of both banks 130 and 129
	//.gtrefclk00_in ({2{gt_refclk0_buf}}),
	.gtrefclk00_in (gt_refclk0_buf),
	.gthrxn_in (gt_rxn),
	.gthrxp_in (gt_rxp),
	.qpll0lock_out (qpll0_locked),
	.qpll1lock_out (qpll1_locked),
	.cplllock_out (cpll_locked),
	.rxcdrlock_out (cdr_locked),
	.rx8b10ben_in ({NUM_LANES{1'b1}}),
	.rxcommadeten_in ({NUM_LANES{1'b1}}),
	.rxmcommaalignen_in (xcvr_comma_det_align_en),
	.rxpcommaalignen_in (xcvr_comma_det_align_en),
	.rxpolarity_in (gt_rxpolarity),
	.txpolarity_in (gt_txpolarity),
	.tx8b10ben_in ({NUM_LANES{1'b1}}),
	.txctrl0_in (xcvr_txctrl0),
	.txctrl1_in (xcvr_txctrl1),
	.txctrl2_in (xcvr_txctrl2),
	.gthtxn_out (gt_txn),
	.gthtxp_out (gt_txp),
	.gtpowergood_out (),
	.rxbyteisaligned_out (xcvr_rx_byte_aligned),
	.rxbyterealign_out (xcvr_rx_byte_realigned),
	.rxcommadet_out (),
	.rxctrl0_out (xcvr_rxctrl0),
	.rxctrl1_out (xcvr_rxctrl1),
	.rxctrl2_out (xcvr_rxctrl2),
	.rxctrl3_out (xcvr_rxctrl3),
	.rxpmaresetdone_out (xcvr_rxpmaresetdone),
	.txpmaresetdone_out (xcvr_txpmaresetdone)
);

end
endgenerate

assign mgt_gpio_out = {GT_USERIO_OUT_WIDTH{1'b0}};

endmodule
`default_nettype wire