//START: Updating RX NCO

SPIWrite 0015,00,0,7	//timing_controller=0x0; 	Address(0x15[7:7])
SPIWrite 0018,20,0,7	//macro=0x1; 	Address(0x18[5:5])
SPIRead 00f0,0,0

//Read	MACRO_READY=0x1; 	Address(0xf0[0:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,e3,0,7	//MACRO_OPERAND_REG0=0xe38e0000; 	Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,8e,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,00,0,7
SPIWrite 00a7,00,0,7	//MACRO_OPERAND_REG1=0x3e1d8; 	Address(0xa4[7:0],0xa5[7:0],0xa6[7:0],0xa7[7:0],0xa8[7:0])
SPIWrite 00a6,03,0,7
SPIWrite 00a5,e1,0,7
SPIWrite 00a4,d8,0,7
SPIWrite 0193,38,0,7	//MACRO_OPCODE=0x38; 	Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read	MACRO_DONE=0x1; 	Address(0xf0[2:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

//Read	MACRO_ERROR=0x0; 	Address(0xf0[3:3])

SPIRead 00f1,0,7

//Read	MACRO_ERROR_OPCODE=0x0; 	Address(0xf1[7:0],0xf2[7:0])

SPIRead 00f0,4,4

//Read	MACRO_ERROR_IN_OPCODE=0x0; 	Address(0xf0[4:4])

SPIRead 00f0,5,5

//Read	MACRO_ERROR_OPCODE_NOT_ALLOWED=0x0; 	Address(0xf0[5:5])

SPIRead 00f0,6,6

//Read	MACRO_ERROR_IN_OPERAND=0x0; 	Address(0xf0[6:6])

SPIRead 00f0,7,7

//Read	MACRO_ERROR_IN_EXECUTION=0x0; 	Address(0xf0[7:7])

SPIRead 00f3,0,7
SPIRead 00f2,0,7

//Read	MACRO_ERROR_EXTENDED_CODE=0x0; 	Address(0xf2[7:0],0xf3[7:0],0xf4[7:0])

SPIRead 00f7,0,7
SPIRead 00f6,0,7
SPIRead 00f5,0,7
SPIRead 00f4,0,7

//Read	MACRO_ERROR_EXTENDED_CODE_2=0x0; 	Address(0xf4[7:0],0xf5[7:0],0xf6[7:0],0xf7[7:0],0xf8[7:0])


//END: Updating RX NCO