.ALIASES
Kn_K2            K2() CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1152@ANALOG.K_Linear.Normal(chips)
L_L1            L1(1=N01114 2=N01018 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1038@ANALOG.L.Normal(chips)
L_L2            L2(1=N01024 2=0 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1058@ANALOG.L.Normal(chips)
R_R1            R1(1=N01368 2=N01018 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS936@ANALOG.R.Normal(chips)
L_L3            L3(1=N01650 2=0 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1299@ANALOG.L.Normal(chips)
C_C_bulk          C_bulk(1=0 2=N01368 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1350@ANALOG.C.Normal(chips)
X_M1            M1(D=N01114 G=N03088 S=N01569 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1493@SILICONIX.NAMS20.Normal(chips)
R_Rcs           Rcs(1=0 2=N01569 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1520@ANALOG.R.Normal(chips)
R_Rvdd          Rvdd(1=VDD 2=N01679 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1663@ANALOG.R.Normal(chips)
C_Cbias          Cbias(1=0 2=N01650 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1901@ANALOG.C.Normal(chips)
R_Rsu           Rsu(1=VDD 2=N01368 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS1990@ANALOG.R.Normal(chips)
C_Cvdd          Cvdd(1=0 2=VDD ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS2084@ANALOG.C.Normal(chips)
R_Rovp1          Rovp1(1=N02272 2=N01650 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS2230@ANALOG.R.Normal(chips)
R_Rovp2          Rovp2(1=0 2=N02272 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS2246@ANALOG.R.Normal(chips)
R_Rpl           Rpl(1=N03192 2=N01569 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS2615@ANALOG.R.Normal(chips)
R_R2            R2(1=N02913 2=N01368 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS2843@ANALOG.R.Normal(chips)
C_C1            C1(1=N02913 2=N01368 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS2868@ANALOG.C.Normal(chips)
C_C2            C2(1=VDD 2=0 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS3242@ANALOG.C.Normal(chips)
X_D5            D5(1=N01024 2=N01024 3=N03620 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS3311@DIODE.MUR10005CT.Normal(chips)
C_CSS           CSS(1=0 2=N03940 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS3528@ANALOG.C.Normal(chips)
C_Cout          Cout(1=N036140 2=N03620 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS3604@ANALOG.C.Normal(chips)
R_Rout          Rout(1=0 2=N03620 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS3719@ANALOG.R.Normal(chips)
R_R3            R3(1=0 2=N036140 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS5120@ANALOG.R.Normal(chips)
R_R9            R9(1=FB 2=0 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS7938@ANALOG.R.Normal(chips)
X_D6            D6(1=N01650 2=N01650 3=N01679 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS8100@DIODE.MUR10005CT.Normal(chips)
X_U2            U2(1=N01114 2=N01114 3=N02913 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS8577@JDIODE.D1D2C1.Normal(chips)
R_R10           R10(1=N08897 2=0 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS8881@ANALOG.R.Normal(chips)
V_V2            V2(+=N01368 -=0 ) CN @UC28600_SIM.SCHEMATIC1(sch_1):INS9268@SOURCE.VPULSE.Normal(chips)
X_U4            U4(SS=N03940 FB=FB CS=N03192 GND=0 OUT=N03088 VDD=VDD OVP=N02272 STATUS=N08897 ) CN
+@UC28600_SIM.SCHEMATIC1(sch_1):INS11648@UCC28600.UCC28600_0.Normal(chips)
_    _(FB=FB)
_    _(VDD=VDD)
.ENDALIASES
