Texas Instruments ti.com MSPM0G351X This preliminary header file does not have a version number - build date: 2024-07-25 04:30:36 ARM Device Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 32 32 read-write 0x00000000 0xFFFFFFFF CM0 r0p1 little true false 3 false UART0 UART 1.0 PERIPHERALREGION 0x40108000 0x0 0x1F00 registers 1 24 0 UART0_GPRCM[%s] 0x800 UART0_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 UART0_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 UART0_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 UART0_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 UART0_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 UART0_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 UART0_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 UART0_CPU_INT[%s] 0x1020 UART0_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 FEFG UART framing error interrupt; Interrupt Flag: FE 0x2 PEFG UART parity error interrupt; Interrupt Flag: PE 0x3 BEFG UART break error interrupt; Interrupt Flag: BE 0x4 OEFG UART receive overrun error interrupt; Interrupt Flag: OE 0x5 RXNE Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE 0x6 RXPE Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE 0x7 LINC0 LIN capture 0 / match interrupt; Interrupt Flag: LINC0 0x8 LINC1 LIN capture 1 interrupt; Interrupt Flag: LINC1 0x9 LINOVF LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF 0xA RXIFG UART receive interrupt; Interrupt Flag: RX 0xB TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC EOT UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT 0xD MODE_9B 9-bit mode address match interrupt; Interrupt Flag: MODE_9B 0xE CTS UART Clear to Send Modem interrupt; Interrupt Flag: CTS 0xF DMA_DONE_RX DMA DONE on RX 0x10 DMA_DONE_TX DMA DONE on TX 0x11 NERR_EVT Noise Error Event 0x12 UART0_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PARERR Enable UART Parity Error Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 BRKERR Enable UART Break Error Interrupt. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 LINOVF Enable LIN Hardware Counter Overflow Interrupt. 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTS Enable UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX Enable DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX Enable DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 LINC0 Enable LIN Capture 0 / Match Interrupt . 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 LINC1 Enable LIN Capture 1 Interrupt. 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART0_CPU_INT_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINC0 LIN Capture 0 / Match Interrupt . 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINC1 LIN Capture 1 Interrupt. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINOVF LIN Hardware Counter Overflow Interrupt. 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_RX DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_TX DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART0_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR Masked UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR Masked UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINC0 Masked LIN Capture 0 / Match Interrupt . 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINC1 Masked LIN Capture 1 Interrupt. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINOVF Masked LIN Hardware Counter Overflow Interrupt. 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS Masked UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_RX Masked DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_TX Masked DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART0_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 FRMERR Set UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PARERR Set UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 BRKERR Set UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 LINC0 Set LIN Capture 0 / Match Interrupt . 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 LINC1 Set LIN Capture 1 Interrupt. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 LINOVF Set LIN Hardware Counter Overflow Interrupt. 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTS Set UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing this has no effect 0x0 SET Set the interrupt 0x1 UART0_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PARERR Clear UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 BRKERR Clear UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 LINC0 Clear LIN Capture 0 / Match Interrupt . 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 LINC1 Clear LIN Capture 1 Interrupt. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 LINOVF Clear LIN Hardware Counter Overflow Interrupt. 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTS Clear UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART0_DMA_TRIG_RX[%s] 0x1050 UART0_DMA_TRIG_RX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 RXIFG UART receive interrupt; Interrupt Flag: RX 0xB UART0_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART0_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART0_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART0_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART0_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART0_DMA_TRIG_TX[%s] 0x1080 UART0_DMA_TRIG_TX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC UART0_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART0_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART0_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART0_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART0_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 UART0_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 UART0_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 UART0_CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write DISABLE Disable Module 0x0 ENABLE Enable module 0x1 HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write OVS16 16x oversampling. 0x0 OVS8 8x oversampling. 0x1 OVS3 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled. 0x2 LBE UART Loop Back Enable 0x2 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The UARTxTX path is fed through the UARTxRX path internally. 0x1 RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write DISABLE The receive section of the UART is disabled. 0x0 ENABLE The receive section of the UART is enabled. 0x1 TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write DISABLE The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled. 0x0 ENABLE The transmit section of the UART is enabled. 0x1 RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CLR Signal not RTS 0x0 SET Signal RTS 0x1 RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write DISABLE RTS hardware flow control is disabled. 0x0 ENABLE RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries. 0x1 CTSEN Enable Clear To Send 0xE 0x1 read-write DISABLE CTS hardware flow control is disabled. 0x0 ENABLE CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted. 0x1 MENC Manchester Encode enable 0x7 0x1 read-write DISABLE Disable Manchester Encoding 0x0 ENABLE Enable Manchester Encoding 0x1 MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write UART Normal operation 0x0 RS485 RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data. 0x1 IDLELINE The UART operates in IDLE Line Mode 0x2 ADDR9BIT The UART operates in 9 Bit Address mode 0x3 SMART ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. 0x4 DALI DALI Mode: 0x5 FEN UART Enable FIFOs 0x11 0x1 read-write DISABLE The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 0x0 ENABLE The transmit and receive FIFO buffers are enabled (FIFO mode). 0x1 TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write LOW TXD pin is low 0x0 HIGH TXD pin is high 0x1 TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 0x5 0x1 read-write DISABLE TXD pin can not be controlled by TXD_OUT 0x0 ENABLE TXD pin can be controlled by TXD_OUT 0x1 MAJVOTE Majority Vote Enable When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (i.e. all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set. Oversampling of 16 : bits 7, 8, 9 are used Oversampling of 8 : bits 3, 4, 5 are used Disabled : Single sample value (center value) used 0x12 0x1 read-write DISABLE Majority voting is disabled 0x0 ENABLE Majority voting is enabled 0x1 MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write DISABLE Least significant bit is sent first in the protocol packet 0x0 ENABLE Most significant bit is sent first in the protocol packet 0x1 UART0_LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write DISABLE Normal use. 0x0 ENABLE A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0x1 PEN UART Parity Enable 0x1 0x1 read-write DISABLE Parity is disabled and no parity bit is added to the data frame. 0x0 ENABLE Parity checking and generation is enabled. 0x1 EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write ODD Odd parity is performed, which checks for an odd number of 1s. 0x0 EVEN Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0x1 STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write DISABLE One stop bit is transmitted at the end of a frame. 0x0 ENABLE Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid. 0x1 WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write DATABIT5 5 bits (default) 0x0 DATABIT6 6 bits 0x1 DATABIT7 7 bits 0x2 DATABIT8 8 bits 0x3 SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write DISABLE Disable Stick Parity 0x0 ENABLE Enable Stick Parity 0x1 SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write DISABLE Disable Send Idle Pattern 0x0 ENABLE Enable Send Idle Pattern 0x1 EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write UART0_STAT UART Status Register 0x1108 32 read-only BUSY UART Busy This bit is set as soon as the transmit FIFO or TXDATA register becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only CLEARED The UART is not busy. 0x0 SET The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register. 0x1 TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only CLEARED The transmitter is not full. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0x1 RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only CLEARED The receiver can receive data. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0x1 TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only CLEARED The transmitter has data to transmit. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0x1 CTS Clear To Send 0x8 0x1 read-only CLEARED The CTS signal is not asserted (high). 0x0 SET The CTS signal is asserted (low). 0x1 IDLE IDLE mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only CLEARED IDLE has not been detected before last received character. (In idle-line multiprocessor mode). 0x0 SET IDLE has been detected before last received character. (In idle-line multiprocessor mode). 0x1 RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only CLEARED The receiver is not empty. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0x1 UART0_IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_EMPTY TX FIFO is empty 0x5 LVL_1 TX FIFO >= 1 entry free Note: esp. required for DMA Trigger 0x7 RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write LVL_1_4_RES RX FIFO >= 1/4 full Note: For ULP Domain 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_FULL_RES RX FIFO is full Note: For ULP Domain 0x4 LVL_FULL RX FIFO is full 0x5 LVL_1 RX FIFO >= 1 entry available Note: esp. required for DMA Trigger 0x7 RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write UART0_IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write UART0_FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write UART0_GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. 0x9 0x2 read-write AGLIT_5 Pulses shorter then 5ns length are filtered. 0x0 AGLIT_10 Pulses shorter then 10ns length are filtered. 0x1 AGLIT_25 Pulses shorter then 25ns length are filtered. 0x2 AGLIT_50 Pulses shorter then 50ns length are filtered. 0x3 AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write DISABLE Analog Glitch Filter disable 0x0 ENABLE Analog Glitch Filter enable 0x1 DGFSEL Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The value programmed in this field gives the number of cycles of functional clock up to which the glitch has to be suppressed on the RX line. In IRDA mode: The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK) 0x0 0x6 read-write DISABLED Bypass GF 0x0 CHAIN Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0xB 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 UART0_TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write UART0_RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff DATA Received Data. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only CLR No framing error has occurred 0x0 SET The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1). 0x1 PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only CLR No parity error has occurred 0x0 SET The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0x1 BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only CLR No break condition has occurred 0x0 SET A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0x1 OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only CLR No data has been lost due to a receive overrun. 0x0 SET New data was received but could not be stored, because the previous data was not read (resulting in data loss). 0x1 NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only CLR No noise error occured 0x0 SET Noise error occured during majority voting 0x1 UART0_LINCNT UART LIN Mode Counter Register 0x1130 32 read-write 0x00000000 0xffffffff LINCNT 16 bit up counter clocked by the functional clock of the UART. 0x0 0x10 read-write UART0_LINCTL UART LIN Mode Control Register 0x1134 32 read-write 0x00000000 0xffffffff CTRENA LIN Counter Enable. LIN counter will only count when enabled. 0x0 0x1 read-write DISABLE Counter disabled 0x0 ENABLE Counter enabled 0x1 ZERONE Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD 0x1 0x1 read-write DISABLE Zero on negative edge disabled 0x0 ENABLE Zero on negative edge enabled 0x1 CNTRXLOW Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments. 0x2 0x1 read-write DISABLE Count while low Signal on UARTxRXD disabled 0x0 ENABLE Count while low Signal on UARTxRXD enabled 0x1 LINC0CAP Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled. 0x4 0x1 read-write DISABLE Capture counter on negative UARTxRXD edge disabled 0x0 ENABLE Capture counter on negative UARTxRXD edge enabled 0x1 LINC1CAP Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled. 0x5 0x1 read-write DISABLE Capture counter on positive UARTxRXD edge disabled 0x0 ENABLE Capture counter on positive UARTxRXD edge enabled 0x1 LINC0_MATCH Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled. 0x6 0x1 read-write DISABLE Counter compare match mode disabled (capture mode enabled) 0x0 ENABLE Counter compare match enabled (capture mode disabled) 0x1 UART0_LINC0 UART LIN Mode Capture 0 Register 0x1138 32 read-write 0x00000000 0xffffffff DATA 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge and can generate a LINC0 interrupt when capture is enabled (LINC0CAP = 1). If compare mode is enabled (LINC0_MATCH = 1), a counter match can generate a LINC0 interrupt. 0x0 0x10 read-write UART0_LINC1 UART LIN Mode Capture 1 Register 0x113C 32 read-write 0x00000000 0xffffffff DATA 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge and can generate a LINC1 interrupt when capture is enabled (LINC1CAP = 1) 0x0 0x10 read-write UART0_IRCTL eUSCI_Ax IrDA Control Word Register 0x1140 32 read-write 0x00000000 0x0000ffff IRTXPL Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / [2 * f(IRTXCLK)] (IRTXCLK = functional clock of the UART) 0x2 0x6 read-write IRRXPL IrDA receive input UCAxRXD polarity 0x9 0x1 read-write HIGH IrDA transceiver delivers a high pulse when a light pulse is seen 0x0 LOW IrDA transceiver delivers a low pulse when a light pulse is seen 0x1 IREN IrDA encoder/decoder enable 0x0 0x1 read-write DISABLE IrDA encoder/decoder disabled 0x0 ENABLE IrDA encoder/decoder enabled 0x1 IRTXCLK IrDA transmit pulse clock select 0x1 0x1 read-write BITCLK IrDA encode data is based on the functional clock. 0x0 BRCLK IrDA encode data is based on the Baud Rate clock< when select 8x oversampling, the IRTXPL cycle should less 8; when select 16x oversampling, the IRTXPL cycle should less 16. 0x1 UART0_AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff MSK Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register must match. 0x0 0x8 read-write UART0_ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh. 0x0 0x8 read-write UART0_CLKDIV2 Clock Divider 0x1160 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMA0 TIMA 1.0 PERIPHERALREGION 0x40860000 0x0 0x1F00 registers TIMA0_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMA0_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMA0_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMA0_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMA0_GPRCM[%s] 0x800 TIMA0_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMA0_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMA0_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMA0_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMA0_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMA0_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMA0_INT_EVENT[%s] 0x1020 TIMA0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMA0_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 F Fault Event mask 0x18 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 CCD2 Capture or Compare DN event mask CCP2 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD3 Capture or Compare DN event mask CCP3 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU2 Capture or Compare UP event mask CCP2 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU3 Capture or Compare UP event mask CCP3 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD4 Compare DN event mask CCP4 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD5 Compare DN event mask CCP5 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU4 Compare UP event mask CCP4 0xE 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU5 Compare UP event mask CCP5 0xF 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 REPC Repeat Counter Zero Event mask 0x1A 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TIMA0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 F Fault 0x18 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD2 Capture or compare down event generated an interrupt CCP2 0x6 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD3 Capture or compare down event generated an interrupt CCP3 0x7 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU2 Capture or compare up event generated an interrupt CCP2 0xA 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU3 Capture or compare up event generated an interrupt CCP3 0xB 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD4 Compare down event generated an interrupt CCD4 0xC 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD5 Compare down event generated an interrupt CCD5 0xD 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU4 Compare up event generated an interrupt CCU4 0xE 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU5 Compare up event generated an interrupt CCP5 0xF 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 REPC Repeat Counter Zero 0x1A 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMA0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 F Fault 0x18 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD2 Capture or compare down event generated an interrupt CCP2 0x6 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD3 Capture or compare down event generated an interrupt CCP3 0x7 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU2 Capture or compare up event generated an interrupt CCP2 0xA 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU3 Capture or compare up event generated an interrupt CCP3 0xB 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD4 Compare down event generated an interrupt CCP4 0xC 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD5 Compare down event generated an interrupt CCP5 0xD 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU4 Compare up event generated an interrupt CCP4 0xE 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU5 Compare up event generated an interrupt CCP5 0xF 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 REPC Repeat Counter Zero 0x1A 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMA0_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 F Fault event SET 0x18 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD2 Capture or compare down event SET 0x6 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD3 Capture or compare down event SET 0x7 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU2 Capture or compare up event SET 0xA 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU3 Capture or compare up event SET 0xB 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD4 Compare down event 4 SET 0xC 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD5 Compare down event 5 SET 0xD 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU4 Compare up event 4 SET 0xE 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU5 Compare up event 5 SET 0xF 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 REPC Repeat Counter Zero event SET 0x1A 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMA0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 F Fault event CLEAR 0x18 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD2 Capture or compare down event CLEAR 0x6 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD3 Capture or compare down event CLEAR 0x7 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU2 Capture or compare up event CLEAR 0xA 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU3 Capture or compare up event CLEAR 0xB 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD4 Compare down event 4 CLEAR 0xC 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD5 Compare down event 5 CLEAR 0xD 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU4 Compare up event 4 CLEAR 0xE 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU5 Compare up event 5 CLEAR 0xF 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 REPC Repeat Counter Zero event CLEAR 0x1A 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMA0_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMA0_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 40 0 TIMA0_COMMONREGS[%s] 0x1100 TIMA0_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP2 Counter CCP2 0x2 0x1 INPUT input 0x0 OUTPUT Output 0x1 C0CCP3 Counter CCP3 0x3 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMA0_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 C0CCP2 Counter CCP2 Disable Mask Defines whether CCP2 of Counter n is forced low or not 0x2 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[2]. 0x0 CCP_OUTPUT_LOW CCP output occpout[2] is forced low. 0x1 C0CCP3 Counter CCP3 Disable Mask Defines whether CCP3 of Counter n is forced low or not 0x3 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[2]. 0x0 CCP_OUTPUT_LOW CCP output occpout[3] is forced low. 0x1 TIMA0_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMA0_CPS Clock Prescale Register 0xC 32 read-write PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write TIMA0_CPSV Clock prescale count status register 0x10 32 read-only CPSVAL Current Prescale Count Value 0x0 0x8 read-only TIMA0_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMA0_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 TIMA0_FSCTL Fault Source Control 0x20 32 read-write FCEN This field controls whether the fault caused by the system clock fault is enable. 0: DISABLE 1: ENABLE 0x0 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FAC0EN This field controls whether the fault signal detected by the analog comparator0 is enable 0: DISABLE 1: ENABLE 0x1 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FAC1EN This field controls whether the fault signal detected by the analog comparator1 is enable 0: DISABLE 1: ENABLE 0x2 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FAC2EN This field controls whether the fault signal detected by the analog comparator2 is enable 0: DISABLE 1: ENABLE 0x3 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FEX0EN This field controls whether the fault caused by external fault pin0 is enable. 0: DISABLE 1: ENABLE 0x4 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FEX1EN This field controls whether the fault caused by external fault pin1 is enable. 0: DISABLE 1: ENABLE 0x5 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FEX2EN This field controls whether the fault caused by external fault pin2 is enable. 0: DISABLE 1: ENABLE 0x6 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 TIMA0_GCTL Shadow to active load mask 0x24 32 read-write SHDWLDEN Enables shadow to active load of bufferred registers and register fields. 0x0 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 1 216 0 TIMA0_COUNTERREGS[%s] 0x1800 TIMA0_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x10 read-write TIMA0_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 FB Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0 0x12 0x1 read-write CONT_COUNT Continues counting 0x0 SUSP_COUNT Suspends counting 0x1 FRB Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition. 0x13 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 PLEN Phase Load Enable. This bit allows the timer to have phase load feature. 0x18 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 SLZERCNEZ Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero. This bit suppresses the generation of the Z (zero) and L (load) events from the counter when the repeat counter (RC) value is not 0. 0x17 0x1 read-write DISABLED Disabled. Z and L events are always generated from the counter when their conditions are generated. 0x0 ENABLED Enabled. Z and L events are generated from the counter when their conditions are generated and the RC register value is 0. 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMA0_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x10 read-write 2 4 0,1 TIMA0_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMA0_CC_23[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x18 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMA0_CC_45[%s] Compare Register 4 to Compare Register 5 0x20 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMA0_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 SCERCNEZ Suppress Compare Event if Repeat Counter is Not Equal to Zero This bit suppresses the generation of the compare (CCD, CCU and RC) events from the counter when the repeat counter (RC) value is not 0. 0x19 0x1 read-write DISABLED CCD, CCU and RC events are always generated from the counter when their conditions are generated. 0x0 ENABLED CCD, CCU and RC events are generated from the counter when their conditions are generated and the RC register value is 0. 0x1 CCUPD Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0). 0x12 0x3 read-write Immediately Writes to the CCx_y register is written to the register directly and has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCx_y register are stored in shadow register and transferred to ECCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LD. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. 0x6 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMA0_CCCTL_23[%s] Capture or Compare Control Registers 0x38 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 SCERCNEZ Suppress Compare Event if Repeat Counter is Not Equal to Zero This bit suppresses the generation of the compare (CCD, CCU and RC) events from the counter when the repeat counter (RCn) value is not 0. 0x19 0x1 read-write DISABLED CCD, CCU and RC events are always generated from the counter when their conditions are generated. 0x0 ENABLED CCD, CCU and RC events are generated from the counter when their conditions are generated and the RC register value is 0. 0x1 CCUPD Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0). 0x12 0x3 read-write Immediately Writes to the CCx_y register is written to the register directly and has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. 0x6 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACTx_y register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMA0_CCCTL_45[%s] Capture or Compare Control Registers 0x40 32 read-write 0x00000000 0xffffffff SCERCNEZ Suppress Compare Event if Repeat Counter is Not Equal to Zero This bit suppresses the generation of the compare (CCD, CCU and RC) events from the counter when the repeat counter (RC) value is not 0. 0x19 0x1 read-write DISABLED CCD, CCU and RC events are always generated from the counter when their conditions are generated. 0x0 ENABLED CCD, CCU and RC events are generated from the counter when their conditions are generated and the RC register value is 0. 0x1 CCUPD Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0). 0x12 0x3 read-write Immediately Writes to the CCx_y register is written to the register directly and has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCx_y register are stored in shadow register and transferred to ECCx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LD. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. 0x6 2 4 0,1 TIMA0_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMA0_OCTL_23[%s] CCP Output Control Registers 0x58 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMA0_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 FENACT CCP Output Action on Fault Entry This field describes the resulting action of the signal generator upon detecting a fault. 0x16 0x3 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CCP_HIGHZ CCP output value is tristated 0x4 FEXACT CCP Output Action on Fault Exit This field describes the resulting action of the signal generator upon exiting the fault condition. 0x19 0x3 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CCP_HIGHZ CCP output value is tristated 0x4 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 SWFRCACT_CMPL CCP_CMPL Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1E 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP_CMPL output value is set high 0x1 CCP_LOW CCP_CMPL output value is set low 0x2 2 4 0,1 TIMA0_CCACT_23[%s] Capture or Compare Action Registers 0x78 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 FENACT CCP Output Action on Fault Entry This field describes the resulting action of the signal generator upon detecting a fault. 0x16 0x3 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CCP_HIGHZ CCP output value is tristated 0x4 FEXACT CCP Output Action on Fault Exit This field describes the resulting action of the signal generator upon exiting the fault condition. 0x19 0x3 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CCP_HIGHZ CCP output value is tristated 0x4 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 SWFRCACT_CMPL CCP_CMPL Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1E 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP_CMPL output value is set high 0x1 CCP_LOW CCP_CMPL output value is set low 0x2 2 4 0,1 TIMA0_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 2 4 0,1 TIMA0_IFCTL_23[%s] Input Filter Control Register 0x88 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMA0_PL Counter Register 0xA0 32 read-write 0x00000000 0xffffffff PHASE Phase Load value 0x0 0x10 read-write TIMA0_DBCTL Dead Band insertion control register 0xA4 32 read-write RISEDELAY Rise Delay The number of TIMCLK periods inserted between the fall of CCPi and the rise of CCPAo. 0x0 0xC FALLDELAY Fall Delay The number of TIMCLK periods inserted between the fall of CCPi and the rise of CCPBo 0x10 0xC M1_ENABLE Dead Band Mode 1 Enable. 0xC 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 TIMA0_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 TIMA0_RC Repeat counter 0xB4 32 read-only 0x00000000 0xffffffff RC Repeat Counter Value 0x0 0x8 read-only TIMA0_RCLD Repeat counter 0xB8 32 read-write 0x00000000 0xffffffff RCLD Repeat Counter Load Value This field provides the value loaded into the repeat counter at a load event following the repeat counter value equaling 0. 0x0 0x8 read-write TIMA0_FCTL Fault Control Register 0xD0 32 read-write FIEN Fault Input Enable This bit enables the input for fault detection. 0x0 0x1 read-write DISABLED Fault Input Disabled 0x0 ENABLED Fault Input Enabled 0x1 FI Fault Input Specifies whether the overall fault condition is dependent on the sensed fault pin. 0x2 0x1 read-write INDEPENDENT Overall Fault condition is not dependent on sensed input. 0x0 DEPENDENT Overall Fault condition is dependent on sensed input. 0x1 TFIM Trigger Fault Input Mask Specifies whether the selected trigger participates as a fault input. If enabled and the trigger asserts, the trigger is treated as a fault. 0x7 0x1 read-write DISABLED Selected trigger does not participate in fault condition generation 0x0 ENABLED Selected trigger participates in fault condition generation 0x1 FL Fault Latch mode Specifies whether the fault condition is latched and configures the latch clear conditions. 0x3 0x2 read-write NO_LATCH Overall fault condition is not dependent on the F bit in RIS 0x0 LATCH_SW_CLR Overall fault condition is dependent on the F bit in RIS 0x1 LATCH_Z_CLR Fault condition is latched. Fault condition is cleared on a zero event if the fault input is 0. 0x2 LATCH_LD_CLR Fault condition is latched. Fault condition is cleared on a load event if the fault input is 0. 0x3 FSENAC0 Specifies whether the analog comparator0 fault sense is high or low active 0x8 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENAC1 Specifies whether the analog comparator1 fault sense is high or low active 0x9 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENAC2 Specifies whether the analog comparator2 fault sense is high or low active 0xA 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENEXT0 Specifies whether the external fault pin0 sense is high or low active 0xB 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENEXT1 Specifies whether the external fault pin1 fault sense is high or low active 0xC 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENEXT2 Specifies whether the external fault pin3 fault sense is high or low active 0xD 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 TIMA0_FIFCTL Fault input Filter control register 0xD4 32 read-write FP Filter Period This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x0 0x2 read-write PER_3 Filter Period 3 0x0 PER_5 Filter Period 5 0x1 PER_8 Filter Period 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0x3 0x1 read-write CONSEC_PER Consecutive Periods. The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 VOTING Voting. The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output 0x1 FILTEN Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to go directly to the optional pre-scale filter and then to the edge detect. 0x4 0x1 read-write BYPASS Bypass 0x0 FILTERED Filtered. 0x1 MATHACL MATHACL 1.0 PERIPHERALREGION 0x40410000 0x0 0x1500 registers 1 24 0 MATHACL_GPRCM[%s] 0x800 MATHACL_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 MATHACL_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 MATHACL_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 MATHACL_CTL Control Register 0x1100 32 read-write 0x00000000 FUNC ULP_ADCHP Enable Conversions. 0x0 0x5 read-write NOP No operation 0x0 SINCOS Sine and Cosine operation 0x1 ATAN2 Arc tangent with x and y values as operands. 0x2 DIV Divide, the operands are numerator, denominator, and the divide type. Result is the quotient and reminder. 0x4 SQRT Do square root. Operand is the number whoose square root needs to be computed. The number if outside the range needs to be scaled up down by 2 power 2n to bring it with in the range. 0x5 MPY32 32-bit Multiply Result 0x6 SQUARE32 32-bit square result 0x7 MPY64 64-bit multiply result 0x8 SQUARE64 64-bit multiply result 0x9 MAC Multiply and accumulate operation 0xA SAC Square and accumulate operation 0xB QVAL Indicates the fractional bits in the operands, ranges from 0 to 31. Applicable to DIV function. 0x8 0x5 read-write Q0 Q0 operands 0x0 Q1 Q1 operands 0x1 Q2 Q2 operands 0x2 Q3 Q3 operands 0x3 Q4 Q4 operands 0x4 Q5 Q5 operands 0x5 Q6 Q6 operands 0x6 Q7 Q7 operands 0x7 Q8 Q8 operands 0x8 Q9 Q9 operands 0x9 Q10 Q10 operands 0xA Q11 Q11 operands 0xB Q12 Q12 operands 0xC Q13 Q13 operands 0xD Q14 Q14 operands 0xE Q15 Q15 operands 0xF Q16 Q16 operands 0x10 Q17 Q17 operands 0x11 Q18 Q18 operands 0x12 Q19 Q19 operands 0x13 Q20 Q20 operands 0x14 Q21 Q21 operands 0x15 Q22 Q22 operands 0x16 Q23 Q23 operands 0x17 Q24 Q24 operands 0x18 Q25 Q25 operands 0x19 Q26 Q26 operands 0x1A Q27 Q27 operands 0x1B Q28 Q28 operands 0x1C Q29 Q29 operands 0x1D Q30 Q30 operands 0x1E Q31 Q31 operands 0x1F OPTYPE Operand type, could signed or unsigned. applicable to DIV function. 0x5 0x1 read-write UNSIGNED Unsigned operands 0x0 SIGNED Signed operands. 0x1 NUMITER Number of iterations, applicable if the function does the computations iteratively, for example sine/cosine/atan2/sqrt. Note: A value of 0 is interpreted as 31. 0x18 0x5 SFACTOR Scaling factor. In case of SQRT function, the input operand needs to be in a range. If not it has to be scaled to 2^(+/-n). This field should be written with the value 'n'. 0x10 0x6 SATEN Saturation enable This bit is shared among DIV, SQUARE32, MPY32, MAC and SAC functions. When enabled, it will make the result to saturate to maximum value in case of an overflow event When disabled, the result will overflow to an unknown value. 0x16 0x1 DISABLE Saturation is disabled 0x0 ENABLE Saturation is enabled 0x1 MATHACL_OP2 Operand 2 register. 0x1118 32 read-write 0x00000000 MATHACL_OP1 Operand 1 register. 0x111C 32 read-write 0x00000000 MATHACL_RES1 Result 1 register. 0x1120 32 read-write 0x00000000 MATHACL_RES2 Result 2 register. 0x1124 32 read-write 0x00000000 MATHACL_STATUS Status Register 0x1130 32 read-only 0x00000000 UF Underflow Flag 0x0 0x1 read-only NO_UNDERFLOW No undreflow error. 0x0 UNDERFLOW Underflow error. 0x1 OVF Overflow bit for MPY32, SQUARE32, DIV, MAC, and SAC functions This bit will be set on overflow and will retain its value until cleared by writing 1 into CLR.CLR_OVF 0x1 0x1 read-only ERR Incorrect inputs/outputs. 0x2 0x2 read-only NOERROR No Error in computation. 0x0 DIVBY0 DIVBY0 error 0x1 BUSY MATHACL busy bit. 0x8 0x1 read-only DONE Compute has completed. 0x0 NOTDONE Compute ongoing 0x1 MATHACL_STATUSCLR Status flag clear register 0x1140 32 write-only 0x00000000 CLR_OVF Write 1 to this bit to clear STATUS.OVF bit 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear STATUS.OVF 0x1 CLR_UF Write 1 to this bit to clear STATUS.UF bit 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear STATUS.UF 0x1 CLR_ERR Write 1 to this bit to clear STATUS.ERR field 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear STATUS.ERR 0x1 TIMG12 TIMG 1.0 PERIPHERALREGION 0x40870000 0x0 0x1F00 registers TIMG12_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG12_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG12_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG12_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMG12_GPRCM[%s] 0x800 TIMG12_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMG12_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMG12_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMG12_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMG12_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMG12_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMG12_INT_EVENT[%s] 0x1020 TIMG12_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMG12_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TIMG12_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG12_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD4 Compare down event generated an interrupt CCP4 0xC 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD5 Compare down event generated an interrupt CCP5 0xD 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU4 Compare up event generated an interrupt CCP4 0xE 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU5 Compare up event generated an interrupt CCP5 0xF 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG12_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMG12_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMG12_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMG12_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 32 0 TIMG12_COMMONREGS[%s] 0x1100 TIMG12_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMG12_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 TIMG12_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMG12_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMG12_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 1 180 0 TIMG12_COUNTERREGS[%s] 0x1800 TIMG12_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x20 read-write TIMG12_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMG12_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x20 read-write 2 4 0,1 TIMG12_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x20 read-write 2 4 0,1 TIMG12_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCUPD Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0). 0x12 0x3 read-write Immediately Writes to the CCx_y register is written to the register directly and has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCx_y register are stored in shadow register and transferred to ECCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LD. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. 0x6 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMG12_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMG12_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 2 4 0,1 TIMG12_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMG12_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 SPI0 SPI 1.0 PERIPHERALREGION 0x40468000 0x0 0x1F00 registers 1 24 0 SPI0_GPRCM[%s] 0x800 SPI0_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 SPI0_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 SPI0_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write DISABLE Not block async clock request 0x0 ENABLE Block async clock request 0x1 SPI0_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 SPI0_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 SPI0_CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 SYSCLK_SEL Selects SYSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 SPI0_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 SPI0_CPU_INT[%s] 0x1020 SPI0_CPU_INT_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RXFIFO_OFV_EVT RX FIFO Overflow Event/interrupt pending 0x1 PER_EVT Transmit Parity Event/interrupt pending 0x2 RTOUT_EVT SPI receive time-out interrupt 0x3 RX_EVT Receive Event/interrupt pending 0x4 TX_EVT Transmit Event/interrupt pending 0x5 TX_EMPTY Transmit Buffer Empty Event/interrupt pending 0x6 IDLE_EVT End of Transmit Event/interrupt pending 0x7 DMA_DONE_RX_EVT DMA Done for Receive Event/interrupt pending 0x8 DMA_DONE_TX_EVT DMA Done for Transmit Event/interrupt pending 0x9 TXFIFO_UNF_EVT TX FIFO underflow interrupt 0xA RXFULL_EVT RX FIFO Full Interrupt 0xB SPI0_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TX Transmit FIFO event mask. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXEMPTY Transmit FIFO Empty event mask. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PER Parity error event mask. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX DMA Done 1 event for RX event mask. 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFIFO_OVF RXFIFO overflow event mask. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX DMA Done 1 event for TX event mask. 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 IDLE SPI Idle event mask. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFULL RX FIFO Full Interrupt Mask 0xA 0x1 read-write CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXFIFO_UNF TX FIFO underflow interrupt mask 0x9 0x1 read-write CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI0_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TX Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 PER Parity error event: this bit is set if a Parity error has been detected 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_RX DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFIFO_OVF RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_TX DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 IDLE SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out event. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXFIFO_UNF TX FIFO Underflow Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFULL RX FIFO Full Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI0_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RX Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TX Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXEMPTY Masked Transmit FIFO Empty event. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 PER Masked Parity error event: this bit if a Parity error has been detected 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_RX Masked DMA Done 1 event for RX. 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFIFO_OVF Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_TX Masked DMA Done 1 event for TX. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 IDLE Masked SPI IDLE mode event. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT Masked SPI Receive Time-Out Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFULL RX FIFO Full Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXFIFO_UNF TX FIFO underflow interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI0_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 RX Set Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TX Set Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXEMPTY Set Transmit FIFO Empty event. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PER Set Parity error event. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done 1 event for RX. 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXFIFO_OVF Set RXFIFO overflow event. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done 1 event for TX. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 IDLE Set SPI IDLE mode event. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RTOUT Set SPI Receive Time-Out Event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt Mask 0x1 TXFIFO_UNF Set TX FIFO Underflow Event 0x9 0x1 NO_EFFECT Writing has no effect 0x0 SET Set interrupt 0x1 RXFULL Set RX FIFO Full Event 0xA 0x1 NO_EFFECT Writing has no effect 0x0 SET Set Interrupt 0x1 SPI0_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RX Clear Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TX Clear Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXEMPTY Clear Transmit FIFO Empty event. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PER Clear Parity error event. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done 1 event for RX. 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXFIFO_OVF Clear RXFIFO overflow event. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done 1 event for TX. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 IDLE Clear SPI IDLE mode event. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RTOUT Clear SPI Receive Time-Out Event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Set Interrupt Mask 0x1 TXFIFO_UNF Clear TXFIFO underflow event 0x9 0x1 NO_EFFECT Writing has no effect 0x0 CLR Clear interrupt 0x1 RXFULL Clear RX FIFO underflow event 0xA 0x1 NO_EFFECT Writing has no effect 0x0 CLR Clear interrupt 0x1 1 44 0 SPI0_DMA_TRIG_RX[%s] 0x1050 SPI0_DMA_TRIG_RX_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTOUT_EVT SPI receive time-out interrupt 0x3 RX_EVT Receive Event/interrupt pending 0x4 SPI0_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RX Receive FIFO event mask. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RTOUT SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI0_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out Event. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI0_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RX Receive FIFO event mask. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI0_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RX Set Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RTOUT Set SPI Receive Time-Out event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt Mask 0x1 SPI0_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RX Clear Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RTOUT Clear SPI Receive Time-Out event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Set Interrupt Mask 0x1 1 44 0 SPI0_DMA_TRIG_TX[%s] 0x1080 SPI0_DMA_TRIG_TX_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TX_EVT Transmit Event/interrupt pending 0x5 SPI0_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TX Transmit FIFO event mask. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI0_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TX Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI0_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TX Masked Transmit FIFO event 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI0_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TX Set Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 SPI0_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TX Clear Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 SPI0_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 SPI0_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 SPI0_CTL0 SPI control register 0 0x1100 32 read-write 0x00000000 DSS Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit 0x0 0x5 read-write DSS_4 Data Size Select bits: 4 0x3 DSS_5 Data Size Select bits: 5 0x4 DSS_6 Data Size Select bits: 6 0x5 DSS_7 Data Size Select bits: 7 0x6 DSS_8 Data Size Select bits: 8 0x7 DSS_9 Data Size Select bits: 9 0x8 DSS_10 Data Size Select bits: 10 0x9 DSS_11 Data Size Select bits: 11 0xA DSS_12 Data Size Select bits: 12 0xB DSS_13 Data Size Select bits: 13 0xC DSS_14 Data Size Select bits: 14 0xD DSS_15 Data Size Select bits: 15 0xE DSS_16 Data Size Select bits: 16 0xF FRF Frame format Select 0x5 0x2 read-write MOTOROLA_3WIRE Motorola SPI frame format (3 wire mode) 0x0 MOTOROLA_4WIRE Motorola SPI frame format (4 wire mode) 0x1 TI_SYNC TI synchronous serial frame format 0x2 MIRCOWIRE National Microwire frame format 0x3 SPO CLKOUT polarity (Motorola SPI frame format only) 0x8 0x1 read-write LOW SPI produces a steady state LOW value on the CLKOUT 0x0 HIGH SPI produces a steady state HIGH value on the CLKOUT 0x1 SPH CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 0x9 0x1 read-write FIRST Data is captured on the first clock edge transition. 0x0 SECOND Data is captured on the second clock edge transition. 0x1 CSSEL Select the CS line to control on data transfer This bit is applicable for both controller/target mode 0xC 0x2 read-write CSSEL_0 CS line select: 0 0x0 CSSEL_1 CS line select: 1 0x1 CSSEL_2 CS line select: 2 0x2 CSSEL_3 CS line select: 3 0x3 CSCLR Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.CP=0. 0xE 0x1 read-write DISABLE Disable automatic clear of shift register when CS goes to disable. 0x0 ENABLE Enable automatic clear of shift register when CS goes to disable. 0x1 PACKEN Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP 0x7 0x1 read-write DISABLED Packing feature disabled 0x0 ENABLED Packing feature enabled 0x1 SPI0_CTL1 SPI control register 1 0x1104 32 read-write 0x00000004 LBM Loop back mode 0x1 0x1 read-write DISABLE Disable loopback mode 0x0 ENABLE Enable loopback mode 0x1 CP Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0. 0x2 0x1 read-write DISABLE Select Peripheral mode 0x0 ENABLE Select Controller Mode 0x1 POD Peripheral-mode: Data output disabled This bit is relevant only in Peripheral mode. In multiple-peripheral system topologies, SPI controller can broadcast a message to all peripherals, while only one peripheral drives the line. POD can be used by the SPI peripheral to disable driving data on the line. 0x3 0x1 read-write DISABLE SPI can drive the MISO output in peripheral mode. 0x0 ENABLE SPI cannot drive the MISO output in peripheral mode. 0x1 MSB MSB first select. Controls the direction of the receive and transmit shift register. 0x4 0x1 read-write DISABLE LSB first 0x0 ENABLE MSB first 0x1 PREN Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set. 0x5 0x1 read-write DISABLE Disable Parity receive function 0x0 ENABLE Enable Parity receive function 0x1 REPEATTX Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral. 0x10 0x8 read-write DISABLE REPEATTX disable 0x0 PES Even Parity Select 0x6 0x1 read-write DISABLE Odd Parity mode 0x0 ENABLE Even Parity mode 0x1 CDMODE Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low. 0xC 0x4 read-write DATA Manual mode: Data 0x0 COMMAND Manual mode: Command 0xF ENABLE SPI enable 0x0 0x1 read-write DISABLE Disable module function 0x0 ENABLE Enable module function 0x1 RXTIMEOUT Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function. 0x18 0x6 read-write CDENABLE Command/Data Mode enable 0xB 0x1 read-write DISABLE CS3 is used for Chip Select 0x0 ENABLE CS3 is used as CD signal 0x1 PTEN Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes. 0x8 0x1 read-write DISABLE Parity transmission is disabled 0x0 ENABLE Parity transmission is enabled 0x1 SPI0_CLKCTL Clock prescaler and divider register. 0x1108 32 read-write 0x00000000 SCR Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023. 0x0 0xA read-write DSAMPLE Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations. 0x1C 0x4 read-write SPI0_IFLS Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000012 0xffffffff TXIFLSEL SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 0x0 0x3 read-write LVL_OFF Reserved 0x0 LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_RES4 Reserved 0x4 LVL_EMPTY TX FIFO is empty 0x5 LVL_RES6 Reserved 0x6 LEVEL_1 Trigger when TX FIFO has >= 1 frame free Should be used with DMA 0x7 RXIFLSEL SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: 0x3 0x3 read-write LVL_OFF Reserved 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_RES4 Reserved 0x4 LVL_FULL RX FIFO is full 0x5 LVL_RES6 Reserved 0x6 LEVEL_1 Trigger when RX FIFO contains >= 1 frame 0x7 SPI0_STAT Status Register 0x1110 32 read-only TFE Transmit FIFO empty. 0x0 0x1 NOT_EMPTY Transmit FIFO is not empty. 0x0 EMPTY Transmit FIFO is empty. 0x1 TNF Transmit FIFO not full 0x1 0x1 FULL Transmit FIFO is full. 0x0 NOT_FULL Transmit FIFO is not full. 0x1 RFE Receive FIFO empty. 0x2 0x1 NOT_EMPTY Receive FIFO is not empty. 0x0 EMPTY Receive FIFO is empty. 0x1 RNF Receive FIFO not full 0x3 0x1 FULL Receive FIFO is full. 0x0 NOT_FULL Receive FIFO is not full. 0x1 BUSY Busy 0x4 0x1 IDLE SPI is in idle mode. 0x0 ACTIVE SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty. 0x1 SPI0_RXDATA RXDATA Register 0x1130 32 read-only 0x00000000 DATA Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer. 0x0 0x10 read-only SPI0_TXDATA TXDATA Register 0x1140 32 read-write 0x00000000 DATA Transmit Data When read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. 0x0 0x10 read-write WUC WUC 1.0 PERIPHERALREGION 0x40424000 0x0 0x500 registers WUC_FSUB_0 Subscriber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 WUC_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 COMP2 COMP 1.0 PERIPHERALREGION 0x4000C000 0x0 0x1F00 registers COMP2_FSUB_0 Subscriber Port 0 0x400 32 read-write CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 COMP2_FSUB_1 Subscriber Port 1 0x404 32 read-write CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 COMP2_FPUB_1 Publisher port 1 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 COMP2_GPRCM[%s] 0x800 COMP2_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 COMP2_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 COMP2_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable disable COMP to request SYSOSC 0x0 Enable enable COMP to request SYSOSC 0x1 COMP2_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 1 44 0 COMP2_CPU_INT[%s] 0x1020 COMP2_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x2 read-only NO_INTR No pending interrupt 0x0 COMPIFG Comparator output interrupt 0x2 COMPINVIFG Comparator output inverted interrupt 0x3 OUTRDYIFG Comparator output ready interrupt 0x4 COMP2_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 COMPIFG Masks COMPIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMPINVIFG Masks COMPINVIFG 0x2 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 OUTRDYIFG Masks OUTRDYIFG 0x3 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMP2_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 COMPIFG Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x1 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMPINVIFG Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x2 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 OUTRDYIFG Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid. 0x3 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMP2_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 COMPIFG Masked interrupt status for COMPIFG 0x1 0x1 CLR COMPIFG does not request an interrupt service routine 0x0 SET COMPIFG requests an interrupt service routine 0x1 COMPINVIFG Masked interrupt status for COMPINVIFG 0x2 0x1 CLR COMPINVIFG does not request an interrupt service routine 0x0 SET COMPINVIFG requests an interrupt service routine 0x1 OUTRDYIFG Masked interrupt status for OUTRDYIFG 0x3 0x1 CLR OUTRDYIFG does not request an interrupt service routine 0x0 SET OUTRDYIFG requests an interrupt service routine 0x1 COMP2_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 COMPIFG Sets COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPIFG is set 0x1 COMPINVIFG Sets COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPINVIFG is set 0x1 OUTRDYIFG Sets OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to OUTRDYIFG is set 0x1 COMP2_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 COMPIFG Clears COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPIFG is cleared 0x1 COMPINVIFG Clears COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPINVIFG is cleared 0x1 OUTRDYIFG Clears OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to OUTRDYIFG is cleared 0x1 1 44 0 COMP2_GEN_EVENT[%s] 0x1050 COMP2_GEN_EVENT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x2 read-only NO_INTR No pending interrupt 0x0 COMPIFG Comparator output interrupt 0x2 COMPINVIFG Comparator output inverted interrupt 0x3 OUTRDYIFG Comparator output ready interrupt 0x4 COMP2_GEN_EVENT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 COMPIFG Masks COMPIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMPINVIFG Masks COMPINVIFG 0x2 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 OUTRDYIFG Masks OUTRDYIFG 0x3 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMP2_GEN_EVENT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 COMPIFG Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x1 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMPINVIFG Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x2 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 OUTRDYIFG Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid. 0x3 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMP2_GEN_EVENT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 COMPIFG Masked interrupt status for COMPIFG 0x1 0x1 CLR COMPIFG does not request an interrupt service routine 0x0 SET COMPIFG requests an interrupt service routine 0x1 COMPINVIFG Masked interrupt status for COMPINVIFG 0x2 0x1 CLR COMPINVIFG does not request an interrupt service routine 0x0 SET COMPINVIFG requests an interrupt service routine 0x1 OUTRDYIFG Masked interrupt status for OUTRDYIFG 0x3 0x1 CLR OUTRDYIFG does not request an interrupt service routine 0x0 SET OUTRDYIFG requests an interrupt service routine 0x1 COMP2_GEN_EVENT_ISET Interrupt set 0x20 32 write-only 0x00000000 COMPIFG Sets COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPIFG is set 0x1 COMPINVIFG Sets COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPINVIFG is set 0x1 OUTRDYIFG Sets OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to OUTRDYIFG is set 0x1 COMP2_GEN_EVENT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 COMPIFG Clears COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPIFG is cleared 0x1 COMPINVIFG Clears COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPINVIFG is cleared 0x1 OUTRDYIFG Clears OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to OUTRDYIFG is cleared 0x1 COMP2_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000009 INT0_CFG Event line mode select for event corresponding to CPU_INT 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to GEN_EVENT 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 COMP2_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 read-only MAJREV Major rev of the IP 0x4 0x4 read-only FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only COMP2_CTL0 Control 0 0x1100 32 read-write 0x00000000 IPSEL Channel input selected for the positive terminal of the comparator if IPEN is set to 1. 0x0 0x3 read-write CH_0 Channel 0 selected 0x0 CH_1 Channel 1 selected 0x1 CH_2 Channel 2 selected 0x2 CH_3 Channel 3 selected 0x3 CH_4 Channel 4 selected 0x4 CH_5 Channel 5 selected 0x5 CH_6 Channel 6 selected 0x6 CH_7 Channel 7 selected 0x7 IPEN Channel input enable for the positive terminal of the comparator. 0xF 0x1 read-write DISABLE Selected analog input channel for positive terminal is disabled 0x0 ENABLE Selected analog input channel for positive terminal is enabled 0x1 IMEN Channel input enable for the negative terminal of the comparator. 0x1F 0x1 read-write DISABLE Selected analog input channel for negative terminal is disabled 0x0 ENABLE Selected analog input channel for negative terminal is enabled 0x1 IMSEL Channel input selected for the negative terminal of the comparator if IMEN is set to 1. 0x10 0x3 read-write CH_0 Channel 0 selected 0x0 CH_1 Channel 1 selected 0x1 CH_2 Channel 2 selected 0x2 CH_3 Channel 3 selected 0x3 CH_4 Channel 4 selected 0x4 CH_5 Channel 5 selected 0x5 CH_6 Channel 6 selected 0x6 CH_7 Channel 7 selected 0x7 COMP2_CTL1 Control 1 0x1104 32 read-write 0x00000000 ENABLE This bit turns on the comparator. When the comparator is turned off it consumes no power. 0x0 0x1 read-write OFF Comparator is off 0x0 ON Comparator is on 0x1 MODE This bit selects the comparator operating mode. 0x1 0x1 read-write FAST Comparator is in fast mode 0x0 ULP Comparator is in ultra-low power mode 0x1 EXCH This bit exchanges the comparator inputs and inverts the comparator output. 0x2 0x1 read-write NO_EXC Comparator inputs not exchanged and output not inverted 0x0 EXC Comparator inputs exchanged and output inverted 0x1 SHORT This bit shorts the positive and negative input terminals of the comparator. 0x3 0x1 read-write NO_SHT Comparator positive and negative input terminals are not shorted 0x0 SHT Comparator positive and negative input terminals are shorted 0x1 IES This bit selected the interrupt edge for COMPIFG and COMPINVIFG. 0x4 0x1 read-write RISING Rising edge sets COMPIFG and falling edge sets COMPINVIFG 0x0 FALLING Falling edge sets COMPIFG and rising edge sets COMPINVIFG 0x1 HYST These bits select the hysteresis setting of the comparator. 0x5 0x2 read-write NO_HYS No hysteresis 0x0 LOW_HYS Low hysteresis, typical 10mV 0x1 MED_HYS Medium hysteresis, typical 20mV 0x2 HIGH_HYS High hysteresis, typical 30mV 0x3 OUTPOL This bit selects the comparator output polarity. 0x7 0x1 read-write NON_INV Comparator output is non-inverted 0x0 INV Comparator output is inverted 0x1 FLTEN This bit enables the analog filter at comparator output. 0x8 0x1 read-write DISABLE Comparator output filter is disabled 0x0 ENABLE Comparator output filter is enabled 0x1 FLTDLY These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings. 0x9 0x2 read-write DLY_0 Typical filter delay of 70 ns 0x0 DLY_1 Typical filter delay of 500 ns 0x1 DLY_2 Typical filter delay of 1200 ns 0x2 DLY_3 Typical filter delay of 2700 ns 0x3 WINCOMPEN This bit enables window comparator operation of comparator. 0xC 0x1 read-write OFF window comparator is disable 0x0 ON window comparator is enable 0x1 COMP2_CTL2 Control 2 0x1108 32 read-write 0x00000000 REFMODE This bit requests ULP_REF bandgap operation in fast mode(static) or low power mode (sampled). The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Fast mode operation offers higher accuracy but consumes higher current. Low power operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL > 0. 0x0 0x1 read-write STATIC ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in static mode. 0x0 SAMPLED ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in sampled mode. 0x1 REFSRC These bits select the reference source for the comparator. 0x3 0x3 read-write OFF Reference voltage generator is disabled (local reference buffer as well as DAC). 0x0 VDDA_DAC VDDA selected as the reference source to DAC and DAC output applied as reference to comparator. 0x1 VREF_DAC VREF selected as reference to DAC and DAC output applied as reference to comparator. 0x2 VREF In devices where internal VREF is buffered and hookedup to extrernal VREF pin, VREF applied as reference to comparator. DAC is switched off. Note: In LEGO_A3, DAC is turned off in this selection, in other deviced DAC is kept on. 0x3 VDDA VDDA is used as comparator reference. Note: In LEGO_A3, DAC is turned off in this selection, in other deviced DAC is kept on. 0x5 INTVREF_DAC Internal reference selected as the reference source to DAC and DAC output applied as reference to comparator. 0x6 INTVREF Internal VREF is used as the source of comparator. Not all devices will have this option. 0x7 REFSEL This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator. 0x7 0x1 read-write POSITIVE If EXCH bit is 0, the selected reference is applied to positive terminal. If EXCH bit is 1, the selected reference is applied to negative terminal. 0x0 NEGATIVE If EXCH bit is 0, the selected reference is applied to negative terminal. If EXCH bit is 1, the selected reference is applied to positive terminal. 0x1 DACCTL This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1. 0x10 0x1 read-write COMPOUT_SEL Comparator output controls selection between DACCODE0 and DACCODE1 0x0 DACSW_SEL DACSW bit controls selection between DACCODE0 and DACCODE1 0x1 DACSW This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1. 0x11 0x1 read-write DACCODE0_SEL DACCODE0 selected for 8-bit DAC 0x0 DACCODE1_SEL DACCODE1 selected for 8-bit DAC 0x1 BLANKSRC These bits select the blanking source for the comparator. 0x8 0x3 read-write DISABLE Blanking source disabled 0x0 BLANKSRC1 Select Blanking Source 1 0x1 BLANKSRC2 Select Blanking Source 2 0x2 BLANKSRC3 Select Blanking Source 3 0x3 BLANKSRC4 Select Blanking Source 4 0x4 BLANKSRC5 Select Blanking Source 5 0x5 BLANKSRC6 Select Blanking Source 6 0x6 SAMPMODE Enable sampled mode of comparator. 0x18 0x1 read-write DISABLE Sampled mode disabled 0x0 ENABLE Sampled mode enabled 0x1 COMP2_CTL3 Control 3 0x110C 32 read-write 0x00000000 DACCODE0 This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. 0x0 0x8 read-write DACCODE1 This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. 0x10 0x8 read-write COMP2_STAT Status 0x1120 32 read-only 0x00000000 OUT This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output. 0x0 0x1 read-only LOW Comparator output is low 0x0 HIGH Comparator output is high 0x1 I2C0 I2C 1.0 PERIPHERALREGION 0x400F0000 0x0 0x1F00 registers 1 24 0 I2C0_GPRCM[%s] 0x800 I2C0_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 I2C0_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 I2C0_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write DISABLE Not block async clock request 0x0 ENABLE Block async clock request 0x1 I2C0_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 I2C0_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 I2C0_CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 I2C0_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 I2C0_CPU_INT[%s] 0x1020 I2C0_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXDONEFG Controller data received 0x1 CTXDONEFG Controller data transmitted 0x2 CRXFIFOTRG Controller receive FIFO Trigger Level 0x3 CTXFIFOTRG Controller transmit FIFO Trigger level 0x4 CRXFIFOFULL RX FIFO FULL Event/interrupt pending 0x5 CTX_EMPTY Transmit FIFO/Buffer Empty Event/interrupt pending 0x6 CNACKFG Address/Data NACK 0x8 CSTARTFG Start Event 0x9 CSTOPFG Stop Event 0xA CARBLOSTFG Arbitration Lost 0xB CDMA_DONE_TX DMA DONE on Channel TX 0xC CDMA_DONE_RX DMA DONE on Channel RX 0xD CPEC_RX_ERR Controller PEC Receive Error Event 0xE TIMEOUTA Timeout A Event 0xF TIMEOUTB Timeout B Event 0x10 TRXDONEFG Target Data Event 0x11 TTXDONEFG Target Data Event 0x12 TRXFIFOTRG Target receive FIFO Trigger Level 0x13 TTXFIFOTRG Target transmit FIFO Trigger level 0x14 TRXFIFOFULL RX FIFO FULL Event/interrupt pending 0x15 TTXEMPTY Transmit FIFO/Buffer Empty Event/interrupt pending 0x16 TSTARTFG Start Event 0x17 TSTOPFG Stop Event 0x18 TGENCALL General Call Event 0x19 TDMA_DONE_TX DMA DONE on Channel TX 0x1A TDMA_DONE_RX DMA DONE on Channel RX 0x1B TPEC_RX_ERR Target PEC receive error event 0x1C TTX_UNFL Target TX FIFO underflow 0x1D TRX_OVFL Target RX FIFO overflow event 0x1E TARBLOST Target arbitration lost event 0x1F INTR_OVFL Interrupt overflow event 0x20 I2C0_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXDONE Controller Receive Transaction completed Interrupt 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXEMPTY Target Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an Target RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TSTART Start Condition Interrupt 0x16 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TDMA_DONE_TX Target DMA Done on Event Channel TX 0x19 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TDMA_DONE_RX Target DMA Done on Event Channel RX 0x1A 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Clear Set Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 INTR_OVFL Interrupt Overflow Interrupt Mask 0x1F 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_CPU_INT_RIS Raw interrupt status 0x10 32 read-only CRXDONE Controller Receive Transaction completed Interrupt 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TSTART Start Condition Interrupt 0x16 0x1 CLR Clear interrupt 0x0 SET Set Interrupt 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 CLR Clear Interrupt 0x0 SET Set interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 CLR Clear interrupt 0x0 SET Set interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 CLR Clear interrupt 0x0 SET Set interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt Occured 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Interrupt did not occur 0x0 SET Interrupt ocuured 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Interrupt did not occur 0x0 SET Interrupt Occured 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INTR_OVFL Interrupt overflow interrupt It is set when CSTART or CSTOP interrupts overflow i.e. occur twice without being serviced 0x1F 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 I2C0_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXDONE Controller Receive Data Interrupt 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if the RX FIFO is full. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TSTART Target START Detection Interrupt 0x16 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TSTOP Target STOP Detection Interrupt 0x17 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 I2C0_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXDONE Controller Receive Data Interrupt Signals that a byte has been received 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TIMEOUTA Timeout A interrupt 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CSTART START Detection Interrupt 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CRXFIFOFULL RXFIFO full event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TGENCALL General Call Interrupt 0x18 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TSTART Start Condition Interrupt 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 NO_EFFECT No effect 0x0 SET Set interrupt 0x1 I2C0_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXDONE Controller Receive Data Interrupt Signals that a byte has been received 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TIMEOUTA Timeout A interrupt 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CSTART START Detection Interrupt 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CRXFIFOFULL RXFIFO full event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TGENCALL General Call Interrupt 0x18 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TSTART Target START Detection Interrupt 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TSTOP Target STOP Detection Interrupt 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clear interrupt 0x1 1 44 0 I2C0_DMA_TRIG1[%s] 0x1050 I2C0_DMA_TRIG1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXFIFOTRG Controller receive FIFO Trigger Level 0x1 CTXFIFOTRG Controller transmit FIFO Trigger level 0x2 TRXFIFOTRG Target receive FIFO Trigger Level 0x3 TTXFIFOTRG Target transmit FIFO Trigger level 0x4 I2C0_DMA_TRIG1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_DMA_TRIG1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_DMA_TRIG1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_DMA_TRIG1_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_DMA_TRIG1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 1 44 0 I2C0_DMA_TRIG0[%s] 0x1080 I2C0_DMA_TRIG0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXFIFOTRG Controller receive FIFO Trigger Level 0x1 CTXFIFOTRG Controller transmit FIFO Trigger level 0x2 TRXFIFOTRG Target receive FIFO Trigger Level 0x3 TTXFIFOTRG Target transmit FIFO Trigger level 0x4 I2C0_DMA_TRIG0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_DMA_TRIG0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_DMA_TRIG0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_DMA_TRIG0_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C0_DMA_TRIG0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 I2C0_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG0] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 I2C0_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 I2C0_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 I2C0_GFCTL I2C Glitch Filter Control 0x1200 32 read-write AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only) 0x9 0x2 read-write AGLIT_5 Pulses shorter then 5ns length are filtered. 0x0 AGLIT_10 Pulses shorter then 10ns length are filtered. 0x1 AGLIT_25 Pulses shorter then 25ns length are filtered. 0x2 AGLIT_50 Pulses shorter then 50ns length are filtered. 0x3 DGFSEL Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only) 0x0 0x3 read-write DISABLED Bypass 0x0 CLK_1 1 clock 0x1 CLK_2 2 clocks 0x2 CLK_3 3 clocks 0x3 CLK_4 4 clocks 0x4 CLK_8 8 clocks 0x5 CLK_16 16 clocks 0x6 CLK_31 31 clocks 0x7 AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write DISABLE Analog Glitch Filter disable 0x0 ENABLE Analog Glitch Filter enable 0x1 CHAIN Analog and digital noise filters chaining enable. 0xB 0x1 DISABLE When 0, chaining is disabled and only digital filter output is available to IP logic for oversampling 0x0 ENABLE When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for oversampling 0x1 I2C0_TIMEOUT_CTL I2C Timeout Count Control Register 0x1204 32 read-write 0x00020002 0xffffffff TCNTLA Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us. 0x0 0x8 read-write TCNTAEN Timeout Counter A Enable 0xF 0x1 read-write DISABLE Disable Timeout Counter B 0x0 ENABLE Enable Timeout Counter B 0x1 TCNTLB Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns. 0x10 0x8 read-write TCNTBEN Timeout Counter B Enable 0x1F 0x1 read-write DISABLE Disable Timeout Counter B 0x0 ENABLE Enable Timeout Counter B 0x1 I2C0_TIMEOUT_CNT I2C Timeout Count Register 0x1208 32 read-only 0x00020002 0xffffffff TCNTA Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A 0x0 0x8 read-only TCNTB Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B 0x10 0x8 1 56 0 I2C0_CONTROLLER[%s] 0x1210 I2C0_CSA I2C Controller Target Address Register 0x0 32 read-write 0x00000000 DIR Receive/Send The DIR bit specifies if the next Controller operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive 0x0 0x1 TRANSMIT The Controller is in transmit mode. 0x0 RECEIVE The Controller is in receive mode. 0x1 TADDR I2C Target Address This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care 0x1 0xA CMODE This bit selects the adressing mode to be used in Controller mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 MODE7 7-bit addressing mode 0x0 MODE10 10-bit addressing mode 0x1 I2C0_CCTR I2C Controller Control Register 0x4 32 read-write 0x00000000 0xffffffff BURSTRUN I2C Controller Enable and start transaction 0x0 0x1 read-write DISABLE In standard mode, this encoding means the Controller is unable to transmit or receive data. 0x0 ENABLE The Controller is able to transmit or receive data. 0x1 START Generate START 0x1 0x1 read-write DISABLE The controller does not generate the START condition. 0x0 ENABLE The controller generates the START or repeated START condition. 0x1 STOP Generate STOP 0x2 0x1 read-write DISABLE The controller does not generate the STOP condition. 0x0 ENABLE The controller generates the STOP condition. 0x1 ACK Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. 0x3 0x1 read-write DISABLE The last received data byte of a transaction is not acknowledged automatically by the Controller. 0x0 ENABLE The last received data byte of a transaction is acknowledged automatically by the Controller. 0x1 CBLEN I2C transaction length This field contains the programmed length of bytes of the Transaction. 0x10 0xC read-write CACKOEN Controller ACK overrride Enable 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When 1 and the Controller is receiving data and the number of bytes indicated in MBLEN have been received, the state machine will generate an rxdone interrupt and wait at the start of the ACK for FW to indicate if an ACK or NACK should be sent. The ACK or NACK is selected by writing the MCTR register and setting ACK accordingly. The other fields in this register can also be written at this time to continue on with the transaction. If a NACK is sent the state machine will automatically send a Stop. 0x1 RD_ON_TXEMPTY Read on TX Empty 0x5 0x1 DISABLE No special behavior 0x0 ENABLE When 1 the Controller will transmit all bytes from the TX FIFO before continuing with the programmed Burst Run Read. If the DIR is not set to Read in the MSA then this bit is ignored. The Start must be set in the MCTR for proper I2C protocol. The Controller will first send the Start Condition, I2C Address with R/W bit set to write, before sending the bytes in the TX FIFO. When the TX FIFO is empty, the I2C transaction will continue as programmed in MTCR and MSA without sending a Stop Condition. This is intended to be used to perform simple I2C command based reads transition that will complete after initiating them without having to get an interrupt to turn the bus around. 0x1 I2C0_CSR I2C Controller Status Register 0x8 32 read-only BUSY I2C Controller FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction. 0x0 0x1 read-only CLEARED The controller is idle. 0x0 SET The controller is busy. 0x1 ERR Error The error can be from the Target address not being acknowledged or the transmit data not being acknowledged. 0x1 0x1 read-only CLEARED No error was detected on the last operation. 0x0 SET An error occurred on the last operation. 0x1 ADRACK Acknowledge Address 0x2 0x1 read-only CLEARED The transmitted address was acknowledged 0x0 SET The transmitted address was not acknowledged. 0x1 DATACK Acknowledge Data 0x3 0x1 read-only CLEARED The transmitted data was acknowledged 0x0 SET The transmitted data was not acknowledged. 0x1 ARBLST Arbitration Lost 0x4 0x1 read-only CLEARED The I2C controller won arbitration. 0x0 SET The I2C controller lost arbitration. 0x1 IDLE I2C Idle 0x5 0x1 read-only CLEARED The I2C controller is not idle. 0x0 SET The I2C controller is idle. 0x1 BUSBSY I2C Bus is Busy Controller State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0x6 0x1 read-only CLEARED The I2C bus is idle. 0x0 SET 'This Status bit is set on a START or when SCL goes low. It is cleared on a STOP, or when a SCL high bus busy timeout occurs and SCL and SDA are both high. This status is cleared when the ACTIVE bit is low. Note that the Controller State Machine will wait until this bit is cleared before starting an I2C transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0x1 CBCNT I2C Controller Transaction Count This field contains the current count-down value of the transaction. 0x10 0xC read-only I2C0_CRXDATA I2C Controller RXData 0xC 32 read-only 0x00000000 0xffffffff VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only I2C0_CTXDATA I2C Controller TXData 0x10 32 read-write 0x00000000 0xffffffff VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write I2C0_CTPR I2C Controller Timer Period 0x14 32 read-write 0x00000001 0xffffffff TPR Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns. 0x0 0x7 read-write I2C0_CCR I2C Controller Configuration 0x18 32 read-write 0x00000000 0xffffffff LPBK I2C Loopback 0x8 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The controller in a test mode loopback configuration. 0x1 MCTL MultiController mode. In MultiController mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller. 0x1 0x1 read-write DISABLE Disable MultiController mode. 0x0 ENABLE Enable MultiController mode. 0x1 ACTIVE Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0x0 0x1 read-write DISABLE Disables the I2C Controller operation. 0x0 ENABLE Enables the I2C Controller operation. 0x1 CLKSTRETCH Clock Stretching. This bit controls the support for clock stretching of the I2C bus. 0x2 0x1 read-write DISABLE Disables the clock stretching detection. This can be disabled if no Target on the bus does support clock stretching, so that the maximum speed on the bus can be reached. 0x0 ENABLE Enables the clock stretching detection. Enabling the clock stretching ensures compliance to the I2C standard but could limit the speed due the clock stretching. 0x1 I2C0_CBMON I2C Controller Bus Monitor 0x24 32 read-only 0x00000003 0xffffffff SCL I2C SCL Status 0x0 0x1 read-only CLEARED The I2CSCL signal is low. 0x0 SET The I2CSCL signal is high. Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations. 0x1 SDA I2C SDA Status 0x1 0x1 read-only CLEARED The I2CSDA signal is low. 0x0 SET The I2CSDA signal is high. Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations. 0x1 I2C0_CFIFOCTL I2C Controller FIFO Control 0x28 32 read-write 0x00000000 TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 EMPTY Trigger when the TX FIFO is empty. 0x0 LEVEL_1 Trigger when TX FIFO contains 1 byte 0x1 LEVEL_2 Trigger when TX FIFO contains 2 byte 0x2 LEVEL_3 Trigger when TX FIFO contains 3 byte 0x3 LEVEL_4 Trigger when TX FIFO contains 4 byte 0x4 LEVEL_5 Trigger when TX FIFO contains 5 byte 0x5 LEVEL_6 Trigger when TX FIFO contains 6 byte 0x6 LEVEL_7 Trigger when TX FIFO contains 7 byte 0x7 TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 LEVEL_1 Trigger when RX FIFO contains >= 1 byte 0x0 LEVEL_2 Trigger when RX FIFO contains >= 2 byte 0x1 LEVEL_3 Trigger when RX FIFO contains >= 3 byte 0x2 LEVEL_4 Trigger when RX FIFO contains >= 4 byte 0x3 LEVEL_5 Trigger when RX FIFO contains >= 5 byte 0x4 LEVEL_6 Trigger when RX FIFO contains >= 6 byte 0x5 LEVEL_7 Trigger when RX FIFO contains >= 7 byte 0x6 LEVEL_8 Trigger when RX FIFO contains >= 8 byte 0x7 RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 I2C0_CFIFOSR I2C Controller FIFO Status Register 0x2C 32 read-only 0x00000800 RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 I2C0_CONTROLLER_I2CPECCTL I2C Controller PEC control register 0x30 32 read-write 0x00000000 0xffffffff PECCNT PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Controller use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Target Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the Controller_I2CPECCTL Register will clear the current PEC Byte Count in the Controller State Machine. 0x0 0x9 PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits except the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 DISABLE PEC is disabled in Controller mode 0x0 ENABLE PEC is enabled in Controller mode 0x1 I2C0_CONTROLLER_PECSR I2C Controller PEC status register 0x34 32 read-only 0x00000000 0xffffffff PECBYTECNT PEC Byte Count This is the current PEC Byte Count of the Controller State Machine. 0x0 0x9 PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 CLEARED Indicates PEC was not checked in the transaction that occurred before the last Stop 0x0 SET Indicates if the PEC was checked in the transaction that occurred before the last Stop 0x1 PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 CLEARED Indicates PEC check error did not occurr in the transaction that occurred before the last Stop 0x0 SET Indicates if a PEC check error occurred in the transaction that occurred before the last Stop 0x1 1 44 0 I2C0_TARGET[%s] 0x1250 I2C0_TOAR I2C Target Own Address 0x0 32 read-write 0x00004000 0xffffffff OAR I2C Target Own Address: This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care 0x0 0xA read-write OAREN I2C Target Own Address Enable 0xE 0x1 DISABLE Disable OAR address 0x0 ENABLE Enable OAR address 0x1 TMODE This bit selects the adressing mode to be used in Target mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 MODE7 Enable 7-bit addressing 0x0 MODE10 Enable 10-bit addressing 0x1 I2C0_TOAR2 I2C Target Own Address 2 0x4 32 read-write 0x00000000 0xffffffff OAR2 I2C Target Own Address 2 This field specifies the alternate OAR2 address. 0x0 0x7 read-write OAR2EN I2C Target Own Address 2 Enable 0x7 0x1 read-write DISABLE The alternate address is disabled. 0x0 ENABLE Enables the use of the alternate address in the OAR2 field. 0x1 OAR2_MASK I2C Target Own Address 2 Mask: This field specifies bits A6 through A0 of the Target address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care. 0x10 0x7 I2C0_TCTR I2C Target Control Register 0x8 32 read-write 0x00000404 0xffffffff ACTIVE Device Active. Setting this bit enables the Target functionality. 0x0 0x1 read-write DISABLE Disables the I2C Target operation. 0x0 ENABLE Enables the I2C Target operation. 0x1 GENCALL General call response enable Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call 0x1 0x1 read-write DISABLE Do not respond to a general call 0x0 ENABLE Respond to a general call 0x1 TCLKSTRETCH Target Clock Stretch Enable 0x2 0x1 DISABLE Target clock stretching is disabled 0x0 ENABLE Target clock stretching is enabled 0x1 TXEMPTY_ON_TREQ Tx Empty Interrupt on TREQ 0x3 0x1 DISABLE When 0, RIS:TTXEMPTY will be set when only the Target TX FIFO is empty. This allows the TTXEMPTY interrupt to be used to indicate that the I2C bus is being clock stretched and that Target TX data is required. 0x0 ENABLE When 1, RIS:TTXEMPTY will be set when the Target State Machine is in the TX_WAIT state which occurs when the TX FIFO is empty AND the I2C transaction is clock stretched waiting for the FIFO to receive data. 0x1 TXTRIG_TXMODE Tx Trigger when Target FSM is in Tx Mode 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When 1, RIS:TXFIFOTRG will be set when the Target TX FIFO has reached the trigger level AND the Target State Machine is in the TXMODE as defined in the SSR register. When cleared RIS:TXFIFOTRG will be set when the Target TX FIFO is at or above the trigger level. This setting can be used to hold off the TX DMA until a transaction starts. This allows the DMA to be configured when the I2C is idle but have it wait till the transaction starts to load the Target TX FIFO, so it can load from a memory buffer that might be changing over time. 0x1 TXWAIT_STALE_TXFIFO Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Target State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale. 0x5 0x1 DISABLE When 0, the TX FIFO empty signal to the Target State Machine indicates that the TX FIFO is empty. 0x0 ENABLE When 1, the TX FIFO empty signal to the Target State Machine will indicate that the TX FIFO is empty or that the TX FIFO data is stale. The TX FIFO data is determined to be stale when there is data in the TX FIFO when the Target State Machine leaves the TXMODE as defined in the SSR register. This can occur is a Stop or timeout occur when there are bytes left in the TX FIFO. 0x1 RXFULL_ON_RREQ Rx full interrupt generated on RREQ condition as indicated in SSR 0x6 0x1 DISABLE When 0, RIS:TRXFULL will be set when only the Target RX FIFO is full. This allows the TRXFULL interrupt to be used to indicate that the I2C bus is being clock stretched and that the FW must either read the RX FIFO or ACK/NACK the current Rx byte. 0x0 ENABLE When 1, RIS:TRXFULL will be set when the Target State Machine is in the RX_WAIT or RX_ACK_WAIT states which occurs when the I2C transaction is clock stretched because the RX FIFO is full or the ACKOEN has been set and the state machine is waiting for FW to ACK/NACK the current byte. 0x1 EN_DEFHOSTADR Enable Default Host Address 0x7 0x1 DISABLE When this bit is 0, the default host address is not matched NOTE: it may still be matched if programmed inside SOAR/SOAR2 0x0 ENABLE When this bit is 1, default host address of 7h000_1000 is always matched by the Target address match logic. 0x1 EN_ALRESPADR Enable Alert Response Address 0x8 0x1 DISABLE When this bit is 0, the alert response address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2 0x0 ENABLE When this bit is 1, alert response address of 7h000_1100 is always matched by the Target address match logic. 0x1 EN_DEFDEVADR Enable Deault device address 0x9 0x1 DISABLE When this bit is 0, the default device address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2. 0x0 ENABLE When this bit is 1, default device address of 7h110_0001 is always matched by the Target address match logic. 0x1 TWUEN Target Wakeup Enable 0xA 0x1 DISABLE When 0, the Target is not allowed to clock stretch on START detection 0x0 ENABLE When 1, the Target is allowed to clock stretch on START detection and wait for faster clock to be abvailable. This allows clean wake up support for I2C in low power mode use cases 0x1 I2C0_TSR I2C Target Status Register 0xC 32 read-only 0x00000000 0xffffffff RREQ Receive Request 0x0 0x1 read-only CLEARED No outstanding receive data. 0x0 SET The I2C controller has outstanding receive data from the I2C Controller and is using clock stretching to delay the Controller until the data has been read from the TRXDATA FIFO (Target RX FIFO is full). 0x1 TREQ Transmit Request 0x1 0x1 read-only CLEARED No outstanding transmit request. 0x0 SET The I2C controller has been addressed as a Target transmitter and is using clock stretching to delay the Controller until data has been written to the TTXDATA FIFO (Target TX FIFO is empty). 0x1 OAR2SEL OAR2 Address Matched This bit gets reevaluated after every address comparison. 0x3 0x1 read-only CLEARED Either the OAR2 address is not matched or the match is in legacy mode. 0x0 SET OAR2 address matched and ACKed by the Target. 0x1 QCMDST Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction 0x4 0x1 read-only CLEARED The last transaction was a normal transaction or a transaction has not occurred. 0x0 SET The last transaction was a Quick Command transaction. 0x1 QCMDRW Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read 0x5 0x1 read-only CLEARED Quick command was a write 0x0 SET Quick command was a read 0x1 RXMODE Target FSM is in Rx MODE 0x2 0x1 CLEARED The Target State Machine is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. 0x0 SET The Target State Machine is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. 0x1 BUSBSY I2C bus is busy 0x6 0x1 CLEARED The I2C Bus is not busy 0x0 SET The I2C Bus is busy. This is cleared on a timeout. 0x1 TXMODE Target FSM is in TX MODE 0x7 0x1 CLEARED The Target State Machine is not in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. 0x0 SET The Target State Machine is in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. 0x1 STALE_TXFIFO Stale Tx FIFO 0x8 0x1 CLEARED Tx FIFO is not stale 0x0 SET The TX FIFO is stale. This occurs when the TX FIFO was not emptied during the previous I2C transaction. 0x1 ADDRMATCH Indicates the address for which Target address match happened 0x9 0xA I2C0_TRXDATA I2C Target RXData 0x10 32 read-only 0x00000000 0xffffffff VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only I2C0_TTXDATA I2C Target TXData 0x14 32 read-write 0x00000000 0xffffffff VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write I2C0_TACKCTL I2C Target ACK Control 0x18 32 read-write 0x00000000 0xffffffff ACKOEN I2C Target ACK Override Enable 0x0 0x1 read-write DISABLE A response in not provided. 0x0 ENABLE An ACK or NACK is sent according to the value written to the ACKOVAL bit. 0x1 ACKOVAL I2C Target ACK Override Value Note: for General Call this bit will be ignored if set to NACK and Target continues to receive data. 0x1 0x1 read-write DISABLE An ACK is sent indicating valid data or command. 0x0 ENABLE A NACK is sent indicating invalid data or command. 0x1 ACKOEN_ON_START When set this bit will automatically turn on the Target ACKOEN field following a Start Condition. 0x2 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following a Start Condition. 0x1 ACKOEN_ON_PECNEXT When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing Target_SACKCTL. 0x3 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing Target_SACKCTL. 0x1 ACKOEN_ON_PECDONE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte. 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte. 0x1 I2C0_TFIFOCTL I2C Target FIFO Control 0x1C 32 read-write 0x00000000 TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 LEVEL_4 Trigger when TX FIFO contains 4 byte 0x4 LEVEL_5 Trigger when TX FIFO contains 5 byte 0x5 LEVEL_6 Trigger when TX FIFO contains 6 byte 0x6 LEVEL_7 Trigger when TX FIFO contains 7 byte 0x7 TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 LEVEL_5 Trigger when RX FIFO contains >= 5 byte 0x4 LEVEL_6 Trigger when RX FIFO contains >= 6 byte 0x5 LEVEL_7 Trigger when RX FIFO contains >= 7 byte 0x6 LEVEL_8 Trigger when RX FIFO contains >= 8 byte 0x7 I2C0_TFIFOSR I2C Target FIFO Status Register 0x20 32 read-only 0x00000800 RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 INACTIVE FIFOFlush not active 0x0 ACTIVE FIFO Flush active 0x1 I2C0_TARGET_PECCTL I2C Target PEC control register 0x24 32 read-write 0x00000000 0xffffffff PECCNT When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Target use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction 0x0 0x9 PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits except the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 DISABLE PEC transmission and check is disabled 0x0 ENABLE PEC transmission and check is enabled 0x1 I2C0_TARGET_PECSR I2C Target PEC status register 0x28 32 read-only 0x00000000 0xffffffff PECBYTECNT This is the current PEC Byte Count of the Target State Machine. 0x0 0x9 PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 CLEARED Indicates PEC was not checked in the transaction that occurred before the last Stop 0x0 SET Indicates PEC was checked in the transaction that occurred before the last Stop 0x1 PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 CLEARED Indicates PEC check error did not occurr in the transaction that occurred before the last Stop 0x0 SET Indicates PEC check error occurred in the transaction that occurred before the last Stop 0x1 CPUSS CPUSS 1.0 CPUSSMMR 0x40400000 0x0 0x1F00 registers CPUSS_EVT_MODE Event Mode 0x10E0 32 read-only INT_CFG Event line mode select 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 CPUSS_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 read-only MAJREV Major rev of the IP 0x4 0x4 read-only FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only 1 44 0 CPUSS_CPU_INT_GROUP0[%s] 0x1100 CPUSS_CPU_INT_GROUP0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No pending interrupt 0x0 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x3 INT3 Interrupt 3 0x4 INT4 Interrupt 4 0x5 INT5 Interrupt 5 0x6 INT6 Interrupt 6 0x7 INT7 Interrupt 7 0x8 CPUSS_CPU_INT_GROUP0_IMASK Interrupt mask 0x8 32 read-only 0x000000ff INT Masks the corresponding interrupt 0x0 0x8 read-only INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CPU_INT_GROUP0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INT Raw interrupt status for INT 0x0 0x8 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CPU_INT_GROUP0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INT Masked interrupt status for INT0 0x0 0x8 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CPU_INT_GROUP0_ISET Interrupt set 0x20 32 write-only 0x00000000 INT Sets INT in RIS register 0x0 0x8 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CPU_INT_GROUP0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INT Clears INT in RIS register 0x0 0x8 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 1 44 0 CPUSS_CPU_INT_GROUP1[%s] 0x1130 CPUSS_CPU_INT_GROUP1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No pending interrupt 0x0 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x3 INT3 Interrupt 3 0x4 INT4 Interrupt 4 0x5 INT5 Interrupt 5 0x6 INT6 Interrupt 6 0x7 INT7 Interrupt 7 0x8 CPUSS_CPU_INT_GROUP1_IMASK Interrupt mask 0x8 32 read-only 0x000000ff INT Masks the corresponding interrupt 0x0 0x8 read-only INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CPU_INT_GROUP1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INT Raw interrupt status for INT 0x0 0x8 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CPU_INT_GROUP1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INT Masked interrupt status for INT0 0x0 0x8 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CPU_INT_GROUP1_ISET Interrupt set 0x20 32 write-only 0x00000000 INT Sets INT in RIS register 0x0 0x8 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CPU_INT_GROUP1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INT Clears INT in RIS register 0x0 0x8 INT0 Interrupt 0 0x1 INT1 Interrupt 1 0x2 INT2 Interrupt 2 0x4 INT3 Interrupt 3 0x8 INT4 Interrupt 4 0x10 INT5 Interrupt 5 0x20 INT6 Interrupt 6 0x40 INT7 Interrupt 7 0x80 CPUSS_CTL Prefetch/Cache control 0x1300 32 read-write 0x00000007 PREFETCH Used to enable/disable instruction prefetch to Flash. 0x0 0x1 read-write DISABLE Disable instruction prefetch. 0x0 ENABLE Enable instruction prefetch. 0x1 ICACHE Used to enable/disable Instruction caching on flash access. 0x1 0x1 read-write DISABLE Disable instruction caching. 0x0 ENABLE Enable instruction caching. 0x1 LITEN Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals 0x2 0x1 read-write DISABLE Literal caching disabled 0x0 ENABLE Literal caching enabled 0x1 GPIOA GPIOA 1.0 PERIPHERALREGION 0x400A0000 0x0 0x1F00 registers GPIOA_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOA_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOA_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOA_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 GPIOA_GPRCM[%s] 0x800 GPIOA_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 GPIOA_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 GPIOA_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 GPIOA_CLKOVR Clock Override 0x1010 32 read-write 0x00000000 OVERRIDE Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request 0x0 0x1 read-write DISABLED Override disabled 0x0 ENABLED Override enabled 0x1 RUN_STOP If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system 0x1 0x1 read-write RUN Run/ungate functional clock 0x0 STOP Stop/gate functional clock 0x1 GPIOA_PDBGCTL Peripheral Debug Control 0x1018 32 read-write 0x00000001 FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 1 44 0 GPIOA_CPU_INT[%s] 0x1020 GPIOA_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO0 DIO0 interrupt 0x1 DIO1 DIO1 interrupt 0x2 DIO2 DIO2 interrupt 0x3 DIO3 DIO3 interrupt 0x4 DIO4 DIO4 interrupt 0x5 DIO5 DIO5 interrupt 0x6 DIO6 DIO6 interrupt 0x7 DIO7 DIO7 interrupt 0x8 DIO8 DIO8 interrupt 0x9 DIO9 DIO9 interrupt 0xA DIO10 DIO10 interrupt 0xB DIO11 DIO11 interrupt 0xC DIO12 DIO12 interrupt 0xD DIO13 DIO13 interrupt 0xE DIO14 DIO14 interrupt 0xF DIO15 DIO15 interrupt 0x10 DIO16 DIO16 interrupt 0x11 DIO17 DIO17 interrupt 0x12 DIO18 DIO18 interrupt 0x13 DIO19 DIO19 interrupt 0x14 DIO20 DIO20 interrupt 0x15 DIO21 DIO21 interrupt 0x16 DIO22 DIO22 interrupt 0x17 DIO23 DIO23 interrupt 0x18 DIO24 DIO24 interrupt 0x19 DIO25 DIO25 interrupt 0x1A DIO26 DIO26 interrupt 0x1B DIO27 DIO27 interrupt 0x1C DIO28 DIO28 interrupt 0x1D DIO29 DIO29 interrupt 0x1E DIO30 DIO30 interrupt 0x1F DIO31 DIO31 interrupt 0x20 GPIOA_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO0 DIO0 event mask 0x0 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO1 DIO1 event mask 0x1 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO2 DIO2 event mask 0x2 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO3 DIO3 event mask 0x3 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO4 DIO4 event mask 0x4 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO5 DIO5 event mask 0x5 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO6 DIO6 event mask 0x6 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO7 DIO7 event mask 0x7 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO8 DIO8 event mask 0x8 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO9 DIO9 event mask 0x9 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO10 DIO10 event mask 0xA 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO11 DIO11 event mask 0xB 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO12 DIO12 event mask 0xC 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO13 DIO13 event mask 0xD 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO14 DIO14 event mask 0xE 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO15 DIO15 event mask 0xF 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO16 DIO16 event mask 0x10 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO17 DIO17 event mask 0x11 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO18 DIO18 event mask 0x12 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO19 DIO19 event mask 0x13 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO20 DIO20 event mask 0x14 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO21 DIO21 event mask 0x15 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO22 DIO22 event mask 0x16 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO23 DIO23 event mask 0x17 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO24 DIO24 event mask 0x18 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO25 DIO25 event mask 0x19 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO26 DIO26 event mask 0x1A 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO27 DIO27 event mask 0x1B 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO28 DIO28 event mask 0x1C 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO29 DIO29 event mask 0x1D 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO30 DIO30 event mask 0x1E 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO31 DIO31 event mask 0x1F 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOA_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOA_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOA_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 SET Sets DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 SET Sets DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 SET Sets DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 SET Sets DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 SET Sets DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 SET Sets DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 SET Sets DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 SET Sets DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 SET Sets DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 SET Sets DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 SET Sets DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 SET Sets DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 SET Sets DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 SET Sets DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 SET Sets DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 SET Sets DIO15 in RIS register 0x1 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 SET Sets DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 SET Sets DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 SET Sets DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 SET Sets DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 SET Sets DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 SET Sets DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 SET Sets DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 SET Sets DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 SET Sets DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 SET Sets DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 SET Sets DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 SET Sets DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 SET Sets DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 SET Sets DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 SET Sets DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 SET Sets DIO31 in RIS register 0x1 GPIOA_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO15 in RIS register 0x1 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO31 in RIS register 0x1 1 44 0 GPIOA_GEN_EVENT0[%s] 0x1050 GPIOA_GEN_EVENT0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO0 DIO0 interrupt 0x1 DIO1 DIO1 interrupt 0x2 DIO2 DIO2 interrupt 0x3 DIO3 DIO3 interrupt 0x4 DIO4 DIO4 interrupt 0x5 DIO5 DIO5 interrupt 0x6 DIO6 DIO6 interrupt 0x7 DIO7 DIO7 interrupt 0x8 DIO8 DIO8 interrupt 0x9 DIO9 DIO9 interrupt 0xA DIO10 DIO10 interrupt 0xB DIO11 DIO11 interrupt 0xC DIO12 DIO12 interrupt 0xD DIO13 DIO13 interrupt 0xE DIO14 DIO14 interrupt 0xF DIO15 DIO15 interrupt 0x10 GPIOA_GEN_EVENT0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO0 DIO0 event mask 0x0 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO1 DIO1 event mask 0x1 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO2 DIO2 event mask 0x2 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO3 DIO3 event mask 0x3 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO4 DIO4 event mask 0x4 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO5 DIO5 event mask 0x5 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO6 DIO6 event mask 0x6 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO7 DIO7 event mask 0x7 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO8 DIO8 event mask 0x8 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO9 DIO9 event mask 0x9 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO10 DIO10 event mask 0xA 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO11 DIO11 event mask 0xB 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO12 DIO12 event mask 0xC 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO13 DIO13 event mask 0xD 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO14 DIO14 event mask 0xE 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO15 DIO15 event mask 0xF 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOA_GEN_EVENT0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 GPIOA_GEN_EVENT0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 GPIOA_GEN_EVENT0_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 SET Sets DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 SET Sets DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 SET Sets DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 SET Sets DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 SET Sets DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 SET Sets DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 SET Sets DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 SET Sets DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 SET Sets DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 SET Sets DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 SET Sets DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 SET Sets DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 SET Sets DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 SET Sets DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 SET Sets DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 SET Sets DIO15 in RIS register 0x1 GPIOA_GEN_EVENT0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO15 in RIS register 0x1 1 44 0 GPIOA_GEN_EVENT1[%s] 0x1080 GPIOA_GEN_EVENT1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO16 DIO0 interrupt 0x1 DIO17 DIO1 interrupt 0x2 DIO18 DIO2 interrupt 0x3 DIO19 DIO3 interrupt 0x4 DIO20 DIO4 interrupt 0x5 DIO21 DIO5 interrupt 0x6 DIO22 DIO6 interrupt 0x7 DIO23 DIO7 interrupt 0x8 DIO24 DIO8 interrupt 0x9 DIO25 DIO9 interrupt 0xA DIO26 DIO10 interrupt 0xB DIO27 DIO11 interrupt 0xC DIO28 DIO12 interrupt 0xD DIO29 DIO13 interrupt 0xE DIO30 DIO14 interrupt 0xF DIO31 DIO15 interrupt 0x10 GPIOA_GEN_EVENT1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO16 DIO16 event mask 0x10 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO17 DIO17 event mask 0x11 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO18 DIO18 event mask 0x12 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO19 DIO19 event mask 0x13 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO20 DIO20 event mask 0x14 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO21 DIO21 event mask 0x15 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO22 DIO22 event mask 0x16 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO23 DIO23 event mask 0x17 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO24 DIO24 event mask 0x18 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO25 DIO25 event mask 0x19 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO26 DIO26 event mask 0x1A 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO27 DIO27 event mask 0x1B 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO28 DIO28 event mask 0x1C 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO29 DIO29 event mask 0x1D 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO30 DIO30 event mask 0x1E 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO31 DIO31 event mask 0x1F 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOA_GEN_EVENT1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOA_GEN_EVENT1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOA_GEN_EVENT1_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 SET Sets DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 SET Sets DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 SET Sets DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 SET Sets DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 SET Sets DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 SET Sets DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 SET Sets DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 SET Sets DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 SET Sets DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 SET Sets DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 SET Sets DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 SET Sets DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 SET Sets DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 SET Sets DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 SET Sets DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 SET Sets DIO31 in RIS register 0x1 GPIOA_GEN_EVENT1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO31 in RIS register 0x1 GPIOA_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 GPIOA_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 GPIOA_DOUT3_0 Data output 3 to 0 0x1200 32 write-only 0x00000000 DIO0 This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO1 This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO2 This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO3 This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUT7_4 Data output 7 to 4 0x1204 32 write-only 0x00000000 DIO4 This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO5 This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO6 This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO7 This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUT11_8 Data output 11 to 8 0x1208 32 write-only 0x00000000 DIO8 This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO9 This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO10 This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO11 This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUT15_12 Data output 15 to 12 0x120C 32 write-only 0x00000000 DIO12 This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO13 This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO14 This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO15 This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUT19_16 Data output 19 to 16 0x1210 32 write-only 0x00000000 DIO16 This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO17 This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO18 This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO19 This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUT23_20 Data output 23 to 20 0x1214 32 write-only 0x00000000 DIO20 This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO21 This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO22 This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO23 This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUT27_24 Data output 27 to 24 0x1218 32 write-only 0x00000000 DIO24 This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO25 This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO26 This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO27 This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUT31_28 Data output 31 to 28 0x121C 32 write-only 0x00000000 DIO28 This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO29 This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO30 This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO31 This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUT31_0 Data output 31 to 0 0x1280 32 read-write 0x00000000 DIO0 This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register. 0x0 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO1 This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register. 0x1 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO2 This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register. 0x2 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO3 This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register. 0x3 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO4 This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register. 0x4 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO5 This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register. 0x5 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO6 This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register. 0x6 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO7 This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register. 0x7 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO8 This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register. 0x8 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO9 This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register. 0x9 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO10 This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register. 0xA 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO11 This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register. 0xB 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO12 This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register. 0xC 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO13 This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register. 0xD 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO14 This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register. 0xE 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO15 This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register. 0xF 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO16 This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register. 0x10 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO17 This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register. 0x11 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO18 This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register. 0x12 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO19 This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register. 0x13 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO20 This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register. 0x14 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO21 This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register. 0x15 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO22 This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register. 0x16 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO23 This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register. 0x17 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO24 This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register. 0x18 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO25 This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register. 0x19 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO26 This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register. 0x1A 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO27 This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register. 0x1B 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO28 This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register. 0x1C 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO29 This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register. 0x1D 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO30 This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register. 0x1E 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO31 This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register. 0x1F 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOA_DOUTSET31_0 Data output set 31 to 0 0x1290 32 write-only 0x00000000 DIO0 Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO0 in DOUT31_0 0x1 DIO1 Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO1 in DOUT31_0 0x1 DIO2 Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO2 in DOUT31_0 0x1 DIO3 Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO3 in DOUT31_0 0x1 DIO4 Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO4 in DOUT31_0 0x1 DIO5 Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO5 in DOUT31_0 0x1 DIO6 Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO6 in DOUT31_0 0x1 DIO7 Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO7 in DOUT31_0 0x1 DIO8 Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO8 in DOUT31_0 0x1 DIO9 Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO9 in DOUT31_0 0x1 DIO10 Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO10 in DOUT31_0 0x1 DIO11 Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO11 in DOUT31_0 0x1 DIO12 Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO12 in DOUT31_0 0x1 DIO13 Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO13 in DOUT31_0 0x1 DIO14 Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO14 in DOUT31_0 0x1 DIO15 Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO15 in DOUT31_0 0x1 DIO16 Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO16 in DOUT31_0 0x1 DIO17 Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO17 in DOUT31_0 0x1 DIO18 Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO18 in DOUT31_0 0x1 DIO19 Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO19 in DOUT31_0 0x1 DIO20 Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO20 in DOUT31_0 0x1 DIO21 Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO21 in DOUT31_0 0x1 DIO22 Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO22 in DOUT31_0 0x1 DIO23 Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO23 in DOUT31_0 0x1 DIO24 Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO24 in DOUT31_0 0x1 DIO25 Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO25 in DOUT31_0 0x1 DIO26 Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO26 in DOUT31_0 0x1 DIO27 Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO27 in DOUT31_0 0x1 DIO28 Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO28 in DOUT31_0 0x1 DIO29 Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO29 in DOUT31_0 0x1 DIO30 Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO30 in DOUT31_0 0x1 DIO31 Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO31 in DOUT31_0 0x1 GPIOA_DOUTCLR31_0 Data output clear 31 to 0 0x12A0 32 write-only 0x00000000 DIO0 Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO0 in DOUT31_0 0x1 DIO1 Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO1 in DOUT31_0 0x1 DIO2 Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO2 in DOUT31_0 0x1 DIO3 Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO3 in DOUT31_0 0x1 DIO4 Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO4 in DOUT31_0 0x1 DIO5 Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO5 in DOUT31_0 0x1 DIO6 Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO6 in DOUT31_0 0x1 DIO7 Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO7 in DOUT31_0 0x1 DIO8 Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO8 in DOUT31_0 0x1 DIO9 Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO9 in DOUT31_0 0x1 DIO10 Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO10 in DOUT31_0 0x1 DIO11 Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO11 in DOUT31_0 0x1 DIO12 Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO12 in DOUT31_0 0x1 DIO13 Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO13 in DOUT31_0 0x1 DIO14 Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO14 in DOUT31_0 0x1 DIO15 Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO15 in DOUT31_0 0x1 DIO16 Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO16 in DOUT31_0 0x1 DIO17 Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO17 in DOUT31_0 0x1 DIO18 Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO18 in DOUT31_0 0x1 DIO19 Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO19 in DOUT31_0 0x1 DIO20 Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO20 in DOUT31_0 0x1 DIO21 Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO21 in DOUT31_0 0x1 DIO22 Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO22 in DOUT31_0 0x1 DIO23 Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO23 in DOUT31_0 0x1 DIO24 Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO24 in DOUT31_0 0x1 DIO25 Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO25 in DOUT31_0 0x1 DIO26 Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO26 in DOUT31_0 0x1 DIO27 Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO27 in DOUT31_0 0x1 DIO28 Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO28 in DOUT31_0 0x1 DIO29 Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO29 in DOUT31_0 0x1 DIO30 Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO30 in DOUT31_0 0x1 DIO31 Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO31 in DOUT31_0 0x1 GPIOA_DOUTTGL31_0 Data output toggle 31 to 0 0x12B0 32 write-only 0x00000000 DIO0 This bit is used to toggle DIO0 output. 0x0 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO1 This bit is used to toggle DIO1 output. 0x1 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO2 This bit is used to toggle DIO2 output. 0x2 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO3 This bit is used to toggle DIO3 output. 0x3 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO4 This bit is used to toggle DIO4 output. 0x4 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO5 This bit is used to toggle DIO5 output. 0x5 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO6 This bit is used to toggle DIO6 output. 0x6 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO7 This bit is used to toggle DIO7 output. 0x7 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO8 This bit is used to toggle DIO8 output. 0x8 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO9 This bit is used to toggle DIO9 output. 0x9 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO10 This bit is used to toggle DIO10 output. 0xA 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO11 This bit is used to toggle DIO11 output. 0xB 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO12 This bit is used to toggle DIO12 output. 0xC 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO13 This bit is used to toggle DIO13 output. 0xD 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO14 This bit is used to toggle DIO14 output. 0xE 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO15 This bit is used to toggle DIO15 output. 0xF 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO16 This bit is used to toggle DIO16 output. 0x10 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO17 This bit is used to toggle DIO17 output. 0x11 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO18 This bit is used to toggle DIO18 output. 0x12 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO19 This bit is used to toggle DIO19 output. 0x13 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO20 This bit is used to toggle DIO20 output. 0x14 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO21 This bit is used to toggle DIO21 output. 0x15 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO22 This bit is used to toggle DIO22 output. 0x16 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO23 This bit is used to toggle DIO23 output. 0x17 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO24 This bit is used to toggle DIO24 output. 0x18 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO25 This bit is used to toggle DIO25 output. 0x19 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO26 This bit is used to toggle DIO26 output. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO27 This bit is used to toggle DIO27 output. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO28 This bit is used to toggle DIO28 output. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO29 This bit is used to toggle DIO29 output. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO30 This bit is used to toggle DIO30 output. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO31 This bit is used to toggle DIO31 output. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 GPIOA_DOE31_0 Data output enable 31 to 0 0x12C0 32 read-write 0x00000000 DIO0 Enables data output for DIO0. 0x0 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO1 Enables data output for DIO1. 0x1 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO2 Enables data output for DIO2. 0x2 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO3 Enables data output for DIO3. 0x3 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO4 Enables data output for DIO4. 0x4 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO5 Enables data output for DIO5. 0x5 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO6 Enables data output for DIO6. 0x6 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO7 Enables data output for DIO7. 0x7 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO8 Enables data output for DIO8. 0x8 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO9 Enables data output for DIO9. 0x9 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO10 Enables data output for DIO10. 0xA 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO11 Enables data output for DIO11. 0xB 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO12 Enables data output for DIO12. 0xC 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO13 Enables data output for DIO13. 0xD 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO14 Enables data output for DIO14. 0xE 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO15 Enables data output for DIO15. 0xF 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO16 Enables data output for DIO16. 0x10 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO17 Enables data output for DIO17. 0x11 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO18 Enables data output for DIO18. 0x12 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO19 Enables data output for DIO19. 0x13 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO20 Enables data output for DIO20. 0x14 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO21 Enables data output for DIO21. 0x15 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO22 Enables data output for DIO22. 0x16 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO23 Enables data output for DIO23. 0x17 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO24 Enables data output for DIO24. 0x18 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO25 Enables data output for DIO25. 0x19 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO26 Enables data output for DIO26. 0x1A 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO27 Enables data output for DIO27. 0x1B 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO28 Enables data output for DIO28. 0x1C 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO29 Enables data output for DIO29. 0x1D 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO30 Enables data output for DIO30. 0x1E 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO31 Enables data output for DIO31. 0x1F 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 GPIOA_DOESET31_0 Data output enable set 31 to 0 0x12D0 32 write-only 0x00000000 DIO0 Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO0 in DOE31_0 0x1 DIO1 Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO1 in DOE31_0 0x1 DIO2 Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO2 in DOE31_0 0x1 DIO3 Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO3 in DOE31_0 0x1 DIO4 Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO4 in DOE31_0 0x1 DIO5 Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO5 in DOE31_0 0x1 DIO6 Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO6 in DOE31_0 0x1 DIO7 Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO7 in DOE31_0 0x1 DIO8 Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO8 in DOE31_0 0x1 DIO9 Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO9 in DOE31_0 0x1 DIO10 Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO10 in DOE31_0 0x1 DIO11 Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO11 in DOE31_0 0x1 DIO12 Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO12 in DOE31_0 0x1 DIO13 Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO13 in DOE31_0 0x1 DIO14 Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO14 in DOE31_0 0x1 DIO15 Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO15 in DOE31_0 0x1 DIO16 Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO16 in DOE31_0 0x1 DIO17 Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO17 in DOE31_0 0x1 DIO18 Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO18 in DOE31_0 0x1 DIO19 Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO19 in DOE31_0 0x1 DIO20 Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO20 in DOE31_0 0x1 DIO21 Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO21 in DOE31_0 0x1 DIO22 Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO22 in DOE31_0 0x1 DIO23 Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO23 in DOE31_0 0x1 DIO24 Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO24 in DOE31_0 0x1 DIO25 Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO25 in DOE31_0 0x1 DIO26 Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO26 in DOE31_0 0x1 DIO27 Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO27 in DOE31_0 0x1 DIO28 Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO28 in DOE31_0 0x1 DIO29 Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO29 in DOE31_0 0x1 DIO30 Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO30 in DOE31_0 0x1 DIO31 Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO31 in DOE31_0 0x1 GPIOA_DOECLR31_0 Data output enable clear 31 to 0 0x12E0 32 write-only 0x00000000 DIO0 Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO0 in DOE31_0 0x1 DIO1 Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO1 in DOE31_0 0x1 DIO2 Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO2 in DOE31_0 0x1 DIO3 Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO3 in DOE31_0 0x1 DIO4 Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO4 in DOE31_0 0x1 DIO5 Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO5 in DOE31_0 0x1 DIO6 Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO6 in DOE31_0 0x1 DIO7 Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO7 in DOE31_0 0x1 DIO8 Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO8 in DOE31_0 0x1 DIO9 Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO9 in DOE31_0 0x1 DIO10 Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO10 in DOE31_0 0x1 DIO11 Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO11 in DOE31_0 0x1 DIO12 Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO12 in DOE31_0 0x1 DIO13 Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO13 in DOE31_0 0x1 DIO14 Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO14 in DOE31_0 0x1 DIO15 Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO15 in DOE31_0 0x1 DIO16 Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO16 in DOE31_0 0x1 DIO17 Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO17 in DOE31_0 0x1 DIO18 Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO18 in DOE31_0 0x1 DIO19 Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO19 in DOE31_0 0x1 DIO20 Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO20 in DOE31_0 0x1 DIO21 Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO21 in DOE31_0 0x1 DIO22 Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO22 in DOE31_0 0x1 DIO23 Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO23 in DOE31_0 0x1 DIO24 Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO24 in DOE31_0 0x1 DIO25 Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO25 in DOE31_0 0x1 DIO26 Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO26 in DOE31_0 0x1 DIO27 Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO27 in DOE31_0 0x1 DIO28 Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO28 in DOE31_0 0x1 DIO29 Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO29 in DOE31_0 0x1 DIO30 Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO30 in DOE31_0 0x1 DIO31 Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO31 in DOE31_0 0x1 GPIOA_DIN3_0 Data input 3 to 0 0x1300 32 read-only 0x00000000 DIO0 This bit reads the data input value of DIO0. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO1 This bit reads the data input value of DIO1. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO2 This bit reads the data input value of DIO2. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO3 This bit reads the data input value of DIO3. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_DIN7_4 Data input 7 to 4 0x1304 32 read-only 0x00000000 DIO4 This bit reads the data input value of DIO4. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO5 This bit reads the data input value of DIO5. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO6 This bit reads the data input value of DIO6. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO7 This bit reads the data input value of DIO7. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_DIN11_8 Data input 11 to 8 0x1308 32 read-only 0x00000000 DIO8 This bit reads the data input value of DIO8. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO9 This bit reads the data input value of DIO9. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO10 This bit reads the data input value of DIO10. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO11 This bit reads the data input value of DIO11. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_DIN15_12 Data input 15 to 12 0x130C 32 read-only 0x00000000 DIO12 This bit reads the data input value of DIO12. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO13 This bit reads the data input value of DIO13. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO14 This bit reads the data input value of DIO14. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO15 This bit reads the data input value of DIO15. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_DIN19_16 Data input 19 to 16 0x1310 32 read-only 0x00000000 DIO16 This bit reads the data input value of DIO16. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO17 This bit reads the data input value of DIO17. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO18 This bit reads the data input value of DIO18. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO19 This bit reads the data input value of DIO19. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_DIN23_20 Data input 23 to 20 0x1314 32 read-only 0x00000000 DIO20 This bit reads the data input value of DIO20. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO21 This bit reads the data input value of DIO21. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO22 This bit reads the data input value of DIO22. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO23 This bit reads the data input value of DIO23. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_DIN27_24 Data input 27 to 24 0x1318 32 read-only 0x00000000 DIO24 This bit reads the data input value of DIO24. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO25 This bit reads the data input value of DIO25. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO26 This bit reads the data input value of DIO26. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO27 This bit reads the data input value of DIO27. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_DIN31_28 Data input 31 to 28 0x131C 32 read-only 0x00000000 DIO28 This bit reads the data input value of DIO28. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO29 This bit reads the data input value of DIO29. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO30 This bit reads the data input value of DIO30. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO31 This bit reads the data input value of DIO31. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_DIN31_0 Data input 31 to 0 0x1380 32 read-only 0x00000000 DIO0 This bit reads the data input value of DIO0. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO1 This bit reads the data input value of DIO1. 0x1 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO2 This bit reads the data input value of DIO2. 0x2 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO3 This bit reads the data input value of DIO3. 0x3 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO4 This bit reads the data input value of DIO4. 0x4 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO5 This bit reads the data input value of DIO5. 0x5 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO6 This bit reads the data input value of DIO6. 0x6 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO7 This bit reads the data input value of DIO7. 0x7 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO8 This bit reads the data input value of DIO8. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO9 This bit reads the data input value of DIO9. 0x9 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO10 This bit reads the data input value of DIO10. 0xA 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO11 This bit reads the data input value of DIO11. 0xB 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO12 This bit reads the data input value of DIO12. 0xC 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO13 This bit reads the data input value of DIO13. 0xD 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO14 This bit reads the data input value of DIO14. 0xE 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO15 This bit reads the data input value of DIO15. 0xF 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO16 This bit reads the data input value of DIO16. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO17 This bit reads the data input value of DIO17. 0x11 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO18 This bit reads the data input value of DIO18. 0x12 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO19 This bit reads the data input value of DIO19. 0x13 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO20 This bit reads the data input value of DIO20. 0x14 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO21 This bit reads the data input value of DIO21. 0x15 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO22 This bit reads the data input value of DIO22. 0x16 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO23 This bit reads the data input value of DIO23. 0x17 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO24 This bit reads the data input value of DIO24. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO25 This bit reads the data input value of DIO25. 0x19 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO26 This bit reads the data input value of DIO26. 0x1A 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO27 This bit reads the data input value of DIO27. 0x1B 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO28 This bit reads the data input value of DIO28. 0x1C 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO29 This bit reads the data input value of DIO29. 0x1D 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO30 This bit reads the data input value of DIO30. 0x1E 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO31 This bit reads the data input value of DIO31. 0x1F 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOA_POLARITY15_0 Polarity 15 to 0 0x1390 32 read-write 0x00000000 DIO0 Enables and configures edge detection polarity for DIO0. 0x0 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO1 Enables and configures edge detection polarity for DIO1. 0x2 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO2 Enables and configures edge detection polarity for DIO2. 0x4 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO3 Enables and configures edge detection polarity for DIO3. 0x6 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO4 Enables and configures edge detection polarity for DIO4. 0x8 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO5 Enables and configures edge detection polarity for DIO5. 0xA 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO6 Enables and configures edge detection polarity for DIO6. 0xC 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO7 Enables and configures edge detection polarity for DIO7. 0xE 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO8 Enables and configures edge detection polarity for DIO8. 0x10 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO9 Enables and configures edge detection polarity for DIO9. 0x12 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO10 Enables and configures edge detection polarity for DIO10. 0x14 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO11 Enables and configures edge detection polarity for DIO11. 0x16 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO12 Enables and configures edge detection polarity for DIO12. 0x18 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO13 Enables and configures edge detection polarity for DIO13. 0x1A 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO14 Enables and configures edge detection polarity for DIO14. 0x1C 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO15 Enables and configures edge detection polarity for DIO15. 0x1E 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 GPIOA_POLARITY31_16 Polarity 31 to 16 0x13A0 32 read-write 0x00000000 DIO16 Enables and configures edge detection polarity for DIO16. 0x0 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO17 Enables and configures edge detection polarity for DIO17. 0x2 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO18 Enables and configures edge detection polarity for DIO18. 0x4 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO19 Enables and configures edge detection polarity for DIO19. 0x6 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO20 Enables and configures edge detection polarity for DIO20. 0x8 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO21 Enables and configures edge detection polarity for DIO21. 0xA 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO22 Enables and configures edge detection polarity for DIO22. 0xC 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO23 Enables and configures edge detection polarity for DIO23. 0xE 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO24 Enables and configures edge detection polarity for DIO24. 0x10 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO25 Enables and configures edge detection polarity for DIO25. 0x12 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO26 Enables and configures edge detection polarity for DIO26. 0x14 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO27 Enables and configures edge detection polarity for DIO27. 0x16 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO28 Enables and configures edge detection polarity for DIO28. 0x18 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO29 Enables and configures edge detection polarity for DIO29. 0x1A 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO30 Enables and configures edge detection polarity for DIO30. 0x1C 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO31 Enables and configures edge detection polarity for DIO31. 0x1E 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 GPIOA_CTL FAST WAKE GLOBAL EN 0x1400 32 read-write 0x00000000 FASTWAKEONLY FASTWAKEONLY for the global control of fastwake 0x0 0x1 read-write NOT_GLOBAL_EN The global control of fastwake is not enabled, per bit fast wake feature depends on FASTWAKE.DIN 0x0 GLOBAL_EN The global control of fastwake is enabled 0x1 GPIOA_FASTWAKE FAST WAKE ENABLE 0x1404 32 read-write 0x00000000 DIN0 Enable fastwake feature for DIN0 0x0 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN1 Enable fastwake feature for DIN1 0x1 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN2 Enable fastwake feature for DIN2 0x2 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN3 Enable fastwake feature for DIN3 0x3 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN4 Enable fastwake feature for DIN4 0x4 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN5 Enable fastwake feature for DIN5 0x5 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN6 Enable fastwake feature for DIN6 0x6 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN7 Enable fastwake feature for DIN7 0x7 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN8 Enable fastwake feature for DIN8 0x8 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN9 Enable fastwake feature for DIN9 0x9 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN10 Enable fastwake feature for DIN10 0xA 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN11 Enable fastwake feature for DIN11 0xB 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN12 Enable fastwake feature for DIN12 0xC 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN13 Enable fastwake feature for DIN13 0xD 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN14 Enable fastwake feature for DIN14 0xE 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN15 Enable fastwake feature for DIN15 0xF 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN16 Enable fastwake feature for DIN16 0x10 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN17 Enable fastwake feature for DIN17 0x11 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN18 Enable fastwake feature for DIN18 0x12 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN19 Enable fastwake feature for DIN19 0x13 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN20 Enable fastwake feature for DIN20 0x14 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN21 Enable fastwake feature for DIN21 0x15 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN22 Enable fastwake feature for DIN22 0x16 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN23 Enable fastwake feature for DIN23 0x17 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN24 Enable fastwake feature for DIN24 0x18 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN25 Enable fastwake feature for DIN25 0x19 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN26 Enable fastwake feature for DIN26 0x1A 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN27 Enable fastwake feature for DIN27 0x1B 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN28 Enable fastwake feature for DIN29 0x1C 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN29 Enable fastwake feature for DIN29 0x1D 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN30 Enable fastwake feature for DIN30 0x1E 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN31 Enable fastwake feature for DIN31 0x1F 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 GPIOA_SUB0CFG Subscriber 0 configuration 0x1500 32 read-write 0x00000000 ENABLE This bit is used to enable subscriber 0 event. 0x0 0x1 read-write CLR Subscriber 0 event is disabled 0x0 SET Subscriber 0 event is enabled 0x1 OUTPOLICY These bits configure the output policy for subscriber 0 event. 0x8 0x2 read-write SET Selected DIO pins are set 0x0 CLR Selected DIO pins are cleared 0x1 TOGGLE Selected DIO pins are toggled 0x2 INDEX Indicates the specific bit among lower 16 bits that is targeted by the subscriber action 0x10 0x4 read-write MIN specific bit targeted by the subscriber action is bit0 0x0 MAX specific bit targeted by the subscriber action is bit15 0xF GPIOA_FILTEREN15_0 Filter Enable 15 to 0 0x1508 32 read-write 0x00000000 DIN0 Programmable counter length of digital glitch filter for DIN0 0x0 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN1 Programmable counter length of digital glitch filter for DIN1 0x2 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN2 Programmable counter length of digital glitch filter for DIN2 0x4 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN3 Programmable counter length of digital glitch filter for DIN3 0x6 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN4 Programmable counter length of digital glitch filter for DIN4 0x8 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN5 Programmable counter length of digital glitch filter for DIN5 0xA 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN6 Programmable counter length of digital glitch filter for DIN6 0xC 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN7 Programmable counter length of digital glitch filter for DIN7 0xE 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN8 Programmable counter length of digital glitch filter for DIN8 0x10 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN9 Programmable counter length of digital glitch filter for DIN9 0x12 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN10 Programmable counter length of digital glitch filter for DIN10 0x14 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN11 Programmable counter length of digital glitch filter for DIN11 0x16 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN12 Programmable counter length of digital glitch filter for DIN12 0x18 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN13 Programmable counter length of digital glitch filter for DIN13 0x1A 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN14 Programmable counter length of digital glitch filter for DIN14 0x1C 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN15 Programmable counter length of digital glitch filter for DIN15 0x1E 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 GPIOA_FILTEREN31_16 Filter Enable 31 to 16 0x150C 32 read-write 0x00000000 DIN16 Programmable counter length of digital glitch filter for DIN16 0x0 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN17 Programmable counter length of digital glitch filter for DIN17 0x2 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN18 Programmable counter length of digital glitch filter for DIN18 0x4 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN19 Programmable counter length of digital glitch filter for DIN19 0x6 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN20 Programmable counter length of digital glitch filter for DIN20 0x8 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN21 Programmable counter length of digital glitch filter for DIN21 0xA 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN22 Programmable counter length of digital glitch filter for DIN22 0xC 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN23 Programmable counter length of digital glitch filter for DIN23 0xE 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN24 Programmable counter length of digital glitch filter for DIN24 0x10 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN25 Programmable counter length of digital glitch filter for DIN25 0x12 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN26 Programmable counter length of digital glitch filter for DIN26 0x14 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN27 Programmable counter length of digital glitch filter for DIN27 0x16 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN28 Programmable counter length of digital glitch filter for DIN28 0x18 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN29 Programmable counter length of digital glitch filter for DIN29 0x1A 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN30 Programmable counter length of digital glitch filter for DIN30 0x1C 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN31 Programmable counter length of digital glitch filter for DIN31 0x1E 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 GPIOA_DMAMASK DMA Write MASK 0x1510 32 read-write 0x00000000 DOUT0 DMA is allowed to modify DOUT0 0x0 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT1 DMA is allowed to modify DOUT1 0x1 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT2 DMA is allowed to modify DOUT2 0x2 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT3 DMA is allowed to modify DOUT3 0x3 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT4 DMA is allowed to modify DOUT4 0x4 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT5 DMA is allowed to modify DOUT5 0x5 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT6 DMA is allowed to modify DOUT6 0x6 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT7 DMA is allowed to modify DOUT7 0x7 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT8 DMA is allowed to modify DOUT8 0x8 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT9 DMA is allowed to modify DOUT9 0x9 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT10 DMA is allowed to modify DOUT10 0xA 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT11 DMA is allowed to modify DOUT11 0xB 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT12 DMA is allowed to modify DOUT12 0xC 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT13 DMA is allowed to modify DOUT13 0xD 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT14 DMA is allowed to modify DOUT14 0xE 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT15 DMA is allowed to modify DOUT15 0xF 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT16 DMA is allowed to modify DOUT16 0x10 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT17 DMA is allowed to modify DOUT17 0x11 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT18 DMA is allowed to modify DOUT18 0x12 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT19 DMA is allowed to modify DOUT19 0x13 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT20 DMA is allowed to modify DOUT20 0x14 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT21 DMA is allowed to modify DOUT21 0x15 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT22 DMA is allowed to modify DOUT22 0x16 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT23 DMA is allowed to modify DOUT23 0x17 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT24 DMA is allowed to modify DOUT24 0x18 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT25 DMA is allowed to modify DOUT25 0x19 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT26 DMA is allowed to modify DOUT26 0x1A 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT27 DMA is allowed to modify DOUT27 0x1B 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT28 DMA is allowed to modify DOUT28 0x1C 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT29 DMA is allowed to modify DOUT29 0x1D 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT30 DMA is allowed to modify DOUT30 0x1E 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT31 DMA is allowed to modify DOUT31 0x1F 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 GPIOA_SUB1CFG Subscriber 1 configuration 0x1520 32 read-write 0x00000000 ENABLE This bit is used to enable subscriber 1 event. 0x0 0x1 read-write CLR Subscriber 1 event is disabled 0x0 SET Subscriber 1 event is enabled 0x1 OUTPOLICY These bits configure the output policy for subscriber 1 event. 0x8 0x2 read-write SET Selected DIO pins are set 0x0 CLR Selected DIO pins are cleared 0x1 TOGGLE Selected DIO pins are toggled 0x2 INDEX indicates the specific bit in the upper 16 bits that is targeted by the subscriber action 0x10 0x4 read-write MIN specific bit targeted by the subscriber action is bit16 0x0 MAX specific bit targeted by the subscriber action is bit31 0xF GPIOB GPIOB 1.0 PERIPHERALREGION 0x400A2000 0x0 0x1F00 registers GPIOB_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOB_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOB_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOB_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 GPIOB_GPRCM[%s] 0x800 GPIOB_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 GPIOB_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 GPIOB_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 GPIOB_CLKOVR Clock Override 0x1010 32 read-write 0x00000000 OVERRIDE Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request 0x0 0x1 read-write DISABLED Override disabled 0x0 ENABLED Override enabled 0x1 RUN_STOP If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system 0x1 0x1 read-write RUN Run/ungate functional clock 0x0 STOP Stop/gate functional clock 0x1 GPIOB_PDBGCTL Peripheral Debug Control 0x1018 32 read-write 0x00000001 FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 1 44 0 GPIOB_CPU_INT[%s] 0x1020 GPIOB_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO0 DIO0 interrupt 0x1 DIO1 DIO1 interrupt 0x2 DIO2 DIO2 interrupt 0x3 DIO3 DIO3 interrupt 0x4 DIO4 DIO4 interrupt 0x5 DIO5 DIO5 interrupt 0x6 DIO6 DIO6 interrupt 0x7 DIO7 DIO7 interrupt 0x8 DIO8 DIO8 interrupt 0x9 DIO9 DIO9 interrupt 0xA DIO10 DIO10 interrupt 0xB DIO11 DIO11 interrupt 0xC DIO12 DIO12 interrupt 0xD DIO13 DIO13 interrupt 0xE DIO14 DIO14 interrupt 0xF DIO15 DIO15 interrupt 0x10 DIO16 DIO16 interrupt 0x11 DIO17 DIO17 interrupt 0x12 DIO18 DIO18 interrupt 0x13 DIO19 DIO19 interrupt 0x14 DIO20 DIO20 interrupt 0x15 DIO21 DIO21 interrupt 0x16 DIO22 DIO22 interrupt 0x17 DIO23 DIO23 interrupt 0x18 DIO24 DIO24 interrupt 0x19 DIO25 DIO25 interrupt 0x1A DIO26 DIO26 interrupt 0x1B DIO27 DIO27 interrupt 0x1C DIO28 DIO28 interrupt 0x1D DIO29 DIO29 interrupt 0x1E DIO30 DIO30 interrupt 0x1F DIO31 DIO31 interrupt 0x20 GPIOB_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO0 DIO0 event mask 0x0 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO1 DIO1 event mask 0x1 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO2 DIO2 event mask 0x2 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO3 DIO3 event mask 0x3 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO4 DIO4 event mask 0x4 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO5 DIO5 event mask 0x5 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO6 DIO6 event mask 0x6 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO7 DIO7 event mask 0x7 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO8 DIO8 event mask 0x8 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO9 DIO9 event mask 0x9 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO10 DIO10 event mask 0xA 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO11 DIO11 event mask 0xB 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO12 DIO12 event mask 0xC 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO13 DIO13 event mask 0xD 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO14 DIO14 event mask 0xE 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO15 DIO15 event mask 0xF 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO16 DIO16 event mask 0x10 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO17 DIO17 event mask 0x11 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO18 DIO18 event mask 0x12 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO19 DIO19 event mask 0x13 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO20 DIO20 event mask 0x14 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO21 DIO21 event mask 0x15 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO22 DIO22 event mask 0x16 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO23 DIO23 event mask 0x17 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO24 DIO24 event mask 0x18 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO25 DIO25 event mask 0x19 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO26 DIO26 event mask 0x1A 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO27 DIO27 event mask 0x1B 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO28 DIO28 event mask 0x1C 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO29 DIO29 event mask 0x1D 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO30 DIO30 event mask 0x1E 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO31 DIO31 event mask 0x1F 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOB_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOB_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOB_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 SET Sets DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 SET Sets DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 SET Sets DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 SET Sets DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 SET Sets DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 SET Sets DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 SET Sets DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 SET Sets DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 SET Sets DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 SET Sets DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 SET Sets DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 SET Sets DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 SET Sets DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 SET Sets DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 SET Sets DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 SET Sets DIO15 in RIS register 0x1 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 SET Sets DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 SET Sets DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 SET Sets DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 SET Sets DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 SET Sets DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 SET Sets DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 SET Sets DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 SET Sets DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 SET Sets DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 SET Sets DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 SET Sets DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 SET Sets DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 SET Sets DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 SET Sets DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 SET Sets DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 SET Sets DIO31 in RIS register 0x1 GPIOB_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO15 in RIS register 0x1 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO31 in RIS register 0x1 1 44 0 GPIOB_GEN_EVENT0[%s] 0x1050 GPIOB_GEN_EVENT0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO0 DIO0 interrupt 0x1 DIO1 DIO1 interrupt 0x2 DIO2 DIO2 interrupt 0x3 DIO3 DIO3 interrupt 0x4 DIO4 DIO4 interrupt 0x5 DIO5 DIO5 interrupt 0x6 DIO6 DIO6 interrupt 0x7 DIO7 DIO7 interrupt 0x8 DIO8 DIO8 interrupt 0x9 DIO9 DIO9 interrupt 0xA DIO10 DIO10 interrupt 0xB DIO11 DIO11 interrupt 0xC DIO12 DIO12 interrupt 0xD DIO13 DIO13 interrupt 0xE DIO14 DIO14 interrupt 0xF DIO15 DIO15 interrupt 0x10 GPIOB_GEN_EVENT0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO0 DIO0 event mask 0x0 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO1 DIO1 event mask 0x1 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO2 DIO2 event mask 0x2 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO3 DIO3 event mask 0x3 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO4 DIO4 event mask 0x4 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO5 DIO5 event mask 0x5 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO6 DIO6 event mask 0x6 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO7 DIO7 event mask 0x7 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO8 DIO8 event mask 0x8 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO9 DIO9 event mask 0x9 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO10 DIO10 event mask 0xA 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO11 DIO11 event mask 0xB 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO12 DIO12 event mask 0xC 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO13 DIO13 event mask 0xD 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO14 DIO14 event mask 0xE 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO15 DIO15 event mask 0xF 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOB_GEN_EVENT0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 GPIOB_GEN_EVENT0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 GPIOB_GEN_EVENT0_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 SET Sets DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 SET Sets DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 SET Sets DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 SET Sets DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 SET Sets DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 SET Sets DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 SET Sets DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 SET Sets DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 SET Sets DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 SET Sets DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 SET Sets DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 SET Sets DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 SET Sets DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 SET Sets DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 SET Sets DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 SET Sets DIO15 in RIS register 0x1 GPIOB_GEN_EVENT0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO15 in RIS register 0x1 1 44 0 GPIOB_GEN_EVENT1[%s] 0x1080 GPIOB_GEN_EVENT1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO16 DIO0 interrupt 0x1 DIO17 DIO1 interrupt 0x2 DIO18 DIO2 interrupt 0x3 DIO19 DIO3 interrupt 0x4 DIO20 DIO4 interrupt 0x5 DIO21 DIO5 interrupt 0x6 DIO22 DIO6 interrupt 0x7 DIO23 DIO7 interrupt 0x8 DIO24 DIO8 interrupt 0x9 DIO25 DIO9 interrupt 0xA DIO26 DIO10 interrupt 0xB DIO27 DIO11 interrupt 0xC DIO28 DIO12 interrupt 0xD DIO29 DIO13 interrupt 0xE DIO30 DIO14 interrupt 0xF DIO31 DIO15 interrupt 0x10 GPIOB_GEN_EVENT1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO16 DIO16 event mask 0x10 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO17 DIO17 event mask 0x11 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO18 DIO18 event mask 0x12 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO19 DIO19 event mask 0x13 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO20 DIO20 event mask 0x14 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO21 DIO21 event mask 0x15 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO22 DIO22 event mask 0x16 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO23 DIO23 event mask 0x17 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO24 DIO24 event mask 0x18 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO25 DIO25 event mask 0x19 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO26 DIO26 event mask 0x1A 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO27 DIO27 event mask 0x1B 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO28 DIO28 event mask 0x1C 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO29 DIO29 event mask 0x1D 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO30 DIO30 event mask 0x1E 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO31 DIO31 event mask 0x1F 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOB_GEN_EVENT1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOB_GEN_EVENT1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOB_GEN_EVENT1_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 SET Sets DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 SET Sets DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 SET Sets DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 SET Sets DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 SET Sets DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 SET Sets DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 SET Sets DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 SET Sets DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 SET Sets DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 SET Sets DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 SET Sets DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 SET Sets DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 SET Sets DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 SET Sets DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 SET Sets DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 SET Sets DIO31 in RIS register 0x1 GPIOB_GEN_EVENT1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO31 in RIS register 0x1 GPIOB_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 GPIOB_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 GPIOB_DOUT3_0 Data output 3 to 0 0x1200 32 write-only 0x00000000 DIO0 This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO1 This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO2 This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO3 This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUT7_4 Data output 7 to 4 0x1204 32 write-only 0x00000000 DIO4 This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO5 This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO6 This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO7 This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUT11_8 Data output 11 to 8 0x1208 32 write-only 0x00000000 DIO8 This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO9 This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO10 This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO11 This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUT15_12 Data output 15 to 12 0x120C 32 write-only 0x00000000 DIO12 This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO13 This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO14 This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO15 This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUT19_16 Data output 19 to 16 0x1210 32 write-only 0x00000000 DIO16 This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO17 This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO18 This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO19 This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUT23_20 Data output 23 to 20 0x1214 32 write-only 0x00000000 DIO20 This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO21 This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO22 This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO23 This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUT27_24 Data output 27 to 24 0x1218 32 write-only 0x00000000 DIO24 This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO25 This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO26 This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO27 This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUT31_28 Data output 31 to 28 0x121C 32 write-only 0x00000000 DIO28 This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO29 This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO30 This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO31 This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUT31_0 Data output 31 to 0 0x1280 32 read-write 0x00000000 DIO0 This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register. 0x0 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO1 This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register. 0x1 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO2 This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register. 0x2 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO3 This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register. 0x3 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO4 This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register. 0x4 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO5 This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register. 0x5 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO6 This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register. 0x6 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO7 This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register. 0x7 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO8 This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register. 0x8 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO9 This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register. 0x9 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO10 This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register. 0xA 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO11 This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register. 0xB 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO12 This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register. 0xC 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO13 This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register. 0xD 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO14 This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register. 0xE 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO15 This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register. 0xF 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO16 This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register. 0x10 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO17 This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register. 0x11 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO18 This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register. 0x12 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO19 This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register. 0x13 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO20 This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register. 0x14 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO21 This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register. 0x15 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO22 This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register. 0x16 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO23 This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register. 0x17 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO24 This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register. 0x18 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO25 This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register. 0x19 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO26 This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register. 0x1A 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO27 This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register. 0x1B 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO28 This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register. 0x1C 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO29 This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register. 0x1D 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO30 This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register. 0x1E 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO31 This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register. 0x1F 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOB_DOUTSET31_0 Data output set 31 to 0 0x1290 32 write-only 0x00000000 DIO0 Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO0 in DOUT31_0 0x1 DIO1 Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO1 in DOUT31_0 0x1 DIO2 Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO2 in DOUT31_0 0x1 DIO3 Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO3 in DOUT31_0 0x1 DIO4 Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO4 in DOUT31_0 0x1 DIO5 Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO5 in DOUT31_0 0x1 DIO6 Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO6 in DOUT31_0 0x1 DIO7 Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO7 in DOUT31_0 0x1 DIO8 Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO8 in DOUT31_0 0x1 DIO9 Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO9 in DOUT31_0 0x1 DIO10 Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO10 in DOUT31_0 0x1 DIO11 Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO11 in DOUT31_0 0x1 DIO12 Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO12 in DOUT31_0 0x1 DIO13 Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO13 in DOUT31_0 0x1 DIO14 Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO14 in DOUT31_0 0x1 DIO15 Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO15 in DOUT31_0 0x1 DIO16 Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO16 in DOUT31_0 0x1 DIO17 Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO17 in DOUT31_0 0x1 DIO18 Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO18 in DOUT31_0 0x1 DIO19 Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO19 in DOUT31_0 0x1 DIO20 Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO20 in DOUT31_0 0x1 DIO21 Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO21 in DOUT31_0 0x1 DIO22 Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO22 in DOUT31_0 0x1 DIO23 Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO23 in DOUT31_0 0x1 DIO24 Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO24 in DOUT31_0 0x1 DIO25 Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO25 in DOUT31_0 0x1 DIO26 Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO26 in DOUT31_0 0x1 DIO27 Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO27 in DOUT31_0 0x1 DIO28 Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO28 in DOUT31_0 0x1 DIO29 Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO29 in DOUT31_0 0x1 DIO30 Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO30 in DOUT31_0 0x1 DIO31 Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO31 in DOUT31_0 0x1 GPIOB_DOUTCLR31_0 Data output clear 31 to 0 0x12A0 32 write-only 0x00000000 DIO0 Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO0 in DOUT31_0 0x1 DIO1 Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO1 in DOUT31_0 0x1 DIO2 Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO2 in DOUT31_0 0x1 DIO3 Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO3 in DOUT31_0 0x1 DIO4 Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO4 in DOUT31_0 0x1 DIO5 Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO5 in DOUT31_0 0x1 DIO6 Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO6 in DOUT31_0 0x1 DIO7 Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO7 in DOUT31_0 0x1 DIO8 Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO8 in DOUT31_0 0x1 DIO9 Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO9 in DOUT31_0 0x1 DIO10 Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO10 in DOUT31_0 0x1 DIO11 Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO11 in DOUT31_0 0x1 DIO12 Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO12 in DOUT31_0 0x1 DIO13 Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO13 in DOUT31_0 0x1 DIO14 Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO14 in DOUT31_0 0x1 DIO15 Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO15 in DOUT31_0 0x1 DIO16 Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO16 in DOUT31_0 0x1 DIO17 Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO17 in DOUT31_0 0x1 DIO18 Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO18 in DOUT31_0 0x1 DIO19 Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO19 in DOUT31_0 0x1 DIO20 Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO20 in DOUT31_0 0x1 DIO21 Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO21 in DOUT31_0 0x1 DIO22 Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO22 in DOUT31_0 0x1 DIO23 Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO23 in DOUT31_0 0x1 DIO24 Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO24 in DOUT31_0 0x1 DIO25 Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO25 in DOUT31_0 0x1 DIO26 Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO26 in DOUT31_0 0x1 DIO27 Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO27 in DOUT31_0 0x1 DIO28 Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO28 in DOUT31_0 0x1 DIO29 Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO29 in DOUT31_0 0x1 DIO30 Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO30 in DOUT31_0 0x1 DIO31 Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO31 in DOUT31_0 0x1 GPIOB_DOUTTGL31_0 Data output toggle 31 to 0 0x12B0 32 write-only 0x00000000 DIO0 This bit is used to toggle DIO0 output. 0x0 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO1 This bit is used to toggle DIO1 output. 0x1 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO2 This bit is used to toggle DIO2 output. 0x2 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO3 This bit is used to toggle DIO3 output. 0x3 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO4 This bit is used to toggle DIO4 output. 0x4 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO5 This bit is used to toggle DIO5 output. 0x5 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO6 This bit is used to toggle DIO6 output. 0x6 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO7 This bit is used to toggle DIO7 output. 0x7 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO8 This bit is used to toggle DIO8 output. 0x8 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO9 This bit is used to toggle DIO9 output. 0x9 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO10 This bit is used to toggle DIO10 output. 0xA 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO11 This bit is used to toggle DIO11 output. 0xB 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO12 This bit is used to toggle DIO12 output. 0xC 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO13 This bit is used to toggle DIO13 output. 0xD 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO14 This bit is used to toggle DIO14 output. 0xE 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO15 This bit is used to toggle DIO15 output. 0xF 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO16 This bit is used to toggle DIO16 output. 0x10 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO17 This bit is used to toggle DIO17 output. 0x11 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO18 This bit is used to toggle DIO18 output. 0x12 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO19 This bit is used to toggle DIO19 output. 0x13 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO20 This bit is used to toggle DIO20 output. 0x14 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO21 This bit is used to toggle DIO21 output. 0x15 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO22 This bit is used to toggle DIO22 output. 0x16 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO23 This bit is used to toggle DIO23 output. 0x17 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO24 This bit is used to toggle DIO24 output. 0x18 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO25 This bit is used to toggle DIO25 output. 0x19 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO26 This bit is used to toggle DIO26 output. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO27 This bit is used to toggle DIO27 output. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO28 This bit is used to toggle DIO28 output. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO29 This bit is used to toggle DIO29 output. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO30 This bit is used to toggle DIO30 output. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO31 This bit is used to toggle DIO31 output. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 GPIOB_DOE31_0 Data output enable 31 to 0 0x12C0 32 read-write 0x00000000 DIO0 Enables data output for DIO0. 0x0 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO1 Enables data output for DIO1. 0x1 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO2 Enables data output for DIO2. 0x2 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO3 Enables data output for DIO3. 0x3 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO4 Enables data output for DIO4. 0x4 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO5 Enables data output for DIO5. 0x5 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO6 Enables data output for DIO6. 0x6 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO7 Enables data output for DIO7. 0x7 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO8 Enables data output for DIO8. 0x8 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO9 Enables data output for DIO9. 0x9 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO10 Enables data output for DIO10. 0xA 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO11 Enables data output for DIO11. 0xB 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO12 Enables data output for DIO12. 0xC 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO13 Enables data output for DIO13. 0xD 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO14 Enables data output for DIO14. 0xE 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO15 Enables data output for DIO15. 0xF 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO16 Enables data output for DIO16. 0x10 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO17 Enables data output for DIO17. 0x11 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO18 Enables data output for DIO18. 0x12 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO19 Enables data output for DIO19. 0x13 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO20 Enables data output for DIO20. 0x14 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO21 Enables data output for DIO21. 0x15 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO22 Enables data output for DIO22. 0x16 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO23 Enables data output for DIO23. 0x17 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO24 Enables data output for DIO24. 0x18 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO25 Enables data output for DIO25. 0x19 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO26 Enables data output for DIO26. 0x1A 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO27 Enables data output for DIO27. 0x1B 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO28 Enables data output for DIO28. 0x1C 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO29 Enables data output for DIO29. 0x1D 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO30 Enables data output for DIO30. 0x1E 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO31 Enables data output for DIO31. 0x1F 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 GPIOB_DOESET31_0 Data output enable set 31 to 0 0x12D0 32 write-only 0x00000000 DIO0 Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO0 in DOE31_0 0x1 DIO1 Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO1 in DOE31_0 0x1 DIO2 Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO2 in DOE31_0 0x1 DIO3 Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO3 in DOE31_0 0x1 DIO4 Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO4 in DOE31_0 0x1 DIO5 Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO5 in DOE31_0 0x1 DIO6 Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO6 in DOE31_0 0x1 DIO7 Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO7 in DOE31_0 0x1 DIO8 Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO8 in DOE31_0 0x1 DIO9 Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO9 in DOE31_0 0x1 DIO10 Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO10 in DOE31_0 0x1 DIO11 Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO11 in DOE31_0 0x1 DIO12 Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO12 in DOE31_0 0x1 DIO13 Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO13 in DOE31_0 0x1 DIO14 Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO14 in DOE31_0 0x1 DIO15 Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO15 in DOE31_0 0x1 DIO16 Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO16 in DOE31_0 0x1 DIO17 Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO17 in DOE31_0 0x1 DIO18 Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO18 in DOE31_0 0x1 DIO19 Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO19 in DOE31_0 0x1 DIO20 Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO20 in DOE31_0 0x1 DIO21 Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO21 in DOE31_0 0x1 DIO22 Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO22 in DOE31_0 0x1 DIO23 Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO23 in DOE31_0 0x1 DIO24 Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO24 in DOE31_0 0x1 DIO25 Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO25 in DOE31_0 0x1 DIO26 Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO26 in DOE31_0 0x1 DIO27 Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO27 in DOE31_0 0x1 DIO28 Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO28 in DOE31_0 0x1 DIO29 Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO29 in DOE31_0 0x1 DIO30 Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO30 in DOE31_0 0x1 DIO31 Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO31 in DOE31_0 0x1 GPIOB_DOECLR31_0 Data output enable clear 31 to 0 0x12E0 32 write-only 0x00000000 DIO0 Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO0 in DOE31_0 0x1 DIO1 Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO1 in DOE31_0 0x1 DIO2 Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO2 in DOE31_0 0x1 DIO3 Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO3 in DOE31_0 0x1 DIO4 Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO4 in DOE31_0 0x1 DIO5 Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO5 in DOE31_0 0x1 DIO6 Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO6 in DOE31_0 0x1 DIO7 Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO7 in DOE31_0 0x1 DIO8 Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO8 in DOE31_0 0x1 DIO9 Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO9 in DOE31_0 0x1 DIO10 Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO10 in DOE31_0 0x1 DIO11 Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO11 in DOE31_0 0x1 DIO12 Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO12 in DOE31_0 0x1 DIO13 Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO13 in DOE31_0 0x1 DIO14 Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO14 in DOE31_0 0x1 DIO15 Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO15 in DOE31_0 0x1 DIO16 Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO16 in DOE31_0 0x1 DIO17 Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO17 in DOE31_0 0x1 DIO18 Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO18 in DOE31_0 0x1 DIO19 Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO19 in DOE31_0 0x1 DIO20 Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO20 in DOE31_0 0x1 DIO21 Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO21 in DOE31_0 0x1 DIO22 Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO22 in DOE31_0 0x1 DIO23 Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO23 in DOE31_0 0x1 DIO24 Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO24 in DOE31_0 0x1 DIO25 Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO25 in DOE31_0 0x1 DIO26 Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO26 in DOE31_0 0x1 DIO27 Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO27 in DOE31_0 0x1 DIO28 Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO28 in DOE31_0 0x1 DIO29 Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO29 in DOE31_0 0x1 DIO30 Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO30 in DOE31_0 0x1 DIO31 Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO31 in DOE31_0 0x1 GPIOB_DIN3_0 Data input 3 to 0 0x1300 32 read-only 0x00000000 DIO0 This bit reads the data input value of DIO0. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO1 This bit reads the data input value of DIO1. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO2 This bit reads the data input value of DIO2. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO3 This bit reads the data input value of DIO3. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_DIN7_4 Data input 7 to 4 0x1304 32 read-only 0x00000000 DIO4 This bit reads the data input value of DIO4. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO5 This bit reads the data input value of DIO5. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO6 This bit reads the data input value of DIO6. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO7 This bit reads the data input value of DIO7. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_DIN11_8 Data input 11 to 8 0x1308 32 read-only 0x00000000 DIO8 This bit reads the data input value of DIO8. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO9 This bit reads the data input value of DIO9. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO10 This bit reads the data input value of DIO10. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO11 This bit reads the data input value of DIO11. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_DIN15_12 Data input 15 to 12 0x130C 32 read-only 0x00000000 DIO12 This bit reads the data input value of DIO12. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO13 This bit reads the data input value of DIO13. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO14 This bit reads the data input value of DIO14. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO15 This bit reads the data input value of DIO15. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_DIN19_16 Data input 19 to 16 0x1310 32 read-only 0x00000000 DIO16 This bit reads the data input value of DIO16. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO17 This bit reads the data input value of DIO17. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO18 This bit reads the data input value of DIO18. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO19 This bit reads the data input value of DIO19. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_DIN23_20 Data input 23 to 20 0x1314 32 read-only 0x00000000 DIO20 This bit reads the data input value of DIO20. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO21 This bit reads the data input value of DIO21. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO22 This bit reads the data input value of DIO22. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO23 This bit reads the data input value of DIO23. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_DIN27_24 Data input 27 to 24 0x1318 32 read-only 0x00000000 DIO24 This bit reads the data input value of DIO24. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO25 This bit reads the data input value of DIO25. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO26 This bit reads the data input value of DIO26. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO27 This bit reads the data input value of DIO27. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_DIN31_28 Data input 31 to 28 0x131C 32 read-only 0x00000000 DIO28 This bit reads the data input value of DIO28. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO29 This bit reads the data input value of DIO29. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO30 This bit reads the data input value of DIO30. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO31 This bit reads the data input value of DIO31. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_DIN31_0 Data input 31 to 0 0x1380 32 read-only 0x00000000 DIO0 This bit reads the data input value of DIO0. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO1 This bit reads the data input value of DIO1. 0x1 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO2 This bit reads the data input value of DIO2. 0x2 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO3 This bit reads the data input value of DIO3. 0x3 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO4 This bit reads the data input value of DIO4. 0x4 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO5 This bit reads the data input value of DIO5. 0x5 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO6 This bit reads the data input value of DIO6. 0x6 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO7 This bit reads the data input value of DIO7. 0x7 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO8 This bit reads the data input value of DIO8. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO9 This bit reads the data input value of DIO9. 0x9 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO10 This bit reads the data input value of DIO10. 0xA 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO11 This bit reads the data input value of DIO11. 0xB 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO12 This bit reads the data input value of DIO12. 0xC 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO13 This bit reads the data input value of DIO13. 0xD 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO14 This bit reads the data input value of DIO14. 0xE 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO15 This bit reads the data input value of DIO15. 0xF 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO16 This bit reads the data input value of DIO16. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO17 This bit reads the data input value of DIO17. 0x11 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO18 This bit reads the data input value of DIO18. 0x12 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO19 This bit reads the data input value of DIO19. 0x13 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO20 This bit reads the data input value of DIO20. 0x14 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO21 This bit reads the data input value of DIO21. 0x15 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO22 This bit reads the data input value of DIO22. 0x16 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO23 This bit reads the data input value of DIO23. 0x17 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO24 This bit reads the data input value of DIO24. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO25 This bit reads the data input value of DIO25. 0x19 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO26 This bit reads the data input value of DIO26. 0x1A 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO27 This bit reads the data input value of DIO27. 0x1B 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO28 This bit reads the data input value of DIO28. 0x1C 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO29 This bit reads the data input value of DIO29. 0x1D 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO30 This bit reads the data input value of DIO30. 0x1E 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO31 This bit reads the data input value of DIO31. 0x1F 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOB_POLARITY15_0 Polarity 15 to 0 0x1390 32 read-write 0x00000000 DIO0 Enables and configures edge detection polarity for DIO0. 0x0 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO1 Enables and configures edge detection polarity for DIO1. 0x2 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO2 Enables and configures edge detection polarity for DIO2. 0x4 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO3 Enables and configures edge detection polarity for DIO3. 0x6 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO4 Enables and configures edge detection polarity for DIO4. 0x8 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO5 Enables and configures edge detection polarity for DIO5. 0xA 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO6 Enables and configures edge detection polarity for DIO6. 0xC 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO7 Enables and configures edge detection polarity for DIO7. 0xE 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO8 Enables and configures edge detection polarity for DIO8. 0x10 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO9 Enables and configures edge detection polarity for DIO9. 0x12 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO10 Enables and configures edge detection polarity for DIO10. 0x14 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO11 Enables and configures edge detection polarity for DIO11. 0x16 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO12 Enables and configures edge detection polarity for DIO12. 0x18 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO13 Enables and configures edge detection polarity for DIO13. 0x1A 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO14 Enables and configures edge detection polarity for DIO14. 0x1C 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO15 Enables and configures edge detection polarity for DIO15. 0x1E 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 GPIOB_POLARITY31_16 Polarity 31 to 16 0x13A0 32 read-write 0x00000000 DIO16 Enables and configures edge detection polarity for DIO16. 0x0 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO17 Enables and configures edge detection polarity for DIO17. 0x2 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO18 Enables and configures edge detection polarity for DIO18. 0x4 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO19 Enables and configures edge detection polarity for DIO19. 0x6 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO20 Enables and configures edge detection polarity for DIO20. 0x8 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO21 Enables and configures edge detection polarity for DIO21. 0xA 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO22 Enables and configures edge detection polarity for DIO22. 0xC 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO23 Enables and configures edge detection polarity for DIO23. 0xE 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO24 Enables and configures edge detection polarity for DIO24. 0x10 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO25 Enables and configures edge detection polarity for DIO25. 0x12 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO26 Enables and configures edge detection polarity for DIO26. 0x14 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO27 Enables and configures edge detection polarity for DIO27. 0x16 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO28 Enables and configures edge detection polarity for DIO28. 0x18 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO29 Enables and configures edge detection polarity for DIO29. 0x1A 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO30 Enables and configures edge detection polarity for DIO30. 0x1C 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO31 Enables and configures edge detection polarity for DIO31. 0x1E 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 GPIOB_CTL FAST WAKE GLOBAL EN 0x1400 32 read-write 0x00000000 FASTWAKEONLY FASTWAKEONLY for the global control of fastwake 0x0 0x1 read-write NOT_GLOBAL_EN The global control of fastwake is not enabled, per bit fast wake feature depends on FASTWAKE.DIN 0x0 GLOBAL_EN The global control of fastwake is enabled 0x1 GPIOB_FASTWAKE FAST WAKE ENABLE 0x1404 32 read-write 0x00000000 DIN0 Enable fastwake feature for DIN0 0x0 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN1 Enable fastwake feature for DIN1 0x1 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN2 Enable fastwake feature for DIN2 0x2 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN3 Enable fastwake feature for DIN3 0x3 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN4 Enable fastwake feature for DIN4 0x4 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN5 Enable fastwake feature for DIN5 0x5 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN6 Enable fastwake feature for DIN6 0x6 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN7 Enable fastwake feature for DIN7 0x7 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN8 Enable fastwake feature for DIN8 0x8 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN9 Enable fastwake feature for DIN9 0x9 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN10 Enable fastwake feature for DIN10 0xA 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN11 Enable fastwake feature for DIN11 0xB 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN12 Enable fastwake feature for DIN12 0xC 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN13 Enable fastwake feature for DIN13 0xD 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN14 Enable fastwake feature for DIN14 0xE 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN15 Enable fastwake feature for DIN15 0xF 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN16 Enable fastwake feature for DIN16 0x10 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN17 Enable fastwake feature for DIN17 0x11 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN18 Enable fastwake feature for DIN18 0x12 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN19 Enable fastwake feature for DIN19 0x13 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN20 Enable fastwake feature for DIN20 0x14 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN21 Enable fastwake feature for DIN21 0x15 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN22 Enable fastwake feature for DIN22 0x16 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN23 Enable fastwake feature for DIN23 0x17 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN24 Enable fastwake feature for DIN24 0x18 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN25 Enable fastwake feature for DIN25 0x19 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN26 Enable fastwake feature for DIN26 0x1A 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN27 Enable fastwake feature for DIN27 0x1B 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN28 Enable fastwake feature for DIN29 0x1C 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN29 Enable fastwake feature for DIN29 0x1D 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN30 Enable fastwake feature for DIN30 0x1E 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN31 Enable fastwake feature for DIN31 0x1F 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 GPIOB_SUB0CFG Subscriber 0 configuration 0x1500 32 read-write 0x00000000 ENABLE This bit is used to enable subscriber 0 event. 0x0 0x1 read-write CLR Subscriber 0 event is disabled 0x0 SET Subscriber 0 event is enabled 0x1 OUTPOLICY These bits configure the output policy for subscriber 0 event. 0x8 0x2 read-write SET Selected DIO pins are set 0x0 CLR Selected DIO pins are cleared 0x1 TOGGLE Selected DIO pins are toggled 0x2 INDEX Indicates the specific bit among lower 16 bits that is targeted by the subscriber action 0x10 0x4 read-write MIN specific bit targeted by the subscriber action is bit0 0x0 MAX specific bit targeted by the subscriber action is bit15 0xF GPIOB_FILTEREN15_0 Filter Enable 15 to 0 0x1508 32 read-write 0x00000000 DIN0 Programmable counter length of digital glitch filter for DIN0 0x0 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN1 Programmable counter length of digital glitch filter for DIN1 0x2 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN2 Programmable counter length of digital glitch filter for DIN2 0x4 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN3 Programmable counter length of digital glitch filter for DIN3 0x6 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN4 Programmable counter length of digital glitch filter for DIN4 0x8 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN5 Programmable counter length of digital glitch filter for DIN5 0xA 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN6 Programmable counter length of digital glitch filter for DIN6 0xC 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN7 Programmable counter length of digital glitch filter for DIN7 0xE 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN8 Programmable counter length of digital glitch filter for DIN8 0x10 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN9 Programmable counter length of digital glitch filter for DIN9 0x12 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN10 Programmable counter length of digital glitch filter for DIN10 0x14 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN11 Programmable counter length of digital glitch filter for DIN11 0x16 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN12 Programmable counter length of digital glitch filter for DIN12 0x18 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN13 Programmable counter length of digital glitch filter for DIN13 0x1A 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN14 Programmable counter length of digital glitch filter for DIN14 0x1C 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN15 Programmable counter length of digital glitch filter for DIN15 0x1E 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 GPIOB_FILTEREN31_16 Filter Enable 31 to 16 0x150C 32 read-write 0x00000000 DIN16 Programmable counter length of digital glitch filter for DIN16 0x0 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN17 Programmable counter length of digital glitch filter for DIN17 0x2 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN18 Programmable counter length of digital glitch filter for DIN18 0x4 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN19 Programmable counter length of digital glitch filter for DIN19 0x6 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN20 Programmable counter length of digital glitch filter for DIN20 0x8 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN21 Programmable counter length of digital glitch filter for DIN21 0xA 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN22 Programmable counter length of digital glitch filter for DIN22 0xC 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN23 Programmable counter length of digital glitch filter for DIN23 0xE 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN24 Programmable counter length of digital glitch filter for DIN24 0x10 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN25 Programmable counter length of digital glitch filter for DIN25 0x12 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN26 Programmable counter length of digital glitch filter for DIN26 0x14 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN27 Programmable counter length of digital glitch filter for DIN27 0x16 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN28 Programmable counter length of digital glitch filter for DIN28 0x18 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN29 Programmable counter length of digital glitch filter for DIN29 0x1A 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN30 Programmable counter length of digital glitch filter for DIN30 0x1C 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN31 Programmable counter length of digital glitch filter for DIN31 0x1E 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 GPIOB_DMAMASK DMA Write MASK 0x1510 32 read-write 0x00000000 DOUT0 DMA is allowed to modify DOUT0 0x0 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT1 DMA is allowed to modify DOUT1 0x1 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT2 DMA is allowed to modify DOUT2 0x2 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT3 DMA is allowed to modify DOUT3 0x3 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT4 DMA is allowed to modify DOUT4 0x4 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT5 DMA is allowed to modify DOUT5 0x5 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT6 DMA is allowed to modify DOUT6 0x6 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT7 DMA is allowed to modify DOUT7 0x7 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT8 DMA is allowed to modify DOUT8 0x8 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT9 DMA is allowed to modify DOUT9 0x9 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT10 DMA is allowed to modify DOUT10 0xA 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT11 DMA is allowed to modify DOUT11 0xB 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT12 DMA is allowed to modify DOUT12 0xC 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT13 DMA is allowed to modify DOUT13 0xD 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT14 DMA is allowed to modify DOUT14 0xE 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT15 DMA is allowed to modify DOUT15 0xF 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT16 DMA is allowed to modify DOUT16 0x10 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT17 DMA is allowed to modify DOUT17 0x11 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT18 DMA is allowed to modify DOUT18 0x12 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT19 DMA is allowed to modify DOUT19 0x13 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT20 DMA is allowed to modify DOUT20 0x14 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT21 DMA is allowed to modify DOUT21 0x15 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT22 DMA is allowed to modify DOUT22 0x16 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT23 DMA is allowed to modify DOUT23 0x17 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT24 DMA is allowed to modify DOUT24 0x18 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT25 DMA is allowed to modify DOUT25 0x19 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT26 DMA is allowed to modify DOUT26 0x1A 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT27 DMA is allowed to modify DOUT27 0x1B 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT28 DMA is allowed to modify DOUT28 0x1C 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT29 DMA is allowed to modify DOUT29 0x1D 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT30 DMA is allowed to modify DOUT30 0x1E 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT31 DMA is allowed to modify DOUT31 0x1F 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 GPIOB_SUB1CFG Subscriber 1 configuration 0x1520 32 read-write 0x00000000 ENABLE This bit is used to enable subscriber 1 event. 0x0 0x1 read-write CLR Subscriber 1 event is disabled 0x0 SET Subscriber 1 event is enabled 0x1 OUTPOLICY These bits configure the output policy for subscriber 1 event. 0x8 0x2 read-write SET Selected DIO pins are set 0x0 CLR Selected DIO pins are cleared 0x1 TOGGLE Selected DIO pins are toggled 0x2 INDEX indicates the specific bit in the upper 16 bits that is targeted by the subscriber action 0x10 0x4 read-write MIN specific bit targeted by the subscriber action is bit16 0x0 MAX specific bit targeted by the subscriber action is bit31 0xF UART1 UART 1.0 PERIPHERALREGION 0x40100000 0x0 0x1F00 registers 1 24 0 UART1_GPRCM[%s] 0x800 UART1_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 UART1_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 UART1_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 UART1_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 UART1_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 UART1_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 UART1_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 UART1_CPU_INT[%s] 0x1020 UART1_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 FEFG UART framing error interrupt; Interrupt Flag: FE 0x2 PEFG UART parity error interrupt; Interrupt Flag: PE 0x3 BEFG UART break error interrupt; Interrupt Flag: BE 0x4 OEFG UART receive overrun error interrupt; Interrupt Flag: OE 0x5 RXNE Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE 0x6 RXPE Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE 0x7 LINC0 LIN capture 0 / match interrupt; Interrupt Flag: LINC0 0x8 LINC1 LIN capture 1 interrupt; Interrupt Flag: LINC1 0x9 LINOVF LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF 0xA RXIFG UART receive interrupt; Interrupt Flag: RX 0xB TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC EOT UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT 0xD MODE_9B 9-bit mode address match interrupt; Interrupt Flag: MODE_9B 0xE CTS UART Clear to Send Modem interrupt; Interrupt Flag: CTS 0xF DMA_DONE_RX DMA DONE on RX 0x10 DMA_DONE_TX DMA DONE on TX 0x11 NERR_EVT Noise Error Event 0x12 UART1_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PARERR Enable UART Parity Error Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 BRKERR Enable UART Break Error Interrupt. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTS Enable UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX Enable DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX Enable DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART1_CPU_INT_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_RX DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_TX DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART1_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR Masked UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR Masked UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS Masked UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_RX Masked DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_TX Masked DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART1_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 FRMERR Set UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PARERR Set UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 BRKERR Set UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTS Set UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing this has no effect 0x0 SET Set the interrupt 0x1 UART1_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PARERR Clear UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 BRKERR Clear UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTS Clear UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART1_DMA_TRIG_RX[%s] 0x1050 UART1_DMA_TRIG_RX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 RXIFG UART receive interrupt; Interrupt Flag: RX 0xB UART1_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART1_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART1_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART1_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART1_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART1_DMA_TRIG_TX[%s] 0x1080 UART1_DMA_TRIG_TX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC UART1_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART1_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART1_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART1_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART1_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 UART1_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 UART1_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 UART1_CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write DISABLE Disable Module 0x0 ENABLE Enable module 0x1 HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write OVS16 16x oversampling. 0x0 OVS8 8x oversampling. 0x1 OVS3 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled. 0x2 LBE UART Loop Back Enable 0x2 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The UARTxTX path is fed through the UARTxRX path internally. 0x1 RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write DISABLE The receive section of the UART is disabled. 0x0 ENABLE The receive section of the UART is enabled. 0x1 TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write DISABLE The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled. 0x0 ENABLE The transmit section of the UART is enabled. 0x1 RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CLR Signal not RTS 0x0 SET Signal RTS 0x1 RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write DISABLE RTS hardware flow control is disabled. 0x0 ENABLE RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries. 0x1 CTSEN Enable Clear To Send 0xE 0x1 read-write DISABLE CTS hardware flow control is disabled. 0x0 ENABLE CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted. 0x1 MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write UART Normal operation 0x0 RS485 RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data. 0x1 IDLELINE The UART operates in IDLE Line Mode 0x2 ADDR9BIT The UART operates in 9 Bit Address mode 0x3 SMART ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. 0x4 DALI DALI Mode: 0x5 FEN UART Enable FIFOs 0x11 0x1 read-write DISABLE The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 0x0 ENABLE The transmit and receive FIFO buffers are enabled (FIFO mode). 0x1 TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write LOW TXD pin is low 0x0 HIGH TXD pin is high 0x1 TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 0x5 0x1 read-write DISABLE TXD pin can not be controlled by TXD_OUT 0x0 ENABLE TXD pin can be controlled by TXD_OUT 0x1 MAJVOTE Majority Vote Enable When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (i.e. all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set. Oversampling of 16 : bits 7, 8, 9 are used Oversampling of 8 : bits 3, 4, 5 are used Disabled : Single sample value (center value) used 0x12 0x1 read-write DISABLE Majority voting is disabled 0x0 ENABLE Majority voting is enabled 0x1 MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write DISABLE Least significant bit is sent first in the protocol packet 0x0 ENABLE Most significant bit is sent first in the protocol packet 0x1 UART1_LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write DISABLE Normal use. 0x0 ENABLE A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0x1 PEN UART Parity Enable 0x1 0x1 read-write DISABLE Parity is disabled and no parity bit is added to the data frame. 0x0 ENABLE Parity checking and generation is enabled. 0x1 EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write ODD Odd parity is performed, which checks for an odd number of 1s. 0x0 EVEN Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0x1 STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write DISABLE One stop bit is transmitted at the end of a frame. 0x0 ENABLE Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid. 0x1 WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write DATABIT5 5 bits (default) 0x0 DATABIT6 6 bits 0x1 DATABIT7 7 bits 0x2 DATABIT8 8 bits 0x3 SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write DISABLE Disable Stick Parity 0x0 ENABLE Enable Stick Parity 0x1 SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write DISABLE Disable Send Idle Pattern 0x0 ENABLE Enable Send Idle Pattern 0x1 EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write UART1_STAT UART Status Register 0x1108 32 read-only BUSY UART Busy This bit is set as soon as the transmit FIFO or TXDATA register becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only CLEARED The UART is not busy. 0x0 SET The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register. 0x1 TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only CLEARED The transmitter is not full. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0x1 RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only CLEARED The receiver can receive data. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0x1 TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only CLEARED The transmitter has data to transmit. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0x1 CTS Clear To Send 0x8 0x1 read-only CLEARED The CTS signal is not asserted (high). 0x0 SET The CTS signal is asserted (low). 0x1 IDLE IDLE mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only CLEARED IDLE has not been detected before last received character. (In idle-line multiprocessor mode). 0x0 SET IDLE has been detected before last received character. (In idle-line multiprocessor mode). 0x1 RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only CLEARED The receiver is not empty. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0x1 UART1_IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_EMPTY TX FIFO is empty 0x5 LVL_1 TX FIFO >= 1 entry free Note: esp. required for DMA Trigger 0x7 RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write LVL_1_4_RES RX FIFO >= 1/4 full Note: For ULP Domain 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_FULL_RES RX FIFO is full Note: For ULP Domain 0x4 LVL_FULL RX FIFO is full 0x5 LVL_1 RX FIFO >= 1 entry available Note: esp. required for DMA Trigger 0x7 RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write UART1_IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write UART1_FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write UART1_GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. 0x9 0x2 read-write AGLIT_5 Pulses shorter then 5ns length are filtered. 0x0 AGLIT_10 Pulses shorter then 10ns length are filtered. 0x1 AGLIT_25 Pulses shorter then 25ns length are filtered. 0x2 AGLIT_50 Pulses shorter then 50ns length are filtered. 0x3 AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write DISABLE Analog Glitch Filter disable 0x0 ENABLE Analog Glitch Filter enable 0x1 CHAIN Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0xB 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 UART1_TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write UART1_RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff DATA Received Data. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only CLR No framing error has occurred 0x0 SET The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1). 0x1 PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only CLR No parity error has occurred 0x0 SET The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0x1 BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only CLR No break condition has occurred 0x0 SET A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0x1 OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only CLR No data has been lost due to a receive overrun. 0x0 SET New data was received but could not be stored, because the previous data was not read (resulting in data loss). 0x1 NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only CLR No noise error occured 0x0 SET Noise error occured during majority voting 0x1 UART1_AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff MSK Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register must match. 0x0 0x8 read-write UART1_ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh. 0x0 0x8 read-write WWDT0 WWDT 1.0 WWDT 0x40080000 0x0 0x1500 registers 1 24 0 WWDT0_GPRCM[%s] 0x800 WWDT0_PWREN Power enable 0x0 32 read-write ENABLE Enable the power Note: For safety devices the power cannot be disabled once enabled. 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 WWDT0_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear [GPRCM.STAT.RESETSTKY] 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible. 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 WWDT0_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 WWDT0_PDBGCTL Peripheral Debug Control 0x1018 32 read-write 0x00000000 FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 1 44 0 WWDT0_INT_EVENT[%s] 0x1020 WWDT0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 0x0 0x5 read-only NO_INTR No interrupt pending 0x0 INTTIM Interval Timer Interrupt; Interrupt Flag: INTTIM; Interrupt Priority: Highest 0x1 WWDT0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 WWDT0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 WWDT0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 WWDT0_ISET Interrupt set 0x20 32 write-only 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 WWDT0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 WWDT0_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 WWDT0_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 WWDT0_WWDTCTL0 Window Watchdog Timer Control Register 0 0x1100 32 read-write 0x00000043 0xffffffff PER Timer Period of the WWDT. These bits select the total watchdog timer count. 0x4 0x3 read-write EN_25 Total timer count is 2^25 0x0 EN_21 Total timer count is 2^21 0x1 EN_18 Total timer count is 2^18 0x2 EN_15 Total timer count is 2^15 0x3 EN_12 Total timer count is 2^12 (default) 0x4 EN_10 Total timer count is 2^10 0x5 EN_8 Total timer count is 2^8 0x6 EN_6 Total timer count is 2^6 0x7 WINDOW0 Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1). 0x8 0x3 read-write SIZE_0 0% (No closed Window) 0x0 SIZE_12 12.50% of the total timer period is closed window 0x1 SIZE_18 18.75% of the total timer period is closed window 0x2 SIZE_25 25% of the total timer period is closed window 0x3 SIZE_50 50% of the total timer period is closed window 0x4 SIZE_75 75% of the total timer period is closed window 0x5 SIZE_81 81.25% of the total timer period is closed window 0x6 SIZE_87 87.50% of the total timer period is closed window 0x7 MODE Window Watchdog Timer Mode 0x10 0x1 read-write WINDOW Window Watchdog Timer Mode. The WWDT will generate a error signal to the ESM when following conditions occur: - Timer Expiration (Timeout) - Reset WWDT during the active window closed period - Keyword violation 0x0 INTERVAL Interval Timer Mode. The WWDT acts as an interval timer. It generates an interrupt on timeout. 0x1 STISM Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported. 0x11 0x1 read-write CONT The WWDT continues to function in Sleep mode. 0x0 STOP The WWDT stops in Sleep mode and resumes where it was stopped after wakeup. 0x1 CLKDIV Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0. 0x0 0x3 read-write WINDOW1 Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1). 0xC 0x3 read-write SIZE_0 0% (No closed Window) 0x0 SIZE_12 12.50% of the total timer period is closed window 0x1 SIZE_18 18.75% of the total timer period is closed window 0x2 SIZE_25 25% of the total timer period is closed window 0x3 SIZE_50 50% of the total timer period is closed window 0x4 SIZE_75 75% of the total timer period is closed window 0x5 SIZE_81 81.25% of the total timer period is closed window 0x6 SIZE_87 87.50% of the total timer period is closed window 0x7 WWDT0_WWDTCTL1 Window Watchdog Timer Control Register 0 0x1104 32 read-write 0x00000000 0xffffffff WINSEL Close Window Select 0x0 0x1 read-write WIN0 In window mode field WINDOW0 of WDDTCTL0 defines the closed window size. 0x0 WIN1 In window mode field WINDOW1 of WDDTCTL0 defines the closed window size. 0x1 WWDT0_WWDTCNTRST Window Watchdog Timer Counter Reset Register 0x1108 32 read-write 0x00000000 0xffffffff RESTART Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0. 0x0 0x20 read-write WWDT0_WWDTSTAT Window Watchdog Timer Status Register 0x110C 32 read-only 0x00000000 0xffffffff RUN Watchdog running status flag. 0x0 0x1 read-only OFF Watchdog counter stopped. 0x0 ON Watchdog running. 0x1 COMP1 COMP 1.0 PERIPHERALREGION 0x4000A000 0x0 0x1F00 registers COMP1_FSUB_0 Subscriber Port 0 0x400 32 read-write CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 COMP1_FSUB_1 Subscriber Port 1 0x404 32 read-write CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 COMP1_FPUB_1 Publisher port 1 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 COMP1_GPRCM[%s] 0x800 COMP1_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 COMP1_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 COMP1_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable disable COMP to request SYSOSC 0x0 Enable enable COMP to request SYSOSC 0x1 COMP1_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 1 44 0 COMP1_CPU_INT[%s] 0x1020 COMP1_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x2 read-only NO_INTR No pending interrupt 0x0 COMPIFG Comparator output interrupt 0x2 COMPINVIFG Comparator output inverted interrupt 0x3 OUTRDYIFG Comparator output ready interrupt 0x4 COMP1_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 COMPIFG Masks COMPIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMPINVIFG Masks COMPINVIFG 0x2 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 OUTRDYIFG Masks OUTRDYIFG 0x3 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMP1_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 COMPIFG Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x1 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMPINVIFG Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x2 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 OUTRDYIFG Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid. 0x3 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMP1_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 COMPIFG Masked interrupt status for COMPIFG 0x1 0x1 CLR COMPIFG does not request an interrupt service routine 0x0 SET COMPIFG requests an interrupt service routine 0x1 COMPINVIFG Masked interrupt status for COMPINVIFG 0x2 0x1 CLR COMPINVIFG does not request an interrupt service routine 0x0 SET COMPINVIFG requests an interrupt service routine 0x1 OUTRDYIFG Masked interrupt status for OUTRDYIFG 0x3 0x1 CLR OUTRDYIFG does not request an interrupt service routine 0x0 SET OUTRDYIFG requests an interrupt service routine 0x1 COMP1_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 COMPIFG Sets COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPIFG is set 0x1 COMPINVIFG Sets COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPINVIFG is set 0x1 OUTRDYIFG Sets OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to OUTRDYIFG is set 0x1 COMP1_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 COMPIFG Clears COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPIFG is cleared 0x1 COMPINVIFG Clears COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPINVIFG is cleared 0x1 OUTRDYIFG Clears OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to OUTRDYIFG is cleared 0x1 1 44 0 COMP1_GEN_EVENT[%s] 0x1050 COMP1_GEN_EVENT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x2 read-only NO_INTR No pending interrupt 0x0 COMPIFG Comparator output interrupt 0x2 COMPINVIFG Comparator output inverted interrupt 0x3 OUTRDYIFG Comparator output ready interrupt 0x4 COMP1_GEN_EVENT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 COMPIFG Masks COMPIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMPINVIFG Masks COMPINVIFG 0x2 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 OUTRDYIFG Masks OUTRDYIFG 0x3 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMP1_GEN_EVENT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 COMPIFG Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x1 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMPINVIFG Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x2 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 OUTRDYIFG Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid. 0x3 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMP1_GEN_EVENT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 COMPIFG Masked interrupt status for COMPIFG 0x1 0x1 CLR COMPIFG does not request an interrupt service routine 0x0 SET COMPIFG requests an interrupt service routine 0x1 COMPINVIFG Masked interrupt status for COMPINVIFG 0x2 0x1 CLR COMPINVIFG does not request an interrupt service routine 0x0 SET COMPINVIFG requests an interrupt service routine 0x1 OUTRDYIFG Masked interrupt status for OUTRDYIFG 0x3 0x1 CLR OUTRDYIFG does not request an interrupt service routine 0x0 SET OUTRDYIFG requests an interrupt service routine 0x1 COMP1_GEN_EVENT_ISET Interrupt set 0x20 32 write-only 0x00000000 COMPIFG Sets COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPIFG is set 0x1 COMPINVIFG Sets COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPINVIFG is set 0x1 OUTRDYIFG Sets OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to OUTRDYIFG is set 0x1 COMP1_GEN_EVENT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 COMPIFG Clears COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPIFG is cleared 0x1 COMPINVIFG Clears COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPINVIFG is cleared 0x1 OUTRDYIFG Clears OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to OUTRDYIFG is cleared 0x1 COMP1_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000009 INT0_CFG Event line mode select for event corresponding to CPU_INT 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to GEN_EVENT 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 COMP1_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 read-only MAJREV Major rev of the IP 0x4 0x4 read-only FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only COMP1_CTL0 Control 0 0x1100 32 read-write 0x00000000 IPSEL Channel input selected for the positive terminal of the comparator if IPEN is set to 1. 0x0 0x3 read-write CH_0 Channel 0 selected 0x0 CH_1 Channel 1 selected 0x1 CH_2 Channel 2 selected 0x2 CH_3 Channel 3 selected 0x3 CH_4 Channel 4 selected 0x4 CH_5 Channel 5 selected 0x5 CH_6 Channel 6 selected 0x6 CH_7 Channel 7 selected 0x7 IPEN Channel input enable for the positive terminal of the comparator. 0xF 0x1 read-write DISABLE Selected analog input channel for positive terminal is disabled 0x0 ENABLE Selected analog input channel for positive terminal is enabled 0x1 IMEN Channel input enable for the negative terminal of the comparator. 0x1F 0x1 read-write DISABLE Selected analog input channel for negative terminal is disabled 0x0 ENABLE Selected analog input channel for negative terminal is enabled 0x1 IMSEL Channel input selected for the negative terminal of the comparator if IMEN is set to 1. 0x10 0x3 read-write CH_0 Channel 0 selected 0x0 CH_1 Channel 1 selected 0x1 CH_2 Channel 2 selected 0x2 CH_3 Channel 3 selected 0x3 CH_4 Channel 4 selected 0x4 CH_5 Channel 5 selected 0x5 CH_6 Channel 6 selected 0x6 CH_7 Channel 7 selected 0x7 COMP1_CTL1 Control 1 0x1104 32 read-write 0x00000000 ENABLE This bit turns on the comparator. When the comparator is turned off it consumes no power. 0x0 0x1 read-write OFF Comparator is off 0x0 ON Comparator is on 0x1 MODE This bit selects the comparator operating mode. 0x1 0x1 read-write FAST Comparator is in fast mode 0x0 ULP Comparator is in ultra-low power mode 0x1 EXCH This bit exchanges the comparator inputs and inverts the comparator output. 0x2 0x1 read-write NO_EXC Comparator inputs not exchanged and output not inverted 0x0 EXC Comparator inputs exchanged and output inverted 0x1 SHORT This bit shorts the positive and negative input terminals of the comparator. 0x3 0x1 read-write NO_SHT Comparator positive and negative input terminals are not shorted 0x0 SHT Comparator positive and negative input terminals are shorted 0x1 IES This bit selected the interrupt edge for COMPIFG and COMPINVIFG. 0x4 0x1 read-write RISING Rising edge sets COMPIFG and falling edge sets COMPINVIFG 0x0 FALLING Falling edge sets COMPIFG and rising edge sets COMPINVIFG 0x1 HYST These bits select the hysteresis setting of the comparator. 0x5 0x2 read-write NO_HYS No hysteresis 0x0 LOW_HYS Low hysteresis, typical 10mV 0x1 MED_HYS Medium hysteresis, typical 20mV 0x2 HIGH_HYS High hysteresis, typical 30mV 0x3 OUTPOL This bit selects the comparator output polarity. 0x7 0x1 read-write NON_INV Comparator output is non-inverted 0x0 INV Comparator output is inverted 0x1 FLTEN This bit enables the analog filter at comparator output. 0x8 0x1 read-write DISABLE Comparator output filter is disabled 0x0 ENABLE Comparator output filter is enabled 0x1 FLTDLY These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings. 0x9 0x2 read-write DLY_0 Typical filter delay of 70 ns 0x0 DLY_1 Typical filter delay of 500 ns 0x1 DLY_2 Typical filter delay of 1200 ns 0x2 DLY_3 Typical filter delay of 2700 ns 0x3 WINCOMPEN This bit enables window comparator operation of comparator. 0xC 0x1 read-write OFF window comparator is disable 0x0 ON window comparator is enable 0x1 COMP1_CTL2 Control 2 0x1108 32 read-write 0x00000000 REFMODE This bit requests ULP_REF bandgap operation in fast mode(static) or low power mode (sampled). The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Fast mode operation offers higher accuracy but consumes higher current. Low power operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL > 0. 0x0 0x1 read-write STATIC ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in static mode. 0x0 SAMPLED ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in sampled mode. 0x1 REFSRC These bits select the reference source for the comparator. 0x3 0x3 read-write OFF Reference voltage generator is disabled (local reference buffer as well as DAC). 0x0 VDDA_DAC VDDA selected as the reference source to DAC and DAC output applied as reference to comparator. 0x1 VREF_DAC VREF selected as reference to DAC and DAC output applied as reference to comparator. 0x2 VREF In devices where internal VREF is buffered and hookedup to extrernal VREF pin, VREF applied as reference to comparator. DAC is switched off. Note: In LEGO_A3, DAC is turned off in this selection, in other deviced DAC is kept on. 0x3 VDDA VDDA is used as comparator reference. Note: In LEGO_A3, DAC is turned off in this selection, in other deviced DAC is kept on. 0x5 INTVREF_DAC Internal reference selected as the reference source to DAC and DAC output applied as reference to comparator. 0x6 INTVREF Internal VREF is used as the source of comparator. Not all devices will have this option. 0x7 REFSEL This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator. 0x7 0x1 read-write POSITIVE If EXCH bit is 0, the selected reference is applied to positive terminal. If EXCH bit is 1, the selected reference is applied to negative terminal. 0x0 NEGATIVE If EXCH bit is 0, the selected reference is applied to negative terminal. If EXCH bit is 1, the selected reference is applied to positive terminal. 0x1 DACCTL This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1. 0x10 0x1 read-write COMPOUT_SEL Comparator output controls selection between DACCODE0 and DACCODE1 0x0 DACSW_SEL DACSW bit controls selection between DACCODE0 and DACCODE1 0x1 DACSW This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1. 0x11 0x1 read-write DACCODE0_SEL DACCODE0 selected for 8-bit DAC 0x0 DACCODE1_SEL DACCODE1 selected for 8-bit DAC 0x1 BLANKSRC These bits select the blanking source for the comparator. 0x8 0x3 read-write DISABLE Blanking source disabled 0x0 BLANKSRC1 Select Blanking Source 1 0x1 BLANKSRC2 Select Blanking Source 2 0x2 BLANKSRC3 Select Blanking Source 3 0x3 BLANKSRC4 Select Blanking Source 4 0x4 BLANKSRC5 Select Blanking Source 5 0x5 BLANKSRC6 Select Blanking Source 6 0x6 SAMPMODE Enable sampled mode of comparator. 0x18 0x1 read-write DISABLE Sampled mode disabled 0x0 ENABLE Sampled mode enabled 0x1 COMP1_CTL3 Control 3 0x110C 32 read-write 0x00000000 DACCODE0 This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. 0x0 0x8 read-write DACCODE1 This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. 0x10 0x8 read-write COMP1_STAT Status 0x1120 32 read-only 0x00000000 OUT This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output. 0x0 0x1 read-only LOW Comparator output is low 0x0 HIGH Comparator output is high 0x1 DAC0 DAC 1.0 PERIPHERALREGION 0x40018000 0x0 0x1F00 registers DAC0_FSUB_0 Subscriber Port 0 0x400 32 read-write CHANID 0 = disconnected. others = connected to channel_ID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 DAC0_FPUB_1 Publisher port 1 0x444 32 read-write CHANID 0 = disconnected. others = connected to channel_ID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 DAC0_GPRCM[%s] 0x800 DAC0_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 DAC0_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 DAC0_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 1 44 0 DAC0_CPU_INT[%s] 0x1020 DAC0_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x4 read-only NO_INTR No pending interrupt 0x0 MODRDYIFG Module ready interrupt 0x2 FIFOFULLIFG FIFO full interrupt 0x9 FIFO1B4IFG FIFO one fourth empty interrupt 0xA FIFO1B2IFG FIFO half empty interrupt 0xB FIFO3B4IFG FIFO three fourth empty interrupt 0xC FIFOEMPTYIFG FIFO empty interrupt 0xD FIFOURUNIFG FIFO underrun interrupt 0xE DMADONEIFG DMA done interrupt 0xF DAC0_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 MODRDYIFG Masks MODRDYIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO1B2IFG Masks FIFO1B2IFG 0xA 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOEMPTYIFG Masks FIFOEMPTYIFG 0xC 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO1B4IFG Masks FIFO1B4IFG 0x9 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO3B4IFG Masks FIFO3B4IFG 0xB 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOFULLIFG Masks FIFOFULLIFG 0x8 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOURUNIFG Masks FIFOURUNIFG 0xD 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 DMADONEIFG Masks DMADONEIFG 0xE 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 DAC0_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00001e00 MODRDYIFG Raw interrupt status for MODRDYIFG 0x1 0x1 CLR DAC module ready event did not occur 0x0 SET DAC module ready event occurred 0x1 FIFOEMPTYIFG Raw interrupt status for FIFOEMPTYIFG 0xC 0x1 CLR FIFO empty condition did not occur 0x0 SET FIFO empty condition occurred 0x1 FIFO1B4IFG Raw interrupt status for FIFO1B4IFG 0x9 0x1 CLR FIFO one fourth empty condition did not occur 0x0 SET FIFO one fourth empty condition occurred 0x1 FIFO1B2IFG Raw interrupt status for FIFO1B2IFG 0xA 0x1 CLR FIFO half empty condition did not occur 0x0 SET FIFO half empty condition occurred 0x1 FIFO3B4IFG Raw interrupt status for FIFO3B4IFG 0xB 0x1 CLR FIFO three fourth empty condition did not occur 0x0 SET FIFO three fourth empty condition occurred 0x1 FIFOFULLIFG Raw interrupt status for FIFOFULLIFG 0x8 0x1 CLR FIFO full condition did not occur 0x0 SET FIFO full condition occurred 0x1 FIFOURUNIFG Raw interrupt status for FIFOURUNIFG 0xD 0x1 CLR FIFO underrun condition did not occur 0x0 SET FIFO underrun condition occurred 0x1 DMADONEIFG Raw interrupt status for DMADONEIFG 0xE 0x1 CLR DMA done condition did not occur 0x0 SET DMA done condition occurred 0x1 DAC0_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 MODRDYIFG Masked interrupt status for MODRDYIFG 0x1 0x1 CLR MODRDYIFG does not request an interrupt service routine 0x0 SET MODRDYIFG requests an interrupt service routine 0x1 FIFOEMPTYIFG Masked interrupt status for FIFOEMPTYIFG 0xC 0x1 CLR FIFOEMPTYIFG does not request an interrupt service routine 0x0 SET FIFOEMPTYIFG requests an interrupt service routine 0x1 FIFO1B4IFG Masked interrupt status for FIFO1B4IFG 0x9 0x1 CLR FIFO1B4IFG does not request an interrupt service routine 0x0 SET FIFO1B4IFG requests an interrupt service routine 0x1 FIFO1B2IFG Masked interrupt status for FIFO1B2IFG 0xA 0x1 CLR FIFO1B2IFG does not request an interrupt service routine 0x0 SET FIFO1B2IFG requests an interrupt service routine 0x1 FIFO3B4IFG Masked interrupt status for FIFO3B4IFG 0xB 0x1 CLR FIFO3B4IFG does not request an interrupt service routine 0x0 SET FIFO3B4IFG requests an interrupt service routine 0x1 FIFOFULLIFG Masked interrupt status for FIFOFULLIFG 0x8 0x1 CLR FIFOFULLIFG does not request an interrupt service routine 0x0 SET FIFOFULLIFG requests an interrupt service routine 0x1 FIFOURUNIFG Masked interrupt status for FIFOURUNIFG 0xD 0x1 CLR FIFOURUNIFG does not request an interrupt service routine 0x0 SET FIFOURUNIFG requests an interrupt service routine 0x1 DMADONEIFG Masked interrupt status for DMADONEIFG 0xE 0x1 CLR DMADONEIFG does not request an interrupt service routine 0x0 SET DMADONEIFG requests an interrupt service routine 0x1 DAC0_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 MODRDYIFG Sets MODRDYIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to MODRDYIFG is set 0x1 FIFOEMPTYIFG Sets FIFOEMPTYIFG in RIS register 0xC 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFOEMPTYIFG is set 0x1 FIFO1B4IFG Sets FIFO1B4IFG in RIS register 0x9 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFO1B4IFG is set 0x1 FIFO1B2IFG Sets FIFO1B2IFG in RIS register 0xA 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFO1B2IFG is set 0x1 FIFO3B4IFG Sets FIFO3B4IFG in RIS register 0xB 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFO3B4IFG is set 0x1 FIFOFULLIFG Sets FIFOFULLIFG in RIS register 0x8 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFOFULLIFG is set 0x1 FIFOURUNIFG Sets FIFOURUNIFG in RIS register 0xD 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFOURUNIFG is set 0x1 DMADONEIFG Sets DMADONEIFG in RIS register 0xE 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to DMADONEIFG is set 0x1 DAC0_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 MODRDYIFG Clears MODRDYIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to MODRDYIFG is cleared 0x1 FIFOEMPTYIFG Clears FIFOEMPTYIFG in RIS register 0xC 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFOEMPTYIFG is cleared 0x1 FIFO1B4IFG Clears FIFO1B4IFG in RIS register 0x9 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFO1B4IFG is cleared 0x1 FIFO1B2IFG Clears FIFO1B2IFG in RIS register 0xA 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFO1B2IFG is cleared 0x1 FIFO3B4IFG Clears FIFO3B4IFG in RIS register 0xB 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFO3B4IFG is cleared 0x1 FIFOFULLIFG Clears FIFOFULLIFG in RIS register 0x8 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFOFULLIFG is cleared 0x1 FIFOURUNIFG Clears FIFOURUNIFG in RIS register 0xD 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFOURUNIFG is cleared 0x1 DMADONEIFG Clears DMADONEIFG in RIS register 0xE 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to DMADONEIFG is cleared 0x1 1 44 0 DAC0_GEN_EVENT[%s] 0x1050 DAC0_GEN_EVENT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x4 read-only NO_INTR No pending interrupt 0x0 MODRDYIFG Module ready interrupt 0x2 FIFOFULLIFG FIFO full interrupt 0x9 FIFO1B4IFG FIFO one fourth empty interrupt 0xA FIFO1B2IFG FIFO half empty interrupt 0xB FIFO3B4IFG FIFO three fourth empty interrupt 0xC FIFOEMPTYIFG FIFO empty interrupt 0xD FIFOURUNIFG FIFO underrun interrupt 0xE DMADONEIFG DMA done interrupt 0xF DAC0_GEN_EVENT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 MODRDYIFG Masks MODRDYIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO1B2IFG Masks FIFO1B2IFG 0xA 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOEMPTYIFG Masks FIFOEMPTYIFG 0xC 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO1B4IFG Masks FIFO1B4IFG 0x9 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO3B4IFG Masks FIFO3B4IFG 0xB 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOFULLIFG Masks FIFOFULLIFG 0x8 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOURUNIFG Masks FIFOURUNIFG 0xD 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 DMADONEIFG Masks DMADONEIFG 0xE 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 DAC0_GEN_EVENT_RIS Raw interrupt status 0x10 32 read-only 0x00001e00 MODRDYIFG Raw interrupt status for MODRDYIFG 0x1 0x1 CLR DAC module ready event did not occur 0x0 SET DAC module ready event occurred 0x1 FIFOEMPTYIFG Raw interrupt status for FIFOEMPTYIFG 0xC 0x1 CLR FIFO empty condition did not occur 0x0 SET FIFO empty condition occurred 0x1 FIFO1B4IFG Raw interrupt status for FIFO1B4IFG 0x9 0x1 CLR FIFO one fourth empty condition did not occur 0x0 SET FIFO one fourth empty condition occurred 0x1 FIFO1B2IFG Raw interrupt status for FIFO1B2IFG 0xA 0x1 CLR FIFO half empty condition did not occur 0x0 SET FIFO half empty condition occurred 0x1 FIFO3B4IFG Raw interrupt status for FIFO3B4IFG 0xB 0x1 CLR FIFO three fourth empty condition did not occur 0x0 SET FIFO three fourth empty condition occurred 0x1 FIFOFULLIFG Raw interrupt status for FIFOFULLIFG 0x8 0x1 CLR FIFO full condition did not occur 0x0 SET FIFO full condition occurred 0x1 FIFOURUNIFG Raw interrupt status for FIFOURUNIFG 0xD 0x1 CLR FIFO underrun condition did not occur 0x0 SET FIFO underrun condition occurred 0x1 DMADONEIFG Raw interrupt status for DMADONEIFG 0xE 0x1 CLR DMA done condition did not occur 0x0 SET DMA done condition occurred 0x1 DAC0_GEN_EVENT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 MODRDYIFG Masked interrupt status for MODRDYIFG 0x1 0x1 CLR MODRDYIFG does not request an interrupt service routine 0x0 SET MODRDYIFG requests an interrupt service routine 0x1 FIFOEMPTYIFG Masked interrupt status for FIFOEMPTYIFG 0xC 0x1 CLR FIFOEMPTYIFG does not request an interrupt service routine 0x0 SET FIFOEMPTYIFG requests an interrupt service routine 0x1 FIFO1B4IFG Masked interrupt status for FIFO1B4IFG 0x9 0x1 CLR FIFO1B4IFG does not request an interrupt service routine 0x0 SET FIFO1B4IFG requests an interrupt service routine 0x1 FIFO1B2IFG Masked interrupt status for FIFO1B2IFG 0xA 0x1 CLR FIFO1B2IFG does not request an interrupt service routine 0x0 SET FIFO1B2IFG requests an interrupt service routine 0x1 FIFO3B4IFG Masked interrupt status for FIFO3B4IFG 0xB 0x1 CLR FIFO3B4IFG does not request an interrupt service routine 0x0 SET FIFO3B4IFG requests an interrupt service routine 0x1 FIFOFULLIFG Masked interrupt status for FIFOFULLIFG 0x8 0x1 CLR FIFOFULLIFG does not request an interrupt service routine 0x0 SET FIFOFULLIFG requests an interrupt service routine 0x1 FIFOURUNIFG Masked interrupt status for FIFOURUNIFG 0xD 0x1 CLR FIFOURUNIFG does not request an interrupt service routine 0x0 SET FIFOURUNIFG requests an interrupt service routine 0x1 DMADONEIFG Masked interrupt status for DMADONEIFG 0xE 0x1 CLR DMADONEIFG does not request an interrupt service routine 0x0 SET DMADONEIFG requests an interrupt service routine 0x1 DAC0_GEN_EVENT_ISET Interrupt set 0x20 32 write-only 0x00000000 MODRDYIFG Sets MODRDYIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to MODRDYIFG is set 0x1 FIFOEMPTYIFG Sets FIFOEMPTYIFG in RIS register 0xC 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFOEMPTYIFG is set 0x1 FIFO1B4IFG Sets FIFO1B4IFG in RIS register 0x9 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFO1B4IFG is set 0x1 FIFO1B2IFG Sets FIFO1B2IFG in RIS register 0xA 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFO1B2IFG is set 0x1 FIFO3B4IFG Sets FIFO3B4IFG in RIS register 0xB 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFO3B4IFG is set 0x1 FIFOFULLIFG Sets FIFOFULLIFG in RIS register 0x8 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFOFULLIFG is set 0x1 FIFOURUNIFG Sets FIFOURUNIFG in RIS register 0xD 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to FIFOURUNIFG is set 0x1 DMADONEIFG Sets DMADONEIFG in RIS register 0xE 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to DMADONEIFG is set 0x1 DAC0_GEN_EVENT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 MODRDYIFG Clears MODRDYIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to MODRDYIFG is cleared 0x1 FIFOEMPTYIFG Clears FIFOEMPTYIFG in RIS register 0xC 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFOEMPTYIFG is cleared 0x1 FIFO1B4IFG Clears FIFO1B4IFG in RIS register 0x9 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFO1B4IFG is cleared 0x1 FIFO1B2IFG Clears FIFO1B2IFG in RIS register 0xA 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFO1B2IFG is cleared 0x1 FIFO3B4IFG Clears FIFO3B4IFG in RIS register 0xB 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFO3B4IFG is cleared 0x1 FIFOFULLIFG Clears FIFOFULLIFG in RIS register 0x8 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFOFULLIFG is cleared 0x1 FIFOURUNIFG Clears FIFOURUNIFG in RIS register 0xD 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to FIFOURUNIFG is cleared 0x1 DMADONEIFG Clears DMADONEIFG in RIS register 0xE 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to DMADONEIFG is cleared 0x1 DAC0_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000009 INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 DAC0_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 read-only MAJREV Major rev of the IP 0x4 0x4 read-only FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only DAC0_CTL0 Control 0 0x1100 32 read-write 0x00000000 DFM This bit defines the DAC input data format. 0x10 0x1 read-write BINARY Straight binary 0x0 TWOS_COMP Twos complement 0x1 ENABLE This bit enables the DAC module. 0x0 0x1 read-write CLR DAC is disabled 0x0 SET DAC is enabled 0x1 RES These bits define the DAC output voltage resolution. 0x8 0x1 read-write _8BITS 8-bits resolution 0x0 _12BITS 12-bit resolution 0x1 DAC0_CTL1 Control 1 0x1110 32 read-write 0x00000000 AMPEN AMP_EN - output amplifier enabled or disabled 0 : disabled 1 : enabled 0x0 0x1 read-write DISABLE disable 0x0 ENABLE enable 0x1 REFSP This bit selects the DAC voltage reference source + input. 0x8 0x1 read-write VDDA Analog supply (VDDA) as VR+ 0x0 VEREFP VEREFP pin as VR+ 0x1 OPS These bits select the DAC output on device pin. 0x18 0x1 read-write NOC0 No connect. Both DAC output switches are open. 0x0 OUT0 OUT0 output is selected 0x1 REFSN This bit selects the DAC voltage reference source + input. 0x9 0x1 read-write VEREFN VEREFN pin as VR- 0x0 VSSA Analog supply (VSSA) as VR- 0x1 AMPHIZ AMPHIZ - amplifier output value 0 : amplifier output is high impedance 1 : amplifier output is pulled down to ground 0x1 0x1 read-write HIZ HiZ when disable 0x0 PULLDOWN dacout pulldown when disable 0x1 DAC0_CTL2 Control 2 0x1120 32 read-write 0x00000000 FIFOEN This bit enables the FIFO and the FIFO hardware control state machine. 0x0 0x1 read-write CLR FIFO is disabled 0x0 SET FIFO is enabled 0x1 FIFOTH These bits determine the FIFO threshold. In case of DMA based operation, DAC generates new DMA trigger when the number of empty locations in FIFO match the selected FIFO threshold level. In case of CPU based operation, the FIFO threshold bits are don't care and FIFO level is directly indicated through the respective bits in the RIS register. 0x8 0x2 read-write LOW One fourth of the FIFO locations are empty 0x0 MED Half of the FIFO locations are empty 0x1 HIGH Three fourth of the FIFO locations are empty 0x2 SPARE Reserved value. Defaults to same effect as FIFOTH = 0 (One fourth of the FIFO locations are empty). 0x3 FIFOTRIGSEL These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted, the data from FIFO (as indicated by read pointer) is moved into internal DAC data register. 0x10 0x2 read-write STIM Sample time generator output 0x0 TRIG0 Hardware trigger-0 from event fabric 0x1 SPARE1 Reserved - unimplemented 0x2 SPARE2 Reserved - unimplemented 0x3 DMATRIGEN This bit enables the DMA trigger generation mechanism. When this bit is set along with FIFOEN, the DMA trigger is generated based on the empty FIFO locations qualified by FIFOTH settings. This bit should be cleared by software to stop further DMA triggers. 0x18 0x1 read-write CLR DMA trigger generation mechanism is disabled 0x0 SET DMA trigger generation mechanism is enabled 0x1 DAC0_CTL3 Control 3 0x1130 32 read-write 0x00000000 STIMEN This bit enables the sample time generator. 0x0 0x1 read-write CLR Sample time generator is disabled 0x0 SET Sample time generator is enabled 0x1 STIMCONFIG These bits are used to configure the trigger rate from the sample time generator. The STIMCONFIG values 10 to 15 are reserved and default to same effect as value 0 (500SPS). 0x8 0x4 read-write _500SPS Trigger rate is 500 sps (clock divide value is 4000) 0x0 _1KSPS Trigger rate is 1 ksps (clock divide value is 2000) 0x1 _2KSPS Trigger rate is 2 ksps (clock divide value is 1000) 0x2 _4KSPS Trigger rate is 4 ksps (clock divide value is 500) 0x3 _8KSPS Trigger rate is 8 ksps (clock divide value is 250) 0x4 _16KSPS Trigger rate is 16 ksps (clock divide value is 125) 0x5 _100KSPS Trigger rate is 100 ksps (clock divide value is 20) 0x6 _200KSPS Trigger rate is 200 ksps (clock divide value is 10) 0x7 _500KSPS Trigger rate is 500 ksps (clock divide value is 4) 0x8 _1MSPS Trigger rate is 1 Msps (clock divide value is 2) 0x9 DAC0_CALCTL Calibration control 0x1140 32 read-write 0x00000000 CALON This bit when set initiates the DAC offset error calibration sequence and is automatically reset when the offset error calibration completes. 0x0 0x1 read-write INACTIVE Offset error calibration is not active 0x0 ACTIVE Initiate offset error calibration or offset error calibration is already in progress 0x1 CALSEL This bit is used to select between factory trim or self calibration trim. 0x1 0x1 read-write FACTORYTRIM Factory Trim Calibration Values are used when calibration is enabled 0x0 SELFCALIBRATIONTRIM Self Calibration Trim Values are used when calibration is enabled 0x1 DAC0_CALDATA Calibration data 0x1160 32 read-only 0x00000000 DATA DAC offset error calibration data. The DAC offset error calibration data is represented in twos complement format providing a range of 64 to +63. This is read-only bit, reflecting the calibration data. Writing to this register will have no effect, it will not change the calibration value. 0x0 0x7 read-only DAC0_DATA0 Data 0 0x1200 32 read-write 0x00000000 DATA_VALUE This is the data written for digital to analog conversion. 0x0 0xC read-write VREF VREF 1.0 PERIPHERALREGION 0x40030000 0x0 0x1F00 registers 1 24 0 VREF_GPRCM[%s] 0x800 VREF_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 VREF_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 VREF_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 VREF_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock to be used in sample and hold logic 0x0 0x3 read-write VREF_CLKSEL Clock Selection 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write VREF_CTL0 Control 0 0x1100 32 read-write 0x00000000 ENABLE This bit enables the VREF module. 0x0 0x1 read-write DISABLE VREF is disabled 0x0 ENABLE VREF is enabled 0x1 BUFCONFIG These bits configure output buffer. 0x7 0x1 read-write OUTPUT2P5V Configure Output Buffer to 2.5v 0x0 OUTPUT1P4V Configure Output Buffer to 1.4v 0x1 SHMODE This bit enable sample and hold mode 0x8 0x1 read-write DISABLE Sample and hold mode is disable 0x0 Enable Sample and hold mode is enable 0x1 VREF_CTL1 Control 1 0x1104 32 read-write 0x00000000 READY These bits defines status of VREF 0x0 0x1 read-only NOTRDY VREF output is not ready 0x0 RDY VREF output is ready 0x1 VREF_CTL2 Control 2 0x1108 32 read-write 0x00000000 SHCYCLE Sample and Hold cycle count Total cycles of module clock for sample and hold phase when VREF is working in sample and hold mode in STANDBY to save power. This field should be greater than HCYCLE field. The difference between this field and HCYCLE gives the number of cycles of sample phase. Please refer VREF section of datasheet for recommended values of sample and hold times. 0x0 0x10 read-write HCYCLE Hold cycle count Total cycles of module clock for hold phase when VREF is working in sample and hold mode in STANDBY to save power. Please refer VREF section of datasheet for recommended values of sample and hold times. 0x10 0x10 read-write EVENTLP EVENTLP 1.0 PERIPHERALREGION 0x400C9000 0x0 0x3000 registers EVENTLP_PUBCFG_DESC_EX Extended Module Description 0xF8 32 read-only NUM_SINGLE_CHANNEL Number of single channels contained in this instance of event manager 0x0 0x8 read-only NUM_DUAL_CHANNEL Number of dual channels contained in this instance of event manager 0x8 0x8 read-only NUM_IMPORT Number of import ports available in this EventManager instantiation 0x10 0x8 read-only NUM_EXPORT Number of export ports available in this EventManager instantiation 0x18 0x8 read-only EVENTLP_PUBCFG_DESC Module Description 0xFC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 0 0 EVENTLP_PUBCFG_FSUB[%s] 0x100 EVENTLP_PUBCFG_FSUB_PORT Subscriber channel ID register 0x0 32 read-write 0x00000000 CHANID Channel ID for subscriber to connect to 0x0 0x8 read-write 1 0 0 EVENTLP_PUBCFG_FPUB[%s] 0x300 EVENTLP_PUBCFG_FPUB_PORT Publisher channel ID register 0x0 32 read-write CHANID Channel ID for publisher to connect to 0x0 0x8 read-write 1 4 0 EVENTLP_PUBCFG_EXPORT[%s] 0x500 EVENTLP_PUBCFG_EXPORT_PORT Export channel ID register 0x0 32 read-write CHANID Channel ID for export side to connect to 0x0 0x8 read-write 1 4 0 EVENTLP_PUBCFG_IMPORT[%s] 0x700 EVENTLP_PUBCFG_IMPORT_PORT Import channel ID registe 0x0 32 read-write CHANID Channel ID for import side to connect to 0x0 0x8 read-write 1 0 0 EVENTLP_PUBCFG_CPU_CONNECT[%s] 0x900 EVENTLP_PUBCFG_CPU_NUM CPU connect register 0x0 32 read-write EVENTLP_SECCFG_DESC_EX Extended Module Description 0x10F8 32 read-only NUM_SINGLE_CHANNEL Number of single channels contained in this instance of event manager 0x0 0x8 read-only NUM_DUAL_CHANNEL Number of dual channels contained in this instance of event manager 0x8 0x8 read-only NUM_EXPORT Number of export ports available in this EventManager instantiation 0x18 0x8 read-only NUM_IMPORT Number of import ports available in this EventManager instantiation 0x10 0x8 read-only EVENTLP_SECCFG_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 0 0 EVENTLP_SECCFG_FSUB[%s] 0x1100 EVENTLP_SECCFG_FSUB_PORT Subscriber channel ID register 0x0 8 read-write 0x00000000 CHANID Channel ID for subscriber to connect to 0x0 0x8 read-write 1 0 0 EVENTLP_SECCFG_FPUB[%s] 0x1180 EVENTLP_SECCFG_FPUB_PORT Publisher channel ID register 0x0 8 read-write CHANID Channel ID for publisher to connect to 0x0 0x8 read-write 1 1 0 EVENTLP_SECCFG_EXPORT[%s] 0x1200 EVENTLP_SECCFG_EXPORT_PORT Export channel ID register 0x0 8 read-write CHANID Channel ID for export side to connect to 0x0 0x8 read-write 1 1 0 EVENTLP_SECCFG_IMPORT[%s] 0x1280 EVENTLP_SECCFG_IMPORT_PORT Import channel ID registe 0x0 8 read-write CHANID Channel ID for import side to connect to 0x0 0x8 read-write 1 0 0 EVENTLP_SECCFG_CPU_CONNECT[%s] 0x1300 EVENTLP_SECCFG_CPU_NUM CPU connect register 0x0 8 read-write EVENTLP_CTL Event Manager control register 0x1400 8 read-write OVRWR_EN Enable overwrite of config even if resources are already configured. By default, a configuration cannot be overwritten. 0x0 0x4 read-write DISABLE Overwrite is disabled. Mode is same as in UNASG aperture. 0x5 ENABLED Ovewrite is enabled 0xA 1 1024 0 EVENTLP_LMGMT_SFTYDIAG[%s] 0x1C00 EVENTLP_DIAGPAR192 Diagnostic Parity Register 768 0xEC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR191 Diagnostic Parity Register 191 0xF0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR190 Diagnostic Parity Register 190 0xF4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR189 Diagnostic Parity Register 189 0xF8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR188 Diagnostic Parity Register 188 0xFC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR187 Diagnostic Parity Register 187 0x100 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR186 Diagnostic Parity Register 186 0x104 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR185 Diagnostic Parity Register 185 0x108 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR184 Diagnostic Parity Register 184 0x10C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR183 Diagnostic Parity Register 183 0x110 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR182 Diagnostic Parity Register 182 0x114 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR181 Diagnostic Parity Register 181 0x118 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR180 Diagnostic Parity Register 180 0x11C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR179 Diagnostic Parity Register 179 0x120 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR178 Diagnostic Parity Register 178 0x124 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR177 Diagnostic Parity Register 177 0x128 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR176 Diagnostic Parity Register 176 0x12C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR175 Diagnostic Parity Register 175 0x130 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR174 Diagnostic Parity Register 174 0x134 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR173 Diagnostic Parity Register 173 0x138 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR172 Diagnostic Parity Register 172 0x13C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR171 Diagnostic Parity Register 171 0x140 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR170 Diagnostic Parity Register 170 0x144 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR169 Diagnostic Parity Register 169 0x148 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR168 Diagnostic Parity Register 168 0x14C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR167 Diagnostic Parity Register 167 0x150 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR166 Diagnostic Parity Register 166 0x154 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR165 Diagnostic Parity Register 165 0x158 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR164 Diagnostic Parity Register 164 0x15C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR163 Diagnostic Parity Register 163 0x160 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR162 Diagnostic Parity Register 162 0x164 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR161 Diagnostic Parity Register 161 0x168 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR160 Diagnostic Parity Register 160 0x16C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR159 Diagnostic Parity Register 159 0x170 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR158 Diagnostic Parity Register 158 0x174 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR157 Diagnostic Parity Register 157 0x178 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR156 Diagnostic Parity Register 156 0x17C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR155 Diagnostic Parity Register 155 0x180 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR154 Diagnostic Parity Register 154 0x184 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR153 Diagnostic Parity Register 153 0x188 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR152 Diagnostic Parity Register 152 0x18C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR151 Diagnostic Parity Register 151 0x190 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR150 Diagnostic Parity Register 150 0x194 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR149 Diagnostic Parity Register 149 0x198 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR148 Diagnostic Parity Register 148 0x19C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR147 Diagnostic Parity Register 147 0x1A0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR146 Diagnostic Parity Register 146 0x1A4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR145 Diagnostic Parity Register 145 0x1A8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR144 Diagnostic Parity Register 144 0x1AC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR143 Diagnostic Parity Register 143 0x1B0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR142 Diagnostic Parity Register 142 0x1B4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR141 Diagnostic Parity Register 141 0x1B8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR140 Diagnostic Parity Register 140 0x1BC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR139 Diagnostic Parity Register 139 0x1C0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR138 Diagnostic Parity Register 138 0x1C4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR137 Diagnostic Parity Register 137 0x1C8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR136 Diagnostic Parity Register 136 0x1CC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR135 Diagnostic Parity Register 135 0x1D0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR134 Diagnostic Parity Register 134 0x1D4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR133 Diagnostic Parity Register 133 0x1D8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR132 Diagnostic Parity Register 132 0x1DC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR131 Diagnostic Parity Register 131 0x1E0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR130 Diagnostic Parity Register 130 0x1E4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR129 Diagnostic Parity Register 129 0x1E8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR128 Diagnostic Parity Register 128 0x1EC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR127 Diagnostic Parity Register 127 0x1F0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR126 Diagnostic Parity Register 126 0x1F4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR125 Diagnostic Parity Register 125 0x1F8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR124 Diagnostic Parity Register 124 0x1FC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR123 Diagnostic Parity Register 123 0x200 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR122 Diagnostic Parity Register 122 0x204 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR121 Diagnostic Parity Register 121 0x208 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR120 Diagnostic Parity Register 120 0x20C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR119 Diagnostic Parity Register 119 0x210 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR118 Diagnostic Parity Register 118 0x214 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR117 Diagnostic Parity Register 117 0x218 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR116 Diagnostic Parity Register 116 0x21C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR115 Diagnostic Parity Register 115 0x220 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR114 Diagnostic Parity Register 114 0x224 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR113 Diagnostic Parity Register 113 0x228 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR112 Diagnostic Parity Register 112 0x22C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR111 Diagnostic Parity Register 111 0x230 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR110 Diagnostic Parity Register 110 0x234 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR109 Diagnostic Parity Register 109 0x238 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR108 Diagnostic Parity Register 108 0x23C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR107 Diagnostic Parity Register 107 0x240 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR106 Diagnostic Parity Register 106 0x244 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR105 Diagnostic Parity Register 105 0x248 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR104 Diagnostic Parity Register 104 0x24C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR103 Diagnostic Parity Register 103 0x250 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR102 Diagnostic Parity Register 102 0x254 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR101 Diagnostic Parity Register 101 0x258 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR100 Diagnostic Parity Register 100 0x25C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR99 Diagnostic Parity Register 99 0x260 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR98 Diagnostic Parity Register 98 0x264 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR97 Diagnostic Parity Register 97 0x268 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR96 Diagnostic Parity Register 96 0x26C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR95 Diagnostic Parity Register 95 0x270 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR94 Diagnostic Parity Register 94 0x274 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR93 Diagnostic Parity Register 93 0x278 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR92 Diagnostic Parity Register 92 0x27C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR91 Diagnostic Parity Register 91 0x280 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR90 Diagnostic Parity Register 90 0x284 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR89 Diagnostic Parity Register 89 0x288 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR88 Diagnostic Parity Register 88 0x28C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR87 Diagnostic Parity Register 87 0x290 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR86 Diagnostic Parity Register 86 0x294 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR85 Diagnostic Parity Register 85 0x298 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR84 Diagnostic Parity Register 84 0x29C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR83 Diagnostic Parity Register 83 0x2A0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR82 Diagnostic Parity Register 82 0x2A4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR81 Diagnostic Parity Register 81 0x2A8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR80 Diagnostic Parity Register 80 0x2AC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR79 Diagnostic Parity Register 79 0x2B0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR78 Diagnostic Parity Register 78 0x2B4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR77 Diagnostic Parity Register 77 0x2B8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR76 Diagnostic Parity Register 76 0x2BC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR75 Diagnostic Parity Register 75 0x2C0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR74 Diagnostic Parity Register 74 0x2C4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR73 Diagnostic Parity Register 73 0x2C8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR72 Diagnostic Parity Register 72 0x2CC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR71 Diagnostic Parity Register 71 0x2D0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR70 Diagnostic Parity Register 70 0x2D4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR69 Diagnostic Parity Register 69 0x2D8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR68 Diagnostic Parity Register 68 0x2DC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR67 Diagnostic Parity Register 67 0x2E0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR66 Diagnostic Parity Register 66 0x2E4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR65 Diagnostic Parity Register 65 0x2E8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR64 Diagnostic Parity Register 64 0x2EC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR63 Diagnostic Parity Register 63 0x2F0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR62 Diagnostic Parity Register 62 0x2F4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR61 Diagnostic Parity Register 61 0x2F8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR60 Diagnostic Parity Register 60 0x2FC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR59 Diagnostic Parity Register 59 0x300 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR58 Diagnostic Parity Register 58 0x304 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR57 Diagnostic Parity Register 57 0x308 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR56 Diagnostic Parity Register 56 0x30C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR55 Diagnostic Parity Register 55 0x310 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR54 Diagnostic Parity Register 54 0x314 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR53 Diagnostic Parity Register 53 0x318 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR52 Diagnostic Parity Register 52 0x31C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR51 Diagnostic Parity Register 51 0x320 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR50 Diagnostic Parity Register 50 0x324 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR49 Diagnostic Parity Register 49 0x328 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR48 Diagnostic Parity Register 48 0x32C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR47 Diagnostic Parity Register 47 0x330 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR46 Diagnostic Parity Register 46 0x334 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR45 Diagnostic Parity Register 45 0x338 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR44 Diagnostic Parity Register 44 0x33C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR43 Diagnostic Parity Register 43 0x340 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR42 Diagnostic Parity Register 42 0x344 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR41 Diagnostic Parity Register 41 0x348 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR40 Diagnostic Parity Register 40 0x34C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR39 Diagnostic Parity Register 39 0x350 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR38 Diagnostic Parity Register 38 0x354 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR37 Diagnostic Parity Register 37 0x358 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR36 Diagnostic Parity Register 36 0x35C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR35 Diagnostic Parity Register 35 0x360 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR34 Diagnostic Parity Register 34 0x364 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR33 Diagnostic Parity Register 33 0x368 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR32 Diagnostic Parity Register 32 0x36C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR31 Diagnostic Parity Register 31 0x370 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR30 Diagnostic Parity Register 30 0x374 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR29 Diagnostic Parity Register 29 0x378 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR28 Diagnostic Parity Register 28 0x37C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR27 Diagnostic Parity Register 27 0x380 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR26 Diagnostic Parity Register 26 0x384 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR25 Diagnostic Parity Register 25 0x388 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR24 Diagnostic Parity Register 24 0x38C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR23 Diagnostic Parity Register 23 0x390 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR22 Diagnostic Parity Register 22 0x394 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR21 Diagnostic Parity Register 21 0x398 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR20 Diagnostic Parity Register 20 0x39C 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR19 Diagnostic Parity Register 19 0x3A0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR18 Diagnostic Parity Register 18 0x3A4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR17 Diagnostic Parity Register 17 0x3A8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR16 Diagnostic Parity Register 16 0x3AC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR15 Diagnostic Parity Register 15 0x3B0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR14 Diagnostic Parity Register 14 0x3B4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR13 Diagnostic Parity Register 13 0x3B8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR12 Diagnostic Parity Register 12 0x3BC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR11 Diagnostic Parity Register 11 0x3C0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR10 Diagnostic Parity Register 10 0x3C4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR9 Diagnostic Parity Register 9 0x3C8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR8 Diagnostic Parity Register 8 0x3CC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR7 Diagnostic Parity Register 7 0x3D0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR6 Diagnostic Parity Register 6 0x3D4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR5 Diagnostic Parity Register 5 0x3D8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR4 Diagnostic Parity Register 4 0x3DC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR3 Diagnostic Parity Register 3 0x3E0 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR2 Diagnostic Parity Register 2 0x3E4 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR1 Diagnostic Parity Register 1 0x3E8 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGPAR0 Diagnostic Parity Register 0 0x3EC 32 write-only 0x00000000 0xffffffff ASSERTDIAG Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check. 0x0 0x1 NO_EFFECT No Effect 0x0 START Generate diagnostic check 0x1 EVENTLP_DIAGIFRST Diagnostic Interface Reset Register 0x3F4 32 read-write 0x00000000 0xffffffff ASSERTIFRST Writing a 1 will synchronously clear the Diagnostic Interface. The STICKY bits for status and well as the PARFV will be cleared. If a true functional failure still exists, the interface will re-assert FUNCFAIL on the cycle following the interface reset 0x0 0x1 write-only NO_EFFECT No Effect 0x0 CLR Clear 0x1 DIAGPASSCLR Writing a 1 will synchronously clear the PARFV MMR DPINDEX field. The STICKY bit for DIAGPASS status will be cleared as well. 0x1 0x1 write-only NO_EFFECT No Effect 0x0 CLR Clear 0x1 EVENTLP_DIAGPARFV Diagnostic Parity Fail Vector Register 0x3F8 32 read-only 0x00000000 0xffffffff INDEX Index of DIAG MMR creating the failure. NOTE: INDEX value of 1 corresponds to DIAGPAR0, 2 corresponds to DIAGPAR1 and so on. 0x0 0xA DPINDEX Index of DIAG PASS MMR. NOTE: DPINDEX value of 1 corresponds to DIAGPAR0, 2 corresponds to DIAGPAR1 and so on. 0x10 0xA EVENTLP_DIAGSTAT Diagnostic Status Register 0x3FC 32 read-only 0x03010000 0xffffffff STATE Current diagnostic state 0x0 0x3 NONE No failures and no diagnostic 0x0 FUNC_FAIL Functional Failure 0x1 DIAG_FAIL Diagnostic Failure 0x2 DIAG_PASS Diagnostic Pass 0x4 NUMDIAG This is a hardware constant that indicates how many DIAGPAR registers are included in this SFTYDIAG sub-region. 0x10 0xA 1 4 0 EVENTLP_IMPEXPCFG_EXPORT[%s] 0x2000 EVENTLP_IMPEXPCFG_EXPORT_PORT Export channel ID register 0x0 32 read-write CHANID Channel ID for import side to connect to 0x0 0x8 read-write 1 4 0 EVENTLP_IMPEXPCFG_IMPORT[%s] 0x2200 EVENTLP_IMPEXPCFG_IMPORT_PORT Import channel ID registe 0x0 32 read-write CHANID Channel ID for import side to connect to 0x0 0x8 read-write TIMG7 TIMG 1.0 PERIPHERALREGION 0x4086A000 0x0 0x1F00 registers TIMG7_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG7_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG7_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG7_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMG7_GPRCM[%s] 0x800 TIMG7_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMG7_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMG7_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMG7_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMG7_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMG7_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMG7_INT_EVENT[%s] 0x1020 TIMG7_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMG7_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TIMG7_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG7_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD4 Compare down event generated an interrupt CCP4 0xC 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD5 Compare down event generated an interrupt CCP5 0xD 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU4 Compare up event generated an interrupt CCP4 0xE 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU5 Compare up event generated an interrupt CCP5 0xF 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG7_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMG7_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMG7_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMG7_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 40 0 TIMG7_COMMONREGS[%s] 0x1100 TIMG7_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMG7_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 TIMG7_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMG7_CPS Clock Prescale Register 0xC 32 read-write PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write TIMG7_CPSV Clock prescale count status register 0x10 32 read-only CPSVAL Current Prescale Count Value 0x0 0x8 read-only TIMG7_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMG7_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 TIMG7_GCTL Shadow to active load mask 0x24 32 read-write SHDWLDEN Enables shadow to active load of bufferred registers and register fields. 0x0 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 1 180 0 TIMG7_COUNTERREGS[%s] 0x1800 TIMG7_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x10 read-write TIMG7_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMG7_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x10 read-write 2 4 0,1 TIMG7_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMG7_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCUPD Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0). 0x12 0x3 read-write Immediately Writes to the CCx_y register is written to the register directly and has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCx_y register are stored in shadow register and transferred to ECCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LD. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. 0x6 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMG7_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMG7_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 2 4 0,1 TIMG7_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMG7_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 TIMG6 TIMG 1.0 PERIPHERALREGION 0x40868000 0x0 0x1F00 registers TIMG6_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG6_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG6_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG6_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMG6_GPRCM[%s] 0x800 TIMG6_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMG6_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMG6_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMG6_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMG6_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMG6_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMG6_INT_EVENT[%s] 0x1020 TIMG6_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMG6_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TIMG6_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG6_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD4 Compare down event generated an interrupt CCP4 0xC 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD5 Compare down event generated an interrupt CCP5 0xD 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU4 Compare up event generated an interrupt CCP4 0xE 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU5 Compare up event generated an interrupt CCP5 0xF 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG6_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMG6_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMG6_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMG6_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 40 0 TIMG6_COMMONREGS[%s] 0x1100 TIMG6_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMG6_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 TIMG6_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMG6_CPS Clock Prescale Register 0xC 32 read-write PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write TIMG6_CPSV Clock prescale count status register 0x10 32 read-only CPSVAL Current Prescale Count Value 0x0 0x8 read-only TIMG6_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMG6_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 TIMG6_GCTL Shadow to active load mask 0x24 32 read-write SHDWLDEN Enables shadow to active load of bufferred registers and register fields. 0x0 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 1 180 0 TIMG6_COUNTERREGS[%s] 0x1800 TIMG6_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x10 read-write TIMG6_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMG6_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x10 read-write 2 4 0,1 TIMG6_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMG6_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCUPD Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0). 0x12 0x3 read-write Immediately Writes to the CCx_y register is written to the register directly and has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCx_y register are stored in shadow register and transferred to ECCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LD. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. 0x6 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMG6_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMG6_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 2 4 0,1 TIMG6_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMG6_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 SPI1 SPI 1.0 PERIPHERALREGION 0x4046A000 0x0 0x1F00 registers 1 24 0 SPI1_GPRCM[%s] 0x800 SPI1_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 SPI1_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 SPI1_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write DISABLE Not block async clock request 0x0 ENABLE Block async clock request 0x1 SPI1_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 SPI1_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 SPI1_CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 SYSCLK_SEL Selects SYSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 SPI1_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 SPI1_CPU_INT[%s] 0x1020 SPI1_CPU_INT_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RXFIFO_OFV_EVT RX FIFO Overflow Event/interrupt pending 0x1 PER_EVT Transmit Parity Event/interrupt pending 0x2 RTOUT_EVT SPI receive time-out interrupt 0x3 RX_EVT Receive Event/interrupt pending 0x4 TX_EVT Transmit Event/interrupt pending 0x5 TX_EMPTY Transmit Buffer Empty Event/interrupt pending 0x6 IDLE_EVT End of Transmit Event/interrupt pending 0x7 DMA_DONE_RX_EVT DMA Done for Receive Event/interrupt pending 0x8 DMA_DONE_TX_EVT DMA Done for Transmit Event/interrupt pending 0x9 TXFIFO_UNF_EVT TX FIFO underflow interrupt 0xA RXFULL_EVT RX FIFO Full Interrupt 0xB SPI1_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TX Transmit FIFO event mask. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXEMPTY Transmit FIFO Empty event mask. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PER Parity error event mask. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX DMA Done 1 event for RX event mask. 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFIFO_OVF RXFIFO overflow event mask. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX DMA Done 1 event for TX event mask. 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 IDLE SPI Idle event mask. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFULL RX FIFO Full Interrupt Mask 0xA 0x1 read-write CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXFIFO_UNF TX FIFO underflow interrupt mask 0x9 0x1 read-write CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI1_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TX Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 PER Parity error event: this bit is set if a Parity error has been detected 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_RX DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFIFO_OVF RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_TX DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 IDLE SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out event. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXFIFO_UNF TX FIFO Underflow Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFULL RX FIFO Full Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI1_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RX Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TX Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXEMPTY Masked Transmit FIFO Empty event. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 PER Masked Parity error event: this bit if a Parity error has been detected 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_RX Masked DMA Done 1 event for RX. 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFIFO_OVF Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_TX Masked DMA Done 1 event for TX. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 IDLE Masked SPI IDLE mode event. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT Masked SPI Receive Time-Out Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFULL RX FIFO Full Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXFIFO_UNF TX FIFO underflow interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI1_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 RX Set Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TX Set Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXEMPTY Set Transmit FIFO Empty event. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PER Set Parity error event. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done 1 event for RX. 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXFIFO_OVF Set RXFIFO overflow event. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done 1 event for TX. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 IDLE Set SPI IDLE mode event. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RTOUT Set SPI Receive Time-Out Event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt Mask 0x1 TXFIFO_UNF Set TX FIFO Underflow Event 0x9 0x1 NO_EFFECT Writing has no effect 0x0 SET Set interrupt 0x1 RXFULL Set RX FIFO Full Event 0xA 0x1 NO_EFFECT Writing has no effect 0x0 SET Set Interrupt 0x1 SPI1_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RX Clear Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TX Clear Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXEMPTY Clear Transmit FIFO Empty event. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PER Clear Parity error event. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done 1 event for RX. 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXFIFO_OVF Clear RXFIFO overflow event. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done 1 event for TX. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 IDLE Clear SPI IDLE mode event. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RTOUT Clear SPI Receive Time-Out Event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Set Interrupt Mask 0x1 TXFIFO_UNF Clear TXFIFO underflow event 0x9 0x1 NO_EFFECT Writing has no effect 0x0 CLR Clear interrupt 0x1 RXFULL Clear RX FIFO underflow event 0xA 0x1 NO_EFFECT Writing has no effect 0x0 CLR Clear interrupt 0x1 1 44 0 SPI1_DMA_TRIG_RX[%s] 0x1050 SPI1_DMA_TRIG_RX_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTOUT_EVT SPI receive time-out interrupt 0x3 RX_EVT Receive Event/interrupt pending 0x4 SPI1_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RX Receive FIFO event mask. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RTOUT SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI1_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out Event. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI1_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RX Receive FIFO event mask. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI1_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RX Set Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RTOUT Set SPI Receive Time-Out event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt Mask 0x1 SPI1_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RX Clear Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RTOUT Clear SPI Receive Time-Out event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Set Interrupt Mask 0x1 1 44 0 SPI1_DMA_TRIG_TX[%s] 0x1080 SPI1_DMA_TRIG_TX_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TX_EVT Transmit Event/interrupt pending 0x5 SPI1_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TX Transmit FIFO event mask. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI1_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TX Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI1_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TX Masked Transmit FIFO event 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI1_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TX Set Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 SPI1_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TX Clear Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 SPI1_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 SPI1_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 SPI1_CTL0 SPI control register 0 0x1100 32 read-write 0x00000000 DSS Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit 0x0 0x5 read-write DSS_4 Data Size Select bits: 4 0x3 DSS_5 Data Size Select bits: 5 0x4 DSS_6 Data Size Select bits: 6 0x5 DSS_7 Data Size Select bits: 7 0x6 DSS_8 Data Size Select bits: 8 0x7 DSS_9 Data Size Select bits: 9 0x8 DSS_10 Data Size Select bits: 10 0x9 DSS_11 Data Size Select bits: 11 0xA DSS_12 Data Size Select bits: 12 0xB DSS_13 Data Size Select bits: 13 0xC DSS_14 Data Size Select bits: 14 0xD DSS_15 Data Size Select bits: 15 0xE DSS_16 Data Size Select bits: 16 0xF FRF Frame format Select 0x5 0x2 read-write MOTOROLA_3WIRE Motorola SPI frame format (3 wire mode) 0x0 MOTOROLA_4WIRE Motorola SPI frame format (4 wire mode) 0x1 TI_SYNC TI synchronous serial frame format 0x2 MIRCOWIRE National Microwire frame format 0x3 SPO CLKOUT polarity (Motorola SPI frame format only) 0x8 0x1 read-write LOW SPI produces a steady state LOW value on the CLKOUT 0x0 HIGH SPI produces a steady state HIGH value on the CLKOUT 0x1 SPH CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 0x9 0x1 read-write FIRST Data is captured on the first clock edge transition. 0x0 SECOND Data is captured on the second clock edge transition. 0x1 CSSEL Select the CS line to control on data transfer This bit is applicable for both controller/target mode 0xC 0x2 read-write CSSEL_0 CS line select: 0 0x0 CSSEL_1 CS line select: 1 0x1 CSSEL_2 CS line select: 2 0x2 CSSEL_3 CS line select: 3 0x3 CSCLR Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.CP=0. 0xE 0x1 read-write DISABLE Disable automatic clear of shift register when CS goes to disable. 0x0 ENABLE Enable automatic clear of shift register when CS goes to disable. 0x1 PACKEN Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP 0x7 0x1 read-write DISABLED Packing feature disabled 0x0 ENABLED Packing feature enabled 0x1 SPI1_CTL1 SPI control register 1 0x1104 32 read-write 0x00000004 LBM Loop back mode 0x1 0x1 read-write DISABLE Disable loopback mode 0x0 ENABLE Enable loopback mode 0x1 CP Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0. 0x2 0x1 read-write DISABLE Select Peripheral mode 0x0 ENABLE Select Controller Mode 0x1 POD Peripheral-mode: Data output disabled This bit is relevant only in Peripheral mode. In multiple-peripheral system topologies, SPI controller can broadcast a message to all peripherals, while only one peripheral drives the line. POD can be used by the SPI peripheral to disable driving data on the line. 0x3 0x1 read-write DISABLE SPI can drive the MISO output in peripheral mode. 0x0 ENABLE SPI cannot drive the MISO output in peripheral mode. 0x1 MSB MSB first select. Controls the direction of the receive and transmit shift register. 0x4 0x1 read-write DISABLE LSB first 0x0 ENABLE MSB first 0x1 PREN Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set. 0x5 0x1 read-write DISABLE Disable Parity receive function 0x0 ENABLE Enable Parity receive function 0x1 REPEATTX Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral. 0x10 0x8 read-write DISABLE REPEATTX disable 0x0 PES Even Parity Select 0x6 0x1 read-write DISABLE Odd Parity mode 0x0 ENABLE Even Parity mode 0x1 CDMODE Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low. 0xC 0x4 read-write DATA Manual mode: Data 0x0 COMMAND Manual mode: Command 0xF ENABLE SPI enable 0x0 0x1 read-write DISABLE Disable module function 0x0 ENABLE Enable module function 0x1 RXTIMEOUT Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function. 0x18 0x6 read-write CDENABLE Command/Data Mode enable 0xB 0x1 read-write DISABLE CS3 is used for Chip Select 0x0 ENABLE CS3 is used as CD signal 0x1 PTEN Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes. 0x8 0x1 read-write DISABLE Parity transmission is disabled 0x0 ENABLE Parity transmission is enabled 0x1 SPI1_CLKCTL Clock prescaler and divider register. 0x1108 32 read-write 0x00000000 SCR Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023. 0x0 0xA read-write DSAMPLE Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations. 0x1C 0x4 read-write SPI1_IFLS Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000012 0xffffffff TXIFLSEL SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 0x0 0x3 read-write LVL_OFF Reserved 0x0 LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_RES4 Reserved 0x4 LVL_EMPTY TX FIFO is empty 0x5 LVL_RES6 Reserved 0x6 LEVEL_1 Trigger when TX FIFO has >= 1 frame free Should be used with DMA 0x7 RXIFLSEL SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: 0x3 0x3 read-write LVL_OFF Reserved 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_RES4 Reserved 0x4 LVL_FULL RX FIFO is full 0x5 LVL_RES6 Reserved 0x6 LEVEL_1 Trigger when RX FIFO contains >= 1 frame 0x7 SPI1_STAT Status Register 0x1110 32 read-only TFE Transmit FIFO empty. 0x0 0x1 NOT_EMPTY Transmit FIFO is not empty. 0x0 EMPTY Transmit FIFO is empty. 0x1 TNF Transmit FIFO not full 0x1 0x1 FULL Transmit FIFO is full. 0x0 NOT_FULL Transmit FIFO is not full. 0x1 RFE Receive FIFO empty. 0x2 0x1 NOT_EMPTY Receive FIFO is not empty. 0x0 EMPTY Receive FIFO is empty. 0x1 RNF Receive FIFO not full 0x3 0x1 FULL Receive FIFO is full. 0x0 NOT_FULL Receive FIFO is not full. 0x1 BUSY Busy 0x4 0x1 IDLE SPI is in idle mode. 0x0 ACTIVE SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty. 0x1 SPI1_RXDATA RXDATA Register 0x1130 32 read-only 0x00000000 DATA Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer. 0x0 0x10 read-only SPI1_TXDATA TXDATA Register 0x1140 32 read-write 0x00000000 DATA Transmit Data When read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. 0x0 0x10 read-write DMA DMA 1.0 PERIPHERALREGION 0x4042A000 0x0 0x1F00 registers DMA_FSUB_0 Subscriber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-255 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 DMA_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-255 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 DMA_FPUB_1 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-255 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 DMA_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 DMA_CPU_INT[%s] 0x1020 DMA_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DMACH0 DMA Channel 0 size counter reached zero (DMASZ=0). 0x1 DMACH1 DMA Channel 1 size counter reached zero (DMASZ=0). 0x2 DMACH2 DMA Channel 2 size counter reached zero (DMASZ=0). 0x3 DMACH3 DMA Channel 3 size counter reached zero (DMASZ=0). 0x4 DMACH4 DMA Channel 4 size counter reached zero (DMASZ=0). 0x5 DMACH5 DMA Channel 5 size counter reached zero (DMASZ=0). 0x6 DMACH6 DMA Channel 6 size counter reached zero (DMASZ=0). 0x7 DMACH7 DMA Channel 7 size counter reached zero (DMASZ=0). 0x8 DMACH8 DMA Channel 8 size counter reached zero (DMASZ=0). 0x9 DMACH9 DMA Channel 9 size counter reached zero (DMASZ=0). 0xA DMACH10 DMA Channel 10 size counter reached zero (DMASZ=0). 0xB DMACH11 DMA Channel 11 size counter reached zero (DMASZ=0). 0xC DMACH12 DMA Channel 12 size counter reached zero (DMASZ=0). 0xD DMACH13 DMA Channel 13 size counter reached zero (DMASZ=0). 0xE DMACH14 DMA Channel 14 size counter reached zero (DMASZ=0). 0xF DMACH15 DMA Channel 15 size counter reached zero (DMASZ=0). 0x10 PREIRQCH0 PRE-IRQ event for DMA Channel 0. 0x11 PREIRQCH1 PRE-IRQ event for DMA Channel 1. 0x12 PREIRQCH2 PRE-IRQ event for DMA Channel 2. 0x13 PREIRQCH3 PRE-IRQ event for DMA Channel 3. 0x14 PREIRQCH4 PRE-IRQ event for DMA Channel 4. 0x15 PREIRQCH5 PRE-IRQ event for DMA Channel 5. 0x16 PREIRQCH6 PRE-IRQ event for DMA Channel 6. 0x17 PREIRQCH7 PRE-IRQ event for DMA Channel 7. 0x18 ADDRERR DMA address error, SRC address not reachable. 0x19 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x1A DMA_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DMACH0 DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0). 0x0 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH1 DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0). 0x1 0x1 read-write CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH2 DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0). 0x2 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH3 DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0). 0x3 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH4 DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0). 0x4 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH5 DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0). 0x5 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH6 DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0). 0x6 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH7 DMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0). 0x7 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH8 DMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0). 0x8 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH9 DMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0). 0x9 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH10 DMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0). 0xA 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH11 DMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0). 0xB 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH3 DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0). 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH4 DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0). 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH5 DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0). 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH6 DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0). 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH7 DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0). 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH8 DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0). 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH9 DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0). 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH10 DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0). 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH11 DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0). 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH3 DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0). 0x3 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH4 DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0). 0x4 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH5 DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0). 0x5 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH6 DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0). 0x6 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH7 DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0). 0x7 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH8 DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0). 0x8 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH9 DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0). 0x9 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH10 DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0). 0xA 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH11 DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0). 0xB 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH3 DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0). 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH4 DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0). 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH5 DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0). 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH6 DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0). 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH7 DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0). 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH8 DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0). 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH9 DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0). 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH10 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH11 DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0). 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH3 DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0). 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH4 DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0). 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH5 DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0). 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH6 DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0). 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH7 DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0). 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH8 DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0). 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH9 DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0). 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH10 DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0). 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH11 DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0). 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 1 44 0 DMA_GEN_EVENT[%s] 0x1050 DMA_GEN_EVENT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DMACH0 DMA Channel 0 size counter reached zero (DMASZ=0). 0x1 DMACH1 DMA Channel 1 size counter reached zero (DMASZ=0). 0x2 DMACH2 DMA Channel 2 size counter reached zero (DMASZ=0). 0x3 DMACH3 DMA Channel 3 size counter reached zero (DMASZ=0). 0x4 DMACH4 DMA Channel 4 size counter reached zero (DMASZ=0). 0x5 DMACH5 DMA Channel 5 size counter reached zero (DMASZ=0). 0x6 DMACH6 DMA Channel 6 size counter reached zero (DMASZ=0). 0x7 DMACH7 DMA Channel 7 size counter reached zero (DMASZ=0). 0x8 DMACH8 DMA Channel 8 size counter reached zero (DMASZ=0). 0x9 DMACH9 DMA Channel 9 size counter reached zero (DMASZ=0). 0xA DMACH10 DMA Channel 10 size counter reached zero (DMASZ=0). 0xB DMACH11 DMA Channel 11 size counter reached zero (DMASZ=0). 0xC DMACH12 DMA Channel 12 size counter reached zero (DMASZ=0). 0xD DMACH13 DMA Channel 13 size counter reached zero (DMASZ=0). 0xE DMACH14 DMA Channel 14 size counter reached zero (DMASZ=0). 0xF DMACH15 DMA Channel 15 size counter reached zero (DMASZ=0). 0x10 PREIRQCH0 PRE-IRQ event for DMA Channel 0. 0x11 PREIRQCH1 PRE-IRQ event for DMA Channel 1. 0x12 PREIRQCH2 PRE-IRQ event for DMA Channel 2. 0x13 PREIRQCH3 PRE-IRQ event for DMA Channel 3. 0x14 PREIRQCH4 PRE-IRQ event for DMA Channel 4. 0x15 PREIRQCH5 PRE-IRQ event for DMA Channel 5. 0x16 PREIRQCH6 PRE-IRQ event for DMA Channel 6. 0x17 PREIRQCH7 PRE-IRQ event for DMA Channel 7. 0x18 ADDRERR DMA address error, SRC address not reachable. 0x19 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x1A DMA_GEN_EVENT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DMACH0 DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0). 0x0 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH1 DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0). 0x1 0x1 read-write CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH2 DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0). 0x2 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH3 DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0). 0x3 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH4 DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0). 0x4 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH5 DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0). 0x5 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH6 DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0). 0x6 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH7 DMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0). 0x7 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH8 DMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0). 0x8 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH9 DMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0). 0x9 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH10 DMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0). 0xA 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMACH11 DMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0). 0xB 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_GEN_EVENT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH3 DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0). 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH4 DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0). 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH5 DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0). 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH6 DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0). 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH7 DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0). 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH8 DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0). 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH9 DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0). 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH10 DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0). 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMACH11 DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0). 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_GEN_EVENT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH3 DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0). 0x3 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH4 DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0). 0x4 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH5 DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0). 0x5 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH6 DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0). 0x6 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH7 DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0). 0x7 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH8 DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0). 0x8 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH9 DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0). 0x9 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH10 DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0). 0xA 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 DMACH11 DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0). 0xB 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_GEN_EVENT_ISET Interrupt set 0x20 32 write-only 0x00000000 DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH3 DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0). 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH4 DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0). 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH5 DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0). 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH6 DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0). 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH7 DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0). 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH8 DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0). 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH9 DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0). 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH10 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 DMACH11 DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0). 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_GEN_EVENT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH3 DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0). 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH4 DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0). 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH5 DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0). 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH6 DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0). 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH7 DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0). 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH8 DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0). 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH9 DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0). 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH10 DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0). 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 DMACH11 DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0). 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH1 Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold. 0x11 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH2 Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold. 0x12 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH3 Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold. 0x13 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH4 Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold. 0x14 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 PREIRQCH5 Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold. 0x15 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 CLR Clear interrupt mask bit 0x0 SET Set interrupt mask bit 0x1 DMA_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to interrupt event CPU_INT 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to generic event GEN_EVENT 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 DMA_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 FEATUREVER Feature Set for the DMA: number of DMA channel minus one (e.g. 0->1ch, 2->3ch, 15->16ch). 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 DMA_DMAPRIO DMA Channel Priority Control 0x1100 32 read-write ROUNDROBIN Round robin. This bit enables the round-robin DMA channel priorities. 0x0 0x1 DISABLE Roundrobin priority disabled, DMA channel priority is fixed: DMA0-DMA1-DMA2-...-DMA16 0x0 ENABLE Roundrobin priority enabled, DMA channel priority changes with each transfer 0x1 BURSTSZ Define the burst size of a block transfer, before the priority is re-evaluated 0x10 0x2 INFINITI There is no burst size, the whole block transfer is completed on one transfer without interruption 0x0 BURST_8 The burst size is 8, after 9 transfers the block transfer is interrupted and the priority is reevaluated 0x1 BUSRT_16 The burst size is 16, after 17 transfers the block transfer is interrupted and the priority is reevaluated 0x2 BURST_32 The burst size is 32, after 33 transfers the block transfer is interrupted and the priority is reevaluated 0x3 12 4 0,1,2,3,4,5,6,7,8,9,10,11 DMA_DMATRIG[%s] 0x1110 DMA_DMATCTL DMA Trigger Select 0x0 32 read-write DMATSEL DMA Trigger Select Note: Reference the datasheet of the device to see the specific trigger mapping. 0x0 0x6 DMAREQ Software trigger request 0x0 DMATINT DMA Trigger by Internal Channel 0x7 0x1 EXTERNAL DMATSEL will define external trigger select as transfer trigger. 0x0 INTERNAL DMATSEL will define internal channel as transfer trigger select. 0-> Channel0-done, 1-> Channel1-done, ... 0x1 12 16 0,1,2,3,4,5,6,7,8,9,10,11 DMA_DMACHAN[%s] 0x1200 DMA_DMACTL DMA Channel Control 0x0 32 read-write DMAREQ DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0x0 0x1 IDLE Default read value 0x0 REQUEST DMA transfer request (start DMA) 0x1 DMAEN DMA enable 0x1 0x1 DISABLE DMA channel disabled 0x0 ENABLE DMA channel enabled 0x1 DMASRCWDTH DMA source width. This bit selects the source data width as a byte, half word, word, long word or long-long word. 0x8 0x3 BYTE Source data width is BYTE (8-bit) 0x0 HALF Source data width is HALF-WORD (16-bit) 0x1 WORD Source data width is WORD (32-bit) 0x2 LONG Source data width is LONG-WORD (64-bit) 0x3 LONGLONG Source data width is LONG-LONG-WORD (128-bit) 0x4 DMADSTWDTH DMA destination width. This bit selects the destination as a byte, half word, word, long word or long-long word. 0xC 0x3 BYTE Destination data width is BYTE (8-bit) 0x0 HALF Destination data width is HALF-WORD (16-bit) 0x1 WORD Destination data width is WORD (32-bit) 0x2 LONG Destination data width is LONG-WORD (64-bit) 0x3 LONGLONG Source data width is LONG-LONG-WORD (128-bit) 0x4 DMASRCINCR DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4. 0x10 0x4 UNCHANGED Address is unchanged (+0) 0x0 DECREMENT Decremented by 1 (-1 * DMASRCWDTH) 0x2 INCREMENT Incremented by 1 (+1 * DMASRCWDTH) 0x3 STRIDE_2 Stride size 2 (+2 * DMASRCWDTH) 0x8 STRIDE_3 Stride size 3 (+3 * DMASRCWDTH) 0x9 STRIDE_4 Stride size 4 (+4 * DMASRCWDTH) 0xA STRIDE_5 Stride size 5 (+5 * DMASRCWDTH) 0xB STRIDE_6 Stride size 6 (+6 * DMASRCWDTH) 0xC STRIDE_7 Stride size 7 (+7 * DMASRCWDTH) 0xD STRIDE_8 Stride size 8 (+8 * DMASRCWDTH) 0xE STRIDE_9 Stride size 9 (+9 * DMASRCWDTH) 0xF DMADSTINCR DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4. 0x14 0x4 UNCHANGED Address is unchanged (+0) 0x0 DECREMENT Decremented by 1 (-1 * DMADSTWDTH) 0x2 INCREMENT Incremented by 1 (+1 * DMADSTWDTH) 0x3 STRIDE_2 Stride size 2 (+2 * DMADSTWDTH) 0x8 STRIDE_3 Stride size 3 (+3 * DMADSTWDTH) 0x9 STRIDE_4 Stride size 4 (+4 * DMADSTWDTH) 0xA STRIDE_5 Stride size 5 (+5 * DMADSTWDTH) 0xB STRIDE_6 Stride size 6 (+6 * DMADSTWDTH) 0xC STRIDE_7 Stride size 7 (+7 * DMADSTWDTH) 0xD STRIDE_8 Stride size 8 (+8 * DMADSTWDTH) 0xE STRIDE_9 Stride size 9 (+9 * DMADSTWDTH) 0xF DMATM DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set. 0x1C 0x2 SINGLE Single transfer. Each transfers requires a new trigger. When the DMASZ counts down to zero an event can be generated and the DMAEN is cleared. 0x0 BLOCK Block transfer. Each trigger transfers the complete block defined in DMASZ. After the transfer is complete an event can be generated and the DMAEN is cleared. 0x1 RPTSNGL Repeated single transfer. Each transfers requires a new trigger. When the DMASZ counts down to zero an event can be generated. After the last transfer the DMASA, DMADA, DAMSZ registers are restored to its initial value and the DMAEN stays enabled. 0x2 RPTBLCK Repeated block transfer. Each trigger transfers the complete block defined in DMASZ. After the last transfer the DMASA, DMADA, DAMSZ registers are restored to its initial value and the DMAEN stays enabled. 0x3 DMAEM DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0. 0x18 0x2 NORMAL Normal mode is related to transfers from SRC to DST 0x0 GATHERMODE Gather mode will read a data from an address table located at SA, and the data is transfered to the DA 0x1 FILLMODE Fill mode will copy the SA register content as data to DA 0x2 TABLEMODE Table mode will read an address and data value from SA and write the data to address 0x3 DMAPREIRQ Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0. 0x4 0x3 PREIRQ_DISABLE Pre-IRQ event disabled. 0x0 PREIRQ_1 Issure Pre-IRQ event when DMASZ=1 0x1 PREIRQ_2 Issure Pre-IRQ event when DMASZ=2 0x2 PREIRQ_4 Issure Pre-IRQ event when DMASZ=4 0x3 PREIRQ_8 Issure Pre-IRQ event when DMASZ=8 0x4 PREIRQ_32 Issure Pre-IRQ event when DMASZ=32 0x5 PREIRQ_64 Issure Pre-IRQ event when DMASZ=64 0x6 PREIRQ_HALF Issure Pre-IRQ event when DMASZ reached the half size point of the original transfer size 0x7 DMAAUTOEN Automatic DMA channel enable on DMASA, DMADA, DMASZ register write. If channel is configured as SW trigger (DMATCTL=0), the AUTOEN will set the DMAEN and DMAREQ. If channel is configured as HW trigger (DMACTL!=0), the AUTOEN will only set the DMAEN. 0x2 0x2 DISABLE No automatic DMA enable 0x0 DMASA Automatic DMA enable on DMASA register write. 0x1 DMADA Automatic DMA enable on DMADA register write. 0x2 DMASZ Automatic DMA enable on DMASZ register write. 0x3 DMA_DMASA DMA Channel Source Address 0x4 32 read-write ADDR DMA Channel Source Address 0x0 0x20 DMA_DMADA DMA Channel Destination Address 0x8 32 read-write ADDR DMA Channel Destination Address 0x0 0x20 DMA_DMASZ DMA Channel Size 0xC 32 read-write SIZE DMA Channel Size in number of transfers 0x0 0x10 COMP0 COMP 1.0 PERIPHERALREGION 0x40008000 0x0 0x1F00 registers COMP0_FSUB_0 Subscriber Port 0 0x400 32 read-write CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 COMP0_FSUB_1 Subscriber Port 1 0x404 32 read-write CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 COMP0_FPUB_1 Publisher port 1 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 COMP0_GPRCM[%s] 0x800 COMP0_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 COMP0_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 COMP0_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable disable COMP to request SYSOSC 0x0 Enable enable COMP to request SYSOSC 0x1 COMP0_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 1 44 0 COMP0_CPU_INT[%s] 0x1020 COMP0_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x2 read-only NO_INTR No pending interrupt 0x0 COMPIFG Comparator output interrupt 0x2 COMPINVIFG Comparator output inverted interrupt 0x3 OUTRDYIFG Comparator output ready interrupt 0x4 COMP0_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 COMPIFG Masks COMPIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMPINVIFG Masks COMPINVIFG 0x2 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 OUTRDYIFG Masks OUTRDYIFG 0x3 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMP0_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 COMPIFG Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x1 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMPINVIFG Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x2 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 OUTRDYIFG Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid. 0x3 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMP0_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 COMPIFG Masked interrupt status for COMPIFG 0x1 0x1 CLR COMPIFG does not request an interrupt service routine 0x0 SET COMPIFG requests an interrupt service routine 0x1 COMPINVIFG Masked interrupt status for COMPINVIFG 0x2 0x1 CLR COMPINVIFG does not request an interrupt service routine 0x0 SET COMPINVIFG requests an interrupt service routine 0x1 OUTRDYIFG Masked interrupt status for OUTRDYIFG 0x3 0x1 CLR OUTRDYIFG does not request an interrupt service routine 0x0 SET OUTRDYIFG requests an interrupt service routine 0x1 COMP0_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 COMPIFG Sets COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPIFG is set 0x1 COMPINVIFG Sets COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPINVIFG is set 0x1 OUTRDYIFG Sets OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to OUTRDYIFG is set 0x1 COMP0_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 COMPIFG Clears COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPIFG is cleared 0x1 COMPINVIFG Clears COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPINVIFG is cleared 0x1 OUTRDYIFG Clears OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to OUTRDYIFG is cleared 0x1 1 44 0 COMP0_GEN_EVENT[%s] 0x1050 COMP0_GEN_EVENT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x2 read-only NO_INTR No pending interrupt 0x0 COMPIFG Comparator output interrupt 0x2 COMPINVIFG Comparator output inverted interrupt 0x3 OUTRDYIFG Comparator output ready interrupt 0x4 COMP0_GEN_EVENT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 COMPIFG Masks COMPIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMPINVIFG Masks COMPINVIFG 0x2 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 OUTRDYIFG Masks OUTRDYIFG 0x3 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 COMP0_GEN_EVENT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 COMPIFG Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x1 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMPINVIFG Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x2 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 OUTRDYIFG Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid. 0x3 0x1 CLR No interrupt pending 0x0 SET Interrupt pending 0x1 COMP0_GEN_EVENT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 COMPIFG Masked interrupt status for COMPIFG 0x1 0x1 CLR COMPIFG does not request an interrupt service routine 0x0 SET COMPIFG requests an interrupt service routine 0x1 COMPINVIFG Masked interrupt status for COMPINVIFG 0x2 0x1 CLR COMPINVIFG does not request an interrupt service routine 0x0 SET COMPINVIFG requests an interrupt service routine 0x1 OUTRDYIFG Masked interrupt status for OUTRDYIFG 0x3 0x1 CLR OUTRDYIFG does not request an interrupt service routine 0x0 SET OUTRDYIFG requests an interrupt service routine 0x1 COMP0_GEN_EVENT_ISET Interrupt set 0x20 32 write-only 0x00000000 COMPIFG Sets COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPIFG is set 0x1 COMPINVIFG Sets COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to COMPINVIFG is set 0x1 OUTRDYIFG Sets OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to OUTRDYIFG is set 0x1 COMP0_GEN_EVENT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 COMPIFG Clears COMPIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPIFG is cleared 0x1 COMPINVIFG Clears COMPINVIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to COMPINVIFG is cleared 0x1 OUTRDYIFG Clears OUTRDYIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to OUTRDYIFG is cleared 0x1 COMP0_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000009 INT0_CFG Event line mode select for event corresponding to CPU_INT 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to GEN_EVENT 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE Event handled by software. Software must clear the associated RIS flag. 0x1 HARDWARE Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. 0x2 COMP0_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 read-only MAJREV Major rev of the IP 0x4 0x4 read-only FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only COMP0_CTL0 Control 0 0x1100 32 read-write 0x00000000 IPSEL Channel input selected for the positive terminal of the comparator if IPEN is set to 1. 0x0 0x3 read-write CH_0 Channel 0 selected 0x0 CH_1 Channel 1 selected 0x1 CH_2 Channel 2 selected 0x2 CH_3 Channel 3 selected 0x3 CH_4 Channel 4 selected 0x4 CH_5 Channel 5 selected 0x5 CH_6 Channel 6 selected 0x6 CH_7 Channel 7 selected 0x7 IPEN Channel input enable for the positive terminal of the comparator. 0xF 0x1 read-write DISABLE Selected analog input channel for positive terminal is disabled 0x0 ENABLE Selected analog input channel for positive terminal is enabled 0x1 IMEN Channel input enable for the negative terminal of the comparator. 0x1F 0x1 read-write DISABLE Selected analog input channel for negative terminal is disabled 0x0 ENABLE Selected analog input channel for negative terminal is enabled 0x1 IMSEL Channel input selected for the negative terminal of the comparator if IMEN is set to 1. 0x10 0x3 read-write CH_0 Channel 0 selected 0x0 CH_1 Channel 1 selected 0x1 CH_2 Channel 2 selected 0x2 CH_3 Channel 3 selected 0x3 CH_4 Channel 4 selected 0x4 CH_5 Channel 5 selected 0x5 CH_6 Channel 6 selected 0x6 CH_7 Channel 7 selected 0x7 COMP0_CTL1 Control 1 0x1104 32 read-write 0x00000000 ENABLE This bit turns on the comparator. When the comparator is turned off it consumes no power. 0x0 0x1 read-write OFF Comparator is off 0x0 ON Comparator is on 0x1 MODE This bit selects the comparator operating mode. 0x1 0x1 read-write FAST Comparator is in fast mode 0x0 ULP Comparator is in ultra-low power mode 0x1 EXCH This bit exchanges the comparator inputs and inverts the comparator output. 0x2 0x1 read-write NO_EXC Comparator inputs not exchanged and output not inverted 0x0 EXC Comparator inputs exchanged and output inverted 0x1 SHORT This bit shorts the positive and negative input terminals of the comparator. 0x3 0x1 read-write NO_SHT Comparator positive and negative input terminals are not shorted 0x0 SHT Comparator positive and negative input terminals are shorted 0x1 IES This bit selected the interrupt edge for COMPIFG and COMPINVIFG. 0x4 0x1 read-write RISING Rising edge sets COMPIFG and falling edge sets COMPINVIFG 0x0 FALLING Falling edge sets COMPIFG and rising edge sets COMPINVIFG 0x1 HYST These bits select the hysteresis setting of the comparator. 0x5 0x2 read-write NO_HYS No hysteresis 0x0 LOW_HYS Low hysteresis, typical 10mV 0x1 MED_HYS Medium hysteresis, typical 20mV 0x2 HIGH_HYS High hysteresis, typical 30mV 0x3 OUTPOL This bit selects the comparator output polarity. 0x7 0x1 read-write NON_INV Comparator output is non-inverted 0x0 INV Comparator output is inverted 0x1 FLTEN This bit enables the analog filter at comparator output. 0x8 0x1 read-write DISABLE Comparator output filter is disabled 0x0 ENABLE Comparator output filter is enabled 0x1 FLTDLY These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings. 0x9 0x2 read-write DLY_0 Typical filter delay of 70 ns 0x0 DLY_1 Typical filter delay of 500 ns 0x1 DLY_2 Typical filter delay of 1200 ns 0x2 DLY_3 Typical filter delay of 2700 ns 0x3 WINCOMPEN This bit enables window comparator operation of comparator. 0xC 0x1 read-write OFF window comparator is disable 0x0 ON window comparator is enable 0x1 COMP0_CTL2 Control 2 0x1108 32 read-write 0x00000000 REFMODE This bit requests ULP_REF bandgap operation in fast mode(static) or low power mode (sampled). The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Fast mode operation offers higher accuracy but consumes higher current. Low power operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL > 0. 0x0 0x1 read-write STATIC ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in static mode. 0x0 SAMPLED ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in sampled mode. 0x1 REFSRC These bits select the reference source for the comparator. 0x3 0x3 read-write OFF Reference voltage generator is disabled (local reference buffer as well as DAC). 0x0 VDDA_DAC VDDA selected as the reference source to DAC and DAC output applied as reference to comparator. 0x1 VREF_DAC VREF selected as reference to DAC and DAC output applied as reference to comparator. 0x2 VREF In devices where internal VREF is buffered and hookedup to extrernal VREF pin, VREF applied as reference to comparator. DAC is switched off. Note: In LEGO_A3, DAC is turned off in this selection, in other deviced DAC is kept on. 0x3 VDDA VDDA is used as comparator reference. Note: In LEGO_A3, DAC is turned off in this selection, in other deviced DAC is kept on. 0x5 INTVREF_DAC Internal reference selected as the reference source to DAC and DAC output applied as reference to comparator. 0x6 INTVREF Internal VREF is used as the source of comparator. Not all devices will have this option. 0x7 REFSEL This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator. 0x7 0x1 read-write POSITIVE If EXCH bit is 0, the selected reference is applied to positive terminal. If EXCH bit is 1, the selected reference is applied to negative terminal. 0x0 NEGATIVE If EXCH bit is 0, the selected reference is applied to negative terminal. If EXCH bit is 1, the selected reference is applied to positive terminal. 0x1 DACCTL This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1. 0x10 0x1 read-write COMPOUT_SEL Comparator output controls selection between DACCODE0 and DACCODE1 0x0 DACSW_SEL DACSW bit controls selection between DACCODE0 and DACCODE1 0x1 DACSW This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1. 0x11 0x1 read-write DACCODE0_SEL DACCODE0 selected for 8-bit DAC 0x0 DACCODE1_SEL DACCODE1 selected for 8-bit DAC 0x1 BLANKSRC These bits select the blanking source for the comparator. 0x8 0x3 read-write DISABLE Blanking source disabled 0x0 BLANKSRC1 Select Blanking Source 1 0x1 BLANKSRC2 Select Blanking Source 2 0x2 BLANKSRC3 Select Blanking Source 3 0x3 BLANKSRC4 Select Blanking Source 4 0x4 BLANKSRC5 Select Blanking Source 5 0x5 BLANKSRC6 Select Blanking Source 6 0x6 SAMPMODE Enable sampled mode of comparator. 0x18 0x1 read-write DISABLE Sampled mode disabled 0x0 ENABLE Sampled mode enabled 0x1 COMP0_CTL3 Control 3 0x110C 32 read-write 0x00000000 DACCODE0 This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. 0x0 0x8 read-write DACCODE1 This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. 0x10 0x8 read-write COMP0_STAT Status 0x1120 32 read-only 0x00000000 OUT This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output. 0x0 0x1 read-only LOW Comparator output is low 0x0 HIGH Comparator output is high 0x1 TRNG TRNG 1.0 PERIPHERALREGION 0x40444000 0x0 0x1E00 registers 1 24 0 TRNG_GPRCM[%s] 0x800 TRNG_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TRNG_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TRNG_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TRNG_IIDX Interrupt index 0x1020 32 read-only 0x00000000 0x000000ff STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 IRQ_HEALTH_FAIL Indicates that a health test has failed. The TRNG is in an error state until the interrupt is cleared. 0x1 IRQ_CMD_FAIL Indicates that the just issued command was rejected and is not being performed. 0x2 IRQ_CMD_DONE Indicates that the current command/mode is done. This may have different meanings based on the mode: OFF --> Power has been turned off PWRUP_DIG --> Digital powerup tests are done PWRUP_ANA --> Analog powerup tests are done NORM_FUNC --> No IRQ, since mode runs indefinitely until a new command is issued 0x3 IRQ_CAPTURED_RDY Indicates that the captured word buffer is ready to be copied to memory 0x4 TRNG_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 0x0000000f IRQ_HEALTH_FAIL Mask for IRQ_HEALTH_FAIL. Indicates that a health test has failed. 0x0 0x1 read-write DISABLED Interrupt is masked out 0x0 ENABLED Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 IRQ_CAPTURED_RDY Mask for IRQ_CAPTURED_RDY. Indicates to the CPU that the Captured Word is ready to be read. 0x3 0x1 read-write DISABLED Interrupt is masked out 0x0 ENABLED Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 IRQ_CMD_DONE Mask for IRQ_CMD_DONE. Indicates that a command has finished 0x2 0x1 read-write DISABLED Interrupt is masked out 0x0 ENABLED Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 IRQ_CMD_FAIL Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected. 0x1 0x1 read-write DISABLED Interrupt is masked out 0x0 ENABLED Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 TRNG_RIS Raw interrupt status 0x1030 32 read-only 0x00000000 0x0000000f IRQ_CAPTURED_RDY Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt. 0x3 0x1 read-only CLR IRQ_CAPTURED_READY did not occur 0x0 SET IRQ_CAPTURED_READY occurred 0x1 IRQ_HEALTH_FAIL Indicates to the CPU that any of the health tests have failed. Reading the IIDX will clear this interrupt. 0x0 0x1 read-only CLR IRQ_CAPTURED_READY did not occur 0x0 SET IRQ_CAPTURED_READY occurred 0x1 IRQ_CMD_DONE Raw interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed. 0x2 0x1 read-only CLR IRQ_CMD_DONE did not occur 0x0 SET IRQ_CMD_DONE occurred 0x1 IRQ_CMD_FAIL Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected. 0x1 0x1 read-only CLR IRQ_CMD_FAIL did not occur 0x0 SET IRQ_CMD_FAIL occurred 0x1 TRNG_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 0x0000000f IRQ_CAPTURED_RDY Masked interrupt result for CAPTURED_READY. Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt. 0x3 0x1 read-only CLR IRQ_CAPTURED_READY did not request an interrupt service routine 0x0 SET IRQ_CAPTURED_READY requests an interrupt service routine 0x1 IRQ_HEALTH_FAIL Masked interrupt result for HEALTH_FAIL. Indicates to the CPU that any of the health tests have failed for the latest 1024-bit window. 0x0 0x1 read-only CLR IRQ_CAPTURED_READY did not request an interrupt service routine 0x0 SET IRQ_CAPTURED_READY requests an interrupt service routine 0x1 IRQ_CMD_DONE Masked interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed. 0x2 0x1 read-only CLR IRQ_CAPTURED_READY did not request an interrupt service routine 0x0 SET IRQ_CMD_DONE requests an interrupt service routine 0x1 IRQ_CMD_FAIL Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected. 0x1 0x1 read-only CLR IRQ_CMD_FAIL did not request an interrupt service routine 0x0 SET IRQ_CMD_FAIL requests an interrupt service routine 0x1 TRNG_ISET Interrupt set 0x1040 32 write-only IRQ_CAPTURED_RDY Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt. 0x3 0x1 write-only NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to CAPTURED_READY is set 0x1 IRQ_HEALTH_FAIL Indicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt. 0x0 0x1 write-only NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to HEALTH_FAIL is set 0x1 IRQ_CMD_DONE Write to turn on CMD_DONE IRQ. Indicates that the last issued TRNG command has finished. 0x2 0x1 write-only NO_EFFECT Writing a 0 has no effect. 0x0 SET RIS bit corresponding to CMD_DONE is set 0x1 IRQ_CMD_FAIL Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected. 0x1 0x1 write-only NO_EFFECT Writing a 0 has no effect. 0x0 SET RIS bit corresponding to CMD_FAIL is set 0x1 TRNG_ICLR Interrupt clear 0x1048 32 write-only IRQ_CAPTURED_RDY Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt. 0x3 0x1 write-only NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to CAPTURED_READY is cleared 0x1 IRQ_HEALTH_FAIL Indicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt. 0x0 0x1 write-only NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to CAPTURED_READY is cleared 0x1 IRQ_CMD_DONE Write to turn off CMD_DONE IRQ. Indicates that the last issued TRNG command has finished. 0x2 0x1 write-only NO_EFFECT Writing a 0 has no effect. 0x0 CLR RIS bit corresponding to CMD_DONE is cleared 0x1 IRQ_CMD_FAIL Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected. 0x1 0x1 write-only NO_EFFECT Writing a 0 has no effect. 0x0 CLR RIS bit corresponding to CMD_FAIL is cleared 0x1 TRNG_DESC Module descriptions 0x10FC 32 read-only 0x05110000 0xffffffff MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module Identifier - An internal TI page has been created to request unique module IDs 0x10 0x10 TRNG_CTL Controls the command and decimation rate 0x1100 32 read-write 0x00140000 0x001f0703 DECIM_RATE Set decimation rate. Decimate by n 0x0 = Decimation by 1 (no decimation) 0x1 = Decimation by 2 (Skip every other sample) 0x7 = Decimation by 8 (Take every 8th sample) 0x8 0x3 PWRUP_CLKDIV When '1', the powerup sequence will take twice as long (i.e., clock frequency halved) 0x10 0x1 read-write PWRUP_PCHRG_CFG Configure PCHARGE sequence length b00 = Disabled b01 = 20 us PCHARGE b10 = 30 us PCHARGE (default) b11 = 40 us PCHARGE 0x11 0x2 read-write PWRUP_PSTART_CFG Configure pusle startup sequence length b00 = Disabled b01 = rise at 10us, fall at 50us b10 = rise at 10us, fall at 70us (default) b11 = rise at 10us, fall at 90us 0x13 0x2 read-write CMD Sets the TRNG mode through a command. The mode will not be updated until the previous command is done, as indicated by IRQ_CMD_DONE. 00 --> OFF 01 --> PWRUP_DIG 10 --> PWRUP_ANA 11 --> NORM_FUNC 0x0 0x2 PWR_OFF Turns the power off of the analog source and clocks the digital interface 0x0 PWRUP_DIG Initiates the powerup test sequence for the digital components. This verifies that the digital components are properly working. IRQ_CMD_DONE indicates that the test is done. The results of this test are in bits 0:6 in TEST_RESULTS register 0x1 PWRUP_ANA Initiates the powerup test sequence for the analog TRNG. This verifies that the analog component is generating sequences with enough entropy. IRQ_CMD_DONE indicates that the test is done. The results of this test are in bit 7 in TEST_RESULTS register 0x2 NORM_FUNC Normal operating mode for TRNG. All components are turned on. 0x3 TRNG_STAT Status register that informs health test results and last issued command 0x1104 32 read-only 0x00000000 0x000f0303 ADAP_FAIL Indicates that the Adaptive Proportion Test (1,2,3, or 4-bit counters) failed by having too many or too few counted samples in the last 1024 bit window. 0x0 0x1 ISSUED_CMD Indicates the last accepted command that is issued to the TRNG interface. Upon writing a valid command, this register will update and the command will be in progress until CMD_DONE_IRQ is set. CMD_DONE_IRQ indicates that the state is in PWROFF, NORM_FUNC, or ERROR. These states will accept new commands. 00 --> OFF 01 --> PWRUP_DIG 10 --> PWRUP_ANA 11 --> NORM_FUNC 0x8 0x2 read-only FSM_STATE Current state of the front end FSM (behind a clock domain crossing). 2 reads are REQUIRED as there is a chance of metastability when reading this States: 0000: OFF 0001: PWRUP_ES 0011: NORM_FUNC 0111: TEST_DIG 1011: TEST_ANA 1010: ERROR 0010: PWRDOWN_ES 0x10 0x4 read-only REP_FAIL Indicates that the repetition counter test caused the most recent failure. Thus, the health count numbers are most likely not for a complete 1024-bit window. 0x1 0x1 read-only TRNG_DATA_CAPTURE Captured word buffer of RNG data 0x1108 32 read-only 0x00000000 0xffffffff TRNG_TEST_RESULTS Test results from TEST_ANA and TEST_DIG 0x110C 32 read-only 0x00000000 0x000001ff DIG_TEST Bit 0 indicates if the first decimation rate test and health test(verifies conditioning, decimation, and captured buffer) fails and Bit 1 indicates if the second decimation test and health test fails Bit 0 - decim_test0 (decim = 0x0) Bit 1 - decim_test1 (decim = 0x1) ... 0x0 0x8 ANA_TEST Runs through 4096 samples from an enabled entropy source and verifies that none of the health tests failed, indicating sufficient entropy was produced by the analog components 0x8 0x1 TRNG_CLKDIVIDE Clock Divider 0x1110 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_8 Divide clock source by 8 0x7 UART3 UART 1.0 PERIPHERALREGION 0x40500000 0x0 0x1F00 registers 1 24 0 UART3_GPRCM[%s] 0x800 UART3_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 UART3_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 UART3_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 UART3_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 UART3_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 UART3_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 UART3_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 UART3_CPU_INT[%s] 0x1020 UART3_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 FEFG UART framing error interrupt; Interrupt Flag: FE 0x2 PEFG UART parity error interrupt; Interrupt Flag: PE 0x3 BEFG UART break error interrupt; Interrupt Flag: BE 0x4 OEFG UART receive overrun error interrupt; Interrupt Flag: OE 0x5 RXNE Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE 0x6 RXPE Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE 0x7 LINC0 LIN capture 0 / match interrupt; Interrupt Flag: LINC0 0x8 LINC1 LIN capture 1 interrupt; Interrupt Flag: LINC1 0x9 LINOVF LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF 0xA RXIFG UART receive interrupt; Interrupt Flag: RX 0xB TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC EOT UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT 0xD MODE_9B 9-bit mode address match interrupt; Interrupt Flag: MODE_9B 0xE CTS UART Clear to Send Modem interrupt; Interrupt Flag: CTS 0xF DMA_DONE_RX DMA DONE on RX 0x10 DMA_DONE_TX DMA DONE on TX 0x11 NERR_EVT Noise Error Event 0x12 UART3_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PARERR Enable UART Parity Error Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 BRKERR Enable UART Break Error Interrupt. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTS Enable UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX Enable DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX Enable DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART3_CPU_INT_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_RX DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_TX DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART3_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR Masked UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR Masked UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS Masked UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_RX Masked DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_TX Masked DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART3_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 FRMERR Set UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PARERR Set UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 BRKERR Set UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTS Set UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing this has no effect 0x0 SET Set the interrupt 0x1 UART3_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PARERR Clear UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 BRKERR Clear UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTS Clear UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART3_DMA_TRIG_RX[%s] 0x1050 UART3_DMA_TRIG_RX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 RXIFG UART receive interrupt; Interrupt Flag: RX 0xB UART3_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART3_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART3_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART3_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART3_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART3_DMA_TRIG_TX[%s] 0x1080 UART3_DMA_TRIG_TX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC UART3_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART3_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART3_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART3_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART3_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 UART3_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 UART3_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 UART3_CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write DISABLE Disable Module 0x0 ENABLE Enable module 0x1 HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write OVS16 16x oversampling. 0x0 OVS8 8x oversampling. 0x1 OVS3 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled. 0x2 LBE UART Loop Back Enable 0x2 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The UARTxTX path is fed through the UARTxRX path internally. 0x1 RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write DISABLE The receive section of the UART is disabled. 0x0 ENABLE The receive section of the UART is enabled. 0x1 TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write DISABLE The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled. 0x0 ENABLE The transmit section of the UART is enabled. 0x1 RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CLR Signal not RTS 0x0 SET Signal RTS 0x1 RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write DISABLE RTS hardware flow control is disabled. 0x0 ENABLE RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries. 0x1 CTSEN Enable Clear To Send 0xE 0x1 read-write DISABLE CTS hardware flow control is disabled. 0x0 ENABLE CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted. 0x1 MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write UART Normal operation 0x0 RS485 RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data. 0x1 IDLELINE The UART operates in IDLE Line Mode 0x2 ADDR9BIT The UART operates in 9 Bit Address mode 0x3 SMART ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. 0x4 DALI DALI Mode: 0x5 FEN UART Enable FIFOs 0x11 0x1 read-write DISABLE The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 0x0 ENABLE The transmit and receive FIFO buffers are enabled (FIFO mode). 0x1 TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write LOW TXD pin is low 0x0 HIGH TXD pin is high 0x1 TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 0x5 0x1 read-write DISABLE TXD pin can not be controlled by TXD_OUT 0x0 ENABLE TXD pin can be controlled by TXD_OUT 0x1 MAJVOTE Majority Vote Enable When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (i.e. all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set. Oversampling of 16 : bits 7, 8, 9 are used Oversampling of 8 : bits 3, 4, 5 are used Disabled : Single sample value (center value) used 0x12 0x1 read-write DISABLE Majority voting is disabled 0x0 ENABLE Majority voting is enabled 0x1 MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write DISABLE Least significant bit is sent first in the protocol packet 0x0 ENABLE Most significant bit is sent first in the protocol packet 0x1 UART3_LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write DISABLE Normal use. 0x0 ENABLE A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0x1 PEN UART Parity Enable 0x1 0x1 read-write DISABLE Parity is disabled and no parity bit is added to the data frame. 0x0 ENABLE Parity checking and generation is enabled. 0x1 EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write ODD Odd parity is performed, which checks for an odd number of 1s. 0x0 EVEN Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0x1 STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write DISABLE One stop bit is transmitted at the end of a frame. 0x0 ENABLE Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid. 0x1 WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write DATABIT5 5 bits (default) 0x0 DATABIT6 6 bits 0x1 DATABIT7 7 bits 0x2 DATABIT8 8 bits 0x3 SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write DISABLE Disable Stick Parity 0x0 ENABLE Enable Stick Parity 0x1 SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write DISABLE Disable Send Idle Pattern 0x0 ENABLE Enable Send Idle Pattern 0x1 EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write UART3_STAT UART Status Register 0x1108 32 read-only BUSY UART Busy This bit is set as soon as the transmit FIFO or TXDATA register becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only CLEARED The UART is not busy. 0x0 SET The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register. 0x1 TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only CLEARED The transmitter is not full. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0x1 RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only CLEARED The receiver can receive data. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0x1 TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only CLEARED The transmitter has data to transmit. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0x1 CTS Clear To Send 0x8 0x1 read-only CLEARED The CTS signal is not asserted (high). 0x0 SET The CTS signal is asserted (low). 0x1 IDLE IDLE mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only CLEARED IDLE has not been detected before last received character. (In idle-line multiprocessor mode). 0x0 SET IDLE has been detected before last received character. (In idle-line multiprocessor mode). 0x1 RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only CLEARED The receiver is not empty. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0x1 UART3_IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_EMPTY TX FIFO is empty 0x5 LVL_1 TX FIFO >= 1 entry free Note: esp. required for DMA Trigger 0x7 RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write LVL_1_4_RES RX FIFO >= 1/4 full Note: For ULP Domain 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_FULL_RES RX FIFO is full Note: For ULP Domain 0x4 LVL_FULL RX FIFO is full 0x5 LVL_1 RX FIFO >= 1 entry available Note: esp. required for DMA Trigger 0x7 RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write UART3_IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write UART3_FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write UART3_GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb CHAIN Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0xB 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 UART3_TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write UART3_RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff DATA Received Data. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only CLR No framing error has occurred 0x0 SET The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1). 0x1 PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only CLR No parity error has occurred 0x0 SET The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0x1 BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only CLR No break condition has occurred 0x0 SET A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0x1 OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only CLR No data has been lost due to a receive overrun. 0x0 SET New data was received but could not be stored, because the previous data was not read (resulting in data loss). 0x1 NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only CLR No noise error occured 0x0 SET Noise error occured during majority voting 0x1 UART3_AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff MSK Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register must match. 0x0 0x8 read-write UART3_ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh. 0x0 0x8 read-write TIMG0 TIMG 1.0 PERIPHERALREGION 0x40084000 0x0 0x1F00 registers TIMG0_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG0_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG0_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG0_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMG0_GPRCM[%s] 0x800 TIMG0_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMG0_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMG0_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMG0_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMG0_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMG0_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMG0_INT_EVENT[%s] 0x1020 TIMG0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMG0_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TIMG0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG0_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMG0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMG0_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMG0_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 32 0 TIMG0_COMMONREGS[%s] 0x1100 TIMG0_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMG0_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 TIMG0_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMG0_CPS Clock Prescale Register 0xC 32 read-write PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write TIMG0_CPSV Clock prescale count status register 0x10 32 read-only CPSVAL Current Prescale Count Value 0x0 0x8 read-only TIMG0_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMG0_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 1 180 0 TIMG0_COUNTERREGS[%s] 0x1800 TIMG0_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x10 read-write TIMG0_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMG0_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x10 read-write 2 4 0,1 TIMG0_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMG0_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMG0_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMG0_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 2 4 0,1 TIMG0_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMG0_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 TIMA1 TIMA 1.0 PERIPHERALREGION 0x40862000 0x0 0x1F00 registers TIMA1_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMA1_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMA1_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMA1_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMA1_GPRCM[%s] 0x800 TIMA1_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMA1_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMA1_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMA1_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMA1_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMA1_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMA1_INT_EVENT[%s] 0x1020 TIMA1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMA1_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 F Fault Event mask 0x18 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 CCD4 Compare DN event mask CCP4 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD5 Compare DN event mask CCP5 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU4 Compare UP event mask CCP4 0xE 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU5 Compare UP event mask CCP5 0xF 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TIMA1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 F Fault 0x18 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD4 Compare down event generated an interrupt CCD4 0xC 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD5 Compare down event generated an interrupt CCD5 0xD 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU4 Compare up event generated an interrupt CCU4 0xE 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU5 Compare up event generated an interrupt CCP5 0xF 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMA1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 F Fault 0x18 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD4 Compare down event generated an interrupt CCP4 0xC 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD5 Compare down event generated an interrupt CCP5 0xD 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU4 Compare up event generated an interrupt CCP4 0xE 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU5 Compare up event generated an interrupt CCP5 0xF 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMA1_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 F Fault event SET 0x18 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD4 Compare down event 4 SET 0xC 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD5 Compare down event 5 SET 0xD 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU4 Compare up event 4 SET 0xE 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU5 Compare up event 5 SET 0xF 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMA1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 F Fault event CLEAR 0x18 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD4 Compare down event 4 CLEAR 0xC 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD5 Compare down event 5 CLEAR 0xD 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU4 Compare up event 4 CLEAR 0xE 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU5 Compare up event 5 CLEAR 0xF 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMA1_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMA1_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 40 0 TIMA1_COMMONREGS[%s] 0x1100 TIMA1_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMA1_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 TIMA1_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMA1_CPS Clock Prescale Register 0xC 32 read-write PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write TIMA1_CPSV Clock prescale count status register 0x10 32 read-only CPSVAL Current Prescale Count Value 0x0 0x8 read-only TIMA1_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMA1_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 TIMA1_FSCTL Fault Source Control 0x20 32 read-write FCEN This field controls whether the fault caused by the system clock fault is enable. 0: DISABLE 1: ENABLE 0x0 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FAC0EN This field controls whether the fault signal detected by the analog comparator0 is enable 0: DISABLE 1: ENABLE 0x1 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FAC1EN This field controls whether the fault signal detected by the analog comparator1 is enable 0: DISABLE 1: ENABLE 0x2 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FAC2EN This field controls whether the fault signal detected by the analog comparator2 is enable 0: DISABLE 1: ENABLE 0x3 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FEX0EN This field controls whether the fault caused by external fault pin0 is enable. 0: DISABLE 1: ENABLE 0x4 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FEX1EN This field controls whether the fault caused by external fault pin1 is enable. 0: DISABLE 1: ENABLE 0x5 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FEX2EN This field controls whether the fault caused by external fault pin2 is enable. 0: DISABLE 1: ENABLE 0x6 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 TIMA1_GCTL Shadow to active load mask 0x24 32 read-write SHDWLDEN Enables shadow to active load of bufferred registers and register fields. 0x0 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 1 216 0 TIMA1_COUNTERREGS[%s] 0x1800 TIMA1_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x10 read-write TIMA1_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 FB Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0 0x12 0x1 read-write CONT_COUNT Continues counting 0x0 SUSP_COUNT Suspends counting 0x1 FRB Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition. 0x13 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 PLEN Phase Load Enable. This bit allows the timer to have phase load feature. 0x18 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMA1_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x10 read-write 2 4 0,1 TIMA1_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMA1_CC_45[%s] Compare Register 4 to Compare Register 5 0x20 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMA1_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCUPD Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0). 0x12 0x3 read-write Immediately Writes to the CCx_y register is written to the register directly and has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCx_y register are stored in shadow register and transferred to ECCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LD. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. 0x6 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMA1_CCCTL_45[%s] Capture or Compare Control Registers 0x40 32 read-write 0x00000000 0xffffffff 2 4 0,1 TIMA1_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMA1_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 FENACT CCP Output Action on Fault Entry This field describes the resulting action of the signal generator upon detecting a fault. 0x16 0x3 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CCP_HIGHZ CCP output value is tristated 0x4 FEXACT CCP Output Action on Fault Exit This field describes the resulting action of the signal generator upon exiting the fault condition. 0x19 0x3 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CCP_HIGHZ CCP output value is tristated 0x4 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 SWFRCACT_CMPL CCP_CMPL Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1E 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP_CMPL output value is set high 0x1 CCP_LOW CCP_CMPL output value is set low 0x2 2 4 0,1 TIMA1_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMA1_PL Counter Register 0xA0 32 read-write 0x00000000 0xffffffff PHASE Phase Load value 0x0 0x10 read-write TIMA1_DBCTL Dead Band insertion control register 0xA4 32 read-write RISEDELAY Rise Delay The number of TIMCLK periods inserted between the fall of CCPi and the rise of CCPAo. 0x0 0xC FALLDELAY Fall Delay The number of TIMCLK periods inserted between the fall of CCPi and the rise of CCPBo 0x10 0xC M1_ENABLE Dead Band Mode 1 Enable. 0xC 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 TIMA1_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 TIMA1_FCTL Fault Control Register 0xD0 32 read-write FIEN Fault Input Enable This bit enables the input for fault detection. 0x0 0x1 read-write DISABLED Fault Input Disabled 0x0 ENABLED Fault Input Enabled 0x1 FI Fault Input Specifies whether the overall fault condition is dependent on the sensed fault pin. 0x2 0x1 read-write INDEPENDENT Overall Fault condition is not dependent on sensed input. 0x0 DEPENDENT Overall Fault condition is dependent on sensed input. 0x1 TFIM Trigger Fault Input Mask Specifies whether the selected trigger participates as a fault input. If enabled and the trigger asserts, the trigger is treated as a fault. 0x7 0x1 read-write DISABLED Selected trigger does not participate in fault condition generation 0x0 ENABLED Selected trigger participates in fault condition generation 0x1 FL Fault Latch mode Specifies whether the fault condition is latched and configures the latch clear conditions. 0x3 0x2 read-write NO_LATCH Overall fault condition is not dependent on the F bit in RIS 0x0 LATCH_SW_CLR Overall fault condition is dependent on the F bit in RIS 0x1 LATCH_Z_CLR Fault condition is latched. Fault condition is cleared on a zero event if the fault input is 0. 0x2 LATCH_LD_CLR Fault condition is latched. Fault condition is cleared on a load event if the fault input is 0. 0x3 FSENAC0 Specifies whether the analog comparator0 fault sense is high or low active 0x8 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENAC1 Specifies whether the analog comparator1 fault sense is high or low active 0x9 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENAC2 Specifies whether the analog comparator2 fault sense is high or low active 0xA 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENEXT0 Specifies whether the external fault pin0 sense is high or low active 0xB 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENEXT1 Specifies whether the external fault pin1 fault sense is high or low active 0xC 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 FSENEXT2 Specifies whether the external fault pin3 fault sense is high or low active 0xD 0x1 read-write LOWCTIVE Fault Input is active low. 0x0 HIGHACTIVE Fault Input is active high. 0x1 TIMA1_FIFCTL Fault input Filter control register 0xD4 32 read-write FP Filter Period This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x0 0x2 read-write PER_3 Filter Period 3 0x0 PER_5 Filter Period 5 0x1 PER_8 Filter Period 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0x3 0x1 read-write CONSEC_PER Consecutive Periods. The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 VOTING Voting. The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output 0x1 FILTEN Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to go directly to the optional pre-scale filter and then to the edge detect. 0x4 0x1 read-write BYPASS Bypass 0x0 FILTERED Filtered. 0x1 IOMUX IOMUX 1.0 PERIPHERALREGION 0x40428000 0x0 0x2000 registers 251 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250 IOMUX_PINCM[%s] Pin Control Management Register in SECCFG region 0x4 32 read-write 0x00000000 0x7f7fffff PF Peripheral Function selection bits 0x0 0x6 read-write PC Peripheral is Connected 0x7 0x1 read-write UNCONNECTED The output of the peripheral (and its output enable) will not propagate to the IOCELL 0x0 CONNECTED The output latch of the dataflow will be transparent 0x1 WAKESTAT This has the IOPAD WAKEUP signal as status bit. 0xD 0x1 read-only DISABLE wakeup source is NOT from this IOCELL 0x0 ENABLE wakeup source is from this IOCELL 0x1 PIPD Pull Down control selection 0x10 0x1 read-write DISABLE Pull down is disabled. 0x0 ENABLE Pull down is enabled 0x1 PIPU Pull Up control selection 0x11 0x1 read-write DISABLE Pull up is disabled. 0x0 ENABLE Pull up is enabled 0x1 INENA Input Enable Control Selection 0x12 0x1 read-write DISABLE Input enable is disabled. 0x0 ENABLE Input enable is enabled. 0x1 HYSTEN Hysteresis Enable Control Selection 0x13 0x1 read-write DISABLE hysteresis is disabled. 0x0 ENABLE hysteresis is enabled 0x1 DRV Drive strength control selection, for HS IOCELL only 0x14 0x1 read-write DRVVAL0 Drive setting of 0 selected 0x0 DRVVAL1 Drive setting of 1 selected 0x1 HIZ1 High output value will tri-state the output when this bit is enabled 0x19 0x1 read-write DISABLE open-drain is disabled. 0x0 ENABLE open-drain is enabled. 0x1 WUEN Wakeup Enable bit 0x1B 0x1 read-write DISABLE wakeup is disabled. 0x0 ENABLE wakeup is enabled 0x1 WCOMP Wakeup Compare Value bit 0x1C 0x1 read-write MATCH0 Wakeup on a match of 0 0x0 MATCH1 Wakeup on a match of 1 0x1 INV Data inversion selection 0x1A 0x1 read-write DISABLE Data inversion is disabled. 0x0 ENABLE Data inversion is enabled 0x1 DEBUGSS DEBUGSS 1.0 DSSM 0x400C7000 0x0 0x1F00 registers DEBUGSS_IIDX Interrupt index 0x1020 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 NO_INTR No pending interrupt request 0x0 TXIFG TX interrupt 0x1 RXIFG RX interrupt 0x2 PWRUP Power-up interrupt. A debug session has started. 0x3 PWRDWN Power-up interrupt. A debug session has started. 0x4 DEBUGSS_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 TXIFG Masks TXIFG in MIS register 0x0 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 RXIFG Masks RXIFG in MIS register 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 PWRUPIFG Masks PWRUPIFG in MIS register 0x2 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 PWRDWNIFG Masks PWRDWNIFG in MIS register 0x3 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 DEBUGSS_RIS Raw interrupt status 0x1030 32 read-only 0x00000000 TXIFG Raw interrupt status for TXIFG 0x0 0x1 CLR TXIFG did not occur 0x0 SET TXIFG occurred 0x1 RXIFG Raw interrupt status for RXIFG 0x1 0x1 CLR RXIFG did not occur 0x0 SET RXIFG occurred 0x1 PWRUPIFG Raw interrupt status for PWRUPIFG 0x2 0x1 CLR PWRUPIFG did not occur 0x0 SET PWRUPIFG occurred 0x1 PWRDWNIFG Raw interrupt status for PWRDWNIFG 0x3 0x1 CLR PWRUPIFG did not occur 0x0 SET PWRUPIFG occurred 0x1 DEBUGSS_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 TXIFG Masked interrupt status for TXIFG 0x0 0x1 CLR TXIFG did not request an interrupt service routine 0x0 SET TXIFG requests an interrupt service routine 0x1 RXIFG Masked interrupt status for RXIFG 0x1 0x1 CLR RXIFG did not request an interrupt service routine 0x0 SET RXIFG requests an interrupt service routine 0x1 PWRUPIFG Masked interrupt status for PWRUPIFG 0x2 0x1 CLR PWRUPIFG did not request an interrupt service routine 0x0 SET PWRUPIFG requests an interrupt service routine 0x1 PWRDWNIFG Masked interrupt status for PWRDWNIFG 0x3 0x1 CLR PWRUPIFG did not request an interrupt service routine 0x0 SET PWRUPIFG requests an interrupt service routine 0x1 DEBUGSS_ISET Interrupt set 0x1040 32 write-only 0x00000000 TXIFG Sets TXIFG in RIS register 0x0 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to TXIFG is set 0x1 RXIFG Sets RXIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to RXIFG is set 0x1 PWRUPIFG Sets PWRUPIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to PWRUPIFG is set 0x1 PWRDWNIFG Sets PWRDWNIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 SET RIS bit corresponding to PWRUPIFG is set 0x1 DEBUGSS_ICLR Interrupt clear 0x1048 32 write-only 0x00000000 TXIFG Clears TXIFG in RIS register 0x0 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to TXIFG is cleared 0x1 RXIFG Clears RXIFG in RIS register 0x1 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to RXIFG is cleared 0x1 PWRUPIFG Clears PWRUPIFG in RIS register 0x2 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to PWRUPIFG is cleared 0x1 PWRDWNIFG Clears PWRDWNIFG in RIS register 0x3 0x1 NO_EFFECT Writing a 0 has no effect 0x0 CLR RIS bit corresponding to PWRUPIFG is cleared 0x1 DEBUGSS_EVT_MODE Event Mode 0x10E0 32 read-only INT0_CFG Event line mode select for peripheral events 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 DEBUGSS_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 DEBUGSS_TXD Transmit data register 0x1100 32 read-only 0x00000000 DEBUGSS_TXCTL Transmit control register 0x1104 32 read-only 0x00000000 TRANSMIT Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD. A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field. 0x0 0x1 read-only EMPTY TXD is empty 0x0 FULL TXD is full 0x1 TRANSMIT_FLAGS Generic TX flags that can be set by external debug tool. Functionality is defined by SW. 0x1 0x1F read-only DEBUGSS_RXD Receive data register 0x1108 32 read-write 0x00000000 DEBUGSS_RXCTL Receive control register 0x110C 32 read-write 0x00000000 RECEIVE Indicates SW write to the DSSM.RXD register. A read of the DSSM.RXD register by SWD Access Port will clear the RX field. 0x0 0x1 read-only EMPTY RXD empty 0x0 FULL RXD full 0x1 RECEIVE_FLAGS Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW. 0x1 0x7 read-write DEBUGSS_SPECIAL_AUTH Special enable authorization register 0x1200 32 read-only 0x00000013 SECAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP. 0x0 0x1 read-only DISABLE Disable SEC-AP 0x0 ENABLE Enable SEC-AP 0x1 SWDPORTEN When asserted, the SW-DP functions normally. When deasserted, the SW-DP effectively disables all external debug access. 0x1 0x1 read-only DISABLE Disable SWD port 0x0 ENABLE Enable SWD port 0x1 DFTAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. 0x2 0x1 read-only DISABLE Disable DFT-TAP 0x0 ENABLE Enable DFT-TAP 0x1 ETAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. 0x3 0x1 read-only DISABLE Disable ET+ -AP 0x0 ENABLE Enable ET+ -AP 0x1 CFGAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP. 0x4 0x1 read-only DISABLE Disable CFG-AP 0x0 ENABLE Enable CFG-AP 0x1 AHBAPEN Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation. 0x5 0x1 read-only DISABLE Disable AHB-AP 0x0 ENABLE Enable AHB-AP 0x1 PWRAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. 0x6 0x1 read-only DISABLE Disable PWR-AP 0x0 ENABLE Enable PWR-AP 0x1 DEBUGSS_APP_AUTH Application CPU0 authorization register 0x1210 32 read-only 0x00000000 DBGEN Controls invasive debug enable. 0x0 0x1 read-only DISABLE Invasive debug disabled 0x0 ENABLE Invasive debug enabled 0x1 NIDEN Controls non-invasive debug enable. 0x1 0x1 read-only DISABLE Non-invasive debug disabled 0x0 ENABLE Non-invasive debug enabled 0x1 SPIDEN Secure invasive debug enable. 0x2 0x1 read-only DISABLE Invasive debug disabled 0x0 ENABLE Invasive debug enabled 0x1 SPNIDEN Secure non-invasive debug enable. 0x3 0x1 read-only DISABLE Invasive debug disabled 0x0 ENABLE Invasive debug enabled 0x1 CANFD0 CANFD 1.0 PERIPHERALREGION 0x40508000 0x0 0x8000 registers CANFD0_PWREN Power enable 0x6800 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 CANFD0_RSTCTL Reset Control 0x6804 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 CANFD0_STAT Status Register 0x6814 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 1 252 0 CANFD0_MCAN[%s] 0x7000 CANFD0_MCAN_CREL MCAN Core Release Register 0x0 32 read-only 0x32380608 0xffffffff DAY Time Stamp Day. Two digits, BCD-coded. 0x0 0x8 read-only MON Time Stamp Month. Two digits, BCD-coded. 0x8 0x8 read-only YEAR Time Stamp Year. One digit, BCD-coded. 0x10 0x4 read-only SUBSTEP Sub-Step of Core Release. One digit, BCD-coded. 0x14 0x4 read-only STEP Step of Core Release. One digit, BCD-coded. 0x18 0x4 read-only REL Core Release. One digit, BCD-coded. 0x1C 0x4 read-only CANFD0_MCAN_ENDN MCAN Endian Register 0x4 32 read-only 0x87654321 0xffffffff CANFD0_MCAN_DBTP MCAN Data Bit Timing and Prescaler Register 0xC 32 read-write 0x00000a33 0xffffffff DSJW Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x4 read-write DTSEG2 Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x4 0x4 read-write DTSEG1 Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x5 read-write DBRP Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x5 read-write TDC Transmitter Delay Compensation 0 Transmitter Delay Compensation disabled 1 Transmitter Delay Compensation enabled 0x17 0x1 read-write CANFD0_MCAN_TEST MCAN Test Register 0x10 32 read-write 0x00000000 0xffffff7f LBCK Loop Back Mode. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x4 0x1 read-write DISABLE Reset value, Loop Back Mode is disabled 0x0 ENABLE Loop Back Mode is enabled 0x1 TX Control of Transmit Pin 00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at CAN TX pin 10 Dominant ('0') level at CAN TX pin 11 Recessive ('1') at CAN TX pin Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x5 0x2 read-write RX Receive Pin. Monitors the actual value of the CAN receive pin. 0x7 0x1 read-only DOMINANT The CAN bus is dominant (CAN RX pin = '0') 0x0 RECESSIVE The CAN bus is recessive (CAN RX pin = '1') 0x1 CANFD0_MCAN_RWD MCAN RAM Watchdog 0x14 32 read-write 0x00000000 0xffffffff WDC Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of &quot;00&quot; the counter is disabled. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x8 read-write WDV Watchdog Value. Acutal Message RAM Watchdog Counter Value. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock. 0x8 0x8 read-only CANFD0_MCAN_CCCR MCAN CC Control Register 0x18 32 read-write 0x00000001 0xffffffff INIT Initialization 0 Normal Operation 1 Initialization is started Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value. 0x0 0x1 read-write CCE Configuration Change Enable 0 The CPU has no write access to the protected configuration registers 1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1 0x1 read-write ASM Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time. 0 Normal CAN operation 1 Restricted Operation Mode active Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0x1 read-write CSA Clock Stop Acknowledge 0 No clock stop acknowledged 1 MCAN may be set in power down by stopping the Host and CAN clocks 0x3 0x1 read-only CSR Clock Stop Request 0 No clock stop is requested 1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. 0x4 0x1 read-write MON Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time. 0 Bus Monitoring Mode is disabled 1 Bus Monitoring Mode is enabled Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x5 0x1 read-write DAR Disable Automatic Retransmission 0 Automatic retransmission of messages not transmitted successfully enabled 1 Automatic retransmission disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x6 0x1 read-write TEST Test Mode Enable 0 Normal operation, register TEST holds reset values 1 Test Mode, write access to register TEST enabled Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x7 0x1 read-write FDOE Flexible Datarate Operation Enable 0 FD operation disabled 1 FD operation enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x1 read-write BRSE Bit Rate Switch Enable 0 Bit rate switching for transmissions disabled 1 Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x9 0x1 read-write PXHD Protocol Exception Handling Disable 0 Protocol exception handling enabled 1 Protocol exception handling disabled Note: When protocol exception handling is disabled, the MCAN will transmit an error frame when it detects a protocol exception condition. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0xC 0x1 read-write EFBI Edge Filtering during Bus Integration 0 Edge filtering disabled 1 Two consecutive dominant tq required to detect an edge for hard synchronization Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0xD 0x1 read-write TXP Transmit Pause. If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame. 0 Transmit pause disabled 1 Transmit pause enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0xE 0x1 read-write NISO Non ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0 CAN FD frame format according to ISO 11898-1:2015 1 CAN FD frame format according to Bosch CAN FD Specification V1.0 0xF 0x1 read-write CANFD0_MCAN_NBTP MCAN Nominal Bit Timing and Prescaler Register 0x1C 32 read-write 0x06000a03 0xffffffff NTSEG2 Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x7 read-write NTSEG1 Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x8 read-write NBRP Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x9 read-write NSJW Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x19 0x7 read-write CANFD0_MCAN_TSCC MCAN Timestamp Counter Configuration 0x20 32 read-write 0x00000000 0xffffffff TSS Timestamp Select 00 Timestamp counter value always 0x0000 01 Timestamp counter value incremented according to TCP 10 External timestamp counter value used 11 Same as &quot;00&quot; Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x2 read-write TCP Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With CAN FD an external counter is required for timestamp generation (TSS = &quot;10&quot;). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x4 read-write CANFD0_MCAN_TSCV MCAN Timestamp Counter Value 0x24 32 read-write 0x00000000 0xffffffff TSC Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = &quot;01&quot;, the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = &quot;10&quot;, TSC reflects the External Timestamp Counter value, and a write access has no impact. Note: A &quot;wrap around&quot; is a change of the Timestamp Counter value from non-zero to zero not caused by write access to MCAN_TSCV. 0x0 0x10 read-write CANFD0_MCAN_TOCC MCAN Timeout Counter Configuration 0x28 32 read-write 0xffff0000 0xffffffff ETOC Enable Timeout Counter 0 Timeout Counter disabled 1 Timeout Counter enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x1 read-write TOS Timeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00 Continuous operation 01 Timeout controlled by Tx Event FIFO 10 Timeout controlled by Rx FIFO 0 11 Timeout controlled by Rx FIFO 1 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1 0x2 read-write TOP Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x10 read-write CANFD0_MCAN_TOCV MCAN Timeout Counter Value 0x2C 32 read-write 0x0000ffff 0xffffffff TOC Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. 0x0 0x10 read-write CANFD0_MCAN_ECR MCAN Error Counter Register 0x40 32 read-only 0x00000000 0xffffffff TEC Transmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0x0 0x8 read-only REC Receive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0x8 0x7 read-only RP Receive Error Passive 0 The Receive Error Counter is below the error passive level of 128 1 The Receive Error Counter has reached the error passive level of 128 0xF 0x1 read-only CEL CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0x10 0x8 read-only CANFD0_MCAN_PSR MCAN Protocol Status Register 0x44 32 read-only 0x00000707 0xffffffff LEC Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 0 No Error: No error occurred since LEC has been reset by successful reception or transmission. 1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2 Form Error: A fixed format part of a received frame has the wrong format. 3 AckError: The message transmitted by the MCAN was not acknowledged by another node. 4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. 0x0 0x3 read-only ACT Node Activity. Monitors the module's CAN communication state. 00 Synchronizing - node is synchronizing on CAN communication 01 Idle - node is neither receiver nor transmitter 10 Receiver - node is operating as receiver 11 Transmitter - node is operating as transmitter Note: ACT is set to &quot;00&quot; by a Protocol Exception Event. 0x3 0x2 read-only EP Error Passive 0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1 The M_CAN is in the Error_Passive state 0x5 0x1 read-only EW Warning Status 0 Both error counters are below the Error_Warning limit of 96 1 At least one of error counter has reached the Error_Warning limit of 96 0x6 0x1 read-only BO Bus_Off Status 0 The M_CAN is not Bus_Off 1 The M_CAN is in Bus_Off state 0x7 0x1 read-only DLEC Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. 0x8 0x3 read-only RESI ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its ESI flag set 1 Last received CAN FD message had its ESI flag set 0xB 0x1 read-only RBRS BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its BRS flag set 1 Last received CAN FD message had its BRS flag set 0xC 0x1 read-only RFDF Received a CAN FD Message. This bit is set independent of acceptance filtering. 0 Since this bit was reset by the CPU, no CAN FD message has been received 1 Message in CAN FD format with FDF flag set has been received 0xD 0x1 read-only PXE Protocol Exception Event 0 No protocol exception event occurred since last read access 1 Protocol exception event occurred 0xE 0x1 read-only TDCV Transmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. 0x10 0x7 read-only CANFD0_MCAN_TDCR MCAN Transmitter Delay Compensation Register 0x48 32 read-write 0x00000000 0xffffffff TDCF Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x7 read-write TDCO Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x7 read-write CANFD0_MCAN_IR MCAN Interrupt Register 0x50 32 read-write 0x80000000 0xffffffff RF0N Rx FIFO 0 New Message 0 No new message written to Rx FIFO 0 1 New message written to Rx FIFO 0 0x0 0x1 read-write RF0W Rx FIFO 0 Watermark Reached 0 Rx FIFO 0 fill level below watermark 1 Rx FIFO 0 fill level reached watermark 0x1 0x1 read-write RF0F Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full 0x2 0x1 read-write RF0L Rx FIFO 0 Message Lost 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero 0x3 0x1 read-write RF1N Rx FIFO 1 New Message 0 No new message written to Rx FIFO 1 1 New message written to Rx FIFO 1 0x4 0x1 read-write RF1W Rx FIFO 1 Watermark Reached 0 Rx FIFO 1 fill level below watermark 1 Rx FIFO 1 fill level reached watermark 0x5 0x1 read-write RF1F Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full 0x6 0x1 read-write RF1L Rx FIFO 1 Message Lost 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero 0x7 0x1 read-write HPM High Priority Message 0 No high priority message received 1 High priority message received 0x8 0x1 read-write TC Transmission Completed 0 No transmission completed 1 Transmission completed 0x9 0x1 read-write TCF Transmission Cancellation Finished 0 No transmission cancellation finished 1 Transmission cancellation finished 0xA 0x1 read-write TFE Tx FIFO Empty 0 Tx FIFO non-empty 1 Tx FIFO empty 0xB 0x1 read-write TEFN Tx Event FIFO New Entry 0 Tx Event FIFO unchanged 1 Tx Handler wrote Tx Event FIFO element 0xC 0x1 read-write TEFW Tx Event FIFO Watermark Reached 0 Tx Event FIFO fill level below watermark 1 Tx Event FIFO fill level reached watermark 0xD 0x1 read-write TEFF Tx Event FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full 0xE 0x1 read-write TEFL Tx Event FIFO Element Lost 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero 0xF 0x1 read-write TSW Timestamp Wraparound 0 No timestamp counter wrap-around 1 Timestamp counter wrapped around 0x10 0x1 read-write MRAF Message RAM Access Failure. The flag is set, when the Rx Handler: - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. - was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0 No Message RAM access failure occurred 1 Message RAM access failure occurred 0x11 0x1 read-write TOO Timeout Occurred 0 No timeout 1 Timeout reached 0x12 0x1 read-write DRX Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0 No Rx Buffer updated 1 At least one received message stored into an Rx Buffer 0x13 0x1 read-write BEU Bit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. 0 No bit error detected when reading from Message RAM 1 Bit error detected, uncorrected (e.g. parity logic) 0x15 0x1 read-write ELO Error Logging Overflow 0 CAN Error Logging Counter did not overflow 1 Overflow of CAN Error Logging Counter occurred 0x16 0x1 read-write EP Error Passive 0 Error_Passive status unchanged 1 Error_Passive status changed 0x17 0x1 read-write EW Warning Status 0 Error_Warning status unchanged 1 Error_Warning status changed 0x18 0x1 read-write BO Bus_Off Status 0 Bus_Off status unchanged 1 Bus_Off status changed 0x19 0x1 read-write WDI Watchdog Interrupt 0 No Message RAM Watchdog event occurred 1 Message RAM Watchdog event due to missing READY 0x1A 0x1 read-write PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0 No protocol error in arbitration phase 1 Protocol error in arbitration phase detected (PSR.LEC ? 0,7) 0x1B 0x1 read-write PED Protocol Error in Data Phase (Data Bit Time is used) 0 No protocol error in data phase 1 Protocol error in data phase detected (PSR.DLEC ? 0,7) 0x1C 0x1 read-write ARA Access to Reserved Address 0 No access to reserved address occurred 1 Access to reserved address occurred 0x1D 0x1 read-write CANFD0_MCAN_IE MCAN Interrupt Enable 0x54 32 read-write 0x00000000 0xffffffff RF0NE Rx FIFO 0 New Message Enable 0x0 0x1 read-write RF0WE Rx FIFO 0 Watermark Reached Enable 0x1 0x1 read-write RF0FE Rx FIFO 0 Full Enable 0x2 0x1 read-write RF0LE Rx FIFO 0 Message Lost Enable 0x3 0x1 read-write RF1NE Rx FIFO 1 New Message Enable 0x4 0x1 read-write RF1WE Rx FIFO 1 Watermark Reached Enable 0x5 0x1 read-write RF1FE Rx FIFO 1 Full Enable 0x6 0x1 read-write RF1LE Rx FIFO 1 Message Lost Enable 0x7 0x1 read-write HPME High Priority Message Enable 0x8 0x1 read-write TCE Transmission Completed Enable 0x9 0x1 read-write TCFE Transmission Cancellation Finished Enable 0xA 0x1 read-write TFEE Tx FIFO Empty Enable 0xB 0x1 read-write TEFNE Tx Event FIFO New Entry Enable 0xC 0x1 read-write TEFWE Tx Event FIFO Watermark Reached Enable 0xD 0x1 read-write TEFFE Tx Event FIFO Full Enable 0xE 0x1 read-write TEFLE Tx Event FIFO Element Lost Enable 0xF 0x1 read-write TSWE Timestamp Wraparound Enable 0x10 0x1 read-write MRAFE Message RAM Access Failure Enable 0x11 0x1 read-write TOOE Timeout Occurred Enable 0x12 0x1 read-write DRXE Message Stored to Dedicated Rx Buffer Enable 0x13 0x1 read-write BECE Bit Error Corrected Enable A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave this bit cleared to '0'. 0x14 0x1 read-write BEUE Bit Error Uncorrected Enable 0x15 0x1 read-write ELOE Error Logging Overflow Enable 0x16 0x1 read-write EPE Error Passive Enable 0x17 0x1 read-write EWE Warning Status Enable 0x18 0x1 read-write BOE Bus_Off Status Enable 0x19 0x1 read-write WDIE Watchdog Interrupt Enable 0x1A 0x1 read-write PEAE Protocol Error in Arbitration Phase Enable 0x1B 0x1 read-write PEDE Protocol Error in Data Phase Enable 0x1C 0x1 read-write ARAE Access to Reserved Address Enable 0x1D 0x1 read-write CANFD0_MCAN_ILS MCAN Interrupt Line Select 0x58 32 read-write 0x00000000 0xffffffff RF0NL Rx FIFO 0 New Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x0 0x1 read-write RF0WL Rx FIFO 0 Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1 0x1 read-write RF0FL Rx FIFO 0 Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x2 0x1 read-write RF0LL Rx FIFO 0 Message Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x3 0x1 read-write RF1NL Rx FIFO 1 New Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x4 0x1 read-write RF1WL Rx FIFO 1 Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x5 0x1 read-write RF1FL Rx FIFO 1 Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x6 0x1 read-write RF1LL Rx FIFO 1 Message Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x7 0x1 read-write HPML High Priority Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x8 0x1 read-write TCL Transmission Completed Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x9 0x1 read-write TCFL Transmission Cancellation Finished Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xA 0x1 read-write TFEL Tx FIFO Empty Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xB 0x1 read-write TEFNL Tx Event FIFO New Entry Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xC 0x1 read-write TEFWL Tx Event FIFO Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xD 0x1 read-write TEFFL Tx Event FIFO Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xE 0x1 read-write TEFLL Tx Event FIFO Element Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xF 0x1 read-write TSWL Timestamp Wraparound Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x10 0x1 read-write MRAFL Message RAM Access Failure Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x11 0x1 read-write TOOL Timeout Occurred Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x12 0x1 read-write DRXL Message Stored to Dedicated Rx Buffer Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x13 0x1 read-write BECL Bit Error Corrected Line A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave the MCAN_IE.BECE bit cleared to '0' (disabled), thereby relegating this bit to not applicable. 0x14 0x1 read-write BEUL Bit Error Uncorrected Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x15 0x1 read-write ELOL Error Logging Overflow Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x16 0x1 read-write EPL Error Passive Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x17 0x1 read-write EWL Warning Status Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x18 0x1 read-write BOL Bus_Off Status Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x19 0x1 read-write WDIL Watchdog Interrupt Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1A 0x1 read-write PEAL Protocol Error in Arbitration Phase Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1B 0x1 read-write PEDL Protocol Error in Data Phase Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1C 0x1 read-write ARAL Access to Reserved Address Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1D 0x1 read-write CANFD0_MCAN_ILE MCAN Interrupt Line Enable 0x5C 32 read-write 0x00000000 0xffffffff EINT0 Enable Interrupt Line 0 0 Interrupt Line 0 is disabled 1 Interrupt Line 0 is enabled 0x0 0x1 read-write EINT1 Enable Interrupt Line 1 0 Interrupt Line 1 is disabled 1 Interrupt Line 1 is enabled 0x1 0x1 read-write CANFD0_MCAN_GFC MCAN Global Filter Configuration 0x80 32 read-write 0x00000000 0xffffffff RRFE Reject Remote Frames Extended 0 Filter remote frames with 29-bit extended IDs 1 Reject all remote frames with 29-bit extended IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x1 read-write RRFS Reject Remote Frames Standard 0 Filter remote frames with 11-bit standard IDs 1 Reject all remote frames with 11-bit standard IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1 0x1 read-write ANFE Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0x2 read-write ANFS Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x4 0x2 read-write CANFD0_MCAN_SIDFC MCAN Standard ID Filter Configuration 0x84 32 read-write 0x00000000 0xffffffff FLSSA Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address). 0x2 0xE read-write LSS List Size Standard 0 No standard Message ID filter 1-128 Number of standard Message ID filter elements >128 Values greater than 128 are interpreted as 128 0x10 0x8 read-write CANFD0_MCAN_XIDFC MCAN Extended ID Filter Configuration 0x88 32 read-write 0x00000000 0xffffffff FLESA List Size Extended 0 No extended Message ID filter 1-64 Number of extended Message ID filter elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0xE read-write LSE Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x7 read-write CANFD0_MCAN_XIDAM MCAN Extended ID and Mask 0x90 32 read-write 0x1fffffff 0xffffffff EIDM Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x1D read-write CANFD0_MCAN_HPMS MCAN High Priority Message Status 0x94 32 read-only 0x00000000 0xffffffff BIDX Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'. 0x0 0x6 read-only MSI Message Storage Indicator 00 No FIFO selected 01 FIFO message lost 10 Message stored in FIFO 0 11 Message stored in FIFO 1 0x6 0x2 read-only FIDX Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. 0x8 0x7 read-only FLST Filter List. Indicates the filter list of the matching filter element. 0 Standard Filter List 1 Extended Filter List 0xF 0x1 read-only CANFD0_MCAN_NDAT1 MCAN New Data 1 0x98 32 read-write 0x00000000 0xffffffff ND0 New Data RX Buffer 0 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x0 0x1 read-write ND1 New Data RX Buffer 1 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1 0x1 read-write ND2 New Data RX Buffer 2 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x2 0x1 read-write ND3 New Data RX Buffer 3 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x3 0x1 read-write ND4 New Data RX Buffer 4 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x4 0x1 read-write ND5 New Data RX Buffer 5 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x5 0x1 read-write ND6 New Data RX Buffer 6 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x6 0x1 read-write ND7 New Data RX Buffer 7 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x7 0x1 read-write ND8 New Data RX Buffer 8 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x8 0x1 read-write ND9 New Data RX Buffer 9 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x9 0x1 read-write ND10 New Data RX Buffer 10 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xA 0x1 read-write ND11 New Data RX Buffer 11 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xB 0x1 read-write ND12 New Data RX Buffer 12 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xC 0x1 read-write ND13 New Data RX Buffer 13 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xD 0x1 read-write ND14 New Data RX Buffer 14 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xE 0x1 read-write ND15 New Data RX Buffer 15 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xF 0x1 read-write ND16 New Data RX Buffer 16 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x10 0x1 read-write ND17 New Data RX Buffer 17 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x11 0x1 read-write ND18 New Data RX Buffer 18 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x12 0x1 read-write ND19 New Data RX Buffer 19 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x13 0x1 read-write ND20 New Data RX Buffer 20 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x14 0x1 read-write ND21 New Data RX Buffer 21 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x15 0x1 read-write ND22 New Data RX Buffer 22 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x16 0x1 read-write ND23 New Data RX Buffer 23 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x17 0x1 read-write ND24 New Data RX Buffer 24 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x18 0x1 read-write ND25 New Data RX Buffer 25 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x19 0x1 read-write ND26 New Data RX Buffer 26 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1A 0x1 read-write ND27 New Data RX Buffer 27 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1B 0x1 read-write ND28 New Data RX Buffer 28 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1C 0x1 read-write ND29 New Data RX Buffer 29 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1D 0x1 read-write ND30 New Data RX Buffer 30 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1E 0x1 read-write ND31 New Data RX Buffer 31 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1F 0x1 read-write CANFD0_MCAN_NDAT2 MCAN New Data 2 0x9C 32 read-write 0x00000000 0xffffffff ND32 New Data RX Buffer 32 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x0 0x1 read-write ND33 New Data RX Buffer 33 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1 0x1 read-write ND34 New Data RX Buffer 34 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x2 0x1 read-write ND35 New Data RX Buffer 35 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x3 0x1 read-write ND36 New Data RX Buffer 36 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x4 0x1 read-write ND37 New Data RX Buffer 37 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x5 0x1 read-write ND38 New Data RX Buffer 38 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x6 0x1 read-write ND39 New Data RX Buffer 39 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x7 0x1 read-write ND40 New Data RX Buffer 40 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x8 0x1 read-write ND41 New Data RX Buffer 41 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x9 0x1 read-write ND42 New Data RX Buffer 42 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xA 0x1 read-write ND43 New Data RX Buffer 43 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xB 0x1 read-write ND44 New Data RX Buffer 44 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xC 0x1 read-write ND45 New Data RX Buffer 45 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xD 0x1 read-write ND46 New Data RX Buffer 46 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xE 0x1 read-write ND47 New Data RX Buffer 47 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xF 0x1 read-write ND48 New Data RX Buffer 48 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x10 0x1 read-write ND49 New Data RX Buffer 49 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x11 0x1 read-write ND50 New Data RX Buffer 50 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x12 0x1 read-write ND51 New Data RX Buffer 51 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x13 0x1 read-write ND52 New Data RX Buffer 52 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x14 0x1 read-write ND53 New Data RX Buffer 53 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x15 0x1 read-write ND54 New Data RX Buffer 54 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x16 0x1 read-write ND55 New Data RX Buffer 55 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x17 0x1 read-write ND56 New Data RX Buffer 56 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x18 0x1 read-write ND57 New Data RX Buffer 57 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x19 0x1 read-write ND58 New Data RX Buffer 58 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1A 0x1 read-write ND59 New Data RX Buffer 59 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1B 0x1 read-write ND60 New Data RX Buffer 60 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1C 0x1 read-write ND61 New Data RX Buffer 61 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1D 0x1 read-write ND62 New Data RX Buffer 62 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1E 0x1 read-write ND63 New Data RX Buffer 63 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1F 0x1 read-write CANFD0_MCAN_RXF0C MCAN Rx FIFO 0 Configuration 0xA0 32 read-write 0x00000000 0xffffffff F0SA Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0xE read-write F0S Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1. 0 No Rx FIFO 0 1-64 Number of Rx FIFO 0 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x7 read-write F0WM Rx FIFO 0 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x18 0x7 read-write F0OM FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode. 0 FIFO 0 blocking mode 1 FIFO 0 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1F 0x1 read-write CANFD0_MCAN_RXF0S MCAN Rx FIFO 0 Status 0xA4 32 read-only 0x00000000 0xffffffff F0FL Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64. 0x0 0x7 read-only F0GI Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63. 0x8 0x6 read-only F0PI Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63. 0x10 0x6 read-only F0F Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full 0x18 0x1 read-only RF0L Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag. 0x19 0x1 read-only CANFD0_MCAN_RXF0A MCAN Rx FIFO 0 Acknowledge 0xA8 32 read-write 0x00000000 0xffffffff F0AI Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. 0x0 0x6 read-write CANFD0_MCAN_RXBC MCAN Rx Buffer Configuration 0xAC 32 read-write 0x00000000 0xffffffff RBSA Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +I466 0x2 0xE read-write CANFD0_MCAN_RXF1C MCAN Rx FIFO 1 Configuration 0xB0 32 read-write 0x00000000 0xffffffff F1SA Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address). 0x2 0xE read-write F1S Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1. 0 No Rx FIFO 1 1-64 Number of Rx FIFO 1 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x7 read-write F1WM Rx FIFO 1 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x18 0x7 read-write F1OM FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode. 0 FIFO 1 blocking mode 1 FIFO 1 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1F 0x1 read-write CANFD0_MCAN_RXF1S MCAN Rx FIFO 1 Status 0xB4 32 read-only 0x00000000 0xffffffff F1FL Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64. 0x0 0x7 read-only F1GI Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63. 0x8 0x6 read-only F1PI Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63. 0x10 0x6 read-only F1F Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full 0x18 0x1 read-only RF1L Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag. 0x19 0x1 read-only DMS Debug Message Status 00 Idle state, wait for reception of debug messages 01 Debug message A received 10 Debug messages A, B received 11 Debug messages A, B, C received 0x1E 0x2 read-only CANFD0_MCAN_RXF1A MCAN Rx FIFO 1 Acknowledge 0xB8 32 read-write 0x00000000 0xffffffff F1AI Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. 0x0 0x6 read-write CANFD0_MCAN_RXESC MCAN Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write 0x00000000 0xffffffff F0DS Rx FIFO 0 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x3 read-write F1DS Rx FIFO 1 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x4 0x3 read-write RBDS Rx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x3 read-write CANFD0_MCAN_TXBC MCAN Tx Buffer Configuration 0xC0 32 read-write 0x00000000 0xffffffff TBSA Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0xE read-write NDTB Number of Dedicated Transmit Buffers 0 No Dedicated Tx Buffers 1-32 Number of Dedicated Tx Buffers >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x6 read-write TFQS Transmit FIFO/Queue Size 0 No Tx FIFO/Queue 1-32 Number of Tx Buffers used for Tx FIFO/Queue >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x18 0x6 read-write TFQM Tx FIFO/Queue Mode 0 Tx FIFO operation 1 Tx Queue operation Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1E 0x1 read-write CANFD0_MCAN_TXFQS MCAN Tx FIFO / Queue Status 0xC4 32 read-only 0x00000000 0xffffffff TFFL Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1'). 0x0 0x6 read-only TFGI Tx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1'). Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. 0x8 0x5 read-only TFQP Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31. Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. 0x10 0x5 read-only TFQF Tx FIFO/Queue Full 0 Tx FIFO/Queue not full 1 Tx FIFO/Queue full 0x15 0x1 read-only CANFD0_MCAN_TXESC MCAN Tx Buffer Element Size Configuration 0xC8 32 read-write 0x00000000 0xffffffff TBDS Tx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as &quot;0xCC&quot; (padding bytes). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x3 read-write CANFD0_MCAN_TXBRP MCAN Tx Buffer Request Pending 0xCC 32 read-only 0x00000000 0xffffffff TRP0 Transmission Request Pending 0. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF - after successful transmission together with the corresponding TXBTO bit - when the transmission has not yet been started at the point of cancellation - when the transmission has been aborted due to lost arbitration - when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 No transmission request pending 1 Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. 0x0 0x1 read-only TRP1 Transmission Request Pending 1. See description for bit 0. 0x1 0x1 read-only TRP2 Transmission Request Pending 2. See description for bit 0. 0x2 0x1 read-only TRP3 Transmission Request Pending 3. See description for bit 0. 0x3 0x1 read-only TRP4 Transmission Request Pending 4. See description for bit 0. 0x4 0x1 read-only TRP5 Transmission Request Pending 5. See description for bit 0. 0x5 0x1 read-only TRP6 Transmission Request Pending 6. See description for bit 0. 0x6 0x1 read-only TRP7 Transmission Request Pending 7. See description for bit 0. 0x7 0x1 read-only TRP8 Transmission Request Pending 8. See description for bit 0. 0x8 0x1 read-only TRP9 Transmission Request Pending 9. See description for bit 0. 0x9 0x1 read-only TRP10 Transmission Request Pending 10. See description for bit 0. 0xA 0x1 read-only TRP11 Transmission Request Pending 11. See description for bit 0. 0xB 0x1 read-only TRP12 Transmission Request Pending 12. See description for bit 0. 0xC 0x1 read-only TRP13 Transmission Request Pending 13. See description for bit 0. 0xD 0x1 read-only TRP14 Transmission Request Pending 14. See description for bit 0. 0xE 0x1 read-only TRP15 Transmission Request Pending 15. See description for bit 0. 0xF 0x1 read-only TRP16 Transmission Request Pending 16. See description for bit 0. 0x10 0x1 read-only TRP17 Transmission Request Pending 17. See description for bit 0. 0x11 0x1 read-only TRP18 Transmission Request Pending 18. See description for bit 0. 0x12 0x1 read-only TRP19 Transmission Request Pending 19. See description for bit 0. 0x13 0x1 read-only TRP20 Transmission Request Pending 20. See description for bit 0. 0x14 0x1 read-only TRP21 Transmission Request Pending 21. See description for bit 0. 0x15 0x1 read-only TRP22 Transmission Request Pending 22. See description for bit 0. 0x16 0x1 read-only TRP23 Transmission Request Pending 23. See description for bit 0. 0x17 0x1 read-only TRP24 Transmission Request Pending 24. See description for bit 0. 0x18 0x1 read-only TRP25 Transmission Request Pending 25. See description for bit 0. 0x19 0x1 read-only TRP26 Transmission Request Pending 26. See description for bit 0. 0x1A 0x1 read-only TRP27 Transmission Request Pending 27. See description for bit 0. 0x1B 0x1 read-only TRP28 Transmission Request Pending 28. See description for bit 0. 0x1C 0x1 read-only TRP29 Transmission Request Pending 29. See description for bit 0. 0x1D 0x1 read-only TRP30 Transmission Request Pending 30. See description for bit 0. 0x1E 0x1 read-only TRP31 Transmission Request Pending 31. See description for bit 0. 0x1F 0x1 read-only CANFD0_MCAN_TXBAR MCAN Tx Buffer Add Request 0xD0 32 read-write 0x00000000 0xffffffff AR0 Add Request 0. Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 No transmission request added 1 Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. Qualified Write is possible only with CCCR.CCE='0' 0x0 0x1 read-write AR1 Add Request 1. See description for bit 0. 0x1 0x1 read-write AR2 Add Request 2. See description for bit 0. 0x2 0x1 read-write AR3 Add Request 3. See description for bit 0. 0x3 0x1 read-write AR4 Add Request 4. See description for bit 0. 0x4 0x1 read-write AR5 Add Request 5. See description for bit 0. 0x5 0x1 read-write AR6 Add Request 6. See description for bit 0. 0x6 0x1 read-write AR7 Add Request 7. See description for bit 0. 0x7 0x1 read-write AR8 Add Request 8. See description for bit 0. 0x8 0x1 read-write AR9 Add Request 9. See description for bit 0. 0x9 0x1 read-write AR10 Add Request 10. See description for bit 0. 0xA 0x1 read-write AR11 Add Request 11. See description for bit 0. 0xB 0x1 read-write AR12 Add Request 12. See description for bit 0. 0xC 0x1 read-write AR13 Add Request 13. See description for bit 0. 0xD 0x1 read-write AR14 Add Request 14. See description for bit 0. 0xE 0x1 read-write AR15 Add Request 15. See description for bit 0. 0xF 0x1 read-write AR16 Add Request 16. See description for bit 0. 0x10 0x1 read-write AR17 Add Request 17. See description for bit 0. 0x11 0x1 read-write AR18 Add Request 18. See description for bit 0. 0x12 0x1 read-write AR19 Add Request 19. See description for bit 0. 0x13 0x1 read-write AR20 Add Request 20. See description for bit 0. 0x14 0x1 read-write AR21 Add Request 21. See description for bit 0. 0x15 0x1 read-write AR22 Add Request 22. See description for bit 0. 0x16 0x1 read-write AR23 Add Request 23. See description for bit 0. 0x17 0x1 read-write AR24 Add Request 24. See description for bit 0. 0x18 0x1 read-write AR25 Add Request 25. See description for bit 0. 0x19 0x1 read-write AR26 Add Request 26. See description for bit 0. 0x1A 0x1 read-write AR27 Add Request 27. See description for bit 0. 0x1B 0x1 read-write AR28 Add Request 28. See description for bit 0. 0x1C 0x1 read-write AR29 Add Request 29. See description for bit 0. 0x1D 0x1 read-write AR30 Add Request 30. See description for bit 0. 0x1E 0x1 read-write AR31 Add Request 31. See description for bit 0. 0x1F 0x1 read-write CANFD0_MCAN_TXBCR MCAN Tx Buffer Cancellation Request 0xD4 32 read-write 0x00000000 0xffffffff CR0 Cancellation Request 0. Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0 No cancellation pending 1 Cancellation pending Qualified Write is possible only with CCCR.CCE='0' 0x0 0x1 read-write CR1 Cancellation Request 1. See description for bit 0. 0x1 0x1 read-write CR2 Cancellation Request 2. See description for bit 0. 0x2 0x1 read-write CR3 Cancellation Request 3. See description for bit 0. 0x3 0x1 read-write CR4 Cancellation Request 4. See description for bit 0. 0x4 0x1 read-write CR5 Cancellation Request 5. See description for bit 0. 0x5 0x1 read-write CR6 Cancellation Request 6. See description for bit 0. 0x6 0x1 read-write CR7 Cancellation Request 7. See description for bit 0. 0x7 0x1 read-write CR8 Cancellation Request 8. See description for bit 0. 0x8 0x1 read-write CR9 Cancellation Request 9. See description for bit 0. 0x9 0x1 read-write CR10 Cancellation Request 10. See description for bit 0. 0xA 0x1 read-write CR11 Cancellation Request 11. See description for bit 0. 0xB 0x1 read-write CR12 Cancellation Request 12. See description for bit 0. 0xC 0x1 read-write CR13 Cancellation Request 13. See description for bit 0. 0xD 0x1 read-write CR14 Cancellation Request 14. See description for bit 0. 0xE 0x1 read-write CR15 Cancellation Request 15. See description for bit 0. 0xF 0x1 read-write CR16 Cancellation Request 16. See description for bit 0. 0x10 0x1 read-write CR17 Cancellation Request 17. See description for bit 0. 0x11 0x1 read-write CR18 Cancellation Request 18. See description for bit 0. 0x12 0x1 read-write CR19 Cancellation Request 19. See description for bit 0. 0x13 0x1 read-write CR20 Cancellation Request 20. See description for bit 0. 0x14 0x1 read-write CR21 Cancellation Request 21. See description for bit 0. 0x15 0x1 read-write CR22 Cancellation Request 22. See description for bit 0. 0x16 0x1 read-write CR23 Cancellation Request 23. See description for bit 0. 0x17 0x1 read-write CR24 Cancellation Request 24. See description for bit 0. 0x18 0x1 read-write CR25 Cancellation Request 25. See description for bit 0. 0x19 0x1 read-write CR26 Cancellation Request 26. See description for bit 0. 0x1A 0x1 read-write CR27 Cancellation Request 27. See description for bit 0. 0x1B 0x1 read-write CR28 Cancellation Request 28. See description for bit 0. 0x1C 0x1 read-write CR29 Cancellation Request 29. See description for bit 0. 0x1D 0x1 read-write CR30 Cancellation Request 30. See description for bit 0. 0x1E 0x1 read-write CR31 Cancellation Request 31. See description for bit 0. 0x1F 0x1 read-write CANFD0_MCAN_TXBTO MCAN Tx Buffer Transmission Occurred 0xD8 32 read-only 0x00000000 0xffffffff TO0 Transmission Occurred 0. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmission occurred 1 Transmission occurred 0x0 0x1 read-only TO1 Transmission Occurred 1. See description for bit 0. 0x1 0x1 read-only TO2 Transmission Occurred 2. See description for bit 0. 0x2 0x1 read-only TO3 Transmission Occurred 3. See description for bit 0. 0x3 0x1 read-only TO4 Transmission Occurred 4. See description for bit 0. 0x4 0x1 read-only TO5 Transmission Occurred 5. See description for bit 0. 0x5 0x1 read-only TO6 Transmission Occurred 6. See description for bit 0. 0x6 0x1 read-only TO7 Transmission Occurred 7. See description for bit 0. 0x7 0x1 read-only TO8 Transmission Occurred 8. See description for bit 0. 0x8 0x1 read-only TO9 Transmission Occurred 9. See description for bit 0. 0x9 0x1 read-only TO10 Transmission Occurred 10. See description for bit 0. 0xA 0x1 read-only TO11 Transmission Occurred 11. See description for bit 0. 0xB 0x1 read-only TO12 Transmission Occurred 12. See description for bit 0. 0xC 0x1 read-only TO13 Transmission Occurred 13. See description for bit 0. 0xD 0x1 read-only TO14 Transmission Occurred 14. See description for bit 0. 0xE 0x1 read-only TO15 Transmission Occurred 15. See description for bit 0. 0xF 0x1 read-only TO16 Transmission Occurred 16. See description for bit 0. 0x10 0x1 read-only TO17 Transmission Occurred 17. See description for bit 0. 0x11 0x1 read-only TO18 Transmission Occurred 18. See description for bit 0. 0x12 0x1 read-only TO19 Transmission Occurred 19. See description for bit 0. 0x13 0x1 read-only TO20 Transmission Occurred 20. See description for bit 0. 0x14 0x1 read-only TO21 Transmission Occurred 21. See description for bit 0. 0x15 0x1 read-only TO22 Transmission Occurred 22. See description for bit 0. 0x16 0x1 read-only TO23 Transmission Occurred 23. See description for bit 0. 0x17 0x1 read-only TO24 Transmission Occurred 24. See description for bit 0. 0x18 0x1 read-only TO25 Transmission Occurred 25. See description for bit 0. 0x19 0x1 read-only TO26 Transmission Occurred 26. See description for bit 0. 0x1A 0x1 read-only TO27 Transmission Occurred 27. See description for bit 0. 0x1B 0x1 read-only TO28 Transmission Occurred 28. See description for bit 0. 0x1C 0x1 read-only TO29 Transmission Occurred 29. See description for bit 0. 0x1D 0x1 read-only TO30 Transmission Occurred 30. See description for bit 0. 0x1E 0x1 read-only TO31 Transmission Occurred 31. See description for bit 0. 0x1F 0x1 read-only CANFD0_MCAN_TXBCF MCAN Tx Buffer Cancellation Finished 0xDC 32 read-only 0x00000000 0xffffffff CF0 Cancellation Finished 0. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmit buffer cancellation 1 Transmit buffer cancellation finished 0x0 0x1 read-only CF1 Cancellation Finished 1. See description for bit 0. 0x1 0x1 read-only CF2 Cancellation Finished 2. See description for bit 0. 0x2 0x1 read-only CF3 Cancellation Finished 3. See description for bit 0. 0x3 0x1 read-only CF4 Cancellation Finished 4. See description for bit 0. 0x4 0x1 read-only CF5 Cancellation Finished 5. See description for bit 0. 0x5 0x1 read-only CF6 Cancellation Finished 6. See description for bit 0. 0x6 0x1 read-only CF7 Cancellation Finished 7. See description for bit 0. 0x7 0x1 read-only CF8 Cancellation Finished 8. See description for bit 0. 0x8 0x1 read-only CF9 Cancellation Finished 9. See description for bit 0. 0x9 0x1 read-only CF10 Cancellation Finished 10. See description for bit 0. 0xA 0x1 read-only CF11 Cancellation Finished 11. See description for bit 0. 0xB 0x1 read-only CF12 Cancellation Finished 12. See description for bit 0. 0xC 0x1 read-only CF13 Cancellation Finished 13. See description for bit 0. 0xD 0x1 read-only CF14 Cancellation Finished 14. See description for bit 0. 0xE 0x1 read-only CF15 Cancellation Finished 15. See description for bit 0. 0xF 0x1 read-only CF16 Cancellation Finished 16. See description for bit 0. 0x10 0x1 read-only CF17 Cancellation Finished 17. See description for bit 0. 0x11 0x1 read-only CF18 Cancellation Finished 18. See description for bit 0. 0x12 0x1 read-only CF19 Cancellation Finished 19. See description for bit 0. 0x13 0x1 read-only CF20 Cancellation Finished 20. See description for bit 0. 0x14 0x1 read-only CF21 Cancellation Finished 21. See description for bit 0. 0x15 0x1 read-only CF22 Cancellation Finished 22. See description for bit 0. 0x16 0x1 read-only CF23 Cancellation Finished 23. See description for bit 0. 0x17 0x1 read-only CF24 Cancellation Finished 24. See description for bit 0. 0x18 0x1 read-only CF25 Cancellation Finished 25. See description for bit 0. 0x19 0x1 read-only CF26 Cancellation Finished 26. See description for bit 0. 0x1A 0x1 read-only CF27 Cancellation Finished 27. See description for bit 0. 0x1B 0x1 read-only CF28 Cancellation Finished 28. See description for bit 0. 0x1C 0x1 read-only CF29 Cancellation Finished 29. See description for bit 0. 0x1D 0x1 read-only CF30 Cancellation Finished 30. See description for bit 0. 0x1E 0x1 read-only CF31 Cancellation Finished 31. See description for bit 0. 0x1F 0x1 read-only CANFD0_MCAN_TXBTIE MCAN Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write 0x00000000 0xffffffff TIE0 Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x0 0x1 read-write TIE1 Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1 0x1 read-write TIE2 Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x2 0x1 read-write TIE3 Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x3 0x1 read-write TIE4 Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x4 0x1 read-write TIE5 Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x5 0x1 read-write TIE6 Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x6 0x1 read-write TIE7 Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x7 0x1 read-write TIE8 Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x8 0x1 read-write TIE9 Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x9 0x1 read-write TIE10 Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xA 0x1 read-write TIE11 Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xB 0x1 read-write TIE12 Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xC 0x1 read-write TIE13 Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xD 0x1 read-write TIE14 Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xE 0x1 read-write TIE15 Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xF 0x1 read-write TIE16 Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x10 0x1 read-write TIE17 Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x11 0x1 read-write TIE18 Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x12 0x1 read-write TIE19 Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x13 0x1 read-write TIE20 Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x14 0x1 read-write TIE21 Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x15 0x1 read-write TIE22 Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x16 0x1 read-write TIE23 Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x17 0x1 read-write TIE24 Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x18 0x1 read-write TIE25 Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x19 0x1 read-write TIE26 Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1A 0x1 read-write TIE27 Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1B 0x1 read-write TIE28 Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1C 0x1 read-write TIE29 Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1D 0x1 read-write TIE30 Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1E 0x1 read-write TIE31 Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1F 0x1 read-write CANFD0_MCAN_TXBCIE MCAN Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write 0x00000000 0xffffffff CFIE0 Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x0 0x1 read-write CFIE1 Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1 0x1 read-write CFIE2 Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x2 0x1 read-write CFIE3 Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x3 0x1 read-write CFIE4 Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x4 0x1 read-write CFIE5 Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x5 0x1 read-write CFIE6 Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x6 0x1 read-write CFIE7 Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x7 0x1 read-write CFIE8 Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x8 0x1 read-write CFIE9 Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x9 0x1 read-write CFIE10 Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xA 0x1 read-write CFIE11 Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xB 0x1 read-write CFIE12 Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xC 0x1 read-write CFIE13 Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xD 0x1 read-write CFIE14 Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xE 0x1 read-write CFIE15 Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xF 0x1 read-write CFIE16 Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x10 0x1 read-write CFIE17 Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x11 0x1 read-write CFIE18 Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x12 0x1 read-write CFIE19 Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x13 0x1 read-write CFIE20 Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x14 0x1 read-write CFIE21 Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x15 0x1 read-write CFIE22 Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x16 0x1 read-write CFIE23 Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x17 0x1 read-write CFIE24 Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x18 0x1 read-write CFIE25 Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x19 0x1 read-write CFIE26 Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1A 0x1 read-write CFIE27 Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1B 0x1 read-write CFIE28 Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1C 0x1 read-write CFIE29 Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1D 0x1 read-write CFIE30 Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1E 0x1 read-write CFIE31 Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1F 0x1 read-write CANFD0_MCAN_TXEFC MCAN Tx Event FIFO Configuration 0xF0 32 read-write 0x00000000 0xffffffff EFSA Event FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address). 0x2 0xE read-write EFS Event FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1. 0 Tx Event FIFO disabled 1-32 Number of Tx Event FIFO elements >32 Values greater than 32 are interpreted as 32 0x10 0x6 read-write EFWM Event FIFO Watermark 0 Watermark interrupt disabled 1-32 Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32 Watermark interrupt disabled 0x18 0x6 read-write CANFD0_MCAN_TXEFS MCAN Tx Event FIFO Status 0xF4 32 read-only 0x00000000 0xffffffff EFFL Event FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 32. 0x0 0x6 read-only EFGI Event FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31. 0x8 0x5 read-only EFPI Event FIFO Put Index.Tx Event FIFO write index pointer, range 0 to 31. 0x10 0x5 read-only EFF Event FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full 0x18 0x1 read-only TEFL Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. 0x19 0x1 read-only CANFD0_MCAN_TXEFA MCAN Tx Event FIFO Acknowledge 0xF8 32 read-write 0x00000000 0xffffffff EFAI Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. 0x0 0x5 read-write 1 2560 0 CANFD0_TI_WRAPPER[%s] 0x7200 1 1040 0 CANFD0_PROCESSORS[%s] 0x0 1 44 0 CANFD0_MCANSS_REGS[%s] 0x0 CANFD0_MCANSS_PID MCAN Subsystem Revision Register 0x0 32 read-only 0x68e04901 0xffffffff MINOR Minor Revision of the MCAN Subsystem 0x0 0x6 read-only MAJOR Major Revision of the MCAN Subsystem 0x8 0x3 read-only MODULE_ID Module Identification Number 0x10 0xC read-only SCHEME PID Register Scheme 0x1E 0x2 read-only CANFD0_MCANSS_CTRL MCAN Subsystem Control Register 0x4 32 read-write 0x00000008 0xffffffff DBGSUSP_FREE Debug Suspend Free Bit. Enables debug suspend. 0 Honor debug suspend 1 Disregard debug suspend 0x3 0x1 read-write WAKEUPREQEN Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity. 0 Disable wakeup request 1 Enables wakeup request 0x4 0x1 read-write AUTOWAKEUP Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up, on an enabled wakeup request. 0 Disable the automatic write to CCCR.INIT 1 Enable the automatic write to CCCR.INIT 0x5 0x1 read-write EXT_TS_CNTR_EN External Timestamp Counter Enable. 0 External timestamp counter disabled 1 External timestamp counter enabled 0x6 0x1 read-write CANFD0_MCANSS_STAT MCAN Subsystem Status Register 0x8 32 read-only 0x00000000 0xfffffffb RESET Soft Reset Status. 0 Not in reset 1 Reset is in progress 0x0 0x1 read-only MEM_INIT_DONE Memory Initialization Done. 0 Message RAM initialization is in progress 1 Message RAM is initialized for use 0x1 0x1 read-only ENABLE_FDOE Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port, -h = mcanss_enable_fdoe. 0x2 0x1 read-only CANFD0_MCANSS_ICS MCAN Subsystem Interrupt Clear Shadow Register 0xC 32 read-write 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IRS.EXT_TS_CNTR_OVFL bit 0x0 0x1 read-write CANFD0_MCANSS_IRS MCAN Subsystem Interrupt Raw Satus Register 0x10 32 read-write 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter has not overflowed 1 External timestamp counter has overflowed When this bit is set to '1' by HW or SW, the MCANSS_EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1. 0x0 0x1 read-write CANFD0_MCANSS_IECS MCAN Subsystem Interrupt Enable Clear Shadow Register 0x14 32 read-write 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IES.EXT_TS_CNTR_OVFL bit 0x0 0x1 read-write CANFD0_MCANSS_IE MCAN Subsystem Interrupt Enable Register 0x18 32 read-write 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit. 0x0 0x1 read-write CANFD0_MCANSS_IES MCAN Subsystem Interrupt Enable Status 0x1C 32 read-only 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Enable Status. To set, use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear, use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter overflow interrupt is not enabled 1 External timestamp counter overflow interrupt is enabled 0x0 0x1 read-only CANFD0_MCANSS_EOI MCAN Subsystem End of Interrupt 0x20 32 read-write 0x00000000 0xffffffff EOI End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated. 0x00 External TS Interrupt is cleared 0x01 MCAN(0) interrupt is cleared 0x02 MCAN(1) interrupt is cleared Other writes are ignored. 0x0 0x8 read-write CANFD0_MCANSS_EXT_TS_PRESCALER MCAN Subsystem External Timestamp Prescaler 0 0x24 32 read-write 0x00000000 0xffffffff PRESCALER External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001. 0x0 0x18 read-write CANFD0_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR MCAN Subsystem External Timestamp Unserviced Interrupts Counter 0x28 32 read-only 0x00000000 0xffffffff EXT_TS_INTR_CNTR External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an MCANSS_EOI write of '1' to bit 0 will issue another interrupt. The status of this bit field is affected by the MCANSS_IRS.EXT_TS_CNTR_OVFL bit field. 0x0 0x5 read-only 1 528 0 CANFD0_MCAN_ECC_REGS[%s] 0x200 CANFD0_MCANERR_REV MCAN Error Aggregator Revision Register 0x0 32 read-only 0x66a0ea00 0xffffffff REVMIN Minor Revision of the Error Aggregator 0x0 0x6 read-only REVMAJ Major Revision of the Error Aggregator 0x8 0x3 read-only MODULE_ID Module Identification Number 0x10 0xC read-only SCHEME PID Register Scheme 0x1E 0x2 read-only CANFD0_MCANERR_VECTOR MCAN ECC Vector Register 0x8 32 read-write 0x00000000 0xffffffff ECC_VECTOR ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address. 0x000 Message RAM ECC controller is selected Others Reserved (do not use) Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing. 0x0 0xB read-write RD_SVBUS Read Trigger 0xF 0x1 read-write RD_SVBUS_ADDRESS Read Address Offset 0x10 0x8 read-write RD_SVBUS_DONE Read Completion Flag 0x18 0x1 read-only CANFD0_MCANERR_STAT MCAN Error Misc Status 0xC 32 read-only 0x00000002 0xffffffff NUM_RAMS Number of RAMs. Number of ECC RAMs serviced by the aggregator. 0x0 0xB read-only CANFD0_MCANERR_WRAP_REV MCAN ECC Wrapper Revision Register 0x10 32 read-only 0x66a46a02 0xffffffff REVMIN Minor Revision of the Error Aggregator 0x0 0x6 read-only REVMAJ Major Revision of the Error Aggregator 0x8 0x3 read-only MODULE_ID Module Identification Number 0x10 0xC read-only SCHEME PID Register Scheme 0x1E 0x2 read-only CANFD0_MCANERR_CTRL MCAN ECC Control 0x14 32 read-write 0x00000187 0xffffffff ECC_ENABLE Enable ECC Generation 0x0 0x1 read-write ECC_CHECK Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'. 0x1 0x1 read-write ENABLE_RMW Enable read-modify-write on partial word writes 0x2 0x1 read-write FORCE_SEC Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. 0x3 0x1 read-write FORCE_DED Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. 0x4 0x1 read-write FORCE_N_ROW Enable single/double-bit error on the next RAM read, regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode, this applies to writes as well as reads. 0x5 0x1 read-write ERROR_ONCE If this bit is set, the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled, this error will be cleared the cycle following the read when the data is corrected. For double-bit errors, the FORCE_DED bit will be cleared the cycle following the double-bit error. Any subsequent reads will not force an error. 0x6 0x1 read-write CHECK_SVBUS_TIMEOUT Enables Serial VBUS timeout mechanism 0x8 0x1 read-write CANFD0_MCANERR_ERR_CTRL1 MCAN ECC Error Control 1 Register 0x18 32 read-write 0x00000000 0xffffffff CANFD0_MCANERR_ERR_CTRL2 MCAN ECC Error Control 2 Register 0x1C 32 read-write 0x00000000 0xffffffff ECC_BIT1 Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set 0x0 0x10 read-write ECC_BIT2 Second column/data bit that needs to be flipped when FORCE_DED is set 0x10 0x10 read-write CANFD0_MCANERR_ERR_STAT1 MCAN ECC Error Status 1 Register 0x20 32 read-write 0x00000000 0xffffffff ECC_SEC Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared. 0 No single-bit error detected 1 One single-bit error was detected and corrected 2 Two single-bit errors were detected and corrected 3 Three single-bit errors were detected and corrected A write of a non-zero value to this bit field increments it by the value provided. 0x0 0x2 read-write ECC_DED Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared. 0 No double-bit error detected 1 One double-bit error was detected 2 Two double-bit errors were detected 3 Three double-bit errors were detected A write of a non-zero value to this bit field increments it by the value provided. 0x2 0x2 read-write ECC_OTHER SEC While Writeback Error Status 0 No SEC error while writeback pending 1 Indicates that successive single-bit errors have occurred while a writeback is still pending 0x4 0x1 read-write CTRL_REG_ERROR Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to re-write these registers to a known state. A write of 1 will set this interrupt flag. 0x7 0x1 read-write CLR_ECC_SEC Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided. 0x8 0x2 read-write CLR_ECC_DED Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided. 0xA 0x2 read-write CLR_ECC_OTHER Writing a '1' clears the ECC_OTHER bit. 0xC 0x1 read-write CLR_CTRL_REG_ERROR Writing a '1' clears the CTRL_REG_ERROR bit 0xF 0x1 read-write ECC_BIT1 ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error. 0 Bit 0 is in error 1 Bit 1 is in error 2 Bit 2 is in error 3 Bit 3 is in error ... 31 Bit 31 is in error >32 Invalid 0x10 0x10 read-only CANFD0_MCANERR_ERR_STAT2 MCAN ECC Error Status 2 Register 0x24 32 read-only 0x00000000 0xffffffff CANFD0_MCANERR_ERR_STAT3 MCAN ECC Error Status 3 Register 0x28 32 read-write 0x00000000 0xffffffff WB_PEND Delayed Write Back Pending Status 0 No write back pending 1 An ECC data correction write back is pending 0x0 0x1 read-only SVBUS_TIMEOUT Serial VBUS Timeout Flag. Write 1 to set. 0x1 0x1 read-write CLR_SVBUS_TIMEOUT Write 1 to clear the Serial VBUS Timeout Flag 0x9 0x1 read-write CANFD0_MCANERR_SEC_EOI MCAN Single Error Corrected End of Interrupt Register 0x3C 32 read-write 0x00000000 0xffffffff EOI_WR Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_SEC goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. 0x0 0x1 read-write CANFD0_MCANERR_SEC_STATUS MCAN Single Error Corrected Interrupt Status Register 0x40 32 read-write 0x00000000 0xffffffff MSGMEM_PEND Message RAM SEC Interrupt Pending 0 No SEC interrupt is pending 1 SEC interrupt is pending 0x0 0x1 read-only CANFD0_MCANERR_SEC_ENABLE_SET MCAN Single Error Corrected Interrupt Enable Set Register 0x80 32 read-write 0x00000000 0xffffffff MSGMEM_ENABLE_SET Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write CANFD0_MCANERR_SEC_ENABLE_CLR MCAN Single Error Corrected Interrupt Enable Clear Register 0xC0 32 read-write 0x00000000 0xffffffff MSGMEM_ENABLE_CLR Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write CANFD0_MCANERR_DED_EOI MCAN Double Error Detected End of Interrupt Register 0x13C 32 read-write 0x00000000 0xffffffff EOI_WR Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_DED goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. 0x0 0x1 read-write CANFD0_MCANERR_DED_STATUS MCAN Double Error Detected Interrupt Status Register 0x140 32 read-write 0x00000000 0xffffffff MSGMEM_PEND Message RAM DED Interrupt Pending 0 No DED interrupt is pending 1 DED interrupt is pending 0x0 0x1 read-only CANFD0_MCANERR_DED_ENABLE_SET MCAN Double Error Detected Interrupt Enable Set Register 0x180 32 read-write 0x00000000 0xffffffff MSGMEM_ENABLE_SET Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write CANFD0_MCANERR_DED_ENABLE_CLR MCAN Double Error Detected Interrupt Enable Clear Register 0x1C0 32 read-write 0x00000000 0xffffffff MSGMEM_ENABLE_CLR Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write CANFD0_MCANERR_AGGR_ENABLE_SET MCAN Error Aggregator Enable Set Register 0x200 32 read-write 0x00000000 0xffffffff ENABLE_PARITY_SET Write 1 to enable parity errors. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write ENABLE_TIMEOUT_SET Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value. 0x1 0x1 read-write CANFD0_MCANERR_AGGR_ENABLE_CLR MCAN Error Aggregator Enable Clear Register 0x204 32 read-write 0x00000000 0xffffffff ENABLE_PARITY_CLR Write 1 to disable parity errors. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write ENABLE_TIMEOUT_CLR Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value. 0x1 0x1 read-write CANFD0_MCANERR_AGGR_STATUS_SET MCAN Error Aggregator Status Set Register 0x208 32 read-write 0x00000000 0xffffffff AGGR_PARITY_ERR Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field increments it by the value provided. 0x0 0x2 read-write SVBUS_TIMEOUT Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field increments it by the value provided. 0x2 0x2 read-write CANFD0_MCANERR_AGGR_STATUS_CLR MCAN Error Aggregator Status Clear Register 0x20C 32 read-write 0x00000000 0xffffffff AGGR_PARITY_ERR Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. 0x0 0x2 read-write SVBUS_TIMEOUT Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. 0x2 0x2 read-write 1 512 0 CANFD0_MSP[%s] 0x600 1 44 0 CANFD0_CPU_INT[%s] 0x20 CANFD0_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending. 0x0 INTL0 MCAN Interrupt Line 0 interrupt pending. 0x1 INTL1 MCAN Interrupt Line 1 interrupt pending. 0x2 SEC Message RAM SEC (Single Error Correction) interrupt pending. 0x3 DED Message RAM DED (Double Error Detection) interrupt pending. 0x4 EXT_TS_CNTR_OVFL External Timestamp Counter Overflow interrupt pending. 0x5 WAKEUP Clock Stop Wake Up interrupt pending. 0x6 CANFD0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 INTL0 MCAN Interrupt Line 0 mask. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 INTL1 MCAN Interrupt Line 1 mask. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 SEC Message RAM SEC interrupt mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 DED Massage RAM DED interrupt mask. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 EXT_TS_CNTR_OVFL External Timestamp Counter Overflow interrupt mask. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 WAKEUP Clock Stop Wake Up interrupt mask. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 CANFD0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INTL0 MCAN Interrupt Line 0. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INTL1 MCAN Interrupt Line 1. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 SEC Message RAM SEC interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DED Message RAM DED interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EXT_TS_CNTR_OVFL External Timestamp Counter Overflow interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 WAKEUP Clock Stop Wake Up interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CANFD0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INTL0 Masked MCAN Interrupt Line 0. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INTL1 Masked MCAN Interrupt Line 1. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 SEC Masked Message RAM SEC interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DED Masked Message RAM DED interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EXT_TS_CNTR_OVFL Masked External Timestamp Counter Overflow interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 WAKEUP Masked Clock Stop Wake Up interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CANFD0_ISET Interrupt set 0x20 32 write-only 0x00000000 INTL0 Set MCAN Interrupt Line 0. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 INTL1 Set MCAN Interrupt Line 1. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 SEC Set Message RAM SEC interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DED Set Message RAM DED interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EXT_TS_CNTR_OVFL Set External Timestamp Counter Overflow interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 WAKEUP Set Clock Stop Wake Up interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CANFD0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INTL0 Clear MCAN Interrupt Line 0. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 INTL1 Clear MCAN Interrupt Line 1. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 SEC Clear Message RAM SEC interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DED Clear Message RAM DED interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EXT_TS_CNTR_OVFL Clear External Timestamp Counter Overflow interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 WAKEUP Clear Clock Stop Wake Up interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CANFD0_EVT_MODE Event Mode 0xE0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 CANFD0_DESC Module Description 0xFC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 VERSION_0 MCAN module with CAN-FD mode enabled <<Internal Note: This is an in-IP paper spin variant. How does this map to the SYS_MCAN_ENABLE_FD choice value?>> 0x0 VERSION_1 MCAN module with CAN-FD mode disabled <<Internal Note: This is an in-IP paper spin variant. How does this map to the SYS_MCAN_ENABLE_FD choice value?>> 0x1 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CANFD0_MCANSS_CLKEN MCAN module clock enable 0x100 32 CLK_REQEN MCAN functional and MCAN/MCANSS MMR clock request enable bit 0x0 0x1 CLR MCAN module functional clock and Vbusp is not requested. These clocks are gated to the MCAN module. 0x0 SET Setting this bit requests MCAN module functional clock and Vbusp. These clocks are not gated to MCAN module. 0x1 CANFD0_MCANSS_CLKDIV Clock divider 0x104 32 read-write RATIO Clock divide ratio specification. Enables configuring clock divide settings for the MCAN functional clock input to the MCAN-SS. 0x0 0x2 read-write DIV_BY_1_ Divides input clock by 1 0x0 DIV_BY_2_ Divides input clock by 2 0x1 DIV_BY_4_ Divides input clock by 4 0x2 DIV_BY_1_1 Divides input clock by 1 0x3 CANFD0_MCANSS_CLKCTL MCAN-SS clock stop control register 0x108 32 read-write 0x00000000 STOPREQ This bit is used to enable/disable MCAN clock (both host clock and functional clock) gating request. Note: This bit can be reset by HW by Clock-Stop Wake-up via CAN RX Activity. See spec for more details. 0x0 0x1 DISABLE Disable MCAN-SS clock stop request 0x0 ENABLE Enable MCAN-SS clock stop request 0x1 WAKEUP_INT_EN This bit contols enabling or disabling the MCAN IP clock stop wakeup interrupt (when MCANSS_CTRL.WAKEUPREQEN wakeup request is enabled to wakeup MCAN IP upon CAN RXD activity) 0x4 0x1 read-write DISABLE Disable MCAN IP clock stop wakeup interrupt 0x0 ENABLE Enable MCAN IP clock stop wakeup interrupt 0x1 WKUP_GLTFLT_EN Setting this bit enables the glitch filter on MCAN RXD input, which wakes up the MCAN controller to exit clock gating. 0x8 0x1 read-write DISABLE Disable glitch filter enable on RXD input when MCAN is in clock stop mode (waiting for event on RXD input for clock stop wakeup). 0x0 ENABLE Enable glitch filter enable on RXD input when MCAN is in clock stop mode (waiting for event on RXD input for clock stop wakeup). 0x1 CANFD0_MCANSS_CLKSTS MCANSS clock stop status register 0x10C 32 read-only 0x00000000 CLKSTOP_ACKSTS Clock stop acknowledge status from MCAN IP 0x0 0x1 read-only RESET No clock stop acknowledged. 0x0 SET Clock stop has been acknowledged by MCAN IP; MCAN-SS may be clock gated by stopping both the CAN host and functional clocks. 0x1 STOPREQ_HW_OVR MCANSS clock stop HW override status bit. This bit indicates when the MCANSS_CLKCTL.STOPREQ bit has been cleared by HW when a clock-stop wake-up event via CAN RX activity is triggered. 0x4 0x1 read-only RESET MCANSS_CLKCTL.STOPREQ bit has not been cleared by HW. 0x0 SET MCANSS_CLKCTL.STOPREQ bit has been cleared by HW. 0x1 CCLKDONE This bit indicates the status of MCAN contoller clock request from GPRCM. 0x8 0x1 read-only RESET MCAN controller clock is not available to the MCAN IP. 0x0 SET MCAN controller clock is enabled and available to the MCAN IP. 0x1 SPI2 SPI 1.0 PERIPHERALREGION 0x4046C000 0x0 0x1F00 registers 1 24 0 SPI2_GPRCM[%s] 0x800 SPI2_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 SPI2_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 SPI2_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write DISABLE Not block async clock request 0x0 ENABLE Block async clock request 0x1 SPI2_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 SPI2_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 SPI2_CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 SYSCLK_SEL Selects SYSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 SPI2_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 SPI2_CPU_INT[%s] 0x1020 SPI2_CPU_INT_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RXFIFO_OFV_EVT RX FIFO Overflow Event/interrupt pending 0x1 PER_EVT Transmit Parity Event/interrupt pending 0x2 RTOUT_EVT SPI receive time-out interrupt 0x3 RX_EVT Receive Event/interrupt pending 0x4 TX_EVT Transmit Event/interrupt pending 0x5 TX_EMPTY Transmit Buffer Empty Event/interrupt pending 0x6 IDLE_EVT End of Transmit Event/interrupt pending 0x7 DMA_DONE_RX_EVT DMA Done for Receive Event/interrupt pending 0x8 DMA_DONE_TX_EVT DMA Done for Transmit Event/interrupt pending 0x9 TXFIFO_UNF_EVT TX FIFO underflow interrupt 0xA RXFULL_EVT RX FIFO Full Interrupt 0xB SPI2_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TX Transmit FIFO event mask. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXEMPTY Transmit FIFO Empty event mask. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PER Parity error event mask. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX DMA Done 1 event for RX event mask. 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFIFO_OVF RXFIFO overflow event mask. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX DMA Done 1 event for TX event mask. 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 IDLE SPI Idle event mask. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFULL RX FIFO Full Interrupt Mask 0xA 0x1 read-write CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXFIFO_UNF TX FIFO underflow interrupt mask 0x9 0x1 read-write CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI2_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TX Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 PER Parity error event: this bit is set if a Parity error has been detected 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_RX DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFIFO_OVF RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_TX DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 IDLE SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out event. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXFIFO_UNF TX FIFO Underflow Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFULL RX FIFO Full Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI2_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RX Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TX Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXEMPTY Masked Transmit FIFO Empty event. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 PER Masked Parity error event: this bit if a Parity error has been detected 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_RX Masked DMA Done 1 event for RX. 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RXFIFO_OVF Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 DMA_DONE_TX Masked DMA Done 1 event for TX. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 IDLE Masked SPI IDLE mode event. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT Masked SPI Receive Time-Out Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXFULL RX FIFO Full Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TXFIFO_UNF TX FIFO underflow interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI2_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 RX Set Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TX Set Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXEMPTY Set Transmit FIFO Empty event. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PER Set Parity error event. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done 1 event for RX. 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXFIFO_OVF Set RXFIFO overflow event. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done 1 event for TX. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 IDLE Set SPI IDLE mode event. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RTOUT Set SPI Receive Time-Out Event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt Mask 0x1 TXFIFO_UNF Set TX FIFO Underflow Event 0x9 0x1 NO_EFFECT Writing has no effect 0x0 SET Set interrupt 0x1 RXFULL Set RX FIFO Full Event 0xA 0x1 NO_EFFECT Writing has no effect 0x0 SET Set Interrupt 0x1 SPI2_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RX Clear Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TX Clear Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXEMPTY Clear Transmit FIFO Empty event. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PER Clear Parity error event. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done 1 event for RX. 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXFIFO_OVF Clear RXFIFO overflow event. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done 1 event for TX. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 IDLE Clear SPI IDLE mode event. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RTOUT Clear SPI Receive Time-Out Event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Set Interrupt Mask 0x1 TXFIFO_UNF Clear TXFIFO underflow event 0x9 0x1 NO_EFFECT Writing has no effect 0x0 CLR Clear interrupt 0x1 RXFULL Clear RX FIFO underflow event 0xA 0x1 NO_EFFECT Writing has no effect 0x0 CLR Clear interrupt 0x1 1 44 0 SPI2_DMA_TRIG_RX[%s] 0x1050 SPI2_DMA_TRIG_RX_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTOUT_EVT SPI receive time-out interrupt 0x3 RX_EVT Receive Event/interrupt pending 0x4 SPI2_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RX Receive FIFO event mask. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RTOUT SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI2_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out Event. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI2_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RX Receive FIFO event mask. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTOUT SPI Receive Time-Out event mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI2_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RX Set Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RTOUT Set SPI Receive Time-Out event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt Mask 0x1 SPI2_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RX Clear Receive FIFO event. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RTOUT Clear SPI Receive Time-Out event. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Set Interrupt Mask 0x1 1 44 0 SPI2_DMA_TRIG_TX[%s] 0x1080 SPI2_DMA_TRIG_TX_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TX_EVT Transmit Event/interrupt pending 0x5 SPI2_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TX Transmit FIFO event mask. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 SPI2_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TX Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI2_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TX Masked Transmit FIFO event 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 SPI2_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TX Set Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 SPI2_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TX Clear Transmit FIFO event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 SPI2_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 SPI2_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 SPI2_CTL0 SPI control register 0 0x1100 32 read-write 0x00000000 DSS Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit 0x0 0x5 read-write DSS_4 Data Size Select bits: 4 0x3 DSS_5 Data Size Select bits: 5 0x4 DSS_6 Data Size Select bits: 6 0x5 DSS_7 Data Size Select bits: 7 0x6 DSS_8 Data Size Select bits: 8 0x7 DSS_9 Data Size Select bits: 9 0x8 DSS_10 Data Size Select bits: 10 0x9 DSS_11 Data Size Select bits: 11 0xA DSS_12 Data Size Select bits: 12 0xB DSS_13 Data Size Select bits: 13 0xC DSS_14 Data Size Select bits: 14 0xD DSS_15 Data Size Select bits: 15 0xE DSS_16 Data Size Select bits: 16 0xF FRF Frame format Select 0x5 0x2 read-write MOTOROLA_3WIRE Motorola SPI frame format (3 wire mode) 0x0 MOTOROLA_4WIRE Motorola SPI frame format (4 wire mode) 0x1 TI_SYNC TI synchronous serial frame format 0x2 MIRCOWIRE National Microwire frame format 0x3 SPO CLKOUT polarity (Motorola SPI frame format only) 0x8 0x1 read-write LOW SPI produces a steady state LOW value on the CLKOUT 0x0 HIGH SPI produces a steady state HIGH value on the CLKOUT 0x1 SPH CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 0x9 0x1 read-write FIRST Data is captured on the first clock edge transition. 0x0 SECOND Data is captured on the second clock edge transition. 0x1 CSSEL Select the CS line to control on data transfer This bit is applicable for both controller/target mode 0xC 0x2 read-write CSSEL_0 CS line select: 0 0x0 CSSEL_1 CS line select: 1 0x1 CSSEL_2 CS line select: 2 0x2 CSSEL_3 CS line select: 3 0x3 CSCLR Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.CP=0. 0xE 0x1 read-write DISABLE Disable automatic clear of shift register when CS goes to disable. 0x0 ENABLE Enable automatic clear of shift register when CS goes to disable. 0x1 PACKEN Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP 0x7 0x1 read-write DISABLED Packing feature disabled 0x0 ENABLED Packing feature enabled 0x1 SPI2_CTL1 SPI control register 1 0x1104 32 read-write 0x00000004 LBM Loop back mode 0x1 0x1 read-write DISABLE Disable loopback mode 0x0 ENABLE Enable loopback mode 0x1 CP Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0. 0x2 0x1 read-write DISABLE Select Peripheral mode 0x0 ENABLE Select Controller Mode 0x1 POD Peripheral-mode: Data output disabled This bit is relevant only in Peripheral mode. In multiple-peripheral system topologies, SPI controller can broadcast a message to all peripherals, while only one peripheral drives the line. POD can be used by the SPI peripheral to disable driving data on the line. 0x3 0x1 read-write DISABLE SPI can drive the MISO output in peripheral mode. 0x0 ENABLE SPI cannot drive the MISO output in peripheral mode. 0x1 MSB MSB first select. Controls the direction of the receive and transmit shift register. 0x4 0x1 read-write DISABLE LSB first 0x0 ENABLE MSB first 0x1 PREN Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set. 0x5 0x1 read-write DISABLE Disable Parity receive function 0x0 ENABLE Enable Parity receive function 0x1 REPEATTX Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral. 0x10 0x8 read-write DISABLE REPEATTX disable 0x0 PES Even Parity Select 0x6 0x1 read-write DISABLE Odd Parity mode 0x0 ENABLE Even Parity mode 0x1 CDMODE Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low. 0xC 0x4 read-write DATA Manual mode: Data 0x0 COMMAND Manual mode: Command 0xF ENABLE SPI enable 0x0 0x1 read-write DISABLE Disable module function 0x0 ENABLE Enable module function 0x1 RXTIMEOUT Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function. 0x18 0x6 read-write CDENABLE Command/Data Mode enable 0xB 0x1 read-write DISABLE CS3 is used for Chip Select 0x0 ENABLE CS3 is used as CD signal 0x1 PTEN Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes. 0x8 0x1 read-write DISABLE Parity transmission is disabled 0x0 ENABLE Parity transmission is enabled 0x1 SPI2_CLKCTL Clock prescaler and divider register. 0x1108 32 read-write 0x00000000 SCR Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023. 0x0 0xA read-write DSAMPLE Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations. 0x1C 0x4 read-write SPI2_IFLS Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000012 0xffffffff TXIFLSEL SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 0x0 0x3 read-write LVL_OFF Reserved 0x0 LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_RES4 Reserved 0x4 LVL_EMPTY TX FIFO is empty 0x5 LVL_RES6 Reserved 0x6 LEVEL_1 Trigger when TX FIFO has >= 1 frame free Should be used with DMA 0x7 RXIFLSEL SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: 0x3 0x3 read-write LVL_OFF Reserved 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_RES4 Reserved 0x4 LVL_FULL RX FIFO is full 0x5 LVL_RES6 Reserved 0x6 LEVEL_1 Trigger when RX FIFO contains >= 1 frame 0x7 SPI2_STAT Status Register 0x1110 32 read-only TFE Transmit FIFO empty. 0x0 0x1 NOT_EMPTY Transmit FIFO is not empty. 0x0 EMPTY Transmit FIFO is empty. 0x1 TNF Transmit FIFO not full 0x1 0x1 FULL Transmit FIFO is full. 0x0 NOT_FULL Transmit FIFO is not full. 0x1 RFE Receive FIFO empty. 0x2 0x1 NOT_EMPTY Receive FIFO is not empty. 0x0 EMPTY Receive FIFO is empty. 0x1 RNF Receive FIFO not full 0x3 0x1 FULL Receive FIFO is full. 0x0 NOT_FULL Receive FIFO is not full. 0x1 BUSY Busy 0x4 0x1 IDLE SPI is in idle mode. 0x0 ACTIVE SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty. 0x1 SPI2_RXDATA RXDATA Register 0x1130 32 read-only 0x00000000 DATA Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer. 0x0 0x10 read-only SPI2_TXDATA TXDATA Register 0x1140 32 read-write 0x00000000 DATA Transmit Data When read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. 0x0 0x10 read-write UART7 UART 1.0 PERIPHERALREGION 0x4010A000 0x0 0x1F00 registers 1 24 0 UART7_GPRCM[%s] 0x800 UART7_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 UART7_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 UART7_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 UART7_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 UART7_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 UART7_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 UART7_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 UART7_CPU_INT[%s] 0x1020 UART7_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 FEFG UART framing error interrupt; Interrupt Flag: FE 0x2 PEFG UART parity error interrupt; Interrupt Flag: PE 0x3 BEFG UART break error interrupt; Interrupt Flag: BE 0x4 OEFG UART receive overrun error interrupt; Interrupt Flag: OE 0x5 RXNE Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE 0x6 RXPE Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE 0x7 LINC0 LIN capture 0 / match interrupt; Interrupt Flag: LINC0 0x8 LINC1 LIN capture 1 interrupt; Interrupt Flag: LINC1 0x9 LINOVF LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF 0xA RXIFG UART receive interrupt; Interrupt Flag: RX 0xB TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC EOT UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT 0xD MODE_9B 9-bit mode address match interrupt; Interrupt Flag: MODE_9B 0xE CTS UART Clear to Send Modem interrupt; Interrupt Flag: CTS 0xF DMA_DONE_RX DMA DONE on RX 0x10 DMA_DONE_TX DMA DONE on TX 0x11 NERR_EVT Noise Error Event 0x12 UART7_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PARERR Enable UART Parity Error Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 BRKERR Enable UART Break Error Interrupt. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 LINOVF Enable LIN Hardware Counter Overflow Interrupt. 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTS Enable UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX Enable DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX Enable DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 LINC0 Enable LIN Capture 0 / Match Interrupt . 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 LINC1 Enable LIN Capture 1 Interrupt. 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART7_CPU_INT_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINC0 LIN Capture 0 / Match Interrupt . 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINC1 LIN Capture 1 Interrupt. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINOVF LIN Hardware Counter Overflow Interrupt. 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_RX DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_TX DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART7_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR Masked UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR Masked UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINC0 Masked LIN Capture 0 / Match Interrupt . 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINC1 Masked LIN Capture 1 Interrupt. 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 LINOVF Masked LIN Hardware Counter Overflow Interrupt. 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS Masked UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_RX Masked DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_TX Masked DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART7_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 FRMERR Set UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PARERR Set UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 BRKERR Set UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 LINC0 Set LIN Capture 0 / Match Interrupt . 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 LINC1 Set LIN Capture 1 Interrupt. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 LINOVF Set LIN Hardware Counter Overflow Interrupt. 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTS Set UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing this has no effect 0x0 SET Set the interrupt 0x1 UART7_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PARERR Clear UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 BRKERR Clear UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 LINC0 Clear LIN Capture 0 / Match Interrupt . 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 LINC1 Clear LIN Capture 1 Interrupt. 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 LINOVF Clear LIN Hardware Counter Overflow Interrupt. 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTS Clear UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART7_DMA_TRIG_RX[%s] 0x1050 UART7_DMA_TRIG_RX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 RXIFG UART receive interrupt; Interrupt Flag: RX 0xB UART7_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART7_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART7_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART7_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART7_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART7_DMA_TRIG_TX[%s] 0x1080 UART7_DMA_TRIG_TX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC UART7_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART7_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART7_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART7_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART7_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 UART7_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 UART7_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 UART7_CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write DISABLE Disable Module 0x0 ENABLE Enable module 0x1 HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write OVS16 16x oversampling. 0x0 OVS8 8x oversampling. 0x1 OVS3 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled. 0x2 LBE UART Loop Back Enable 0x2 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The UARTxTX path is fed through the UARTxRX path internally. 0x1 RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write DISABLE The receive section of the UART is disabled. 0x0 ENABLE The receive section of the UART is enabled. 0x1 TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write DISABLE The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled. 0x0 ENABLE The transmit section of the UART is enabled. 0x1 RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CLR Signal not RTS 0x0 SET Signal RTS 0x1 RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write DISABLE RTS hardware flow control is disabled. 0x0 ENABLE RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries. 0x1 CTSEN Enable Clear To Send 0xE 0x1 read-write DISABLE CTS hardware flow control is disabled. 0x0 ENABLE CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted. 0x1 MENC Manchester Encode enable 0x7 0x1 read-write DISABLE Disable Manchester Encoding 0x0 ENABLE Enable Manchester Encoding 0x1 MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write UART Normal operation 0x0 RS485 RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data. 0x1 IDLELINE The UART operates in IDLE Line Mode 0x2 ADDR9BIT The UART operates in 9 Bit Address mode 0x3 SMART ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. 0x4 DALI DALI Mode: 0x5 FEN UART Enable FIFOs 0x11 0x1 read-write DISABLE The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 0x0 ENABLE The transmit and receive FIFO buffers are enabled (FIFO mode). 0x1 TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write LOW TXD pin is low 0x0 HIGH TXD pin is high 0x1 TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 0x5 0x1 read-write DISABLE TXD pin can not be controlled by TXD_OUT 0x0 ENABLE TXD pin can be controlled by TXD_OUT 0x1 MAJVOTE Majority Vote Enable When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (i.e. all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set. Oversampling of 16 : bits 7, 8, 9 are used Oversampling of 8 : bits 3, 4, 5 are used Disabled : Single sample value (center value) used 0x12 0x1 read-write DISABLE Majority voting is disabled 0x0 ENABLE Majority voting is enabled 0x1 MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write DISABLE Least significant bit is sent first in the protocol packet 0x0 ENABLE Most significant bit is sent first in the protocol packet 0x1 UART7_LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write DISABLE Normal use. 0x0 ENABLE A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0x1 PEN UART Parity Enable 0x1 0x1 read-write DISABLE Parity is disabled and no parity bit is added to the data frame. 0x0 ENABLE Parity checking and generation is enabled. 0x1 EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write ODD Odd parity is performed, which checks for an odd number of 1s. 0x0 EVEN Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0x1 STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write DISABLE One stop bit is transmitted at the end of a frame. 0x0 ENABLE Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid. 0x1 WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write DATABIT5 5 bits (default) 0x0 DATABIT6 6 bits 0x1 DATABIT7 7 bits 0x2 DATABIT8 8 bits 0x3 SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write DISABLE Disable Stick Parity 0x0 ENABLE Enable Stick Parity 0x1 SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write DISABLE Disable Send Idle Pattern 0x0 ENABLE Enable Send Idle Pattern 0x1 EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write UART7_STAT UART Status Register 0x1108 32 read-only BUSY UART Busy This bit is set as soon as the transmit FIFO or TXDATA register becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only CLEARED The UART is not busy. 0x0 SET The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register. 0x1 TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only CLEARED The transmitter is not full. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0x1 RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only CLEARED The receiver can receive data. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0x1 TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only CLEARED The transmitter has data to transmit. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0x1 CTS Clear To Send 0x8 0x1 read-only CLEARED The CTS signal is not asserted (high). 0x0 SET The CTS signal is asserted (low). 0x1 IDLE IDLE mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only CLEARED IDLE has not been detected before last received character. (In idle-line multiprocessor mode). 0x0 SET IDLE has been detected before last received character. (In idle-line multiprocessor mode). 0x1 RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only CLEARED The receiver is not empty. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0x1 UART7_IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_EMPTY TX FIFO is empty 0x5 LVL_1 TX FIFO >= 1 entry free Note: esp. required for DMA Trigger 0x7 RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write LVL_1_4_RES RX FIFO >= 1/4 full Note: For ULP Domain 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_FULL_RES RX FIFO is full Note: For ULP Domain 0x4 LVL_FULL RX FIFO is full 0x5 LVL_1 RX FIFO >= 1 entry available Note: esp. required for DMA Trigger 0x7 RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write UART7_IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write UART7_FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write UART7_GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. 0x9 0x2 read-write AGLIT_5 Pulses shorter then 5ns length are filtered. 0x0 AGLIT_10 Pulses shorter then 10ns length are filtered. 0x1 AGLIT_25 Pulses shorter then 25ns length are filtered. 0x2 AGLIT_50 Pulses shorter then 50ns length are filtered. 0x3 AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write DISABLE Analog Glitch Filter disable 0x0 ENABLE Analog Glitch Filter enable 0x1 DGFSEL Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The value programmed in this field gives the number of cycles of functional clock up to which the glitch has to be suppressed on the RX line. In IRDA mode: The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK) 0x0 0x6 read-write DISABLED Bypass GF 0x0 CHAIN Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0xB 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 UART7_TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write UART7_RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff DATA Received Data. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only CLR No framing error has occurred 0x0 SET The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1). 0x1 PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only CLR No parity error has occurred 0x0 SET The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0x1 BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only CLR No break condition has occurred 0x0 SET A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0x1 OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only CLR No data has been lost due to a receive overrun. 0x0 SET New data was received but could not be stored, because the previous data was not read (resulting in data loss). 0x1 NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only CLR No noise error occured 0x0 SET Noise error occured during majority voting 0x1 UART7_LINCNT UART LIN Mode Counter Register 0x1130 32 read-write 0x00000000 0xffffffff LINCNT 16 bit up counter clocked by the functional clock of the UART. 0x0 0x10 read-write UART7_LINCTL UART LIN Mode Control Register 0x1134 32 read-write 0x00000000 0xffffffff CTRENA LIN Counter Enable. LIN counter will only count when enabled. 0x0 0x1 read-write DISABLE Counter disabled 0x0 ENABLE Counter enabled 0x1 ZERONE Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD 0x1 0x1 read-write DISABLE Zero on negative edge disabled 0x0 ENABLE Zero on negative edge enabled 0x1 CNTRXLOW Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments. 0x2 0x1 read-write DISABLE Count while low Signal on UARTxRXD disabled 0x0 ENABLE Count while low Signal on UARTxRXD enabled 0x1 LINC0CAP Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled. 0x4 0x1 read-write DISABLE Capture counter on negative UARTxRXD edge disabled 0x0 ENABLE Capture counter on negative UARTxRXD edge enabled 0x1 LINC1CAP Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled. 0x5 0x1 read-write DISABLE Capture counter on positive UARTxRXD edge disabled 0x0 ENABLE Capture counter on positive UARTxRXD edge enabled 0x1 LINC0_MATCH Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled. 0x6 0x1 read-write DISABLE Counter compare match mode disabled (capture mode enabled) 0x0 ENABLE Counter compare match enabled (capture mode disabled) 0x1 UART7_LINC0 UART LIN Mode Capture 0 Register 0x1138 32 read-write 0x00000000 0xffffffff DATA 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge and can generate a LINC0 interrupt when capture is enabled (LINC0CAP = 1). If compare mode is enabled (LINC0_MATCH = 1), a counter match can generate a LINC0 interrupt. 0x0 0x10 read-write UART7_LINC1 UART LIN Mode Capture 1 Register 0x113C 32 read-write 0x00000000 0xffffffff DATA 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge and can generate a LINC1 interrupt when capture is enabled (LINC1CAP = 1) 0x0 0x10 read-write UART7_IRCTL eUSCI_Ax IrDA Control Word Register 0x1140 32 read-write 0x00000000 0x0000ffff IRTXPL Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / [2 * f(IRTXCLK)] (IRTXCLK = functional clock of the UART) 0x2 0x6 read-write IRRXPL IrDA receive input UCAxRXD polarity 0x9 0x1 read-write HIGH IrDA transceiver delivers a high pulse when a light pulse is seen 0x0 LOW IrDA transceiver delivers a low pulse when a light pulse is seen 0x1 IREN IrDA encoder/decoder enable 0x0 0x1 read-write DISABLE IrDA encoder/decoder disabled 0x0 ENABLE IrDA encoder/decoder enabled 0x1 IRTXCLK IrDA transmit pulse clock select 0x1 0x1 read-write BITCLK IrDA encode data is based on the functional clock. 0x0 BRCLK IrDA encode data is based on the Baud Rate clock< when select 8x oversampling, the IRTXPL cycle should less 8; when select 16x oversampling, the IRTXPL cycle should less 16. 0x1 UART7_AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff MSK Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register must match. 0x0 0x8 read-write UART7_ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh. 0x0 0x8 read-write UART7_CLKDIV2 Clock Divider 0x1160 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 UART4 UART 1.0 PERIPHERALREGION 0x40502000 0x0 0x1F00 registers 1 24 0 UART4_GPRCM[%s] 0x800 UART4_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 UART4_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 UART4_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 UART4_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 UART4_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 UART4_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 UART4_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 UART4_CPU_INT[%s] 0x1020 UART4_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 FEFG UART framing error interrupt; Interrupt Flag: FE 0x2 PEFG UART parity error interrupt; Interrupt Flag: PE 0x3 BEFG UART break error interrupt; Interrupt Flag: BE 0x4 OEFG UART receive overrun error interrupt; Interrupt Flag: OE 0x5 RXNE Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE 0x6 RXPE Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE 0x7 LINC0 LIN capture 0 / match interrupt; Interrupt Flag: LINC0 0x8 LINC1 LIN capture 1 interrupt; Interrupt Flag: LINC1 0x9 LINOVF LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF 0xA RXIFG UART receive interrupt; Interrupt Flag: RX 0xB TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC EOT UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT 0xD MODE_9B 9-bit mode address match interrupt; Interrupt Flag: MODE_9B 0xE CTS UART Clear to Send Modem interrupt; Interrupt Flag: CTS 0xF DMA_DONE_RX DMA DONE on RX 0x10 DMA_DONE_TX DMA DONE on TX 0x11 NERR_EVT Noise Error Event 0x12 UART4_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PARERR Enable UART Parity Error Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 BRKERR Enable UART Break Error Interrupt. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTS Enable UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX Enable DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX Enable DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART4_CPU_INT_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_RX DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_TX DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART4_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR Masked UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR Masked UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS Masked UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_RX Masked DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_TX Masked DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART4_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 FRMERR Set UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PARERR Set UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 BRKERR Set UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTS Set UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing this has no effect 0x0 SET Set the interrupt 0x1 UART4_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PARERR Clear UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 BRKERR Clear UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTS Clear UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART4_DMA_TRIG_RX[%s] 0x1050 UART4_DMA_TRIG_RX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 RXIFG UART receive interrupt; Interrupt Flag: RX 0xB UART4_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART4_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART4_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART4_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART4_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART4_DMA_TRIG_TX[%s] 0x1080 UART4_DMA_TRIG_TX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC UART4_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART4_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART4_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART4_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART4_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 UART4_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 UART4_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 UART4_CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write DISABLE Disable Module 0x0 ENABLE Enable module 0x1 HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write OVS16 16x oversampling. 0x0 OVS8 8x oversampling. 0x1 OVS3 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled. 0x2 LBE UART Loop Back Enable 0x2 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The UARTxTX path is fed through the UARTxRX path internally. 0x1 RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write DISABLE The receive section of the UART is disabled. 0x0 ENABLE The receive section of the UART is enabled. 0x1 TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write DISABLE The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled. 0x0 ENABLE The transmit section of the UART is enabled. 0x1 RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CLR Signal not RTS 0x0 SET Signal RTS 0x1 RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write DISABLE RTS hardware flow control is disabled. 0x0 ENABLE RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries. 0x1 CTSEN Enable Clear To Send 0xE 0x1 read-write DISABLE CTS hardware flow control is disabled. 0x0 ENABLE CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted. 0x1 MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write UART Normal operation 0x0 RS485 RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data. 0x1 IDLELINE The UART operates in IDLE Line Mode 0x2 ADDR9BIT The UART operates in 9 Bit Address mode 0x3 SMART ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. 0x4 DALI DALI Mode: 0x5 FEN UART Enable FIFOs 0x11 0x1 read-write DISABLE The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 0x0 ENABLE The transmit and receive FIFO buffers are enabled (FIFO mode). 0x1 TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write LOW TXD pin is low 0x0 HIGH TXD pin is high 0x1 TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 0x5 0x1 read-write DISABLE TXD pin can not be controlled by TXD_OUT 0x0 ENABLE TXD pin can be controlled by TXD_OUT 0x1 MAJVOTE Majority Vote Enable When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (i.e. all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set. Oversampling of 16 : bits 7, 8, 9 are used Oversampling of 8 : bits 3, 4, 5 are used Disabled : Single sample value (center value) used 0x12 0x1 read-write DISABLE Majority voting is disabled 0x0 ENABLE Majority voting is enabled 0x1 MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write DISABLE Least significant bit is sent first in the protocol packet 0x0 ENABLE Most significant bit is sent first in the protocol packet 0x1 UART4_LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write DISABLE Normal use. 0x0 ENABLE A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0x1 PEN UART Parity Enable 0x1 0x1 read-write DISABLE Parity is disabled and no parity bit is added to the data frame. 0x0 ENABLE Parity checking and generation is enabled. 0x1 EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write ODD Odd parity is performed, which checks for an odd number of 1s. 0x0 EVEN Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0x1 STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write DISABLE One stop bit is transmitted at the end of a frame. 0x0 ENABLE Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid. 0x1 WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write DATABIT5 5 bits (default) 0x0 DATABIT6 6 bits 0x1 DATABIT7 7 bits 0x2 DATABIT8 8 bits 0x3 SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write DISABLE Disable Stick Parity 0x0 ENABLE Enable Stick Parity 0x1 SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write DISABLE Disable Send Idle Pattern 0x0 ENABLE Enable Send Idle Pattern 0x1 EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write UART4_STAT UART Status Register 0x1108 32 read-only BUSY UART Busy This bit is set as soon as the transmit FIFO or TXDATA register becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only CLEARED The UART is not busy. 0x0 SET The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register. 0x1 TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only CLEARED The transmitter is not full. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0x1 RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only CLEARED The receiver can receive data. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0x1 TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only CLEARED The transmitter has data to transmit. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0x1 CTS Clear To Send 0x8 0x1 read-only CLEARED The CTS signal is not asserted (high). 0x0 SET The CTS signal is asserted (low). 0x1 IDLE IDLE mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only CLEARED IDLE has not been detected before last received character. (In idle-line multiprocessor mode). 0x0 SET IDLE has been detected before last received character. (In idle-line multiprocessor mode). 0x1 RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only CLEARED The receiver is not empty. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0x1 UART4_IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_EMPTY TX FIFO is empty 0x5 LVL_1 TX FIFO >= 1 entry free Note: esp. required for DMA Trigger 0x7 RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write LVL_1_4_RES RX FIFO >= 1/4 full Note: For ULP Domain 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_FULL_RES RX FIFO is full Note: For ULP Domain 0x4 LVL_FULL RX FIFO is full 0x5 LVL_1 RX FIFO >= 1 entry available Note: esp. required for DMA Trigger 0x7 RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write UART4_IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write UART4_FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write UART4_GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb CHAIN Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0xB 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 UART4_TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write UART4_RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff DATA Received Data. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only CLR No framing error has occurred 0x0 SET The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1). 0x1 PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only CLR No parity error has occurred 0x0 SET The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0x1 BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only CLR No break condition has occurred 0x0 SET A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0x1 OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only CLR No data has been lost due to a receive overrun. 0x0 SET New data was received but could not be stored, because the previous data was not read (resulting in data loss). 0x1 NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only CLR No noise error occured 0x0 SET Noise error occured during majority voting 0x1 UART4_AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff MSK Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register must match. 0x0 0x8 read-write UART4_ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh. 0x0 0x8 read-write GPIOC GPIOC 1.0 PERIPHERALREGION 0x400A4000 0x0 0x1F00 registers GPIOC_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOC_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOC_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 GPIOC_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 GPIOC_GPRCM[%s] 0x800 GPIOC_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 GPIOC_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 GPIOC_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 GPIOC_CLKOVR Clock Override 0x1010 32 read-write 0x00000000 OVERRIDE Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request 0x0 0x1 read-write DISABLED Override disabled 0x0 ENABLED Override enabled 0x1 RUN_STOP If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system 0x1 0x1 read-write RUN Run/ungate functional clock 0x0 STOP Stop/gate functional clock 0x1 GPIOC_PDBGCTL Peripheral Debug Control 0x1018 32 read-write 0x00000001 FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 1 44 0 GPIOC_CPU_INT[%s] 0x1020 GPIOC_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO0 DIO0 interrupt 0x1 DIO1 DIO1 interrupt 0x2 DIO2 DIO2 interrupt 0x3 DIO3 DIO3 interrupt 0x4 DIO4 DIO4 interrupt 0x5 DIO5 DIO5 interrupt 0x6 DIO6 DIO6 interrupt 0x7 DIO7 DIO7 interrupt 0x8 DIO8 DIO8 interrupt 0x9 DIO9 DIO9 interrupt 0xA DIO10 DIO10 interrupt 0xB DIO11 DIO11 interrupt 0xC DIO12 DIO12 interrupt 0xD DIO13 DIO13 interrupt 0xE DIO14 DIO14 interrupt 0xF DIO15 DIO15 interrupt 0x10 DIO16 DIO16 interrupt 0x11 DIO17 DIO17 interrupt 0x12 DIO18 DIO18 interrupt 0x13 DIO19 DIO19 interrupt 0x14 DIO20 DIO20 interrupt 0x15 DIO21 DIO21 interrupt 0x16 DIO22 DIO22 interrupt 0x17 DIO23 DIO23 interrupt 0x18 DIO24 DIO24 interrupt 0x19 DIO25 DIO25 interrupt 0x1A DIO26 DIO26 interrupt 0x1B DIO27 DIO27 interrupt 0x1C DIO28 DIO28 interrupt 0x1D DIO29 DIO29 interrupt 0x1E DIO30 DIO30 interrupt 0x1F DIO31 DIO31 interrupt 0x20 GPIOC_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO0 DIO0 event mask 0x0 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO1 DIO1 event mask 0x1 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO2 DIO2 event mask 0x2 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO3 DIO3 event mask 0x3 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO4 DIO4 event mask 0x4 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO5 DIO5 event mask 0x5 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO6 DIO6 event mask 0x6 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO7 DIO7 event mask 0x7 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO8 DIO8 event mask 0x8 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO9 DIO9 event mask 0x9 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO10 DIO10 event mask 0xA 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO11 DIO11 event mask 0xB 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO12 DIO12 event mask 0xC 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO13 DIO13 event mask 0xD 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO14 DIO14 event mask 0xE 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO15 DIO15 event mask 0xF 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO16 DIO16 event mask 0x10 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO17 DIO17 event mask 0x11 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO18 DIO18 event mask 0x12 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO19 DIO19 event mask 0x13 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO20 DIO20 event mask 0x14 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO21 DIO21 event mask 0x15 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO22 DIO22 event mask 0x16 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO23 DIO23 event mask 0x17 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO24 DIO24 event mask 0x18 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO25 DIO25 event mask 0x19 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO26 DIO26 event mask 0x1A 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO27 DIO27 event mask 0x1B 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO28 DIO28 event mask 0x1C 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO29 DIO29 event mask 0x1D 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO30 DIO30 event mask 0x1E 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO31 DIO31 event mask 0x1F 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOC_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOC_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOC_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 SET Sets DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 SET Sets DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 SET Sets DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 SET Sets DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 SET Sets DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 SET Sets DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 SET Sets DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 SET Sets DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 SET Sets DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 SET Sets DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 SET Sets DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 SET Sets DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 SET Sets DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 SET Sets DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 SET Sets DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 SET Sets DIO15 in RIS register 0x1 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 SET Sets DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 SET Sets DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 SET Sets DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 SET Sets DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 SET Sets DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 SET Sets DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 SET Sets DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 SET Sets DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 SET Sets DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 SET Sets DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 SET Sets DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 SET Sets DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 SET Sets DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 SET Sets DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 SET Sets DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 SET Sets DIO31 in RIS register 0x1 GPIOC_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO15 in RIS register 0x1 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO31 in RIS register 0x1 1 44 0 GPIOC_GEN_EVENT0[%s] 0x1050 GPIOC_GEN_EVENT0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO0 DIO0 interrupt 0x1 DIO1 DIO1 interrupt 0x2 DIO2 DIO2 interrupt 0x3 DIO3 DIO3 interrupt 0x4 DIO4 DIO4 interrupt 0x5 DIO5 DIO5 interrupt 0x6 DIO6 DIO6 interrupt 0x7 DIO7 DIO7 interrupt 0x8 DIO8 DIO8 interrupt 0x9 DIO9 DIO9 interrupt 0xA DIO10 DIO10 interrupt 0xB DIO11 DIO11 interrupt 0xC DIO12 DIO12 interrupt 0xD DIO13 DIO13 interrupt 0xE DIO14 DIO14 interrupt 0xF DIO15 DIO15 interrupt 0x10 GPIOC_GEN_EVENT0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO0 DIO0 event mask 0x0 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO1 DIO1 event mask 0x1 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO2 DIO2 event mask 0x2 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO3 DIO3 event mask 0x3 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO4 DIO4 event mask 0x4 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO5 DIO5 event mask 0x5 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO6 DIO6 event mask 0x6 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO7 DIO7 event mask 0x7 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO8 DIO8 event mask 0x8 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO9 DIO9 event mask 0x9 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO10 DIO10 event mask 0xA 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO11 DIO11 event mask 0xB 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO12 DIO12 event mask 0xC 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO13 DIO13 event mask 0xD 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO14 DIO14 event mask 0xE 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO15 DIO15 event mask 0xF 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOC_GEN_EVENT0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 GPIOC_GEN_EVENT0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO0 DIO0 event 0x0 0x1 CLR DIO0 event did not occur 0x0 SET DIO0 event occurred 0x1 DIO1 DIO1 event 0x1 0x1 CLR DIO1 event did not occur 0x0 SET DIO1 event occurred 0x1 DIO2 DIO2 event 0x2 0x1 CLR DIO2 event did not occur 0x0 SET DIO2 event occurred 0x1 DIO3 DIO3 event 0x3 0x1 CLR DIO3 event did not occur 0x0 SET DIO3 event occurred 0x1 DIO4 DIO4 event 0x4 0x1 CLR DIO4 event did not occur 0x0 SET DIO4 event occurred 0x1 DIO5 DIO5 event 0x5 0x1 CLR DIO5 event did not occur 0x0 SET DIO5 event occurred 0x1 DIO6 DIO6 event 0x6 0x1 CLR DIO6 event did not occur 0x0 SET DIO6 event occurred 0x1 DIO7 DIO7 event 0x7 0x1 CLR DIO7 event did not occur 0x0 SET DIO7 event occurred 0x1 DIO8 DIO8 event 0x8 0x1 CLR DIO8 event did not occur 0x0 SET DIO8 event occurred 0x1 DIO9 DIO9 event 0x9 0x1 CLR DIO9 event did not occur 0x0 SET DIO9 event occurred 0x1 DIO10 DIO10 event 0xA 0x1 CLR DIO10 event did not occur 0x0 SET DIO10 event occurred 0x1 DIO11 DIO11 event 0xB 0x1 CLR DIO11 event did not occur 0x0 SET DIO11 event occurred 0x1 DIO12 DIO12 event 0xC 0x1 CLR DIO12 event did not occur 0x0 SET DIO12 event occurred 0x1 DIO13 DIO13 event 0xD 0x1 CLR DIO13 event did not occur 0x0 SET DIO13 event occurred 0x1 DIO14 DIO14 event 0xE 0x1 CLR DIO14 event did not occur 0x0 SET DIO14 event occurred 0x1 DIO15 DIO15 event 0xF 0x1 CLR DIO15 event did not occur 0x0 SET DIO15 event occurred 0x1 GPIOC_GEN_EVENT0_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 SET Sets DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 SET Sets DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 SET Sets DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 SET Sets DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 SET Sets DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 SET Sets DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 SET Sets DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 SET Sets DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 SET Sets DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 SET Sets DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 SET Sets DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 SET Sets DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 SET Sets DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 SET Sets DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 SET Sets DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 SET Sets DIO15 in RIS register 0x1 GPIOC_GEN_EVENT0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO0 DIO0 event 0x0 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO0 in RIS register 0x1 DIO1 DIO1 event 0x1 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO1 in RIS register 0x1 DIO2 DIO2 event 0x2 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO2 in RIS register 0x1 DIO3 DIO3 event 0x3 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO3 in RIS register 0x1 DIO4 DIO4 event 0x4 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO4 in RIS register 0x1 DIO5 DIO5 event 0x5 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO5 in RIS register 0x1 DIO6 DIO6 event 0x6 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO6 in RIS register 0x1 DIO7 DIO7 event 0x7 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO7 in RIS register 0x1 DIO8 DIO8 event 0x8 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO8 in RIS register 0x1 DIO9 DIO9 event 0x9 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO9 in RIS register 0x1 DIO10 DIO10 event 0xA 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO10 in RIS register 0x1 DIO11 DIO11 event 0xB 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO11 in RIS register 0x1 DIO12 DIO12 event 0xC 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO12 in RIS register 0x1 DIO13 DIO13 event 0xD 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO13 in RIS register 0x1 DIO14 DIO14 event 0xE 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO14 in RIS register 0x1 DIO15 DIO15 event 0xF 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO15 in RIS register 0x1 1 44 0 GPIOC_GEN_EVENT1[%s] 0x1080 GPIOC_GEN_EVENT1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 DIO16 DIO0 interrupt 0x1 DIO17 DIO1 interrupt 0x2 DIO18 DIO2 interrupt 0x3 DIO19 DIO3 interrupt 0x4 DIO20 DIO4 interrupt 0x5 DIO21 DIO5 interrupt 0x6 DIO22 DIO6 interrupt 0x7 DIO23 DIO7 interrupt 0x8 DIO24 DIO8 interrupt 0x9 DIO25 DIO9 interrupt 0xA DIO26 DIO10 interrupt 0xB DIO27 DIO11 interrupt 0xC DIO28 DIO12 interrupt 0xD DIO29 DIO13 interrupt 0xE DIO30 DIO14 interrupt 0xF DIO31 DIO15 interrupt 0x10 GPIOC_GEN_EVENT1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 DIO16 DIO16 event mask 0x10 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO17 DIO17 event mask 0x11 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO18 DIO18 event mask 0x12 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO19 DIO19 event mask 0x13 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO20 DIO20 event mask 0x14 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO21 DIO21 event mask 0x15 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO22 DIO22 event mask 0x16 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO23 DIO23 event mask 0x17 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO24 DIO24 event mask 0x18 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO25 DIO25 event mask 0x19 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO26 DIO26 event mask 0x1A 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO27 DIO27 event mask 0x1B 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO28 DIO28 event mask 0x1C 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO29 DIO29 event mask 0x1D 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO30 DIO30 event mask 0x1E 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 DIO31 DIO31 event mask 0x1F 0x1 CLR Event is masked 0x0 SET Event is unmasked 0x1 GPIOC_GEN_EVENT1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOC_GEN_EVENT1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 DIO16 DIO16 event 0x10 0x1 CLR DIO16 event did not occur 0x0 SET DIO16 event occurred 0x1 DIO17 DIO17 event 0x11 0x1 CLR DIO17 event did not occur 0x0 SET DIO17 event occurred 0x1 DIO18 DIO18 event 0x12 0x1 CLR DIO18 event did not occur 0x0 SET DIO18 event occurred 0x1 DIO19 DIO19 event 0x13 0x1 CLR DIO19 event did not occur 0x0 SET DIO19 event occurred 0x1 DIO20 DIO20 event 0x14 0x1 CLR DIO20 event did not occur 0x0 SET DIO20 event occurred 0x1 DIO21 DIO21 event 0x15 0x1 CLR DIO21 event did not occur 0x0 SET DIO21 event occurred 0x1 DIO22 DIO22 event 0x16 0x1 CLR DIO22 event did not occur 0x0 SET DIO22 event occurred 0x1 DIO23 DIO23 event 0x17 0x1 CLR DIO23 event did not occur 0x0 SET DIO23 event occurred 0x1 DIO24 DIO24 event 0x18 0x1 CLR DIO24 event did not occur 0x0 SET DIO24 event occurred 0x1 DIO25 DIO25 event 0x19 0x1 CLR DIO25 event did not occur 0x0 SET DIO25 event occurred 0x1 DIO26 DIO26 event 0x1A 0x1 CLR DIO26 event did not occur 0x0 SET DIO26 event occurred 0x1 DIO27 DIO27 event 0x1B 0x1 CLR DIO27 event did not occur 0x0 SET DIO27 event occurred 0x1 DIO28 DIO28 event 0x1C 0x1 CLR DIO28 event did not occur 0x0 SET DIO28 event occurred 0x1 DIO29 DIO29 event 0x1D 0x1 CLR DIO29 event did not occur 0x0 SET DIO29 event occurred 0x1 DIO30 DIO30 event 0x1E 0x1 CLR DIO30 event did not occur 0x0 SET DIO30 event occurred 0x1 DIO31 DIO31 event 0x1F 0x1 CLR DIO31 event did not occur 0x0 SET DIO31 event occurred 0x1 GPIOC_GEN_EVENT1_ISET Interrupt set 0x20 32 write-only 0x00000000 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 SET Sets DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 SET Sets DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 SET Sets DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 SET Sets DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 SET Sets DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 SET Sets DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 SET Sets DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 SET Sets DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 SET Sets DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 SET Sets DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 SET Sets DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 SET Sets DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 SET Sets DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 SET Sets DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 SET Sets DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 SET Sets DIO31 in RIS register 0x1 GPIOC_GEN_EVENT1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 DIO16 DIO16 event 0x10 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO16 in RIS register 0x1 DIO17 DIO17 event 0x11 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO17 in RIS register 0x1 DIO18 DIO18 event 0x12 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO18 in RIS register 0x1 DIO19 DIO19 event 0x13 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO19 in RIS register 0x1 DIO20 DIO20 event 0x14 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO20 in RIS register 0x1 DIO21 DIO21 event 0x15 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO21 in RIS register 0x1 DIO22 DIO22 event 0x16 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO22 in RIS register 0x1 DIO23 DIO23 event 0x17 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO23 in RIS register 0x1 DIO24 DIO24 event 0x18 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO24 in RIS register 0x1 DIO25 DIO25 event 0x19 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO25 in RIS register 0x1 DIO26 DIO26 event 0x1A 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO26 in RIS register 0x1 DIO27 DIO27 event 0x1B 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO27 in RIS register 0x1 DIO28 DIO28 event 0x1C 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO28 in RIS register 0x1 DIO29 DIO29 event 0x1D 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO29 in RIS register 0x1 DIO30 DIO30 event 0x1E 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO30 in RIS register 0x1 DIO31 DIO31 event 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clears DIO31 in RIS register 0x1 GPIOC_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 GPIOC_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 GPIOC_DOUT3_0 Data output 3 to 0 0x1200 32 write-only 0x00000000 DIO0 This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO1 This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO2 This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO3 This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUT7_4 Data output 7 to 4 0x1204 32 write-only 0x00000000 DIO4 This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO5 This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO6 This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO7 This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUT11_8 Data output 11 to 8 0x1208 32 write-only 0x00000000 DIO8 This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO9 This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO10 This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO11 This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUT15_12 Data output 15 to 12 0x120C 32 write-only 0x00000000 DIO12 This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO13 This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO14 This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO15 This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUT19_16 Data output 19 to 16 0x1210 32 write-only 0x00000000 DIO16 This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO17 This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO18 This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO19 This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUT23_20 Data output 23 to 20 0x1214 32 write-only 0x00000000 DIO20 This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO21 This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO22 This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO23 This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUT27_24 Data output 27 to 24 0x1218 32 write-only 0x00000000 DIO24 This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO25 This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO26 This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO27 This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUT31_28 Data output 31 to 28 0x121C 32 write-only 0x00000000 DIO28 This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO29 This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO30 This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO31 This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUT31_0 Data output 31 to 0 0x1280 32 read-write 0x00000000 DIO0 This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register. 0x0 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO1 This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register. 0x1 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO2 This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register. 0x2 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO3 This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register. 0x3 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO4 This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register. 0x4 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO5 This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register. 0x5 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO6 This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register. 0x6 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO7 This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register. 0x7 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO8 This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register. 0x8 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO9 This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register. 0x9 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO10 This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register. 0xA 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO11 This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register. 0xB 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO12 This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register. 0xC 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO13 This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register. 0xD 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO14 This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register. 0xE 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO15 This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register. 0xF 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO16 This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register. 0x10 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO17 This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register. 0x11 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO18 This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register. 0x12 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO19 This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register. 0x13 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO20 This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register. 0x14 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO21 This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register. 0x15 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO22 This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register. 0x16 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO23 This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register. 0x17 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO24 This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register. 0x18 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO25 This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register. 0x19 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO26 This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register. 0x1A 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO27 This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register. 0x1B 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO28 This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register. 0x1C 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO29 This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register. 0x1D 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO30 This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register. 0x1E 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 DIO31 This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register. 0x1F 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 GPIOC_DOUTSET31_0 Data output set 31 to 0 0x1290 32 write-only 0x00000000 DIO0 Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO0 in DOUT31_0 0x1 DIO1 Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO1 in DOUT31_0 0x1 DIO2 Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO2 in DOUT31_0 0x1 DIO3 Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO3 in DOUT31_0 0x1 DIO4 Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO4 in DOUT31_0 0x1 DIO5 Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO5 in DOUT31_0 0x1 DIO6 Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO6 in DOUT31_0 0x1 DIO7 Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO7 in DOUT31_0 0x1 DIO8 Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO8 in DOUT31_0 0x1 DIO9 Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO9 in DOUT31_0 0x1 DIO10 Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO10 in DOUT31_0 0x1 DIO11 Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO11 in DOUT31_0 0x1 DIO12 Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO12 in DOUT31_0 0x1 DIO13 Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO13 in DOUT31_0 0x1 DIO14 Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO14 in DOUT31_0 0x1 DIO15 Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO15 in DOUT31_0 0x1 DIO16 Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO16 in DOUT31_0 0x1 DIO17 Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO17 in DOUT31_0 0x1 DIO18 Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO18 in DOUT31_0 0x1 DIO19 Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO19 in DOUT31_0 0x1 DIO20 Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO20 in DOUT31_0 0x1 DIO21 Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO21 in DOUT31_0 0x1 DIO22 Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO22 in DOUT31_0 0x1 DIO23 Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO23 in DOUT31_0 0x1 DIO24 Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO24 in DOUT31_0 0x1 DIO25 Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO25 in DOUT31_0 0x1 DIO26 Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO26 in DOUT31_0 0x1 DIO27 Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO27 in DOUT31_0 0x1 DIO28 Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO28 in DOUT31_0 0x1 DIO29 Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO29 in DOUT31_0 0x1 DIO30 Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO30 in DOUT31_0 0x1 DIO31 Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO31 in DOUT31_0 0x1 GPIOC_DOUTCLR31_0 Data output clear 31 to 0 0x12A0 32 write-only 0x00000000 DIO0 Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO0 in DOUT31_0 0x1 DIO1 Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO1 in DOUT31_0 0x1 DIO2 Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO2 in DOUT31_0 0x1 DIO3 Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO3 in DOUT31_0 0x1 DIO4 Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO4 in DOUT31_0 0x1 DIO5 Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO5 in DOUT31_0 0x1 DIO6 Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO6 in DOUT31_0 0x1 DIO7 Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO7 in DOUT31_0 0x1 DIO8 Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO8 in DOUT31_0 0x1 DIO9 Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO9 in DOUT31_0 0x1 DIO10 Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO10 in DOUT31_0 0x1 DIO11 Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO11 in DOUT31_0 0x1 DIO12 Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO12 in DOUT31_0 0x1 DIO13 Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO13 in DOUT31_0 0x1 DIO14 Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO14 in DOUT31_0 0x1 DIO15 Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO15 in DOUT31_0 0x1 DIO16 Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO16 in DOUT31_0 0x1 DIO17 Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO17 in DOUT31_0 0x1 DIO18 Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO18 in DOUT31_0 0x1 DIO19 Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO19 in DOUT31_0 0x1 DIO20 Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO20 in DOUT31_0 0x1 DIO21 Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO21 in DOUT31_0 0x1 DIO22 Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO22 in DOUT31_0 0x1 DIO23 Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO23 in DOUT31_0 0x1 DIO24 Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO24 in DOUT31_0 0x1 DIO25 Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO25 in DOUT31_0 0x1 DIO26 Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO26 in DOUT31_0 0x1 DIO27 Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO27 in DOUT31_0 0x1 DIO28 Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO28 in DOUT31_0 0x1 DIO29 Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO29 in DOUT31_0 0x1 DIO30 Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO30 in DOUT31_0 0x1 DIO31 Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO31 in DOUT31_0 0x1 GPIOC_DOUTTGL31_0 Data output toggle 31 to 0 0x12B0 32 write-only 0x00000000 DIO0 This bit is used to toggle DIO0 output. 0x0 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO1 This bit is used to toggle DIO1 output. 0x1 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO2 This bit is used to toggle DIO2 output. 0x2 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO3 This bit is used to toggle DIO3 output. 0x3 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO4 This bit is used to toggle DIO4 output. 0x4 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO5 This bit is used to toggle DIO5 output. 0x5 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO6 This bit is used to toggle DIO6 output. 0x6 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO7 This bit is used to toggle DIO7 output. 0x7 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO8 This bit is used to toggle DIO8 output. 0x8 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO9 This bit is used to toggle DIO9 output. 0x9 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO10 This bit is used to toggle DIO10 output. 0xA 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO11 This bit is used to toggle DIO11 output. 0xB 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO12 This bit is used to toggle DIO12 output. 0xC 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO13 This bit is used to toggle DIO13 output. 0xD 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO14 This bit is used to toggle DIO14 output. 0xE 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO15 This bit is used to toggle DIO15 output. 0xF 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO16 This bit is used to toggle DIO16 output. 0x10 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO17 This bit is used to toggle DIO17 output. 0x11 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO18 This bit is used to toggle DIO18 output. 0x12 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO19 This bit is used to toggle DIO19 output. 0x13 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO20 This bit is used to toggle DIO20 output. 0x14 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO21 This bit is used to toggle DIO21 output. 0x15 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO22 This bit is used to toggle DIO22 output. 0x16 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO23 This bit is used to toggle DIO23 output. 0x17 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO24 This bit is used to toggle DIO24 output. 0x18 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO25 This bit is used to toggle DIO25 output. 0x19 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO26 This bit is used to toggle DIO26 output. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO27 This bit is used to toggle DIO27 output. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO28 This bit is used to toggle DIO28 output. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO29 This bit is used to toggle DIO29 output. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO30 This bit is used to toggle DIO30 output. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 DIO31 This bit is used to toggle DIO31 output. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 TOGGLE Toggle output 0x1 GPIOC_DOE31_0 Data output enable 31 to 0 0x12C0 32 read-write 0x00000000 DIO0 Enables data output for DIO0. 0x0 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO1 Enables data output for DIO1. 0x1 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO2 Enables data output for DIO2. 0x2 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO3 Enables data output for DIO3. 0x3 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO4 Enables data output for DIO4. 0x4 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO5 Enables data output for DIO5. 0x5 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO6 Enables data output for DIO6. 0x6 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO7 Enables data output for DIO7. 0x7 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO8 Enables data output for DIO8. 0x8 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO9 Enables data output for DIO9. 0x9 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO10 Enables data output for DIO10. 0xA 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO11 Enables data output for DIO11. 0xB 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO12 Enables data output for DIO12. 0xC 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO13 Enables data output for DIO13. 0xD 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO14 Enables data output for DIO14. 0xE 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO15 Enables data output for DIO15. 0xF 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO16 Enables data output for DIO16. 0x10 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO17 Enables data output for DIO17. 0x11 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO18 Enables data output for DIO18. 0x12 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO19 Enables data output for DIO19. 0x13 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO20 Enables data output for DIO20. 0x14 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO21 Enables data output for DIO21. 0x15 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO22 Enables data output for DIO22. 0x16 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO23 Enables data output for DIO23. 0x17 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO24 Enables data output for DIO24. 0x18 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO25 Enables data output for DIO25. 0x19 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO26 Enables data output for DIO26. 0x1A 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO27 Enables data output for DIO27. 0x1B 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO28 Enables data output for DIO28. 0x1C 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO29 Enables data output for DIO29. 0x1D 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO30 Enables data output for DIO30. 0x1E 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 DIO31 Enables data output for DIO31. 0x1F 0x1 read-write DISABLE Output disabled 0x0 ENABLE Output enabled 0x1 GPIOC_DOESET31_0 Data output enable set 31 to 0 0x12D0 32 write-only 0x00000000 DIO0 Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO0 in DOE31_0 0x1 DIO1 Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO1 in DOE31_0 0x1 DIO2 Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO2 in DOE31_0 0x1 DIO3 Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO3 in DOE31_0 0x1 DIO4 Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO4 in DOE31_0 0x1 DIO5 Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO5 in DOE31_0 0x1 DIO6 Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO6 in DOE31_0 0x1 DIO7 Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO7 in DOE31_0 0x1 DIO8 Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO8 in DOE31_0 0x1 DIO9 Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO9 in DOE31_0 0x1 DIO10 Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO10 in DOE31_0 0x1 DIO11 Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO11 in DOE31_0 0x1 DIO12 Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO12 in DOE31_0 0x1 DIO13 Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO13 in DOE31_0 0x1 DIO14 Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO14 in DOE31_0 0x1 DIO15 Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO15 in DOE31_0 0x1 DIO16 Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO16 in DOE31_0 0x1 DIO17 Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO17 in DOE31_0 0x1 DIO18 Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO18 in DOE31_0 0x1 DIO19 Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO19 in DOE31_0 0x1 DIO20 Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO20 in DOE31_0 0x1 DIO21 Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO21 in DOE31_0 0x1 DIO22 Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO22 in DOE31_0 0x1 DIO23 Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO23 in DOE31_0 0x1 DIO24 Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO24 in DOE31_0 0x1 DIO25 Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO25 in DOE31_0 0x1 DIO26 Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO26 in DOE31_0 0x1 DIO27 Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO27 in DOE31_0 0x1 DIO28 Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO28 in DOE31_0 0x1 DIO29 Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO29 in DOE31_0 0x1 DIO30 Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO30 in DOE31_0 0x1 DIO31 Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 SET Sets DIO31 in DOE31_0 0x1 GPIOC_DOECLR31_0 Data output enable clear 31 to 0 0x12E0 32 write-only 0x00000000 DIO0 Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect. 0x0 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO0 in DOE31_0 0x1 DIO1 Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect. 0x1 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO1 in DOE31_0 0x1 DIO2 Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect. 0x2 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO2 in DOE31_0 0x1 DIO3 Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect. 0x3 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO3 in DOE31_0 0x1 DIO4 Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect. 0x4 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO4 in DOE31_0 0x1 DIO5 Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect. 0x5 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO5 in DOE31_0 0x1 DIO6 Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect. 0x6 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO6 in DOE31_0 0x1 DIO7 Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect. 0x7 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO7 in DOE31_0 0x1 DIO8 Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect. 0x8 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO8 in DOE31_0 0x1 DIO9 Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect. 0x9 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO9 in DOE31_0 0x1 DIO10 Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect. 0xA 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO10 in DOE31_0 0x1 DIO11 Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect. 0xB 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO11 in DOE31_0 0x1 DIO12 Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect. 0xC 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO12 in DOE31_0 0x1 DIO13 Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect. 0xD 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO13 in DOE31_0 0x1 DIO14 Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect. 0xE 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO14 in DOE31_0 0x1 DIO15 Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect. 0xF 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO15 in DOE31_0 0x1 DIO16 Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect. 0x10 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO16 in DOE31_0 0x1 DIO17 Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect. 0x11 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO17 in DOE31_0 0x1 DIO18 Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect. 0x12 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO18 in DOE31_0 0x1 DIO19 Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect. 0x13 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO19 in DOE31_0 0x1 DIO20 Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect. 0x14 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO20 in DOE31_0 0x1 DIO21 Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect. 0x15 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO21 in DOE31_0 0x1 DIO22 Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect. 0x16 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO22 in DOE31_0 0x1 DIO23 Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect. 0x17 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO23 in DOE31_0 0x1 DIO24 Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect. 0x18 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO24 in DOE31_0 0x1 DIO25 Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect. 0x19 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO25 in DOE31_0 0x1 DIO26 Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO26 in DOE31_0 0x1 DIO27 Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO27 in DOE31_0 0x1 DIO28 Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO28 in DOE31_0 0x1 DIO29 Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO29 in DOE31_0 0x1 DIO30 Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO30 in DOE31_0 0x1 DIO31 Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only NO_EFFECT No effect 0x0 CLR Clears DIO31 in DOE31_0 0x1 GPIOC_DIN3_0 Data input 3 to 0 0x1300 32 read-only 0x00000000 DIO0 This bit reads the data input value of DIO0. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO1 This bit reads the data input value of DIO1. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO2 This bit reads the data input value of DIO2. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO3 This bit reads the data input value of DIO3. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_DIN7_4 Data input 7 to 4 0x1304 32 read-only 0x00000000 DIO4 This bit reads the data input value of DIO4. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO5 This bit reads the data input value of DIO5. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO6 This bit reads the data input value of DIO6. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO7 This bit reads the data input value of DIO7. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_DIN11_8 Data input 11 to 8 0x1308 32 read-only 0x00000000 DIO8 This bit reads the data input value of DIO8. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO9 This bit reads the data input value of DIO9. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO10 This bit reads the data input value of DIO10. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO11 This bit reads the data input value of DIO11. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_DIN15_12 Data input 15 to 12 0x130C 32 read-only 0x00000000 DIO12 This bit reads the data input value of DIO12. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO13 This bit reads the data input value of DIO13. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO14 This bit reads the data input value of DIO14. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO15 This bit reads the data input value of DIO15. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_DIN19_16 Data input 19 to 16 0x1310 32 read-only 0x00000000 DIO16 This bit reads the data input value of DIO16. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO17 This bit reads the data input value of DIO17. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO18 This bit reads the data input value of DIO18. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO19 This bit reads the data input value of DIO19. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_DIN23_20 Data input 23 to 20 0x1314 32 read-only 0x00000000 DIO20 This bit reads the data input value of DIO20. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO21 This bit reads the data input value of DIO21. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO22 This bit reads the data input value of DIO22. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO23 This bit reads the data input value of DIO23. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_DIN27_24 Data input 27 to 24 0x1318 32 read-only 0x00000000 DIO24 This bit reads the data input value of DIO24. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO25 This bit reads the data input value of DIO25. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO26 This bit reads the data input value of DIO26. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO27 This bit reads the data input value of DIO27. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_DIN31_28 Data input 31 to 28 0x131C 32 read-only 0x00000000 DIO28 This bit reads the data input value of DIO28. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO29 This bit reads the data input value of DIO29. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO30 This bit reads the data input value of DIO30. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO31 This bit reads the data input value of DIO31. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_DIN31_0 Data input 31 to 0 0x1380 32 read-only 0x00000000 DIO0 This bit reads the data input value of DIO0. 0x0 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO1 This bit reads the data input value of DIO1. 0x1 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO2 This bit reads the data input value of DIO2. 0x2 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO3 This bit reads the data input value of DIO3. 0x3 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO4 This bit reads the data input value of DIO4. 0x4 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO5 This bit reads the data input value of DIO5. 0x5 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO6 This bit reads the data input value of DIO6. 0x6 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO7 This bit reads the data input value of DIO7. 0x7 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO8 This bit reads the data input value of DIO8. 0x8 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO9 This bit reads the data input value of DIO9. 0x9 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO10 This bit reads the data input value of DIO10. 0xA 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO11 This bit reads the data input value of DIO11. 0xB 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO12 This bit reads the data input value of DIO12. 0xC 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO13 This bit reads the data input value of DIO13. 0xD 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO14 This bit reads the data input value of DIO14. 0xE 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO15 This bit reads the data input value of DIO15. 0xF 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO16 This bit reads the data input value of DIO16. 0x10 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO17 This bit reads the data input value of DIO17. 0x11 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO18 This bit reads the data input value of DIO18. 0x12 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO19 This bit reads the data input value of DIO19. 0x13 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO20 This bit reads the data input value of DIO20. 0x14 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO21 This bit reads the data input value of DIO21. 0x15 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO22 This bit reads the data input value of DIO22. 0x16 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO23 This bit reads the data input value of DIO23. 0x17 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO24 This bit reads the data input value of DIO24. 0x18 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO25 This bit reads the data input value of DIO25. 0x19 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO26 This bit reads the data input value of DIO26. 0x1A 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO27 This bit reads the data input value of DIO27. 0x1B 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO28 This bit reads the data input value of DIO28. 0x1C 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO29 This bit reads the data input value of DIO29. 0x1D 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO30 This bit reads the data input value of DIO30. 0x1E 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 DIO31 This bit reads the data input value of DIO31. 0x1F 0x1 read-only ZERO Input value is 0 0x0 ONE Input value is 1 0x1 GPIOC_POLARITY15_0 Polarity 15 to 0 0x1390 32 read-write 0x00000000 DIO0 Enables and configures edge detection polarity for DIO0. 0x0 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO1 Enables and configures edge detection polarity for DIO1. 0x2 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO2 Enables and configures edge detection polarity for DIO2. 0x4 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO3 Enables and configures edge detection polarity for DIO3. 0x6 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO4 Enables and configures edge detection polarity for DIO4. 0x8 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO5 Enables and configures edge detection polarity for DIO5. 0xA 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO6 Enables and configures edge detection polarity for DIO6. 0xC 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO7 Enables and configures edge detection polarity for DIO7. 0xE 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO8 Enables and configures edge detection polarity for DIO8. 0x10 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO9 Enables and configures edge detection polarity for DIO9. 0x12 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO10 Enables and configures edge detection polarity for DIO10. 0x14 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO11 Enables and configures edge detection polarity for DIO11. 0x16 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO12 Enables and configures edge detection polarity for DIO12. 0x18 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO13 Enables and configures edge detection polarity for DIO13. 0x1A 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO14 Enables and configures edge detection polarity for DIO14. 0x1C 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO15 Enables and configures edge detection polarity for DIO15. 0x1E 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 GPIOC_POLARITY31_16 Polarity 31 to 16 0x13A0 32 read-write 0x00000000 DIO16 Enables and configures edge detection polarity for DIO16. 0x0 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO17 Enables and configures edge detection polarity for DIO17. 0x2 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO18 Enables and configures edge detection polarity for DIO18. 0x4 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO19 Enables and configures edge detection polarity for DIO19. 0x6 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO20 Enables and configures edge detection polarity for DIO20. 0x8 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO21 Enables and configures edge detection polarity for DIO21. 0xA 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO22 Enables and configures edge detection polarity for DIO22. 0xC 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO23 Enables and configures edge detection polarity for DIO23. 0xE 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO24 Enables and configures edge detection polarity for DIO24. 0x10 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO25 Enables and configures edge detection polarity for DIO25. 0x12 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO26 Enables and configures edge detection polarity for DIO26. 0x14 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO27 Enables and configures edge detection polarity for DIO27. 0x16 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO28 Enables and configures edge detection polarity for DIO28. 0x18 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO29 Enables and configures edge detection polarity for DIO29. 0x1A 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO30 Enables and configures edge detection polarity for DIO30. 0x1C 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 DIO31 Enables and configures edge detection polarity for DIO31. 0x1E 0x2 read-write DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 RISE_FALL Detects both rising and falling edge of input event 0x3 GPIOC_CTL FAST WAKE GLOBAL EN 0x1400 32 read-write 0x00000000 FASTWAKEONLY FASTWAKEONLY for the global control of fastwake 0x0 0x1 read-write NOT_GLOBAL_EN The global control of fastwake is not enabled, per bit fast wake feature depends on FASTWAKE.DIN 0x0 GLOBAL_EN The global control of fastwake is enabled 0x1 GPIOC_FASTWAKE FAST WAKE ENABLE 0x1404 32 read-write 0x00000000 DIN0 Enable fastwake feature for DIN0 0x0 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN1 Enable fastwake feature for DIN1 0x1 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN2 Enable fastwake feature for DIN2 0x2 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN3 Enable fastwake feature for DIN3 0x3 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN4 Enable fastwake feature for DIN4 0x4 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN5 Enable fastwake feature for DIN5 0x5 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN6 Enable fastwake feature for DIN6 0x6 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN7 Enable fastwake feature for DIN7 0x7 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN8 Enable fastwake feature for DIN8 0x8 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN9 Enable fastwake feature for DIN9 0x9 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN10 Enable fastwake feature for DIN10 0xA 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN11 Enable fastwake feature for DIN11 0xB 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN12 Enable fastwake feature for DIN12 0xC 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN13 Enable fastwake feature for DIN13 0xD 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN14 Enable fastwake feature for DIN14 0xE 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN15 Enable fastwake feature for DIN15 0xF 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN16 Enable fastwake feature for DIN16 0x10 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN17 Enable fastwake feature for DIN17 0x11 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN18 Enable fastwake feature for DIN18 0x12 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN19 Enable fastwake feature for DIN19 0x13 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN20 Enable fastwake feature for DIN20 0x14 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN21 Enable fastwake feature for DIN21 0x15 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN22 Enable fastwake feature for DIN22 0x16 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN23 Enable fastwake feature for DIN23 0x17 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN24 Enable fastwake feature for DIN24 0x18 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN25 Enable fastwake feature for DIN25 0x19 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN26 Enable fastwake feature for DIN26 0x1A 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN27 Enable fastwake feature for DIN27 0x1B 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN28 Enable fastwake feature for DIN29 0x1C 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN29 Enable fastwake feature for DIN29 0x1D 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN30 Enable fastwake feature for DIN30 0x1E 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 DIN31 Enable fastwake feature for DIN31 0x1F 0x1 DISABLE fastwake feature is disabled 0x0 ENABLE fastwake feature is enabled 0x1 GPIOC_SUB0CFG Subscriber 0 configuration 0x1500 32 read-write 0x00000000 ENABLE This bit is used to enable subscriber 0 event. 0x0 0x1 read-write CLR Subscriber 0 event is disabled 0x0 SET Subscriber 0 event is enabled 0x1 OUTPOLICY These bits configure the output policy for subscriber 0 event. 0x8 0x2 read-write SET Selected DIO pins are set 0x0 CLR Selected DIO pins are cleared 0x1 TOGGLE Selected DIO pins are toggled 0x2 INDEX Indicates the specific bit among lower 16 bits that is targeted by the subscriber action 0x10 0x4 read-write MIN specific bit targeted by the subscriber action is bit0 0x0 MAX specific bit targeted by the subscriber action is bit15 0xF GPIOC_FILTEREN15_0 Filter Enable 15 to 0 0x1508 32 read-write 0x00000000 DIN0 Programmable counter length of digital glitch filter for DIN0 0x0 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN1 Programmable counter length of digital glitch filter for DIN1 0x2 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN2 Programmable counter length of digital glitch filter for DIN2 0x4 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN3 Programmable counter length of digital glitch filter for DIN3 0x6 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN4 Programmable counter length of digital glitch filter for DIN4 0x8 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN5 Programmable counter length of digital glitch filter for DIN5 0xA 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN6 Programmable counter length of digital glitch filter for DIN6 0xC 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN7 Programmable counter length of digital glitch filter for DIN7 0xE 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN8 Programmable counter length of digital glitch filter for DIN8 0x10 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN9 Programmable counter length of digital glitch filter for DIN9 0x12 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN10 Programmable counter length of digital glitch filter for DIN10 0x14 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN11 Programmable counter length of digital glitch filter for DIN11 0x16 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN12 Programmable counter length of digital glitch filter for DIN12 0x18 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN13 Programmable counter length of digital glitch filter for DIN13 0x1A 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN14 Programmable counter length of digital glitch filter for DIN14 0x1C 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN15 Programmable counter length of digital glitch filter for DIN15 0x1E 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 GPIOC_FILTEREN31_16 Filter Enable 31 to 16 0x150C 32 read-write 0x00000000 DIN16 Programmable counter length of digital glitch filter for DIN16 0x0 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN17 Programmable counter length of digital glitch filter for DIN17 0x2 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN18 Programmable counter length of digital glitch filter for DIN18 0x4 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN19 Programmable counter length of digital glitch filter for DIN19 0x6 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN20 Programmable counter length of digital glitch filter for DIN20 0x8 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN21 Programmable counter length of digital glitch filter for DIN21 0xA 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN22 Programmable counter length of digital glitch filter for DIN22 0xC 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN23 Programmable counter length of digital glitch filter for DIN23 0xE 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN24 Programmable counter length of digital glitch filter for DIN24 0x10 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN25 Programmable counter length of digital glitch filter for DIN25 0x12 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN26 Programmable counter length of digital glitch filter for DIN26 0x14 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN27 Programmable counter length of digital glitch filter for DIN27 0x16 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN28 Programmable counter length of digital glitch filter for DIN28 0x18 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN29 Programmable counter length of digital glitch filter for DIN29 0x1A 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN30 Programmable counter length of digital glitch filter for DIN30 0x1C 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 DIN31 Programmable counter length of digital glitch filter for DIN31 0x1E 0x2 DISABLE No additional filter beyond the CDC synchronization sample 0x0 ONE_CYCLE 1 ULPCLK minimum sample 0x1 THREE_CYCLE 3 ULPCLK minimum sample 0x2 EIGHT_CYCLE 8 ULPCLK minimum sample 0x3 GPIOC_DMAMASK DMA Write MASK 0x1510 32 read-write 0x00000000 DOUT0 DMA is allowed to modify DOUT0 0x0 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT1 DMA is allowed to modify DOUT1 0x1 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT2 DMA is allowed to modify DOUT2 0x2 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT3 DMA is allowed to modify DOUT3 0x3 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT4 DMA is allowed to modify DOUT4 0x4 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT5 DMA is allowed to modify DOUT5 0x5 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT6 DMA is allowed to modify DOUT6 0x6 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT7 DMA is allowed to modify DOUT7 0x7 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT8 DMA is allowed to modify DOUT8 0x8 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT9 DMA is allowed to modify DOUT9 0x9 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT10 DMA is allowed to modify DOUT10 0xA 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT11 DMA is allowed to modify DOUT11 0xB 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT12 DMA is allowed to modify DOUT12 0xC 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT13 DMA is allowed to modify DOUT13 0xD 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT14 DMA is allowed to modify DOUT14 0xE 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT15 DMA is allowed to modify DOUT15 0xF 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT16 DMA is allowed to modify DOUT16 0x10 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT17 DMA is allowed to modify DOUT17 0x11 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT18 DMA is allowed to modify DOUT18 0x12 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT19 DMA is allowed to modify DOUT19 0x13 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT20 DMA is allowed to modify DOUT20 0x14 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT21 DMA is allowed to modify DOUT21 0x15 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT22 DMA is allowed to modify DOUT22 0x16 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT23 DMA is allowed to modify DOUT23 0x17 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT24 DMA is allowed to modify DOUT24 0x18 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT25 DMA is allowed to modify DOUT25 0x19 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT26 DMA is allowed to modify DOUT26 0x1A 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT27 DMA is allowed to modify DOUT27 0x1B 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT28 DMA is allowed to modify DOUT28 0x1C 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT29 DMA is allowed to modify DOUT29 0x1D 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT30 DMA is allowed to modify DOUT30 0x1E 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 DOUT31 DMA is allowed to modify DOUT31 0x1F 0x1 DISABLE DMA is not allowed to modify this bit lane 0x0 ENABLE DMA is allowed to modify this bit lane 0x1 GPIOC_SUB1CFG Subscriber 1 configuration 0x1520 32 read-write 0x00000000 ENABLE This bit is used to enable subscriber 1 event. 0x0 0x1 read-write CLR Subscriber 1 event is disabled 0x0 SET Subscriber 1 event is enabled 0x1 OUTPOLICY These bits configure the output policy for subscriber 1 event. 0x8 0x2 read-write SET Selected DIO pins are set 0x0 CLR Selected DIO pins are cleared 0x1 TOGGLE Selected DIO pins are toggled 0x2 INDEX indicates the specific bit in the upper 16 bits that is targeted by the subscriber action 0x10 0x4 read-write MIN specific bit targeted by the subscriber action is bit16 0x0 MAX specific bit targeted by the subscriber action is bit31 0xF KEYSTORECTL KEYSTORECTL 1.0 PERIPHERALREGION 0x400AC000 0x0 0x2000 registers KEYSTORECTL_CFG Keystore configuration 0x1100 32 read-write 0x00000001 NK256 Number of 256 bit keys to be held in the key-store. Can not exceed the total number of slots present in the hardware / 2. For eg: if SYS_N_SLOTS = 4, then atmost 2 256-bit keys can be held in the key-store. Incorrect setting of this field will be reported via STATUS register 0x0 0x4 ZERO No 256-bit keys 0x0 ONE One 256-bit key 0x1 TWO Two 256-bit keys 0x2 THREE Three 256-bit keys 0x3 FOUR Four 256-bit keys 0x4 KEYSTORECTL_KEYWR Key write configuration 0x1104 32 read-write 0x00000000 KEYSZSEL Key size selection. Selection of 128 or 256 bit keys 0x0 0x3 K256 256 bit key 0x0 K128 128 bit key 0x1 KEYSLOTSEL Select the key slot to write the key into. NOTE: SW needs to ensure that it is writing to the correct slots. The slot numbering is from 0 through SYS_N_SLOTS-1. Each slot is a 128-bit slot. Therefore, when writing a 256-bit key, two slots will need to budgeted. The selected slot for the 256-bit key needs to be an even numbered slot (eg: 0 or 2). Also all the 256-bit keys need to be stored in lower numbered slots and 128-bit keys stored in higher numbered slots. 0x4 0x4 SLOT0 Slot 0 0x0 SLOT1 Slot 1 0x1 SLOT2 Slot 2 0x2 SLOT3 Slot 3 0x3 SLOT4 Slot 4 0x4 SLOT5 Slot 5 0x5 SLOT6 Slot 6 0x6 SLOT7 Slot 7 0x7 KEYSTORECTL_KEYRD Key read configuration 0x1108 32 read-write 0x00000000 KEYSZSEL Key size selection. Selection of 128 or 256 bit keys 0x0 0x3 K256 256 bit key 0x0 K128 128 bit key 0x1 KEYSLOTSEL Select the key slot to read the key from. NOTE: SW needs to ensure that it is reading from the correct slots. The slot numbering is from 0 through SYS_N_SLOTS-1. Each slot is a 128-bit slot. Therefore, when reading a 256-bit key, two adjacent slots will be read. For a 256-bit key, an even numbered slot index must be specified. 0x4 0x4 CRYPTOSEL Crypto engine selector 0x8 0x2 AES Transfer key to AES 0x0 KEYSTORECTL_STATUS Status 0x110C 32 read-only 0x00020001 STAT Status information 0x0 0x4 VALID Valid configuration 0x0 NO_CFG Key-store has not been configured. NK256 has not been set. 0x1 INVALID_NK256 Invalid value for NK256 field in CFG. 0x2 BUSY_RECEIVE Busy receiving a key deposit 0x3 BUSY_TRANSMIT Busy transmitting a key to a crypto engine 0x4 INVALID_KEYSLOTSELW Invalid keyslot selection for writing 0x5 INVALID_KEYSLOTSELR Invalid keyslot selection for reading 0x6 VALID Bitvector of valid bits to indicate which slots have been configured 0x4 0x8 NKEYSLOTS Size of keystorage: Number of 128-bit key slots 0x10 0x2 read-only TWO Two slots 0x0 THREE Three slots 0x1 FOUR Four slots 0x2 KEYSTORECTL_KEYIN Input key 0x1110 32 write-only 0x00000000 KEYSTORECTL_KEYLOCK Keylock 0x1114 32 read-write LOCKBIT Bitvector of lock bits to lock certain slots from being used by application. 0x0 0x8 WWDT1 WWDT 1.0 WWDT 0x40082000 0x0 0x1500 registers 1 24 0 WWDT1_GPRCM[%s] 0x800 WWDT1_PWREN Power enable 0x0 32 read-write ENABLE Enable the power Note: For safety devices the power cannot be disabled once enabled. 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 WWDT1_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear [GPRCM.STAT.RESETSTKY] 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible. 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 WWDT1_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 WWDT1_PDBGCTL Peripheral Debug Control 0x1018 32 read-write 0x00000000 FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 1 44 0 WWDT1_INT_EVENT[%s] 0x1020 WWDT1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 0x0 0x5 read-only NO_INTR No interrupt pending 0x0 INTTIM Interval Timer Interrupt; Interrupt Flag: INTTIM; Interrupt Priority: Highest 0x1 WWDT1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 WWDT1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 WWDT1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 WWDT1_ISET Interrupt set 0x20 32 write-only 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 WWDT1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INTTIM Interval Timer Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 WWDT1_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 WWDT1_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 WWDT1_WWDTCTL0 Window Watchdog Timer Control Register 0 0x1100 32 read-write 0x00000043 0xffffffff PER Timer Period of the WWDT. These bits select the total watchdog timer count. 0x4 0x3 read-write EN_25 Total timer count is 2^25 0x0 EN_21 Total timer count is 2^21 0x1 EN_18 Total timer count is 2^18 0x2 EN_15 Total timer count is 2^15 0x3 EN_12 Total timer count is 2^12 (default) 0x4 EN_10 Total timer count is 2^10 0x5 EN_8 Total timer count is 2^8 0x6 EN_6 Total timer count is 2^6 0x7 WINDOW0 Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1). 0x8 0x3 read-write SIZE_0 0% (No closed Window) 0x0 SIZE_12 12.50% of the total timer period is closed window 0x1 SIZE_18 18.75% of the total timer period is closed window 0x2 SIZE_25 25% of the total timer period is closed window 0x3 SIZE_50 50% of the total timer period is closed window 0x4 SIZE_75 75% of the total timer period is closed window 0x5 SIZE_81 81.25% of the total timer period is closed window 0x6 SIZE_87 87.50% of the total timer period is closed window 0x7 MODE Window Watchdog Timer Mode 0x10 0x1 read-write WINDOW Window Watchdog Timer Mode. The WWDT will generate a error signal to the ESM when following conditions occur: - Timer Expiration (Timeout) - Reset WWDT during the active window closed period - Keyword violation 0x0 INTERVAL Interval Timer Mode. The WWDT acts as an interval timer. It generates an interrupt on timeout. 0x1 STISM Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported. 0x11 0x1 read-write CONT The WWDT continues to function in Sleep mode. 0x0 STOP The WWDT stops in Sleep mode and resumes where it was stopped after wakeup. 0x1 CLKDIV Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0. 0x0 0x3 read-write WINDOW1 Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1). 0xC 0x3 read-write SIZE_0 0% (No closed Window) 0x0 SIZE_12 12.50% of the total timer period is closed window 0x1 SIZE_18 18.75% of the total timer period is closed window 0x2 SIZE_25 25% of the total timer period is closed window 0x3 SIZE_50 50% of the total timer period is closed window 0x4 SIZE_75 75% of the total timer period is closed window 0x5 SIZE_81 81.25% of the total timer period is closed window 0x6 SIZE_87 87.50% of the total timer period is closed window 0x7 WWDT1_WWDTCTL1 Window Watchdog Timer Control Register 0 0x1104 32 read-write 0x00000000 0xffffffff WINSEL Close Window Select 0x0 0x1 read-write WIN0 In window mode field WINDOW0 of WDDTCTL0 defines the closed window size. 0x0 WIN1 In window mode field WINDOW1 of WDDTCTL0 defines the closed window size. 0x1 WWDT1_WWDTCNTRST Window Watchdog Timer Counter Reset Register 0x1108 32 read-write 0x00000000 0xffffffff RESTART Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0. 0x0 0x20 read-write WWDT1_WWDTSTAT Window Watchdog Timer Status Register 0x110C 32 read-only 0x00000000 0xffffffff RUN Watchdog running status flag. 0x0 0x1 read-only OFF Watchdog counter stopped. 0x0 ON Watchdog running. 0x1 CANFD1 CANFD 1.0 PERIPHERALREGION 0x40510000 0x0 0x8000 registers CANFD1_PWREN Power enable 0x6800 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 CANFD1_RSTCTL Reset Control 0x6804 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 CANFD1_STAT Status Register 0x6814 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 1 252 0 CANFD1_MCAN[%s] 0x7000 CANFD1_MCAN_CREL MCAN Core Release Register 0x0 32 read-only 0x32380608 0xffffffff DAY Time Stamp Day. Two digits, BCD-coded. 0x0 0x8 read-only MON Time Stamp Month. Two digits, BCD-coded. 0x8 0x8 read-only YEAR Time Stamp Year. One digit, BCD-coded. 0x10 0x4 read-only SUBSTEP Sub-Step of Core Release. One digit, BCD-coded. 0x14 0x4 read-only STEP Step of Core Release. One digit, BCD-coded. 0x18 0x4 read-only REL Core Release. One digit, BCD-coded. 0x1C 0x4 read-only CANFD1_MCAN_ENDN MCAN Endian Register 0x4 32 read-only 0x87654321 0xffffffff CANFD1_MCAN_DBTP MCAN Data Bit Timing and Prescaler Register 0xC 32 read-write 0x00000a33 0xffffffff DSJW Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x4 read-write DTSEG2 Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x4 0x4 read-write DTSEG1 Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x5 read-write DBRP Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x5 read-write TDC Transmitter Delay Compensation 0 Transmitter Delay Compensation disabled 1 Transmitter Delay Compensation enabled 0x17 0x1 read-write CANFD1_MCAN_TEST MCAN Test Register 0x10 32 read-write 0x00000000 0xffffff7f LBCK Loop Back Mode. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x4 0x1 read-write DISABLE Reset value, Loop Back Mode is disabled 0x0 ENABLE Loop Back Mode is enabled 0x1 TX Control of Transmit Pin 00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at CAN TX pin 10 Dominant ('0') level at CAN TX pin 11 Recessive ('1') at CAN TX pin Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x5 0x2 read-write RX Receive Pin. Monitors the actual value of the CAN receive pin. 0x7 0x1 read-only DOMINANT The CAN bus is dominant (CAN RX pin = '0') 0x0 RECESSIVE The CAN bus is recessive (CAN RX pin = '1') 0x1 CANFD1_MCAN_RWD MCAN RAM Watchdog 0x14 32 read-write 0x00000000 0xffffffff WDC Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of &quot;00&quot; the counter is disabled. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x8 read-write WDV Watchdog Value. Acutal Message RAM Watchdog Counter Value. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock. 0x8 0x8 read-only CANFD1_MCAN_CCCR MCAN CC Control Register 0x18 32 read-write 0x00000001 0xffffffff INIT Initialization 0 Normal Operation 1 Initialization is started Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value. 0x0 0x1 read-write CCE Configuration Change Enable 0 The CPU has no write access to the protected configuration registers 1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1 0x1 read-write ASM Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time. 0 Normal CAN operation 1 Restricted Operation Mode active Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0x1 read-write CSA Clock Stop Acknowledge 0 No clock stop acknowledged 1 MCAN may be set in power down by stopping the Host and CAN clocks 0x3 0x1 read-only CSR Clock Stop Request 0 No clock stop is requested 1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. 0x4 0x1 read-write MON Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time. 0 Bus Monitoring Mode is disabled 1 Bus Monitoring Mode is enabled Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x5 0x1 read-write DAR Disable Automatic Retransmission 0 Automatic retransmission of messages not transmitted successfully enabled 1 Automatic retransmission disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x6 0x1 read-write TEST Test Mode Enable 0 Normal operation, register TEST holds reset values 1 Test Mode, write access to register TEST enabled Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x7 0x1 read-write FDOE Flexible Datarate Operation Enable 0 FD operation disabled 1 FD operation enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x1 read-write BRSE Bit Rate Switch Enable 0 Bit rate switching for transmissions disabled 1 Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x9 0x1 read-write PXHD Protocol Exception Handling Disable 0 Protocol exception handling enabled 1 Protocol exception handling disabled Note: When protocol exception handling is disabled, the MCAN will transmit an error frame when it detects a protocol exception condition. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0xC 0x1 read-write EFBI Edge Filtering during Bus Integration 0 Edge filtering disabled 1 Two consecutive dominant tq required to detect an edge for hard synchronization Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0xD 0x1 read-write TXP Transmit Pause. If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame. 0 Transmit pause disabled 1 Transmit pause enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0xE 0x1 read-write NISO Non ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0 CAN FD frame format according to ISO 11898-1:2015 1 CAN FD frame format according to Bosch CAN FD Specification V1.0 0xF 0x1 read-write CANFD1_MCAN_NBTP MCAN Nominal Bit Timing and Prescaler Register 0x1C 32 read-write 0x06000a03 0xffffffff NTSEG2 Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x7 read-write NTSEG1 Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x8 read-write NBRP Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x9 read-write NSJW Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x19 0x7 read-write CANFD1_MCAN_TSCC MCAN Timestamp Counter Configuration 0x20 32 read-write 0x00000000 0xffffffff TSS Timestamp Select 00 Timestamp counter value always 0x0000 01 Timestamp counter value incremented according to TCP 10 External timestamp counter value used 11 Same as &quot;00&quot; Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x2 read-write TCP Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With CAN FD an external counter is required for timestamp generation (TSS = &quot;10&quot;). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x4 read-write CANFD1_MCAN_TSCV MCAN Timestamp Counter Value 0x24 32 read-write 0x00000000 0xffffffff TSC Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = &quot;01&quot;, the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = &quot;10&quot;, TSC reflects the External Timestamp Counter value, and a write access has no impact. Note: A &quot;wrap around&quot; is a change of the Timestamp Counter value from non-zero to zero not caused by write access to MCAN_TSCV. 0x0 0x10 read-write CANFD1_MCAN_TOCC MCAN Timeout Counter Configuration 0x28 32 read-write 0xffff0000 0xffffffff ETOC Enable Timeout Counter 0 Timeout Counter disabled 1 Timeout Counter enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x1 read-write TOS Timeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00 Continuous operation 01 Timeout controlled by Tx Event FIFO 10 Timeout controlled by Rx FIFO 0 11 Timeout controlled by Rx FIFO 1 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1 0x2 read-write TOP Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x10 read-write CANFD1_MCAN_TOCV MCAN Timeout Counter Value 0x2C 32 read-write 0x0000ffff 0xffffffff TOC Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. 0x0 0x10 read-write CANFD1_MCAN_ECR MCAN Error Counter Register 0x40 32 read-only 0x00000000 0xffffffff TEC Transmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0x0 0x8 read-only REC Receive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0x8 0x7 read-only RP Receive Error Passive 0 The Receive Error Counter is below the error passive level of 128 1 The Receive Error Counter has reached the error passive level of 128 0xF 0x1 read-only CEL CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0x10 0x8 read-only CANFD1_MCAN_PSR MCAN Protocol Status Register 0x44 32 read-only 0x00000707 0xffffffff LEC Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 0 No Error: No error occurred since LEC has been reset by successful reception or transmission. 1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2 Form Error: A fixed format part of a received frame has the wrong format. 3 AckError: The message transmitted by the MCAN was not acknowledged by another node. 4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. 0x0 0x3 read-only ACT Node Activity. Monitors the module's CAN communication state. 00 Synchronizing - node is synchronizing on CAN communication 01 Idle - node is neither receiver nor transmitter 10 Receiver - node is operating as receiver 11 Transmitter - node is operating as transmitter Note: ACT is set to &quot;00&quot; by a Protocol Exception Event. 0x3 0x2 read-only EP Error Passive 0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1 The M_CAN is in the Error_Passive state 0x5 0x1 read-only EW Warning Status 0 Both error counters are below the Error_Warning limit of 96 1 At least one of error counter has reached the Error_Warning limit of 96 0x6 0x1 read-only BO Bus_Off Status 0 The M_CAN is not Bus_Off 1 The M_CAN is in Bus_Off state 0x7 0x1 read-only DLEC Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. 0x8 0x3 read-only RESI ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its ESI flag set 1 Last received CAN FD message had its ESI flag set 0xB 0x1 read-only RBRS BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its BRS flag set 1 Last received CAN FD message had its BRS flag set 0xC 0x1 read-only RFDF Received a CAN FD Message. This bit is set independent of acceptance filtering. 0 Since this bit was reset by the CPU, no CAN FD message has been received 1 Message in CAN FD format with FDF flag set has been received 0xD 0x1 read-only PXE Protocol Exception Event 0 No protocol exception event occurred since last read access 1 Protocol exception event occurred 0xE 0x1 read-only TDCV Transmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. 0x10 0x7 read-only CANFD1_MCAN_TDCR MCAN Transmitter Delay Compensation Register 0x48 32 read-write 0x00000000 0xffffffff TDCF Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x7 read-write TDCO Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x7 read-write CANFD1_MCAN_IR MCAN Interrupt Register 0x50 32 read-write 0x80000000 0xffffffff RF0N Rx FIFO 0 New Message 0 No new message written to Rx FIFO 0 1 New message written to Rx FIFO 0 0x0 0x1 read-write RF0W Rx FIFO 0 Watermark Reached 0 Rx FIFO 0 fill level below watermark 1 Rx FIFO 0 fill level reached watermark 0x1 0x1 read-write RF0F Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full 0x2 0x1 read-write RF0L Rx FIFO 0 Message Lost 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero 0x3 0x1 read-write RF1N Rx FIFO 1 New Message 0 No new message written to Rx FIFO 1 1 New message written to Rx FIFO 1 0x4 0x1 read-write RF1W Rx FIFO 1 Watermark Reached 0 Rx FIFO 1 fill level below watermark 1 Rx FIFO 1 fill level reached watermark 0x5 0x1 read-write RF1F Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full 0x6 0x1 read-write RF1L Rx FIFO 1 Message Lost 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero 0x7 0x1 read-write HPM High Priority Message 0 No high priority message received 1 High priority message received 0x8 0x1 read-write TC Transmission Completed 0 No transmission completed 1 Transmission completed 0x9 0x1 read-write TCF Transmission Cancellation Finished 0 No transmission cancellation finished 1 Transmission cancellation finished 0xA 0x1 read-write TFE Tx FIFO Empty 0 Tx FIFO non-empty 1 Tx FIFO empty 0xB 0x1 read-write TEFN Tx Event FIFO New Entry 0 Tx Event FIFO unchanged 1 Tx Handler wrote Tx Event FIFO element 0xC 0x1 read-write TEFW Tx Event FIFO Watermark Reached 0 Tx Event FIFO fill level below watermark 1 Tx Event FIFO fill level reached watermark 0xD 0x1 read-write TEFF Tx Event FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full 0xE 0x1 read-write TEFL Tx Event FIFO Element Lost 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero 0xF 0x1 read-write TSW Timestamp Wraparound 0 No timestamp counter wrap-around 1 Timestamp counter wrapped around 0x10 0x1 read-write MRAF Message RAM Access Failure. The flag is set, when the Rx Handler: - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. - was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0 No Message RAM access failure occurred 1 Message RAM access failure occurred 0x11 0x1 read-write TOO Timeout Occurred 0 No timeout 1 Timeout reached 0x12 0x1 read-write DRX Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0 No Rx Buffer updated 1 At least one received message stored into an Rx Buffer 0x13 0x1 read-write BEU Bit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. 0 No bit error detected when reading from Message RAM 1 Bit error detected, uncorrected (e.g. parity logic) 0x15 0x1 read-write ELO Error Logging Overflow 0 CAN Error Logging Counter did not overflow 1 Overflow of CAN Error Logging Counter occurred 0x16 0x1 read-write EP Error Passive 0 Error_Passive status unchanged 1 Error_Passive status changed 0x17 0x1 read-write EW Warning Status 0 Error_Warning status unchanged 1 Error_Warning status changed 0x18 0x1 read-write BO Bus_Off Status 0 Bus_Off status unchanged 1 Bus_Off status changed 0x19 0x1 read-write WDI Watchdog Interrupt 0 No Message RAM Watchdog event occurred 1 Message RAM Watchdog event due to missing READY 0x1A 0x1 read-write PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0 No protocol error in arbitration phase 1 Protocol error in arbitration phase detected (PSR.LEC ? 0,7) 0x1B 0x1 read-write PED Protocol Error in Data Phase (Data Bit Time is used) 0 No protocol error in data phase 1 Protocol error in data phase detected (PSR.DLEC ? 0,7) 0x1C 0x1 read-write ARA Access to Reserved Address 0 No access to reserved address occurred 1 Access to reserved address occurred 0x1D 0x1 read-write CANFD1_MCAN_IE MCAN Interrupt Enable 0x54 32 read-write 0x00000000 0xffffffff RF0NE Rx FIFO 0 New Message Enable 0x0 0x1 read-write RF0WE Rx FIFO 0 Watermark Reached Enable 0x1 0x1 read-write RF0FE Rx FIFO 0 Full Enable 0x2 0x1 read-write RF0LE Rx FIFO 0 Message Lost Enable 0x3 0x1 read-write RF1NE Rx FIFO 1 New Message Enable 0x4 0x1 read-write RF1WE Rx FIFO 1 Watermark Reached Enable 0x5 0x1 read-write RF1FE Rx FIFO 1 Full Enable 0x6 0x1 read-write RF1LE Rx FIFO 1 Message Lost Enable 0x7 0x1 read-write HPME High Priority Message Enable 0x8 0x1 read-write TCE Transmission Completed Enable 0x9 0x1 read-write TCFE Transmission Cancellation Finished Enable 0xA 0x1 read-write TFEE Tx FIFO Empty Enable 0xB 0x1 read-write TEFNE Tx Event FIFO New Entry Enable 0xC 0x1 read-write TEFWE Tx Event FIFO Watermark Reached Enable 0xD 0x1 read-write TEFFE Tx Event FIFO Full Enable 0xE 0x1 read-write TEFLE Tx Event FIFO Element Lost Enable 0xF 0x1 read-write TSWE Timestamp Wraparound Enable 0x10 0x1 read-write MRAFE Message RAM Access Failure Enable 0x11 0x1 read-write TOOE Timeout Occurred Enable 0x12 0x1 read-write DRXE Message Stored to Dedicated Rx Buffer Enable 0x13 0x1 read-write BECE Bit Error Corrected Enable A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave this bit cleared to '0'. 0x14 0x1 read-write BEUE Bit Error Uncorrected Enable 0x15 0x1 read-write ELOE Error Logging Overflow Enable 0x16 0x1 read-write EPE Error Passive Enable 0x17 0x1 read-write EWE Warning Status Enable 0x18 0x1 read-write BOE Bus_Off Status Enable 0x19 0x1 read-write WDIE Watchdog Interrupt Enable 0x1A 0x1 read-write PEAE Protocol Error in Arbitration Phase Enable 0x1B 0x1 read-write PEDE Protocol Error in Data Phase Enable 0x1C 0x1 read-write ARAE Access to Reserved Address Enable 0x1D 0x1 read-write CANFD1_MCAN_ILS MCAN Interrupt Line Select 0x58 32 read-write 0x00000000 0xffffffff RF0NL Rx FIFO 0 New Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x0 0x1 read-write RF0WL Rx FIFO 0 Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1 0x1 read-write RF0FL Rx FIFO 0 Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x2 0x1 read-write RF0LL Rx FIFO 0 Message Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x3 0x1 read-write RF1NL Rx FIFO 1 New Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x4 0x1 read-write RF1WL Rx FIFO 1 Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x5 0x1 read-write RF1FL Rx FIFO 1 Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x6 0x1 read-write RF1LL Rx FIFO 1 Message Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x7 0x1 read-write HPML High Priority Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x8 0x1 read-write TCL Transmission Completed Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x9 0x1 read-write TCFL Transmission Cancellation Finished Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xA 0x1 read-write TFEL Tx FIFO Empty Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xB 0x1 read-write TEFNL Tx Event FIFO New Entry Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xC 0x1 read-write TEFWL Tx Event FIFO Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xD 0x1 read-write TEFFL Tx Event FIFO Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xE 0x1 read-write TEFLL Tx Event FIFO Element Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0xF 0x1 read-write TSWL Timestamp Wraparound Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x10 0x1 read-write MRAFL Message RAM Access Failure Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x11 0x1 read-write TOOL Timeout Occurred Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x12 0x1 read-write DRXL Message Stored to Dedicated Rx Buffer Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x13 0x1 read-write BECL Bit Error Corrected Line A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave the MCAN_IE.BECE bit cleared to '0' (disabled), thereby relegating this bit to not applicable. 0x14 0x1 read-write BEUL Bit Error Uncorrected Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x15 0x1 read-write ELOL Error Logging Overflow Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x16 0x1 read-write EPL Error Passive Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x17 0x1 read-write EWL Warning Status Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x18 0x1 read-write BOL Bus_Off Status Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x19 0x1 read-write WDIL Watchdog Interrupt Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1A 0x1 read-write PEAL Protocol Error in Arbitration Phase Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1B 0x1 read-write PEDL Protocol Error in Data Phase Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1C 0x1 read-write ARAL Access to Reserved Address Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 0x1D 0x1 read-write CANFD1_MCAN_ILE MCAN Interrupt Line Enable 0x5C 32 read-write 0x00000000 0xffffffff EINT0 Enable Interrupt Line 0 0 Interrupt Line 0 is disabled 1 Interrupt Line 0 is enabled 0x0 0x1 read-write EINT1 Enable Interrupt Line 1 0 Interrupt Line 1 is disabled 1 Interrupt Line 1 is enabled 0x1 0x1 read-write CANFD1_MCAN_GFC MCAN Global Filter Configuration 0x80 32 read-write 0x00000000 0xffffffff RRFE Reject Remote Frames Extended 0 Filter remote frames with 29-bit extended IDs 1 Reject all remote frames with 29-bit extended IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x1 read-write RRFS Reject Remote Frames Standard 0 Filter remote frames with 11-bit standard IDs 1 Reject all remote frames with 11-bit standard IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1 0x1 read-write ANFE Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0x2 read-write ANFS Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x4 0x2 read-write CANFD1_MCAN_SIDFC MCAN Standard ID Filter Configuration 0x84 32 read-write 0x00000000 0xffffffff FLSSA Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address). 0x2 0xE read-write LSS List Size Standard 0 No standard Message ID filter 1-128 Number of standard Message ID filter elements >128 Values greater than 128 are interpreted as 128 0x10 0x8 read-write CANFD1_MCAN_XIDFC MCAN Extended ID Filter Configuration 0x88 32 read-write 0x00000000 0xffffffff FLESA List Size Extended 0 No extended Message ID filter 1-64 Number of extended Message ID filter elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0xE read-write LSE Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x7 read-write CANFD1_MCAN_XIDAM MCAN Extended ID and Mask 0x90 32 read-write 0x1fffffff 0xffffffff EIDM Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x1D read-write CANFD1_MCAN_HPMS MCAN High Priority Message Status 0x94 32 read-only 0x00000000 0xffffffff BIDX Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'. 0x0 0x6 read-only MSI Message Storage Indicator 00 No FIFO selected 01 FIFO message lost 10 Message stored in FIFO 0 11 Message stored in FIFO 1 0x6 0x2 read-only FIDX Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. 0x8 0x7 read-only FLST Filter List. Indicates the filter list of the matching filter element. 0 Standard Filter List 1 Extended Filter List 0xF 0x1 read-only CANFD1_MCAN_NDAT1 MCAN New Data 1 0x98 32 read-write 0x00000000 0xffffffff ND0 New Data RX Buffer 0 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x0 0x1 read-write ND1 New Data RX Buffer 1 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1 0x1 read-write ND2 New Data RX Buffer 2 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x2 0x1 read-write ND3 New Data RX Buffer 3 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x3 0x1 read-write ND4 New Data RX Buffer 4 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x4 0x1 read-write ND5 New Data RX Buffer 5 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x5 0x1 read-write ND6 New Data RX Buffer 6 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x6 0x1 read-write ND7 New Data RX Buffer 7 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x7 0x1 read-write ND8 New Data RX Buffer 8 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x8 0x1 read-write ND9 New Data RX Buffer 9 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x9 0x1 read-write ND10 New Data RX Buffer 10 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xA 0x1 read-write ND11 New Data RX Buffer 11 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xB 0x1 read-write ND12 New Data RX Buffer 12 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xC 0x1 read-write ND13 New Data RX Buffer 13 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xD 0x1 read-write ND14 New Data RX Buffer 14 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xE 0x1 read-write ND15 New Data RX Buffer 15 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xF 0x1 read-write ND16 New Data RX Buffer 16 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x10 0x1 read-write ND17 New Data RX Buffer 17 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x11 0x1 read-write ND18 New Data RX Buffer 18 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x12 0x1 read-write ND19 New Data RX Buffer 19 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x13 0x1 read-write ND20 New Data RX Buffer 20 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x14 0x1 read-write ND21 New Data RX Buffer 21 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x15 0x1 read-write ND22 New Data RX Buffer 22 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x16 0x1 read-write ND23 New Data RX Buffer 23 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x17 0x1 read-write ND24 New Data RX Buffer 24 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x18 0x1 read-write ND25 New Data RX Buffer 25 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x19 0x1 read-write ND26 New Data RX Buffer 26 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1A 0x1 read-write ND27 New Data RX Buffer 27 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1B 0x1 read-write ND28 New Data RX Buffer 28 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1C 0x1 read-write ND29 New Data RX Buffer 29 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1D 0x1 read-write ND30 New Data RX Buffer 30 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1E 0x1 read-write ND31 New Data RX Buffer 31 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1F 0x1 read-write CANFD1_MCAN_NDAT2 MCAN New Data 2 0x9C 32 read-write 0x00000000 0xffffffff ND32 New Data RX Buffer 32 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x0 0x1 read-write ND33 New Data RX Buffer 33 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1 0x1 read-write ND34 New Data RX Buffer 34 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x2 0x1 read-write ND35 New Data RX Buffer 35 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x3 0x1 read-write ND36 New Data RX Buffer 36 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x4 0x1 read-write ND37 New Data RX Buffer 37 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x5 0x1 read-write ND38 New Data RX Buffer 38 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x6 0x1 read-write ND39 New Data RX Buffer 39 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x7 0x1 read-write ND40 New Data RX Buffer 40 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x8 0x1 read-write ND41 New Data RX Buffer 41 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x9 0x1 read-write ND42 New Data RX Buffer 42 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xA 0x1 read-write ND43 New Data RX Buffer 43 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xB 0x1 read-write ND44 New Data RX Buffer 44 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xC 0x1 read-write ND45 New Data RX Buffer 45 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xD 0x1 read-write ND46 New Data RX Buffer 46 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xE 0x1 read-write ND47 New Data RX Buffer 47 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0xF 0x1 read-write ND48 New Data RX Buffer 48 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x10 0x1 read-write ND49 New Data RX Buffer 49 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x11 0x1 read-write ND50 New Data RX Buffer 50 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x12 0x1 read-write ND51 New Data RX Buffer 51 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x13 0x1 read-write ND52 New Data RX Buffer 52 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x14 0x1 read-write ND53 New Data RX Buffer 53 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x15 0x1 read-write ND54 New Data RX Buffer 54 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x16 0x1 read-write ND55 New Data RX Buffer 55 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x17 0x1 read-write ND56 New Data RX Buffer 56 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x18 0x1 read-write ND57 New Data RX Buffer 57 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x19 0x1 read-write ND58 New Data RX Buffer 58 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1A 0x1 read-write ND59 New Data RX Buffer 59 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1B 0x1 read-write ND60 New Data RX Buffer 60 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1C 0x1 read-write ND61 New Data RX Buffer 61 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1D 0x1 read-write ND62 New Data RX Buffer 62 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1E 0x1 read-write ND63 New Data RX Buffer 63 0 Rx Buffer not updated 1 Rx Buffer updated from new message 0x1F 0x1 read-write CANFD1_MCAN_RXF0C MCAN Rx FIFO 0 Configuration 0xA0 32 read-write 0x00000000 0xffffffff F0SA Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0xE read-write F0S Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1. 0 No Rx FIFO 0 1-64 Number of Rx FIFO 0 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x7 read-write F0WM Rx FIFO 0 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x18 0x7 read-write F0OM FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode. 0 FIFO 0 blocking mode 1 FIFO 0 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1F 0x1 read-write CANFD1_MCAN_RXF0S MCAN Rx FIFO 0 Status 0xA4 32 read-only 0x00000000 0xffffffff F0FL Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64. 0x0 0x7 read-only F0GI Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63. 0x8 0x6 read-only F0PI Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63. 0x10 0x6 read-only F0F Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full 0x18 0x1 read-only RF0L Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag. 0x19 0x1 read-only CANFD1_MCAN_RXF0A MCAN Rx FIFO 0 Acknowledge 0xA8 32 read-write 0x00000000 0xffffffff F0AI Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. 0x0 0x6 read-write CANFD1_MCAN_RXBC MCAN Rx Buffer Configuration 0xAC 32 read-write 0x00000000 0xffffffff RBSA Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +I466 0x2 0xE read-write CANFD1_MCAN_RXF1C MCAN Rx FIFO 1 Configuration 0xB0 32 read-write 0x00000000 0xffffffff F1SA Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address). 0x2 0xE read-write F1S Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1. 0 No Rx FIFO 1 1-64 Number of Rx FIFO 1 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x7 read-write F1WM Rx FIFO 1 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x18 0x7 read-write F1OM FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode. 0 FIFO 1 blocking mode 1 FIFO 1 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1F 0x1 read-write CANFD1_MCAN_RXF1S MCAN Rx FIFO 1 Status 0xB4 32 read-only 0x00000000 0xffffffff F1FL Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64. 0x0 0x7 read-only F1GI Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63. 0x8 0x6 read-only F1PI Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63. 0x10 0x6 read-only F1F Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full 0x18 0x1 read-only RF1L Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag. 0x19 0x1 read-only DMS Debug Message Status 00 Idle state, wait for reception of debug messages 01 Debug message A received 10 Debug messages A, B received 11 Debug messages A, B, C received 0x1E 0x2 read-only CANFD1_MCAN_RXF1A MCAN Rx FIFO 1 Acknowledge 0xB8 32 read-write 0x00000000 0xffffffff F1AI Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. 0x0 0x6 read-write CANFD1_MCAN_RXESC MCAN Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write 0x00000000 0xffffffff F0DS Rx FIFO 0 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x3 read-write F1DS Rx FIFO 1 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x4 0x3 read-write RBDS Rx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x8 0x3 read-write CANFD1_MCAN_TXBC MCAN Tx Buffer Configuration 0xC0 32 read-write 0x00000000 0xffffffff TBSA Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x2 0xE read-write NDTB Number of Dedicated Transmit Buffers 0 No Dedicated Tx Buffers 1-32 Number of Dedicated Tx Buffers >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x10 0x6 read-write TFQS Transmit FIFO/Queue Size 0 No Tx FIFO/Queue 1-32 Number of Tx Buffers used for Tx FIFO/Queue >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x18 0x6 read-write TFQM Tx FIFO/Queue Mode 0 Tx FIFO operation 1 Tx Queue operation Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x1E 0x1 read-write CANFD1_MCAN_TXFQS MCAN Tx FIFO / Queue Status 0xC4 32 read-only 0x00000000 0xffffffff TFFL Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1'). 0x0 0x6 read-only TFGI Tx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1'). Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. 0x8 0x5 read-only TFQP Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31. Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. 0x10 0x5 read-only TFQF Tx FIFO/Queue Full 0 Tx FIFO/Queue not full 1 Tx FIFO/Queue full 0x15 0x1 read-only CANFD1_MCAN_TXESC MCAN Tx Buffer Element Size Configuration 0xC8 32 read-write 0x00000000 0xffffffff TBDS Tx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as &quot;0xCC&quot; (padding bytes). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. 0x0 0x3 read-write CANFD1_MCAN_TXBRP MCAN Tx Buffer Request Pending 0xCC 32 read-only 0x00000000 0xffffffff TRP0 Transmission Request Pending 0. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF - after successful transmission together with the corresponding TXBTO bit - when the transmission has not yet been started at the point of cancellation - when the transmission has been aborted due to lost arbitration - when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 No transmission request pending 1 Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. 0x0 0x1 read-only TRP1 Transmission Request Pending 1. See description for bit 0. 0x1 0x1 read-only TRP2 Transmission Request Pending 2. See description for bit 0. 0x2 0x1 read-only TRP3 Transmission Request Pending 3. See description for bit 0. 0x3 0x1 read-only TRP4 Transmission Request Pending 4. See description for bit 0. 0x4 0x1 read-only TRP5 Transmission Request Pending 5. See description for bit 0. 0x5 0x1 read-only TRP6 Transmission Request Pending 6. See description for bit 0. 0x6 0x1 read-only TRP7 Transmission Request Pending 7. See description for bit 0. 0x7 0x1 read-only TRP8 Transmission Request Pending 8. See description for bit 0. 0x8 0x1 read-only TRP9 Transmission Request Pending 9. See description for bit 0. 0x9 0x1 read-only TRP10 Transmission Request Pending 10. See description for bit 0. 0xA 0x1 read-only TRP11 Transmission Request Pending 11. See description for bit 0. 0xB 0x1 read-only TRP12 Transmission Request Pending 12. See description for bit 0. 0xC 0x1 read-only TRP13 Transmission Request Pending 13. See description for bit 0. 0xD 0x1 read-only TRP14 Transmission Request Pending 14. See description for bit 0. 0xE 0x1 read-only TRP15 Transmission Request Pending 15. See description for bit 0. 0xF 0x1 read-only TRP16 Transmission Request Pending 16. See description for bit 0. 0x10 0x1 read-only TRP17 Transmission Request Pending 17. See description for bit 0. 0x11 0x1 read-only TRP18 Transmission Request Pending 18. See description for bit 0. 0x12 0x1 read-only TRP19 Transmission Request Pending 19. See description for bit 0. 0x13 0x1 read-only TRP20 Transmission Request Pending 20. See description for bit 0. 0x14 0x1 read-only TRP21 Transmission Request Pending 21. See description for bit 0. 0x15 0x1 read-only TRP22 Transmission Request Pending 22. See description for bit 0. 0x16 0x1 read-only TRP23 Transmission Request Pending 23. See description for bit 0. 0x17 0x1 read-only TRP24 Transmission Request Pending 24. See description for bit 0. 0x18 0x1 read-only TRP25 Transmission Request Pending 25. See description for bit 0. 0x19 0x1 read-only TRP26 Transmission Request Pending 26. See description for bit 0. 0x1A 0x1 read-only TRP27 Transmission Request Pending 27. See description for bit 0. 0x1B 0x1 read-only TRP28 Transmission Request Pending 28. See description for bit 0. 0x1C 0x1 read-only TRP29 Transmission Request Pending 29. See description for bit 0. 0x1D 0x1 read-only TRP30 Transmission Request Pending 30. See description for bit 0. 0x1E 0x1 read-only TRP31 Transmission Request Pending 31. See description for bit 0. 0x1F 0x1 read-only CANFD1_MCAN_TXBAR MCAN Tx Buffer Add Request 0xD0 32 read-write 0x00000000 0xffffffff AR0 Add Request 0. Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 No transmission request added 1 Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. Qualified Write is possible only with CCCR.CCE='0' 0x0 0x1 read-write AR1 Add Request 1. See description for bit 0. 0x1 0x1 read-write AR2 Add Request 2. See description for bit 0. 0x2 0x1 read-write AR3 Add Request 3. See description for bit 0. 0x3 0x1 read-write AR4 Add Request 4. See description for bit 0. 0x4 0x1 read-write AR5 Add Request 5. See description for bit 0. 0x5 0x1 read-write AR6 Add Request 6. See description for bit 0. 0x6 0x1 read-write AR7 Add Request 7. See description for bit 0. 0x7 0x1 read-write AR8 Add Request 8. See description for bit 0. 0x8 0x1 read-write AR9 Add Request 9. See description for bit 0. 0x9 0x1 read-write AR10 Add Request 10. See description for bit 0. 0xA 0x1 read-write AR11 Add Request 11. See description for bit 0. 0xB 0x1 read-write AR12 Add Request 12. See description for bit 0. 0xC 0x1 read-write AR13 Add Request 13. See description for bit 0. 0xD 0x1 read-write AR14 Add Request 14. See description for bit 0. 0xE 0x1 read-write AR15 Add Request 15. See description for bit 0. 0xF 0x1 read-write AR16 Add Request 16. See description for bit 0. 0x10 0x1 read-write AR17 Add Request 17. See description for bit 0. 0x11 0x1 read-write AR18 Add Request 18. See description for bit 0. 0x12 0x1 read-write AR19 Add Request 19. See description for bit 0. 0x13 0x1 read-write AR20 Add Request 20. See description for bit 0. 0x14 0x1 read-write AR21 Add Request 21. See description for bit 0. 0x15 0x1 read-write AR22 Add Request 22. See description for bit 0. 0x16 0x1 read-write AR23 Add Request 23. See description for bit 0. 0x17 0x1 read-write AR24 Add Request 24. See description for bit 0. 0x18 0x1 read-write AR25 Add Request 25. See description for bit 0. 0x19 0x1 read-write AR26 Add Request 26. See description for bit 0. 0x1A 0x1 read-write AR27 Add Request 27. See description for bit 0. 0x1B 0x1 read-write AR28 Add Request 28. See description for bit 0. 0x1C 0x1 read-write AR29 Add Request 29. See description for bit 0. 0x1D 0x1 read-write AR30 Add Request 30. See description for bit 0. 0x1E 0x1 read-write AR31 Add Request 31. See description for bit 0. 0x1F 0x1 read-write CANFD1_MCAN_TXBCR MCAN Tx Buffer Cancellation Request 0xD4 32 read-write 0x00000000 0xffffffff CR0 Cancellation Request 0. Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0 No cancellation pending 1 Cancellation pending Qualified Write is possible only with CCCR.CCE='0' 0x0 0x1 read-write CR1 Cancellation Request 1. See description for bit 0. 0x1 0x1 read-write CR2 Cancellation Request 2. See description for bit 0. 0x2 0x1 read-write CR3 Cancellation Request 3. See description for bit 0. 0x3 0x1 read-write CR4 Cancellation Request 4. See description for bit 0. 0x4 0x1 read-write CR5 Cancellation Request 5. See description for bit 0. 0x5 0x1 read-write CR6 Cancellation Request 6. See description for bit 0. 0x6 0x1 read-write CR7 Cancellation Request 7. See description for bit 0. 0x7 0x1 read-write CR8 Cancellation Request 8. See description for bit 0. 0x8 0x1 read-write CR9 Cancellation Request 9. See description for bit 0. 0x9 0x1 read-write CR10 Cancellation Request 10. See description for bit 0. 0xA 0x1 read-write CR11 Cancellation Request 11. See description for bit 0. 0xB 0x1 read-write CR12 Cancellation Request 12. See description for bit 0. 0xC 0x1 read-write CR13 Cancellation Request 13. See description for bit 0. 0xD 0x1 read-write CR14 Cancellation Request 14. See description for bit 0. 0xE 0x1 read-write CR15 Cancellation Request 15. See description for bit 0. 0xF 0x1 read-write CR16 Cancellation Request 16. See description for bit 0. 0x10 0x1 read-write CR17 Cancellation Request 17. See description for bit 0. 0x11 0x1 read-write CR18 Cancellation Request 18. See description for bit 0. 0x12 0x1 read-write CR19 Cancellation Request 19. See description for bit 0. 0x13 0x1 read-write CR20 Cancellation Request 20. See description for bit 0. 0x14 0x1 read-write CR21 Cancellation Request 21. See description for bit 0. 0x15 0x1 read-write CR22 Cancellation Request 22. See description for bit 0. 0x16 0x1 read-write CR23 Cancellation Request 23. See description for bit 0. 0x17 0x1 read-write CR24 Cancellation Request 24. See description for bit 0. 0x18 0x1 read-write CR25 Cancellation Request 25. See description for bit 0. 0x19 0x1 read-write CR26 Cancellation Request 26. See description for bit 0. 0x1A 0x1 read-write CR27 Cancellation Request 27. See description for bit 0. 0x1B 0x1 read-write CR28 Cancellation Request 28. See description for bit 0. 0x1C 0x1 read-write CR29 Cancellation Request 29. See description for bit 0. 0x1D 0x1 read-write CR30 Cancellation Request 30. See description for bit 0. 0x1E 0x1 read-write CR31 Cancellation Request 31. See description for bit 0. 0x1F 0x1 read-write CANFD1_MCAN_TXBTO MCAN Tx Buffer Transmission Occurred 0xD8 32 read-only 0x00000000 0xffffffff TO0 Transmission Occurred 0. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmission occurred 1 Transmission occurred 0x0 0x1 read-only TO1 Transmission Occurred 1. See description for bit 0. 0x1 0x1 read-only TO2 Transmission Occurred 2. See description for bit 0. 0x2 0x1 read-only TO3 Transmission Occurred 3. See description for bit 0. 0x3 0x1 read-only TO4 Transmission Occurred 4. See description for bit 0. 0x4 0x1 read-only TO5 Transmission Occurred 5. See description for bit 0. 0x5 0x1 read-only TO6 Transmission Occurred 6. See description for bit 0. 0x6 0x1 read-only TO7 Transmission Occurred 7. See description for bit 0. 0x7 0x1 read-only TO8 Transmission Occurred 8. See description for bit 0. 0x8 0x1 read-only TO9 Transmission Occurred 9. See description for bit 0. 0x9 0x1 read-only TO10 Transmission Occurred 10. See description for bit 0. 0xA 0x1 read-only TO11 Transmission Occurred 11. See description for bit 0. 0xB 0x1 read-only TO12 Transmission Occurred 12. See description for bit 0. 0xC 0x1 read-only TO13 Transmission Occurred 13. See description for bit 0. 0xD 0x1 read-only TO14 Transmission Occurred 14. See description for bit 0. 0xE 0x1 read-only TO15 Transmission Occurred 15. See description for bit 0. 0xF 0x1 read-only TO16 Transmission Occurred 16. See description for bit 0. 0x10 0x1 read-only TO17 Transmission Occurred 17. See description for bit 0. 0x11 0x1 read-only TO18 Transmission Occurred 18. See description for bit 0. 0x12 0x1 read-only TO19 Transmission Occurred 19. See description for bit 0. 0x13 0x1 read-only TO20 Transmission Occurred 20. See description for bit 0. 0x14 0x1 read-only TO21 Transmission Occurred 21. See description for bit 0. 0x15 0x1 read-only TO22 Transmission Occurred 22. See description for bit 0. 0x16 0x1 read-only TO23 Transmission Occurred 23. See description for bit 0. 0x17 0x1 read-only TO24 Transmission Occurred 24. See description for bit 0. 0x18 0x1 read-only TO25 Transmission Occurred 25. See description for bit 0. 0x19 0x1 read-only TO26 Transmission Occurred 26. See description for bit 0. 0x1A 0x1 read-only TO27 Transmission Occurred 27. See description for bit 0. 0x1B 0x1 read-only TO28 Transmission Occurred 28. See description for bit 0. 0x1C 0x1 read-only TO29 Transmission Occurred 29. See description for bit 0. 0x1D 0x1 read-only TO30 Transmission Occurred 30. See description for bit 0. 0x1E 0x1 read-only TO31 Transmission Occurred 31. See description for bit 0. 0x1F 0x1 read-only CANFD1_MCAN_TXBCF MCAN Tx Buffer Cancellation Finished 0xDC 32 read-only 0x00000000 0xffffffff CF0 Cancellation Finished 0. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmit buffer cancellation 1 Transmit buffer cancellation finished 0x0 0x1 read-only CF1 Cancellation Finished 1. See description for bit 0. 0x1 0x1 read-only CF2 Cancellation Finished 2. See description for bit 0. 0x2 0x1 read-only CF3 Cancellation Finished 3. See description for bit 0. 0x3 0x1 read-only CF4 Cancellation Finished 4. See description for bit 0. 0x4 0x1 read-only CF5 Cancellation Finished 5. See description for bit 0. 0x5 0x1 read-only CF6 Cancellation Finished 6. See description for bit 0. 0x6 0x1 read-only CF7 Cancellation Finished 7. See description for bit 0. 0x7 0x1 read-only CF8 Cancellation Finished 8. See description for bit 0. 0x8 0x1 read-only CF9 Cancellation Finished 9. See description for bit 0. 0x9 0x1 read-only CF10 Cancellation Finished 10. See description for bit 0. 0xA 0x1 read-only CF11 Cancellation Finished 11. See description for bit 0. 0xB 0x1 read-only CF12 Cancellation Finished 12. See description for bit 0. 0xC 0x1 read-only CF13 Cancellation Finished 13. See description for bit 0. 0xD 0x1 read-only CF14 Cancellation Finished 14. See description for bit 0. 0xE 0x1 read-only CF15 Cancellation Finished 15. See description for bit 0. 0xF 0x1 read-only CF16 Cancellation Finished 16. See description for bit 0. 0x10 0x1 read-only CF17 Cancellation Finished 17. See description for bit 0. 0x11 0x1 read-only CF18 Cancellation Finished 18. See description for bit 0. 0x12 0x1 read-only CF19 Cancellation Finished 19. See description for bit 0. 0x13 0x1 read-only CF20 Cancellation Finished 20. See description for bit 0. 0x14 0x1 read-only CF21 Cancellation Finished 21. See description for bit 0. 0x15 0x1 read-only CF22 Cancellation Finished 22. See description for bit 0. 0x16 0x1 read-only CF23 Cancellation Finished 23. See description for bit 0. 0x17 0x1 read-only CF24 Cancellation Finished 24. See description for bit 0. 0x18 0x1 read-only CF25 Cancellation Finished 25. See description for bit 0. 0x19 0x1 read-only CF26 Cancellation Finished 26. See description for bit 0. 0x1A 0x1 read-only CF27 Cancellation Finished 27. See description for bit 0. 0x1B 0x1 read-only CF28 Cancellation Finished 28. See description for bit 0. 0x1C 0x1 read-only CF29 Cancellation Finished 29. See description for bit 0. 0x1D 0x1 read-only CF30 Cancellation Finished 30. See description for bit 0. 0x1E 0x1 read-only CF31 Cancellation Finished 31. See description for bit 0. 0x1F 0x1 read-only CANFD1_MCAN_TXBTIE MCAN Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write 0x00000000 0xffffffff TIE0 Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x0 0x1 read-write TIE1 Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1 0x1 read-write TIE2 Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x2 0x1 read-write TIE3 Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x3 0x1 read-write TIE4 Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x4 0x1 read-write TIE5 Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x5 0x1 read-write TIE6 Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x6 0x1 read-write TIE7 Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x7 0x1 read-write TIE8 Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x8 0x1 read-write TIE9 Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x9 0x1 read-write TIE10 Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xA 0x1 read-write TIE11 Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xB 0x1 read-write TIE12 Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xC 0x1 read-write TIE13 Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xD 0x1 read-write TIE14 Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xE 0x1 read-write TIE15 Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0xF 0x1 read-write TIE16 Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x10 0x1 read-write TIE17 Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x11 0x1 read-write TIE18 Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x12 0x1 read-write TIE19 Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x13 0x1 read-write TIE20 Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x14 0x1 read-write TIE21 Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x15 0x1 read-write TIE22 Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x16 0x1 read-write TIE23 Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x17 0x1 read-write TIE24 Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x18 0x1 read-write TIE25 Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x19 0x1 read-write TIE26 Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1A 0x1 read-write TIE27 Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1B 0x1 read-write TIE28 Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1C 0x1 read-write TIE29 Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1D 0x1 read-write TIE30 Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1E 0x1 read-write TIE31 Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable 0x1F 0x1 read-write CANFD1_MCAN_TXBCIE MCAN Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write 0x00000000 0xffffffff CFIE0 Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x0 0x1 read-write CFIE1 Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1 0x1 read-write CFIE2 Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x2 0x1 read-write CFIE3 Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x3 0x1 read-write CFIE4 Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x4 0x1 read-write CFIE5 Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x5 0x1 read-write CFIE6 Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x6 0x1 read-write CFIE7 Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x7 0x1 read-write CFIE8 Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x8 0x1 read-write CFIE9 Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x9 0x1 read-write CFIE10 Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xA 0x1 read-write CFIE11 Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xB 0x1 read-write CFIE12 Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xC 0x1 read-write CFIE13 Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xD 0x1 read-write CFIE14 Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xE 0x1 read-write CFIE15 Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0xF 0x1 read-write CFIE16 Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x10 0x1 read-write CFIE17 Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x11 0x1 read-write CFIE18 Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x12 0x1 read-write CFIE19 Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x13 0x1 read-write CFIE20 Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x14 0x1 read-write CFIE21 Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x15 0x1 read-write CFIE22 Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x16 0x1 read-write CFIE23 Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x17 0x1 read-write CFIE24 Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x18 0x1 read-write CFIE25 Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x19 0x1 read-write CFIE26 Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1A 0x1 read-write CFIE27 Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1B 0x1 read-write CFIE28 Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1C 0x1 read-write CFIE29 Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1D 0x1 read-write CFIE30 Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1E 0x1 read-write CFIE31 Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 0x1F 0x1 read-write CANFD1_MCAN_TXEFC MCAN Tx Event FIFO Configuration 0xF0 32 read-write 0x00000000 0xffffffff EFSA Event FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address). 0x2 0xE read-write EFS Event FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1. 0 Tx Event FIFO disabled 1-32 Number of Tx Event FIFO elements >32 Values greater than 32 are interpreted as 32 0x10 0x6 read-write EFWM Event FIFO Watermark 0 Watermark interrupt disabled 1-32 Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32 Watermark interrupt disabled 0x18 0x6 read-write CANFD1_MCAN_TXEFS MCAN Tx Event FIFO Status 0xF4 32 read-only 0x00000000 0xffffffff EFFL Event FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 32. 0x0 0x6 read-only EFGI Event FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31. 0x8 0x5 read-only EFPI Event FIFO Put Index.Tx Event FIFO write index pointer, range 0 to 31. 0x10 0x5 read-only EFF Event FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full 0x18 0x1 read-only TEFL Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. 0x19 0x1 read-only CANFD1_MCAN_TXEFA MCAN Tx Event FIFO Acknowledge 0xF8 32 read-write 0x00000000 0xffffffff EFAI Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. 0x0 0x5 read-write 1 2560 0 CANFD1_TI_WRAPPER[%s] 0x7200 1 1040 0 CANFD1_PROCESSORS[%s] 0x0 1 44 0 CANFD1_MCANSS_REGS[%s] 0x0 CANFD1_MCANSS_PID MCAN Subsystem Revision Register 0x0 32 read-only 0x68e04901 0xffffffff MINOR Minor Revision of the MCAN Subsystem 0x0 0x6 read-only MAJOR Major Revision of the MCAN Subsystem 0x8 0x3 read-only MODULE_ID Module Identification Number 0x10 0xC read-only SCHEME PID Register Scheme 0x1E 0x2 read-only CANFD1_MCANSS_CTRL MCAN Subsystem Control Register 0x4 32 read-write 0x00000008 0xffffffff DBGSUSP_FREE Debug Suspend Free Bit. Enables debug suspend. 0 Honor debug suspend 1 Disregard debug suspend 0x3 0x1 read-write WAKEUPREQEN Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity. 0 Disable wakeup request 1 Enables wakeup request 0x4 0x1 read-write AUTOWAKEUP Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up, on an enabled wakeup request. 0 Disable the automatic write to CCCR.INIT 1 Enable the automatic write to CCCR.INIT 0x5 0x1 read-write EXT_TS_CNTR_EN External Timestamp Counter Enable. 0 External timestamp counter disabled 1 External timestamp counter enabled 0x6 0x1 read-write CANFD1_MCANSS_STAT MCAN Subsystem Status Register 0x8 32 read-only 0x00000000 0xfffffffb RESET Soft Reset Status. 0 Not in reset 1 Reset is in progress 0x0 0x1 read-only MEM_INIT_DONE Memory Initialization Done. 0 Message RAM initialization is in progress 1 Message RAM is initialized for use 0x1 0x1 read-only ENABLE_FDOE Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port, -h = mcanss_enable_fdoe. 0x2 0x1 read-only CANFD1_MCANSS_ICS MCAN Subsystem Interrupt Clear Shadow Register 0xC 32 read-write 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IRS.EXT_TS_CNTR_OVFL bit 0x0 0x1 read-write CANFD1_MCANSS_IRS MCAN Subsystem Interrupt Raw Satus Register 0x10 32 read-write 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter has not overflowed 1 External timestamp counter has overflowed When this bit is set to '1' by HW or SW, the MCANSS_EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1. 0x0 0x1 read-write CANFD1_MCANSS_IECS MCAN Subsystem Interrupt Enable Clear Shadow Register 0x14 32 read-write 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IES.EXT_TS_CNTR_OVFL bit 0x0 0x1 read-write CANFD1_MCANSS_IE MCAN Subsystem Interrupt Enable Register 0x18 32 read-write 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit. 0x0 0x1 read-write CANFD1_MCANSS_IES MCAN Subsystem Interrupt Enable Status 0x1C 32 read-only 0x00000000 0xffffffff EXT_TS_CNTR_OVFL External Timestamp Counter Overflow Interrupt Enable Status. To set, use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear, use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter overflow interrupt is not enabled 1 External timestamp counter overflow interrupt is enabled 0x0 0x1 read-only CANFD1_MCANSS_EOI MCAN Subsystem End of Interrupt 0x20 32 read-write 0x00000000 0xffffffff EOI End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated. 0x00 External TS Interrupt is cleared 0x01 MCAN(0) interrupt is cleared 0x02 MCAN(1) interrupt is cleared Other writes are ignored. 0x0 0x8 read-write CANFD1_MCANSS_EXT_TS_PRESCALER MCAN Subsystem External Timestamp Prescaler 0 0x24 32 read-write 0x00000000 0xffffffff PRESCALER External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001. 0x0 0x18 read-write CANFD1_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR MCAN Subsystem External Timestamp Unserviced Interrupts Counter 0x28 32 read-only 0x00000000 0xffffffff EXT_TS_INTR_CNTR External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an MCANSS_EOI write of '1' to bit 0 will issue another interrupt. The status of this bit field is affected by the MCANSS_IRS.EXT_TS_CNTR_OVFL bit field. 0x0 0x5 read-only 1 528 0 CANFD1_MCAN_ECC_REGS[%s] 0x200 CANFD1_MCANERR_REV MCAN Error Aggregator Revision Register 0x0 32 read-only 0x66a0ea00 0xffffffff REVMIN Minor Revision of the Error Aggregator 0x0 0x6 read-only REVMAJ Major Revision of the Error Aggregator 0x8 0x3 read-only MODULE_ID Module Identification Number 0x10 0xC read-only SCHEME PID Register Scheme 0x1E 0x2 read-only CANFD1_MCANERR_VECTOR MCAN ECC Vector Register 0x8 32 read-write 0x00000000 0xffffffff ECC_VECTOR ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address. 0x000 Message RAM ECC controller is selected Others Reserved (do not use) Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing. 0x0 0xB read-write RD_SVBUS Read Trigger 0xF 0x1 read-write RD_SVBUS_ADDRESS Read Address Offset 0x10 0x8 read-write RD_SVBUS_DONE Read Completion Flag 0x18 0x1 read-only CANFD1_MCANERR_STAT MCAN Error Misc Status 0xC 32 read-only 0x00000002 0xffffffff NUM_RAMS Number of RAMs. Number of ECC RAMs serviced by the aggregator. 0x0 0xB read-only CANFD1_MCANERR_WRAP_REV MCAN ECC Wrapper Revision Register 0x10 32 read-only 0x66a46a02 0xffffffff REVMIN Minor Revision of the Error Aggregator 0x0 0x6 read-only REVMAJ Major Revision of the Error Aggregator 0x8 0x3 read-only MODULE_ID Module Identification Number 0x10 0xC read-only SCHEME PID Register Scheme 0x1E 0x2 read-only CANFD1_MCANERR_CTRL MCAN ECC Control 0x14 32 read-write 0x00000187 0xffffffff ECC_ENABLE Enable ECC Generation 0x0 0x1 read-write ECC_CHECK Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'. 0x1 0x1 read-write ENABLE_RMW Enable read-modify-write on partial word writes 0x2 0x1 read-write FORCE_SEC Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. 0x3 0x1 read-write FORCE_DED Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. 0x4 0x1 read-write FORCE_N_ROW Enable single/double-bit error on the next RAM read, regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode, this applies to writes as well as reads. 0x5 0x1 read-write ERROR_ONCE If this bit is set, the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled, this error will be cleared the cycle following the read when the data is corrected. For double-bit errors, the FORCE_DED bit will be cleared the cycle following the double-bit error. Any subsequent reads will not force an error. 0x6 0x1 read-write CHECK_SVBUS_TIMEOUT Enables Serial VBUS timeout mechanism 0x8 0x1 read-write CANFD1_MCANERR_ERR_CTRL1 MCAN ECC Error Control 1 Register 0x18 32 read-write 0x00000000 0xffffffff CANFD1_MCANERR_ERR_CTRL2 MCAN ECC Error Control 2 Register 0x1C 32 read-write 0x00000000 0xffffffff ECC_BIT1 Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set 0x0 0x10 read-write ECC_BIT2 Second column/data bit that needs to be flipped when FORCE_DED is set 0x10 0x10 read-write CANFD1_MCANERR_ERR_STAT1 MCAN ECC Error Status 1 Register 0x20 32 read-write 0x00000000 0xffffffff ECC_SEC Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared. 0 No single-bit error detected 1 One single-bit error was detected and corrected 2 Two single-bit errors were detected and corrected 3 Three single-bit errors were detected and corrected A write of a non-zero value to this bit field increments it by the value provided. 0x0 0x2 read-write ECC_DED Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared. 0 No double-bit error detected 1 One double-bit error was detected 2 Two double-bit errors were detected 3 Three double-bit errors were detected A write of a non-zero value to this bit field increments it by the value provided. 0x2 0x2 read-write ECC_OTHER SEC While Writeback Error Status 0 No SEC error while writeback pending 1 Indicates that successive single-bit errors have occurred while a writeback is still pending 0x4 0x1 read-write CTRL_REG_ERROR Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to re-write these registers to a known state. A write of 1 will set this interrupt flag. 0x7 0x1 read-write CLR_ECC_SEC Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided. 0x8 0x2 read-write CLR_ECC_DED Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided. 0xA 0x2 read-write CLR_ECC_OTHER Writing a '1' clears the ECC_OTHER bit. 0xC 0x1 read-write CLR_CTRL_REG_ERROR Writing a '1' clears the CTRL_REG_ERROR bit 0xF 0x1 read-write ECC_BIT1 ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error. 0 Bit 0 is in error 1 Bit 1 is in error 2 Bit 2 is in error 3 Bit 3 is in error ... 31 Bit 31 is in error >32 Invalid 0x10 0x10 read-only CANFD1_MCANERR_ERR_STAT2 MCAN ECC Error Status 2 Register 0x24 32 read-only 0x00000000 0xffffffff CANFD1_MCANERR_ERR_STAT3 MCAN ECC Error Status 3 Register 0x28 32 read-write 0x00000000 0xffffffff WB_PEND Delayed Write Back Pending Status 0 No write back pending 1 An ECC data correction write back is pending 0x0 0x1 read-only SVBUS_TIMEOUT Serial VBUS Timeout Flag. Write 1 to set. 0x1 0x1 read-write CLR_SVBUS_TIMEOUT Write 1 to clear the Serial VBUS Timeout Flag 0x9 0x1 read-write CANFD1_MCANERR_SEC_EOI MCAN Single Error Corrected End of Interrupt Register 0x3C 32 read-write 0x00000000 0xffffffff EOI_WR Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_SEC goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. 0x0 0x1 read-write CANFD1_MCANERR_SEC_STATUS MCAN Single Error Corrected Interrupt Status Register 0x40 32 read-write 0x00000000 0xffffffff MSGMEM_PEND Message RAM SEC Interrupt Pending 0 No SEC interrupt is pending 1 SEC interrupt is pending 0x0 0x1 read-only CANFD1_MCANERR_SEC_ENABLE_SET MCAN Single Error Corrected Interrupt Enable Set Register 0x80 32 read-write 0x00000000 0xffffffff MSGMEM_ENABLE_SET Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write CANFD1_MCANERR_SEC_ENABLE_CLR MCAN Single Error Corrected Interrupt Enable Clear Register 0xC0 32 read-write 0x00000000 0xffffffff MSGMEM_ENABLE_CLR Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write CANFD1_MCANERR_DED_EOI MCAN Double Error Detected End of Interrupt Register 0x13C 32 read-write 0x00000000 0xffffffff EOI_WR Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_DED goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. 0x0 0x1 read-write CANFD1_MCANERR_DED_STATUS MCAN Double Error Detected Interrupt Status Register 0x140 32 read-write 0x00000000 0xffffffff MSGMEM_PEND Message RAM DED Interrupt Pending 0 No DED interrupt is pending 1 DED interrupt is pending 0x0 0x1 read-only CANFD1_MCANERR_DED_ENABLE_SET MCAN Double Error Detected Interrupt Enable Set Register 0x180 32 read-write 0x00000000 0xffffffff MSGMEM_ENABLE_SET Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write CANFD1_MCANERR_DED_ENABLE_CLR MCAN Double Error Detected Interrupt Enable Clear Register 0x1C0 32 read-write 0x00000000 0xffffffff MSGMEM_ENABLE_CLR Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write CANFD1_MCANERR_AGGR_ENABLE_SET MCAN Error Aggregator Enable Set Register 0x200 32 read-write 0x00000000 0xffffffff ENABLE_PARITY_SET Write 1 to enable parity errors. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write ENABLE_TIMEOUT_SET Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value. 0x1 0x1 read-write CANFD1_MCANERR_AGGR_ENABLE_CLR MCAN Error Aggregator Enable Clear Register 0x204 32 read-write 0x00000000 0xffffffff ENABLE_PARITY_CLR Write 1 to disable parity errors. Reads return the corresponding enable bit's current value. 0x0 0x1 read-write ENABLE_TIMEOUT_CLR Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value. 0x1 0x1 read-write CANFD1_MCANERR_AGGR_STATUS_SET MCAN Error Aggregator Status Set Register 0x208 32 read-write 0x00000000 0xffffffff AGGR_PARITY_ERR Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field increments it by the value provided. 0x0 0x2 read-write SVBUS_TIMEOUT Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field increments it by the value provided. 0x2 0x2 read-write CANFD1_MCANERR_AGGR_STATUS_CLR MCAN Error Aggregator Status Clear Register 0x20C 32 read-write 0x00000000 0xffffffff AGGR_PARITY_ERR Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. 0x0 0x2 read-write SVBUS_TIMEOUT Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. 0x2 0x2 read-write 1 512 0 CANFD1_MSP[%s] 0x600 1 44 0 CANFD1_CPU_INT[%s] 0x20 CANFD1_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending. 0x0 INTL0 MCAN Interrupt Line 0 interrupt pending. 0x1 INTL1 MCAN Interrupt Line 1 interrupt pending. 0x2 SEC Message RAM SEC (Single Error Correction) interrupt pending. 0x3 DED Message RAM DED (Double Error Detection) interrupt pending. 0x4 EXT_TS_CNTR_OVFL External Timestamp Counter Overflow interrupt pending. 0x5 WAKEUP Clock Stop Wake Up interrupt pending. 0x6 CANFD1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 INTL0 MCAN Interrupt Line 0 mask. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 INTL1 MCAN Interrupt Line 1 mask. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 SEC Message RAM SEC interrupt mask. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 DED Massage RAM DED interrupt mask. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 EXT_TS_CNTR_OVFL External Timestamp Counter Overflow interrupt mask. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 WAKEUP Clock Stop Wake Up interrupt mask. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 CANFD1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INTL0 MCAN Interrupt Line 0. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INTL1 MCAN Interrupt Line 1. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 SEC Message RAM SEC interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DED Message RAM DED interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EXT_TS_CNTR_OVFL External Timestamp Counter Overflow interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 WAKEUP Clock Stop Wake Up interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CANFD1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INTL0 Masked MCAN Interrupt Line 0. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INTL1 Masked MCAN Interrupt Line 1. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 SEC Masked Message RAM SEC interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DED Masked Message RAM DED interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EXT_TS_CNTR_OVFL Masked External Timestamp Counter Overflow interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 WAKEUP Masked Clock Stop Wake Up interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CANFD1_ISET Interrupt set 0x20 32 write-only 0x00000000 INTL0 Set MCAN Interrupt Line 0. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 INTL1 Set MCAN Interrupt Line 1. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 SEC Set Message RAM SEC interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DED Set Message RAM DED interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EXT_TS_CNTR_OVFL Set External Timestamp Counter Overflow interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 WAKEUP Set Clock Stop Wake Up interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CANFD1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INTL0 Clear MCAN Interrupt Line 0. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 INTL1 Clear MCAN Interrupt Line 1. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 SEC Clear Message RAM SEC interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DED Clear Message RAM DED interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EXT_TS_CNTR_OVFL Clear External Timestamp Counter Overflow interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 WAKEUP Clear Clock Stop Wake Up interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CANFD1_EVT_MODE Event Mode 0xE0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 CANFD1_DESC Module Description 0xFC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 VERSION_0 MCAN module with CAN-FD mode enabled <<Internal Note: This is an in-IP paper spin variant. How does this map to the SYS_MCAN_ENABLE_FD choice value?>> 0x0 VERSION_1 MCAN module with CAN-FD mode disabled <<Internal Note: This is an in-IP paper spin variant. How does this map to the SYS_MCAN_ENABLE_FD choice value?>> 0x1 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CANFD1_MCANSS_CLKEN MCAN module clock enable 0x100 32 CLK_REQEN MCAN functional and MCAN/MCANSS MMR clock request enable bit 0x0 0x1 CLR MCAN module functional clock and Vbusp is not requested. These clocks are gated to the MCAN module. 0x0 SET Setting this bit requests MCAN module functional clock and Vbusp. These clocks are not gated to MCAN module. 0x1 CANFD1_MCANSS_CLKDIV Clock divider 0x104 32 read-write RATIO Clock divide ratio specification. Enables configuring clock divide settings for the MCAN functional clock input to the MCAN-SS. 0x0 0x2 read-write DIV_BY_1_ Divides input clock by 1 0x0 DIV_BY_2_ Divides input clock by 2 0x1 DIV_BY_4_ Divides input clock by 4 0x2 DIV_BY_1_1 Divides input clock by 1 0x3 CANFD1_MCANSS_CLKCTL MCAN-SS clock stop control register 0x108 32 read-write 0x00000000 STOPREQ This bit is used to enable/disable MCAN clock (both host clock and functional clock) gating request. Note: This bit can be reset by HW by Clock-Stop Wake-up via CAN RX Activity. See spec for more details. 0x0 0x1 DISABLE Disable MCAN-SS clock stop request 0x0 ENABLE Enable MCAN-SS clock stop request 0x1 WAKEUP_INT_EN This bit contols enabling or disabling the MCAN IP clock stop wakeup interrupt (when MCANSS_CTRL.WAKEUPREQEN wakeup request is enabled to wakeup MCAN IP upon CAN RXD activity) 0x4 0x1 read-write DISABLE Disable MCAN IP clock stop wakeup interrupt 0x0 ENABLE Enable MCAN IP clock stop wakeup interrupt 0x1 WKUP_GLTFLT_EN Setting this bit enables the glitch filter on MCAN RXD input, which wakes up the MCAN controller to exit clock gating. 0x8 0x1 read-write DISABLE Disable glitch filter enable on RXD input when MCAN is in clock stop mode (waiting for event on RXD input for clock stop wakeup). 0x0 ENABLE Enable glitch filter enable on RXD input when MCAN is in clock stop mode (waiting for event on RXD input for clock stop wakeup). 0x1 CANFD1_MCANSS_CLKSTS MCANSS clock stop status register 0x10C 32 read-only 0x00000000 CLKSTOP_ACKSTS Clock stop acknowledge status from MCAN IP 0x0 0x1 read-only RESET No clock stop acknowledged. 0x0 SET Clock stop has been acknowledged by MCAN IP; MCAN-SS may be clock gated by stopping both the CAN host and functional clocks. 0x1 STOPREQ_HW_OVR MCANSS clock stop HW override status bit. This bit indicates when the MCANSS_CLKCTL.STOPREQ bit has been cleared by HW when a clock-stop wake-up event via CAN RX activity is triggered. 0x4 0x1 read-only RESET MCANSS_CLKCTL.STOPREQ bit has not been cleared by HW. 0x0 SET MCANSS_CLKCTL.STOPREQ bit has been cleared by HW. 0x1 CCLKDONE This bit indicates the status of MCAN contoller clock request from GPRCM. 0x8 0x1 read-only RESET MCAN controller clock is not available to the MCAN IP. 0x0 SET MCAN controller clock is enabled and available to the MCAN IP. 0x1 AESADV AESADV 1.0 PERIPHERALREGION 0x40442000 0x0 0x1200 registers 1 24 0 AESADV_GPRCM[%s] 0x800 AESADV_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 AESADV_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 AESADV_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 AESADV_PDBGCTL Peripheral Debug Control 0x1018 32 read-only FREE Free run control 0x0 0x1 read-only RUN The peripheral ignores the state of the Core Halted input 0x1 1 44 0 AESADV_INT_EVENT0[%s] 0x1020 AESADV_INT_EVENT0_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 OUTPUTRDY This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x1 INPUTRDY This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x2 SAVEDCNTXTRDY This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit. 0x3 CNTXTRDY This bit indicates that the context data registers can be overwritten, and the CPU is permitted to write new context. 0x4 AESADV_INT_EVENT0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 OUTPUTRDY This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 INPUTRDY This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 SAVEDCNTXTRDY This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 CNTXTRDY This bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 AESADV_INT_EVENT0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 OUTPUTRDY This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INPUTRDY This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 SAVEDCNTXTRDY This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 CNTXTRDY This bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 AESADV_INT_EVENT0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 OUTPUTRDY This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INPUTRDY This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 SAVEDCNTXTRDY This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 CNTXTRDY This bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 AESADV_INT_EVENT0_ISET Interrupt set 0x20 32 write-only 0x00000000 OUTPUTRDY This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 INPUTRDY This indicates that the engine can take new input.This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 SAVEDCNTXTRDY This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 CNTXTRDY This bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 AESADV_INT_EVENT0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 OUTPUTRDY This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 INPUTRDY This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1) 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 SAVEDCNTXTRDY This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 CNTXTRDY This bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 1 44 0 AESADV_INT_EVENT1[%s] 0x1050 AESADV_INT_EVENT1_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TRIG0 AES trigger 0 DMA (Data Input trigger) 0x1 AESADV_INT_EVENT1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TRIG0 TRIG0 event mask. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 AESADV_INT_EVENT1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 TRIG0 TRIG0 event 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 AESADV_INT_EVENT1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TRIG0 TRIG0 event 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 AESADV_INT_EVENT1_ISET Interrupt set 0x20 32 write-only 0x00000000 TRIG0 TRIG0 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 AESADV_INT_EVENT1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TRIG0 TRIG0 event 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 AESADV_INT_EVENT2[%s] 0x1080 AESADV_INT_EVENT2_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TRIG1 AES DMA Trigger 1 (Data Output trigger) 0x1 AESADV_INT_EVENT2_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TRIG1 TRIG1 event mask. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 AESADV_INT_EVENT2_RIS Raw interrupt status 0x10 32 read-only 0x00000000 TRIG1 TRIG1 event 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 AESADV_INT_EVENT2_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TRIG1 TRIG1 event 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 AESADV_INT_EVENT2_ISET Interrupt set 0x20 32 write-only 0x00000000 TRIG1 TRIG1 event 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 AESADV_INT_EVENT2_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TRIG1 TRIG1 event 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 AESADV_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 AESADV_GCMCCM_TAG0 CBC-MAC third key (LSW) / GCM &amp; CCM Intermediate TAG (LSW) 0x1100 32 write-only 0x00000000 AESADV_GCMCCM_TAG1 CBC-MAC third key / GCM &amp; CCM Intermediate TAG 0x1104 32 write-only 0x00000000 AESADV_GCMCCM_TAG2 CBC-MAC third key / GCM &amp; CCM Intermediate TAG 0x1108 32 write-only 0x00000000 AESADV_GCMCCM_TAG3 CBC-MAC third key (MSW) / GCM &amp; CCM Intermediate TAG (MSW) 0x110C 32 write-only 0x00000000 AESADV_GHASH_H0 CCM &amp; CBC-MAC second key (LSW) / GCM Hash Key input (LSW) 0x1110 32 write-only 0x00000000 AESADV_GHASH_H1 CCM &amp; CBC-MAC second key / GCM Hash Key input 0x1114 32 write-only 0x00000000 AESADV_GHASH_H2 CCM &amp; CBC-MAC second key / GCM Hash Key input 0x1118 32 write-only 0x00000000 AESADV_GHASH_H3 CCM &amp; CBC-MAC second key (MSW) / GCM Hash Key input (MSW) 0x111C 32 write-only 0x00000000 AESADV_KEY0 KEY (LSW) 0x1120 32 write-only 0x00000000 AESADV_KEY1 KEY 0x1124 32 write-only 0x00000000 AESADV_KEY2 KEY 0x1128 32 write-only 0x00000000 AESADV_KEY3 KEY 0x112C 32 write-only 0x00000000 AESADV_KEY4 KEY 0x1130 32 write-only 0x00000000 AESADV_KEY5 KEY 0x1134 32 write-only 0x00000000 AESADV_KEY6 KEY 0x1138 32 write-only 0x00000000 AESADV_KEY7 KEY (MSW) 0x113C 32 write-only 0x00000000 AESADV_IV0 IV (LSW) 0x1140 32 read-write 0x00000000 AESADV_IV1 IV 0x1144 32 read-write 0x00000000 AESADV_IV2 IV 0x1148 32 read-write 0x00000000 AESADV_IV3 IV 0x114C 32 read-write 0x00000000 AESADV_CTRL Input/Output Buffer Control and Mode selection 0x1150 32 read-write 0x80000000 OUTPUT_RDY Output Ready. If 1b, this read-only status bit indicates that an AES output block is available for the CPU to retrieve. 0x0 0x1 read-only NOTREADY Not Ready 0x0 READY Ready 0x1 INPUT_RDY Ready for input. If 1b, this read-only status bit indicates that the 16-byte input buffer is empty, and the CPU is permitted to write the next block of data. After reset, this bit is 0. After writing a context, this bit will become 1b. 0x1 0x1 read-only NOTEMPTY Not Ready 0x0 EMPTY Ready 0x1 DIR Direction. If set to 1b an encrypt operation is performed. If set to 0b a decrypt operation is performed. Note: This bit must be written with a 1b when CBC-MAC is selected. 0x2 0x1 read-write DECRYPT Decryption 0x0 ENCRYPT Encryption 0x1 KEYSIZE Specifies the encryption strength / key width 0x3 0x2 read-write K128 128-bit key 0x1 K256 256-bit key 0x3 CBC If set to 1b, cipher-block-chaining (CBC) mode is selected. 0x5 0x1 read-write DISABLE Disable CBC mode 0x0 ENABLE Select CBC mode 0x1 CTR If set to 1b, AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM, when encryption/decryption is required. 0x6 0x1 read-write DISABLE Disable CBC mode 0x0 ENABLE Select CBC mode 0x1 CTR_WIDTH When the CTR bit is set, specifies the counter width for AES-CTR mode. When the CFB bit is set, specifies the CFB mode feedback width: 0x7 0x2 read-write CTR32 32-bit counter 0x0 CFB128 CFB-128 mode 0x0 CTR64 64-bit counter 0x1 CTR96 96-bit counter 0x2 CTR128 128-bit counter 0x3 ICM When the CFB bit is set, specifies the CFB mode feedback width: 0x9 0x1 read-write DISABLE Disable CBC mode 0x0 ENABLE Select CBC mode 0x1 CFB If set to 1b, AES cipher feedback mode CFB is selected. Use the ctr_width field to specify the feedback width. 0xA 0x1 read-write DISABLE Disable CBC mode 0x0 ENABLE Select CBC mode 0x1 CBCMAC If set to 1b, AES-CBC MAC is selected, the Direction bit must be set to 1 for this mode. 0xF 0x1 read-write DISABLE Disable CBC mode 0x0 ENABLE Select CBC mode 0x1 GCM If not set to 00b, AES-GCM mode is selected, this is a combined mode, using the Galois field multiplier GF(2128) for authentication and AES-CTR mode for encryption, the bits specify the GCM mode: 01b = GHASH with H loaded and Y0-encrypted forced to zero 10b = GHASH with H loaded and Y0-encrypted calculated internally 11b = Autonomous GHASH (both H and Y0-encrypted calculated internally) Note: Besides GCM, the CTR mode bits must also be set to 1b to enable GCM with AES-CTR; if the CTR bit is not set a GHASH (authentication) only operation is performed. A GHASH only operation is only allowed if the GCM mode is set to '01b' and the direction bit is set to '0b'. Other modes may not be selected in combination with GCM. Table 14 below shows the valid combinations for the GCM and CTR mode bits, all other options are invalid and must not be selected. 0x10 0x2 read-write FORCE_ZERO GHASH with H loaded and Y0-encrypted forced to 0. 0x1 LOAD_HASH_KEY GHASH with H loaded and Y0-encrypted calculated internally 0x2 AUTONOMOUS Autonomous GHASH (both H and Y0-encrypted calculated internally) 0x3 CCM If set to 1b, AES-CCM is selected, this is a combined mode, using AES for both authentication and encryption. In addition to the CCM bit, the CTR mode bit must be set such that AES-CTR is enabled. Other combinations with CCM are invalid. 0x12 0x1 read-write DISABLE Disable CBC mode 0x0 ENABLE Select CBC mode 0x1 CCML Defines L that indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. All values are supported. 0x13 0x3 read-write CCMM Defines M that indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one). Note: The EIP-39 always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported. 0x16 0x3 read-write OFB_GCM_CCM_CONT This bit has a dual use, depending on the selection of CCM/GCM, see bits [18:16]. If CCM/GCM is not selected: If this bit is set to 1b, full block AES output feedback mode (OFB-128) is selected. If CCM/GCM is selected: Continue processing of an interrupted AES-GCM or AES-CCM operation in the AAD phase. Set this write-only signal to 1b together with the regular mode bit settings for a GCM or CCM operation, to continue processing from the next full AAD block (128 bits) boundary. Before setting this bit all applicable context to resume processing must have been loaded into the engine: Keys, IV, intermediate digest/TAG, block counter and the CCM align data word (the latter is for CCM mode only). The mode can be written together with this bit, as it is part of the same register. 0x1A 0x1 read-write OFB Enable OFB 0x1 GCM_CCM_CONTINUE Continue GCM/CCM processing in AAD phase 0x1 GET_DIGEST Interrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation. Set this write-only signal to 1b to interrupt GCM or CCM processing at the next full block (128 bits) boundary. An intermediate digest may be requested during the encryption/decryption data phase or in the AAD phase. Note: Interruption can only be done on full block (128 bits) boundaries. The minimum number of remaining bytes to resume and finalize the operation, must be greater than or equal to 1. 0x1B 0x1 read-write NO_EFFECT No effect 0x0 ENABLE Enable 0x1 GCM_CONT Continue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase. Set this write-only signal to 1b together with the regular mode bit settings for a GCM or CCM operation, to continue processing from the next full block (128 bits) boundary. Before setting this bit all applicable context to resume processing must have been loaded into the engine: Keys, IV, intermediate digest/TAG and block counter. The mode can be written together with this bit, as it is part of the same register. 0x1C 0x1 read-write NO_EFFECT No effect 0x0 ENABLE Enable 0x1 SAVE_CNTXT This bit is used to indicate that an authentication TAG or result IV needs to be stored as a result context. If this bit is set, context output DMA and/or interrupt will be asserted if the operation is finished, and related signals are enabled. Typically, this value must be set for authentication modes returning a TAG (CBC-MAC, GCM and CCM), or for basic encryption modes that require future continuation with the current result IV. If this bit is set, the engine will hold its full context until the TAG and/or IV registers are read. Only after reading the TAG or IV, a new DMA request for a new (input) context will be asserted. If this bit is not set, the engine will assert the context input DMA request signal directly after starting to process the last block with the current context. 0x1D 0x1 read-write NO_EFFECT No effect 0x0 ENABLE Enable 0x1 SAVED_CNTXT_RDY If 1b, this read-only status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit. 0x1E 0x1 read-only NOTREADY Not ready 0x0 READY Ready 0x1 CNTXT_RDY If 1b, this read-only status bit indicates that the context data registers can be overwritten, and the CPU is permitted to write the next context. 0x1F 0x1 read-only NOTREADY Not ready 0x0 READY Ready 0x1 AESADV_C_LENGTH_0 Crypto data length (LSW) 0x1154 32 write-only 0x00000000 AESADV_C_LENGTH_1 Crypto data length (MSW) 0x1158 32 write-only 0x00000000 DATA Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261-1) bytes are allowed. For GCM, any value up to 236-32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232-2, resulting in a maximum number of bytes of 236-32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note that for the combined modes, this length does not include the authentication only data; the authentication length is specified in the AES_AAD_LENGTH register below. All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero. For the basic encryption modes (ECB/CBC/CTR/ICM/CFB/OFB) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes; bit aligned data streams are not supported. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. 0x0 0x1D write-only AESADV_AAD_LENGTH AAD Data Length 0x115C 32 write-only 0x00000000 AESADV_DATA0 Data input (LSW) / Data output (LSW) 0x1160 32 read-write 0x00000000 AESADV_DATA1 Data input / Data output 0x1164 32 read-write 0x00000000 AESADV_DATA2 Data input / Data output 0x1168 32 read-write 0x00000000 AESADV_DATA3 Data input (LSW) / Data output (MSW) 0x116C 32 read-write 0x00000000 AESADV_TAG0 Hash result (LSW) 0x1170 32 read-only 0x00000000 AESADV_TAG1 Hash result 0x1174 32 read-only 0x00000000 AESADV_TAG2 Hash result 0x1178 32 read-only 0x00000000 AESADV_TAG3 Hash result (MSW) 0x117C 32 read-only 0x00000000 AESADV_STATUS Status 0x1180 32 read-only KEYWR Key write status. 0 - user write to KEY register is allowed. 1 - user write to KEY register is ignored. In order to allow user write, perform a module reset. 0x0 0x1 read-only ENABLED User write to KEY MMR is allowed 0x0 DISABLED User write to KEY MMR is disabled. Writing has no effect. 0x1 AESADV_DATA_IN Data in alias register 0x1184 32 write-only AESADV_DATA_OUT Data out alias register 0x1188 32 read-only AESADV_FORCE_IN_AV Data control register for input data 0x11D0 32 write-only 0x00000000 AESADV_CCM_ALN_WRD AES-CCM AAD alignment data word 0x11D4 32 read-write 0x00000000 AESADV_BLK_CNT0 Internal block counter (LSW) 0x11D8 32 read-write 0x00000000 AESADV_BLK_CNT1 Internal block counter (MSW) 0x11DC 32 read-write 0x00000000 DATA Internal block counter for AES GCM and CCM operations. These bits read the block count value that represents the number of blocks to go. This value is valid with saved_context_ready after a request for an intermediate GCM/CCM digest. Writing these registers will restore the internal block counter to the programmed value. This only needs to be done to prepare the engine to continue processing of an interrupted GCM or CCM operation. Also refer to the get_digest and gcm_ccm_continue bits in AES_CTRL register. 0x0 0x18 read-write AESADV_DMA_HS Control register for DMA handshaking 0x11F4 32 read-write 0x00000000 DMA_DATA_ACK When this bit is 0b, input and output data acknowledge is I/O register based, as specified in the description of the AES_DATA_IN_n / AES_DATA_OUT_n registers. When this bit is 1b, input and ouput data acknowledge is based on DMA handshake signals. 0x0 0x1 read-write DMA_DISABLE Disable DMA based data handshake 0x0 DMA_ENABLE Enables DMA based handshake 0x1 SYSCTL SYSCTL 1.0 mem_map 0x400AF000 0x0 0x3100 registers SYSCTL_MGMT_ADC12B4MSPS0_PWREN IP Enable Register 0x800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_ADC12B4MSPS0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_ADC12B4MSPS0_CLKCFG IP Clock Configuration Register 0x808 32 read-write 0x00000000 0xff000033 CCONSTOP Conversion Clock is ON during STOP Mode 0x5 0x1 read-write Disable 0x0 Enable 0x1 CCONRUN Conversion Clock is ON during RUN Mode 0x4 0x1 read-write Disable 0x0 Enable 0x1 SAMPCLK Sample Window Clock 0x0 0x2 read-write ULPCLK 0x0 SYSOSC 0x1 HFCLK 0x2 SYSCTL_MGMT_ADC12B4MSPS0_STAT IP State Register - Read Only 0x814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_IIDX SYSCTL interrupt index 0x1020 32 read-only 0x00000000 0x0000000f STAT The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers. 0x0 0x4 read-only NO_INTR No interrupt pending 0x0 LFOSCGOOD LFOSCGOOD interrupt pending 0x1 ANACLKERR 0x2 FLASHSEC 0x3 SRAMSEC 0x4 LFXTGOOD 0x5 HFCLKGOOD 0x6 SYSPLLGOOD 0x7 HSCLKGOOD 0x8 SYSCTL_IMASK SYSCTL interrupt mask 0x1028 32 read-write 0x00000000 0x000000ff LFOSCGOOD Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully. 0x0 0x1 read-write DISABLE Interrupt disabled 0x0 ENABLE Interrupt enabled 0x1 HFCLKGOOD HFCLK GOOD 0x5 0x1 read-write DISABLE 0x0 ENABLE 0x1 SRAMSEC SRAM Single Error Correct 0x3 0x1 read-write DISABLE 0x0 ENABLE 0x1 LFXTGOOD LFXT GOOD 0x4 0x1 read-write DISABLE 0x0 ENABLE 0x1 HSCLKGOOD HSCLK GOOD 0x7 0x1 read-write DISABLE 0x0 ENABLE 0x1 SYSPLLGOOD SYSPLL GOOD 0x6 0x1 read-write DISABLE 0x0 ENABLE 0x1 ANACLKERR Analog Clocking Consistency Error 0x1 0x1 read-write DISABLE 0x0 ENABLE 0x1 FLASHSEC Flash Single Error Correct 0x2 0x1 read-write DISABLE 0x0 ENABLE 0x1 SYSCTL_RIS SYSCTL raw interrupt status 0x1030 32 read-only 0x00000000 0x000000ff LFOSCGOOD Raw status of the LFOSCGOOD interrupt. 0x0 0x1 read-only FALSE No interrupt pending 0x0 TRUE Interrupt pending 0x1 HFCLKGOOD HFCLK GOOD 0x5 0x1 read-only FALSE 0x0 TRUE 0x1 SRAMSEC SRAM Single Error Correct 0x3 0x1 read-only FALSE 0x0 TRUE 0x1 LFXTGOOD LFXT GOOD 0x4 0x1 read-only FALSE 0x0 TRUE 0x1 HSCLKGOOD HSCLK GOOD 0x7 0x1 read-only FALSE 0x0 TRUE 0x1 SYSPLLGOOD SYSPLL GOOD 0x6 0x1 read-only FALSE 0x0 TRUE 0x1 ANACLKERR Analog Clocking Consistency Error 0x1 0x1 read-only FALSE 0x0 TRUE 0x1 FLASHSEC Flash Single Error Correct 0x2 0x1 read-only FALSE 0x0 TRUE 0x1 SYSCTL_MIS SYSCTL masked interrupt status 0x1038 32 read-only 0x00000000 0x000000ff LFOSCGOOD Masked status of the LFOSCGOOD interrupt. 0x0 0x1 read-only FALSE No interrupt pending 0x0 TRUE Interrupt pending 0x1 HFCLKGOOD HFCLK GOOD 0x5 0x1 read-only FALSE 0x0 TRUE 0x1 SRAMSEC SRAM Single Error Correct 0x3 0x1 read-only FALSE 0x0 TRUE 0x1 LFXTGOOD LFXT GOOD 0x4 0x1 read-only FALSE 0x0 TRUE 0x1 HSCLKGOOD HSCLK GOOD 0x7 0x1 read-only FALSE 0x0 TRUE 0x1 SYSPLLGOOD SYSPLL GOOD 0x6 0x1 read-only FALSE 0x0 TRUE 0x1 ANACLKERR Analog Clocking Consistency Error 0x1 0x1 read-only FALSE 0x0 TRUE 0x1 FLASHSEC Flash Single Error Correct 0x2 0x1 read-only FALSE 0x0 TRUE 0x1 SYSCTL_ISET SYSCTL interrupt set 0x1040 32 write-only 0x00000000 0x000000ff LFOSCGOOD Set the LFOSCGOOD interrupt. 0x0 0x1 write-only NO_EFFECT Writing 0h hs no effect 0x0 SET Set interrupt 0x1 HFCLKGOOD HFCLK GOOD 0x5 0x1 write-only NO_EFFECT 0x0 SET 0x1 SRAMSEC SRAM Single Error Correct 0x3 0x1 write-only NO_EFFECT 0x0 SET 0x1 LFXTGOOD LFXT GOOD 0x4 0x1 write-only NO_EFFECT 0x0 SET 0x1 HSCLKGOOD HSCLK GOOD 0x7 0x1 write-only NO_EFFECT 0x0 SET 0x1 SYSPLLGOOD SYSPLL GOOD 0x6 0x1 write-only NO_EFFECT 0x0 SET 0x1 ANACLKERR Analog Clocking Consistency Error 0x1 0x1 write-only NO_EFFECT 0x0 SET 0x1 FLASHSEC Flash Single Error Correct 0x2 0x1 write-only NO_EFFECT 0x0 SET 0x1 SYSCTL_ICLR SYSCTL interrupt clear 0x1048 32 write-only 0x00000000 0x000000ff LFOSCGOOD Clear the LFOSCGOOD interrupt. 0x0 0x1 write-only NO_EFFECT Writing 0h has no effect 0x0 CLR Clear interrupt 0x1 HFCLKGOOD HFCLK GOOD 0x5 0x1 write-only NO_EFFECT 0x0 CLR 0x1 SRAMSEC SRAM Single Error Correct 0x3 0x1 write-only NO_EFFECT 0x0 CLR 0x1 LFXTGOOD LFXT GOOD 0x4 0x1 write-only NO_EFFECT 0x0 CLR 0x1 HSCLKGOOD HSCLK GOOD 0x7 0x1 write-only NO_EFFECT 0x0 CLR 0x1 SYSPLLGOOD SYSPLL GOOD 0x6 0x1 write-only NO_EFFECT 0x0 CLR 0x1 ANACLKERR Analog Clocking Consistency Error 0x1 0x1 write-only NO_EFFECT 0x0 CLR 0x1 FLASHSEC Flash Single Error Correct 0x2 0x1 write-only NO_EFFECT 0x0 CLR 0x1 SYSCTL_NMIIIDX NMI interrupt index 0x1050 32 read-only 0x00000000 0x0000000f STAT The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register. 0x0 0x4 read-only NO_INTR No NMI pending 0x0 BORLVL BOR Threshold NMI pending 0x1 WWDT0 0x2 WWDT1 0x3 LFCLKFAIL 0x4 FLASHDED 0x5 SRAMDED 0x6 SYSCTL_NMIRIS NMI raw interrupt status 0x1060 32 read-only 0x00000000 0x0000003f WWDT1 Watch Dog 0 Fault 0x2 0x1 read-only FALSE 0x0 TRUE 0x1 SRAMDED SRAM Double Error Detect 0x5 0x1 read-only FALSE 0x0 TRUE 0x1 BORLVL Raw status of the BORLVL NMI 0x0 0x1 read-only FALSE No interrupt pending 0x0 TRUE Interrupt pending 0x1 FLASHDED Flash Double Error Detect 0x4 0x1 read-only FALSE 0x0 TRUE 0x1 WWDT0 Watch Dog 0 Fault 0x1 0x1 read-only FALSE 0x0 TRUE 0x1 LFCLKFAIL LFXT-EXLF Monitor Fail 0x3 0x1 read-only FALSE 0x0 TRUE 0x1 SYSCTL_NMIISET NMI interrupt set 0x1070 32 write-only 0x00000000 0x0000003f WWDT1 Watch Dog 0 Fault 0x2 0x1 write-only NO_EFFECT 0x0 SET 0x1 SRAMDED SRAM Double Error Detect 0x5 0x1 write-only NO_EFFECT 0x0 SET 0x1 BORLVL Set the BORLVL NMI 0x0 0x1 write-only NO_EFFECT Writing 0h hs no effect 0x0 SET Set interrupt 0x1 FLASHDED Flash Double Error Detect 0x4 0x1 write-only NO_EFFECT 0x0 SET 0x1 WWDT0 Watch Dog 0 Fault 0x1 0x1 write-only NO_EFFECT 0x0 SET 0x1 LFCLKFAIL LFXT-EXLF Monitor Fail 0x3 0x1 write-only NO_EFFECT 0x0 SET 0x1 SYSCTL_NMIICLR NMI interrupt clear 0x1078 32 write-only 0x00000000 0x0000003f WWDT1 Watch Dog 0 Fault 0x2 0x1 write-only NO_EFFECT 0x0 CLR 0x1 SRAMDED SRAM Double Error Detect 0x5 0x1 write-only NO_EFFECT 0x0 CLR 0x1 BORLVL Clr the BORLVL NMI 0x0 0x1 write-only NO_EFFECT Writing 0h hs no effect 0x0 CLR Clear interrupt 0x1 FLASHDED Flash Double Error Detect 0x4 0x1 write-only NO_EFFECT 0x0 CLR 0x1 WWDT0 Watch Dog 0 Fault 0x1 0x1 write-only NO_EFFECT 0x0 CLR 0x1 LFCLKFAIL LFXT-EXLF Monitor Fail 0x3 0x1 write-only NO_EFFECT 0x0 CLR 0x1 SYSCTL_SYSOSCCFG SYSOSC configuration 0x1100 32 read-write 0x00020000 0x00030703 USE4MHZSTOP USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption. 0x8 0x1 read-write DISABLE Do not gear shift the SYSOSC to 4MHz in STOP mode 0x0 ENABLE Gear shift SYSOSC to 4MHz in STOP mode 0x1 DISABLESTOP DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption. 0x9 0x1 read-write DISABLE Do not disable SYSOSC in STOP mode 0x0 ENABLE Disable SYSOSC in STOP mode and source ULPCLK from LFCLK 0x1 BLOCKASYNCALL BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode. 0x10 0x1 read-write DISABLE Asynchronous fast clock requests are controlled by the requesting peripheral 0x0 ENABLE All asynchronous fast clock requests are blocked 0x1 DISABLE DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK. 0xA 0x1 read-write DISABLE Do not disable SYSOSC 0x0 ENABLE Disable SYSOSC immediately and source MCLK and ULPCLK from LFCLK 0x1 FASTCPUEVENT FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency. 0x11 0x1 read-write DISABLE An interrupt to the CPU will not assert a fast clock request 0x0 ENABLE An interrupt to the CPU will assert a fast clock request 0x1 FREQ Target operating frequency for the system oscillator (SYSOSC) 0x0 0x2 read-write SYSOSCBASE Base frequency (32MHz) 0x0 SYSOSC4M Low frequency (4MHz) 0x1 SYSOSCUSER User-trimmed frequency (16 or 24 MHz) 0x2 SYSCTL_MCLKCFG Main clock (MCLK) configuration 0x1104 32 read-write 0x00000210 0x00711f3f USEMFTICK USEMFTICK specifies whether the 4MHz constant-rate clock (MFCLK) to peripherals is enabled or disabled. When enabled, MDIV must be disabled (set to 0h=/1). 0xC 0x1 read-write DISABLE The 4MHz rate MFCLK to peripherals is enabled 0x0 ENABLE The 4MHz rate MFCLK to peripherals is enabled. 0x1 MDIV MDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC. MDIV=0h corresponds to /1 (no divider). MDIV=1h corresponds to /2 (divide-by-2). MDIV=Fh corresponds to /16 (divide-by-16). MDIV may be set between /1 and /16 on an integer basis. 0x0 0x4 read-write USEHSCLK USEHSCLK, together with USELFCLK, sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes. 0x10 0x1 read-write DISABLE MCLK will not use the high speed clock (HSCLK) 0x0 ENABLE MCLK will use the high speed clock (HSCLK) in RUN and SLEEP mode 0x1 USELFCLK USELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source. Note that setting USELFCLK does not disable SYSOSC, and SYSOSC remains available for direct use by analog modules. 0x14 0x1 read-write DISABLE MCLK will not use the low frequency clock (LFCLK) 0x0 ENABLE MCLK will use the low frequency clock (LFCLK) 0x1 STOPCLKSTBY STOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1). When set, ULPCLK and LFCLK are disabled to all peripherals in STANDBY mode, with the exception of TIMG0 and TIMG1 which continue to run. Wake-up is only possible via an asynchronous fast clock request. 0x15 0x1 read-write DISABLE ULPCLK/LFCLK runs to all PD0 peripherals in STANDBY mode 0x0 ENABLE ULPCLK/LFCLK is disabled to all peripherals in STANDBY mode except TIMG0 and TIMG1 0x1 FLASHWAIT FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK. 0x8 0x4 read-write WAIT0 No flash wait states are applied 0x0 WAIT1 One flash wait state is applied 0x1 WAIT2 2 flash wait states are applied 0x2 MCLKDEADCHK MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled. 0x16 0x1 read-write DISABLE The MCLK dead check monitor is disabled 0x0 ENABLE The MCLK dead check monitor is enabled 0x1 UDIV UDIV specifies the ULPCLK divider when MCLK is sourced from HSCLK. UDIV has no effect when MCLK is sourced from SYSOSC or LFCLK. 0x4 0x2 read-write NODIVIDE ULPCLK is not divided and is equal to MCLK 0x0 DIVIDE2 ULPCLK is MCLK/2 (divided-by-2) 0x1 SYSCTL_HSCLKEN High-speed clock (HSCLK) source enable/disable 0x1108 32 read-write 0x00000000 0x00010101 HFXTEN HFXTEN enables or disables the high frequency crystal oscillator (HFXT). 0x0 0x1 read-write DISABLE Disable the HFXT 0x0 ENABLE Enable the HFXT 0x1 USEEXTHFCLK USEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled, HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously. 0x10 0x1 read-write DISABLE Use HFXT as the HFCLK source 0x0 ENABLE Use the HFCLK_IN digital clock input as the HFCLK source 0x1 SYSPLLEN SYSPLLEN enables or disables the system phase-lock loop (SYSPLL). 0x8 0x1 read-write DISABLE Disable the SYSPLL 0x0 ENABLE Enable the SYSPLL 0x1 SYSCTL_HSCLKCFG High-speed clock (HSCLK) source selection 0x110C 32 read-write 0x00000000 0x00000001 HSCLKSEL HSCLKSEL selects the HSCLK source (SYSPLL or HFCLK). 0x0 0x1 read-write SYSPLL HSCLK is sourced from the SYSPLL 0x0 HFCLKCLK HSCLK is sourced from the HFCLK 0x1 SYSCTL_HFCLKCLKCFG High-frequency clock (HFCLK) configuration 0x1110 32 read-write 0x10000000 0x100030ff HFXTTIME HFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time expires. 0x0 0x8 read-write MINSTARTTIME Minimum startup time (approximatly zero) 0x0 MAXSTARTTIME Maximum startup time (approximatly 16.32ms) 0xFF HFCLKFLTCHK HFCLKFLTCHK enables or disables the HFCLK startup monitor. 0x1C 0x1 read-write DISABLE HFCLK startup is not checked 0x0 ENABLE HFCLK startup is checked 0x1 HFXTRSEL HFXT Range Select 0xC 0x2 read-write RANGE4TO8 4MHz <= HFXT frequency <= 8MHz 0x0 RANGE8TO16 8MHz < HFXT frequency <= 16MHz 0x1 RANGE16TO32 16MHz < HFXT frequency <= 32MHz 0x2 RANGE32TO48 32MHz < HFXT frequency <= 48MHz 0x3 SYSCTL_LFCLKCFG Low frequency crystal oscillator (LFXT) configuration 0x1114 32 read-write 0x00000003 0x00000113 XT1DRIVE XT1DRIVE selects the low frequency crystal oscillator (LFXT) drive strength. 0x0 0x2 read-write LOWESTDRV Lowest drive and current 0x0 LOWERDRV Lower drive and current 0x1 HIGHERDRV Higher drive and current 0x2 HIGHESTDRV Highest drive and current 0x3 MONITOR MONITOR enables or disables the LFCLK monitor, which continuously checks LFXT or LFCLK_IN for a clock stuck fault. 0x4 0x1 read-write DISABLE Clock monitor is disabled 0x0 ENABLE Clock monitor is enabled 0x1 LOWCAP LOWCAP controls the low-power LFXT mode. When the LFXT load capacitance is less than 3pf, LOWCAP may be set for reduced power consumption. 0x8 0x1 read-write DISABLE LFXT low capacitance mode is disabled 0x0 ENABLE LFXT low capacitance mode is enabled 0x1 SYSCTL_SYSPLLCFG0 SYSPLL reference and output configuration 0x1120 32 read-write 0x00000000 0x000fff73 ENABLECLK0 ENABLECLK0 enables or disables the SYSPLLCLK0 output. 0x4 0x1 read-write DISABLE SYSPLLCLK0 is disabled 0x0 ENABLE SYSPLLCLK0 is enabled 0x1 ENABLECLK1 ENABLECLK1 enables or disables the SYSPLLCLK1 output. 0x5 0x1 read-write DISABLE SYSPLLCLK1 is disabled 0x0 ENABLE SYSPLLCLK1 is enabled 0x1 RDIVCLK1 RDIVCLK1 sets the final divider for the SYSPLLCLK1 output. 0xC 0x4 read-write CLK1DIV2 SYSPLLCLK1 is divided by 2 0x0 CLK1DIV4 SYSPLLCLK1 is divided by 4 0x1 CLK1DIV6 SYSPLLCLK1 is divided by 6 0x2 CLK1DIV8 SYSPLLCLK1 is divided by 8 0x3 CLK1DIV10 SYSPLLCLK1 is divided by 10 0x4 CLK1DIV12 SYSPLLCLK1 is divided by 12 0x5 CLK1DIV14 SYSPLLCLK1 is divided by 14 0x6 CLK1DIV16 SYSPLLCLK1 is divided by 16 0x7 CLK1DIV18 SYSPLLCLK1 is divided by 18 0x8 CLK1DIV20 SYSPLLCLK1 is divided by 20 0x9 CLK1DIV22 SYSPLLCLK1 is divided by 22 0xA CLK1DIV24 SYSPLLCLK1 is divided by 24 0xB CLK1DIV26 SYSPLLCLK1 is divided by 26 0xC CLK1DIV28 SYSPLLCLK1 is divided by 28 0xD CLK1DIV30 SYSPLLCLK1 is divided by 30 0xE CLK1DIV32 SYSPLLCLK1 is divided by 32 0xF MCLK2XVCO MCLK2XVCO selects the SYSPLL output which is sent to the HSCLK mux for use by MCLK. 0x1 0x1 read-write DISABLE The SYSPLLCLK0 output is sent to the HSCLK mux 0x0 ENABLE The SYSPLLCLK2X output is sent to the HSCLK mux 0x1 RDIVCLK2X RDIVCLK2X sets the final divider for the SYSPLLCLK2X output. 0x10 0x4 read-write CLK2XDIV1 SYSPLLCLK1 is divided by 1 0x0 CLK2XDIV2 SYSPLLCLK1 is divided by 2 0x1 CLK2XDIV3 SYSPLLCLK1 is divided by 3 0x2 CLK2XDIV4 SYSPLLCLK1 is divided by 4 0x3 CLK2XDIV5 SYSPLLCLK1 is divided by 5 0x4 CLK2XDIV6 SYSPLLCLK1 is divided by 6 0x5 CLK2XDIV7 SYSPLLCLK1 is divided by 7 0x6 CLK2XDIV8 SYSPLLCLK1 is divided by 8 0x7 CLK2XDIV9 SYSPLLCLK1 is divided by 9 0x8 CLK2XDIV10 SYSPLLCLK1 is divided by 10 0x9 CLK2XDIV11 SYSPLLCLK1 is divided by 11 0xA CLK2XDIV12 SYSPLLCLK1 is divided by 12 0xB CLK2XDIV13 SYSPLLCLK1 is divided by 13 0xC CLK2XDIV14 SYSPLLCLK1 is divided by 14 0xD CLK2XDIV15 SYSPLLCLK1 is divided by 15 0xE CLK2XDIV16 SYSPLLCLK1 is divided by 16 0xF RDIVCLK0 RDIVCLK0 sets the final divider for the SYSPLLCLK0 output. 0x8 0x4 read-write CLK0DIV2 SYSPLLCLK0 is divided by 2 0x0 CLK0DIV4 SYSPLLCLK0 is divided by 4 0x1 CLK0DIV6 SYSPLLCLK0 is divided by 6 0x2 CLK0DIV8 SYSPLLCLK0 is divided by 8 0x3 CLK0DIV10 SYSPLLCLK0 is divided by 10 0x4 CLK0DIV12 SYSPLLCLK0 is divided by 12 0x5 CLK0DIV14 SYSPLLCLK0 is divided by 14 0x6 CLK0DIV16 SYSPLLCLK0 is divided by 16 0x7 CLK0DIV18 SYSPLLCLK0 is divided by 18 0x8 CLK0DIV20 SYSPLLCLK0 is divided by 20 0x9 CLK0DIV22 SYSPLLCLK0 is divided by 22 0xA CLK0DIV24 SYSPLLCLK0 is divided by 24 0xB CLK0DIV26 SYSPLLCLK0 is divided by 26 0xC CLK0DIV28 SYSPLLCLK0 is divided by 28 0xD CLK0DIV30 SYSPLLCLK0 is divided by 30 0xE CLK0DIV32 SYSPLLCLK0 is divided by 32 0xF SYSPLLREF SYSPLLREF selects the system PLL (SYSPLL) reference clock source. 0x0 0x1 read-write SYSOSC SYSPLL reference is SYSOSC 0x0 HFCLK SYSPLL reference is HFCLK 0x1 ENABLECLK2X ENABLECLK2X enables or disables the SYSPLLCLK2X output. 0x6 0x1 read-write DISABLE SYSPLLCLK2X is disabled 0x0 ENABLE SYSPLLCLK2X is enabled 0x1 SYSCTL_SYSPLLCFG1 SYSPLL reference and feedback divider 0x1124 32 read-write 0x00000000 0x00007f03 PDIV PDIV selects the SYSPLL reference clock prescale divider. 0x0 0x2 read-write REFDIV1 SYSPLLREF is not divided 0x0 REFDIV2 SYSPLLREF is divided by 2 0x1 REFDIV4 SYSPLLREF is divided by 4 0x2 REFDIV8 SYSPLLREF is divided by 8 0x3 QDIV QDIV selects the SYSPLL feedback path divider. 0x8 0x7 read-write INVALID Divide-by-one is not a valid QDIV option 0x0 QDIVMIN Feedback path is divided by 2 0x1 QDIVMAX Feedback path is divided by 127 (0x7E) 0x7E SYSCTL_SYSPLLPARAM0 SYSPLL PARAM0 (load from FACTORY region) 0x1128 32 read-write 0x00000000 0x9f3f3f3f CPCURRENT Charge pump current 0x10 0x6 read-write CAPBOVERRIDE CAPBOVERRIDE controls the override for Cap B 0x1F 0x1 read-write DISABLE Cap B override disabled 0x0 ENABLE Cap B override enabled 0x1 STARTTIME Startup time from enable to locked clock, in 1us resolution 0x0 0x6 read-write CAPBVAL Override value for Cap B 0x18 0x5 read-write STARTTIMELP Startup time from low power mode exit to locked clock, in 1us resolution 0x8 0x6 read-write SYSCTL_SYSPLLPARAM1 SYSPLL PARAM1 (load from FACTORY region) 0x112C 32 read-write 0x00000000 0xff03ff1f LPFCAPA Loop filter Cap A 0x0 0x5 read-write LPFRESC Loop filter Res C 0x18 0x8 read-write LPFRESA Loop filter Res A 0x8 0xA read-write SYSCTL_GENCLKCFG General clock configuration 0x1138 32 read-write 0x00000000 0x1ffff3f7 HFCLK4MFPCLKDIV HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected. 0xC 0x4 read-write DIV1 HFCLK is not divided before being used for MFPCLK 0x0 DIV2 HFCLK is divided by 2 before being used for MFPCLK 0x1 DIV3 HFCLK is divided by 3 before being used for MFPCLK 0x2 DIV4 HFCLK is divided by 4 before being used for MFPCLK 0x3 DIV5 HFCLK is divided by 5 before being used for MFPCLK 0x4 DIV6 HFCLK is divided by 6 before being used for MFPCLK 0x5 DIV7 HFCLK is divided by 7 before being used for MFPCLK 0x6 DIV8 HFCLK is divided by 8 before being used for MFPCLK 0x7 DIV9 HFCLK is divided by 9 before being used for MFPCLK 0x8 DIV10 HFCLK is divided by 10 before being used for MFPCLK 0x9 DIV11 HFCLK is divided by 11 before being used for MFPCLK 0xA DIV12 HFCLK is divided by 12 before being used for MFPCLK 0xB DIV13 HFCLK is divided by 13 before being used for MFPCLK 0xC DIV14 HFCLK is divided by 14 before being used for MFPCLK 0xD DIV15 HFCLK is divided by 15 before being used for MFPCLK 0xE DIV16 HFCLK is divided by 16 before being used for MFPCLK 0xF MFPCLKSRC MFPCLKSRC selects the MFPCLK (middle frequency precision clock) source. 0x9 0x1 read-write SYSOSC MFPCLK is sourced from SYSOSC 0x0 HFCLK MFPCLK is sourced from HFCLK 0x1 CANCLKSRC CANCLKSRC selects the CANCLK source. 0x8 0x1 read-write HFCLK CANCLK source is HFCLK 0x0 SYSPLLOUT1 CANCLK source is SYSPLLCLK1 0x1 FCCTRIGCNT FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified. 0x18 0x5 read-write ANACPUMPCFG ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method. 0x16 0x2 read-write ONDEMAND VBOOST is enabled on request from a COMP, GPAMP, or OPA 0x0 ONACTIVE VBOOST is enabled when the device is in RUN or SLEEP mode, or when a COMP/GPAMP/OPA is enabled 0x1 ONALWAYS VBOOST is always enabled 0x2 FCCSELCLK FCCSELCLK selectes the frequency clock counter (FCC) clock source. 0x10 0x4 read-write MCLK FCC clock is MCLK 0x0 SYSOSC FCC clock is SYSOSC 0x1 HFCLK FCC clock is HFCLK 0x2 EXTCLK FCC clock is the CLK_OUT selection 0x3 SYSPLLCLK0 FCC clock is SYSPLLCLK0 0x4 SYSPLLCLK1 FCC clock is SYSPLLCLK1 0x5 SYSPLLCLK2X FCC clock is SYSPLLCLK2X 0x6 FCCIN FCC clock is the FCCIN external input 0x7 FCCTRIGSRC FCCTRIGSRC selects the frequency clock counter (FCC) trigger source. 0x14 0x1 read-write EXTPIN FCC trigger is the external pin 0x0 LFCLK FCC trigger is the LFCLK 0x1 FCCLVLTRIG FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode. 0x15 0x1 read-write RISE2RISE Rising edge to rising edge triggered 0x0 LEVEL Level triggered 0x1 EXCLKSRC EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled 0x0 0x3 read-write SYSOSC CLK_OUT is SYSOSC 0x0 ULPCLK CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled) 0x1 LFCLK CLK_OUT is LFCLK 0x2 MFPCLK CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled) 0x3 HFCLK CLK_OUT is HFCLK 0x4 SYSPLLOUT1 CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be <=48MHz) 0x5 EXCLKDIVVAL EXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block. 0x4 0x3 read-write DIV2 CLK_OUT source is divided by 2 0x0 DIV4 CLK_OUT source is divided by 4 0x1 DIV6 CLK_OUT source is divided by 6 0x2 DIV8 CLK_OUT source is divided by 8 0x3 DIV10 CLK_OUT source is divided by 10 0x4 DIV12 CLK_OUT source is divided by 12 0x5 DIV14 CLK_OUT source is divided by 14 0x6 DIV16 CLK_OUT source is divided by 16 0x7 EXCLKDIVEN EXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block. 0x7 0x1 read-write PASSTHRU CLock divider is disabled (passthrough, EXCLKDIVVAL is not applied) 0x0 ENABLE Clock divider is enabled (EXCLKDIVVAL is applied) 0x1 SYSCTL_GENCLKEN General clock enable control 0x113C 32 read-write 0x00000000 0x00000011 EXCLKEN EXCLKEN enables the CLK_OUT external clock output block. 0x0 0x1 read-write DISABLE CLK_OUT block is disabled 0x0 ENABLE CLK_OUT block is enabled 0x1 MFPCLKEN MFPCLKEN enables the middle frequency precision clock (MFPCLK). 0x4 0x1 read-write DISABLE MFPCLK is disabled 0x0 ENABLE MFPCLK is enabled 0x1 SYSCTL_PMODECFG Power mode configuration 0x1140 32 read-write 0x00000000 0x00000003 DSLEEP DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU. 0x0 0x2 read-write STOP STOP mode is entered 0x0 STANDBY STANDBY mode is entered 0x1 SHUTDOWN SHUTDOWN mode is entered 0x2 SYSCTL_FCC Frequency clock counter (FCC) count 0x1150 32 read-only 0x00000000 0x003fffff DATA Frequency clock counter (FCC) count value. 0x0 0x16 read-only SYSCTL_SYSOSCTRIMUSER SYSOSC user-specified trim 0x1170 32 read-write 0x00000000 0x1fff3f73 RESCOARSE RESCOARSE specifies the resister coarse trim. This value changes with the target frequency. 0x8 0x6 read-write RESFINE RESFINE specifies the resister fine trim. This value changes with the target frequency. 0x10 0x4 read-write RDIV RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency. 0x14 0x9 read-write FREQ FREQ specifies the target user-trimmed frequency for SYSOSC. 0x0 0x2 read-write SYSOSC16M 16MHz user frequency 0x1 SYSOSC24M 24MHz user frequency 0x2 CAP CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency. 0x4 0x3 read-write SYSCTL_SRAMBOUNDARY SRAM Write Boundary 0x1178 32 read-write 0x00000000 0x000fffe0 ADDR SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size. 0x5 0xF read-write SYSCTL_SRAMBOUNDARYHIGH SRAM Write Boundary High 0x117C 32 read-write 0x00000000 0x000fffe0 ADDR SRAM boundary high configuration. The value configured into this acts such that: SRAM accesses to greater than value will be RW only. SRAM accesses to addresses less than or equal to value will be RX until meeting SRAMBOUNDARY MMR Value. Value of 0 is default. If value set to less than or equal to SRAMBOUNDARY MMR, the system will only use the SRAMBOUNDARY MMR as criteria. 0x5 0xF read-write SYSCTL_SYSTEMCFG System configuration 0x1180 32 read-write 0x00000006 0xff000007 FLASHECCRSTDIS FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI. 0x2 0x1 read-write FALSE Flash ECC DED will trigger a SYSRST 0x0 TRUE Flash ECC DED will trigger a NMI 0x1 WWDTLP0RSTDIS WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI. 0x0 0x1 read-write FALSE WWDTLP0 Error Event will trigger a BOOTRST 0x0 TRUE WWDTLP0 Error Event will trigger an NMI 0x1 WWDTLP1RSTDIS WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI. 0x1 0x1 read-write FALSE WWDTLP1 Error Event will trigger a SYSRST 0x0 TRUE WWDTLP1 Error Event will trigger an NMI 0x1 SYSCTL_SRAMCFG System SRAM configuration 0x1184 32 read-write 0x00000000 0xff000202 BANKSTOP1 SRAM BANK1 power level for STOP mode 0x9 0x1 read-write FALSE SRAM BANK1 power OFF for STOP mode 0x0 TRUE SRAM BANK1 power RETAIN for STOP mode 0x1 BANKOFF1 SRAM BANK1 power level for RUN mode 0x1 0x1 read-write FALSE SRAM BANK1 power ON for RUN mode 0x0 TRUE SRAM BANK1 power OFF for RUN mode 0x1 SYSCTL_WRITELOCK SYSCTL register write lockout 0x1200 32 read-write 0x00000000 0x00000001 ACTIVE ACTIVE controls whether critical SYSCTL registers are write protected or not. 0x0 0x1 read-write DISABLE Allow writes to lockable registers 0x0 ENABLE Disallow writes to lockable registers 0x1 SYSCTL_CLKSTATUS Clock module (CKM) status 0x1204 32 read-only 0x00000000 0xb3b37fd3 LFOSCGOOD LFOSCGOOD indicates when the LFOSC startup has completed and the LFOSC is ready for use. 0xB 0x1 read-only FALSE LFOSC is not ready 0x0 TRUE LFOSC is ready 0x1 HFCLKGOOD HFCLKGOOD indicates that the HFCLK started correctly. When the HFXT is started or HFCLK_IN is selected as the HFCLK source, this bit will be set by hardware if a valid HFCLK is detected, and cleared if HFCLK is not operating within the expected range. 0x8 0x1 read-only FALSE HFCLK did not start correctly 0x0 TRUE HFCLK started correctly 0x1 HSCLKDEAD HSCLKDEAD is set by hardware if the selected source for HSCLK was started but did not start successfully. 0x14 0x1 read-only FALSE The HSCLK source was not started or started correctly 0x0 TRUE The HSCLK source did not start correctly 0x1 SYSPLLBLKUPD SYSPLLBLKUPD indicates when writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are blocked. 0x1D 0x1 read-only FALSE writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are allowed 0x0 TRUE writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are blocked 0x1 HFCLKOFF HFCLKOFF indicates if the HFCLK is disabled or was dead at startup. When the HFCLK is started, HFCLKOFF is cleared by hardware. Following startup of the HFCLK, if the HFCLK startup monitor determines that the HFCLK was not started correctly, HFCLKOFF is set. 0xD 0x1 read-only FALSE HFCLK started correctly and is enabled 0x0 TRUE HFCLK is disabled or was dead at startup 0x1 HFCLKBLKUPD HFCLKBLKUPD indicates when writes to the HFCLKCLKCFG register are blocked. 0x1C 0x1 read-only FALSE Writes to HFCLKCLKCFG are allowed 0x0 TRUE Writes to HFCLKCLKCFG are blocked 0x1 HSCLKGOOD HSCLKGOOD is set by hardware if the selected clock source for HSCLK started successfully. 0x15 0x1 read-only FALSE The HSCLK source did not start correctly 0x0 TRUE The HSCLK source started correctly 0x1 SYSPLLGOOD SYSPLLGOOD indicates if the SYSPLL started correctly. When the SYSPLL is started, SYSPLLGOOD is cleared by hardware. After the startup settling time has expired, the SYSPLL status is tested. If the SYSPLL started successfully the SYSPLLGOOD bit is set, else it is left cleared. 0x9 0x1 read-only FALSE SYSPLL did not start correctly 0x0 TRUE SYSPLL started correctly 0x1 ANACLKERR ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected. 0x1F 0x1 read-only FALSE No analog clock errors detected 0x0 TRUE Analog clock error detected 0x1 HSCLKMUX HSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK). 0x4 0x1 read-only SYSOSC MCLK is not sourced from HSCLK 0x0 HSCLK MCLK is sourced from HSCLK 0x1 LFCLKMUX LFCLKMUX indicates if LFCLK is sourced from the internal LFOSC, the low frequency crystal (LFXT), or the LFCLK_IN digital clock input. 0x6 0x2 read-only LFOSC LFCLK is sourced from the internal LFOSC 0x0 LFXT LFCLK is sourced from the LFXT (crystal) 0x1 EXLF LFCLK is sourced from LFCLK_IN (external digital clock input) 0x2 SYSOSCFREQ SYSOSCFREQ indicates the current SYSOSC operating frequency. 0x0 0x2 read-only SYSOSC32M SYSOSC is at base frequency (32MHz) 0x0 SYSOSC4M SYSOSC is at low frequency (4MHz) 0x1 SYSOSCUSER SYSOSC is at the user-trimmed frequency (16 or 24MHz) 0x2 SYSOSCTURBO Reserved 0x3 LFXTGOOD LFXTGOOD indicates if the LFXT started correctly. When the LFXT is started, LFXTGOOD is cleared by hardware. After the startup settling time has expired, the LFXT status is tested. If the LFXT started successfully the LFXTGOOD bit is set, else it is left cleared. 0xA 0x1 read-only FALSE LFXT did not start correctly 0x0 TRUE LFXT started correctly 0x1 HSCLKSOFF HSCLKSOFF is set when the high speed clock sources (SYSPLL, HFCLK) are disabled or dead. It is the logical AND of HFCLKOFF and SYSPLLOFF. 0xC 0x1 read-only FALSE SYSPLL, HFCLK, or both were started correctly and remain enabled 0x0 TRUE SYSPLL and HFCLK are both either off or dead 0x1 FCLMODE FCLMODE indicates if the SYSOSC frequency correction loop (FCL) is enabled. 0x18 0x1 read-only DISABLED SYSOSC FCL is disabled 0x0 ENABLED SYSOSC FCL is enabled 0x1 CURHSCLKSEL CURHSCLKSEL indicates the current clock source for HSCLK. 0x10 0x1 read-only SYSPLL HSCLK is currently sourced from the SYSPLL 0x0 HFCLK HSCLK is currently sourced from the HFCLK 0x1 CURMCLKSEL CURMCLKSEL indicates if MCLK is currently sourced from LFCLK. 0x11 0x1 read-only NOTLFCLK MCLK is not sourced from LFCLK 0x0 LFCLK MCLK is sourced from LFCLK 0x1 FCCDONE FCCDONE indicates when a frequency clock counter capture is complete. 0x19 0x1 read-only NOTDONE FCC capture is not done 0x0 DONE FCC capture is done 0x1 SYSPLLOFF SYSPLLOFF indicates if the SYSPLL is disabled or was dead at startup. When the SYSPLL is started, SYSPLLOFF is cleared by hardware. Following startup of the SYSPLL, if the SYSPLL startup monitor determines that the SYSPLL was not started correctly, SYSPLLOFF is set. 0xE 0x1 read-only FALSE SYSPLL started correctly and is enabled 0x0 TRUE SYSPLL is disabled or was dead startup 0x1 LFCLKFAIL LFCLKFAIL indicates when the continous LFCLK monitor detects a LFXT or LFCLK_IN clock stuck failure. 0x17 0x1 read-only FALSE No LFCLK fault detected 0x0 TRUE LFCLK stuck fault detected 0x1 SYSCTL_SYSSTATUS System status information 0x1208 32 read-only 0x00000000 0xc002737f SHDNIOLOCK SHDNIOLOCK indicates when IO is locked due to SHUTDOWN 0xE 0x1 read-only FALSE IO IS NOT Locked due to SHUTDOWN 0x0 TRUE IO IS Locked due to SHUTDOWN 0x1 EXTRSTPINDIS EXTRSTPINDIS indicates when user has disabled the use of external reset pin 0xC 0x1 read-only FALSE External Reset Pin Enabled 0x0 TRUE External Reset Pin Disabled 0x1 PMUIREFGOOD PMUIREFGOOD is set by hardware when the PMU current reference is ready. 0x6 0x1 read-only FALSE IREF is not ready 0x0 TRUE IREF is ready 0x1 SWDCFGDIS SWDCFGDIS indicates when user has disabled the use of SWD Port 0xD 0x1 read-only FALSE SWD Port Enabled 0x0 TRUE SWD Port Disabled 0x1 ANACPUMPGOOD ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready. 0x5 0x1 read-only FALSE VBOOST is not ready 0x0 TRUE VBOOST is ready 0x1 REBOOTATTEMPTS REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts. 0x1E 0x2 read-only BORLVL BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware. 0x4 0x1 read-only FALSE No BOR violation occured 0x0 TRUE A BOR violation occured and the BOR threshold was switched to BOR0 0x1 MCAN1READY MCAN1READY indicates when the MCAN1 peripheral is ready. 0x9 0x1 read-only FALSE MCAN1 is not ready 0x0 TRUE MCAN1 is ready 0x1 MCAN0READY MCAN0READY indicates when the MCAN0 peripheral is ready. 0x8 0x1 read-only FALSE MCAN0 is not ready 0x0 TRUE MCAN0 is ready 0x1 FLASHDED FLASHDED indicates if a flash ECC double bit error was detected (DED). 0x0 0x1 read-only FALSE No flash ECC double bit error detected 0x0 TRUE Flash ECC double bit error detected 0x1 FLASHSEC FLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC). 0x1 0x1 read-only FALSE No flash ECC single bit error detected 0x0 TRUE Flash ECC single bit error was detected and corrected 0x1 SRAMBANK1READY SRAM BANK1 READY STATE 0x11 0x1 read-only FALSE SRAM BANK1 is NOT READY for access 0x0 TRUE SRAM BANK1 is READY for access 0x1 BORCURTHRESHOLD BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration. 0x2 0x2 read-only BORMIN Default minimum threshold; a BOR0- violation triggers a BOR 0x0 BORLEVEL1 A BOR1- violation generates a BORLVL interrupt 0x1 BORLEVEL2 A BOR2- violation generates a BORLVL interrupt 0x2 BORLEVEL3 A BOR3- violation generates a BORLVL interrupt 0x3 SYSCTL_DEDERRADDR Memory DED Address 0x120C 32 read-only 0x00000000 0xffffffff SYSCTL_RSTCAUSE Reset cause 0x1220 32 read-only 0x00000000 0x0000001f ID ID is a read-to-clear field which indicates the lowest level reset cause since the last read. 0x0 0x5 read-only NORST No reset since last read 0x0 PORHWFAIL POR- violation, SHUTDNSTOREx or PMU trim parity fault 0x1 POREXNRST NRST triggered POR (>1s hold) 0x2 PORSW Software triggered POR 0x3 BORSUPPLY BOR0- violation 0x4 BORWAKESHUTDN SHUTDOWN mode exit 0x5 BOOTNONPMUPARITY Non-PMU trim parity fault 0x8 BOOTCLKFAIL Fatal clock failure 0x9 BOOTEXNRST NRST triggered BOOTRST (<1s hold) 0xC BOOTSW Software triggered BOOTRST 0xD BOOTWWDT0 WWDT0 violation 0xE SYSBSLEXIT BSL exit 0x10 SYSBSLENTRY BSL entry 0x11 SYSWWDT1 WWDT1 violation 0x13 SYSFLASHECC Flash uncorrectable ECC error 0x14 SYSCPULOCK CPULOCK violation 0x15 SYSDBG Debug triggered SYSRST 0x1A SYSSW Software triggered SYSRST 0x1B CPUDBG Debug triggered CPURST 0x1C CPUSW Software triggered CPURST 0x1D SYSCTL_RESETLEVEL Reset level for application-triggered reset command 0x1300 32 read-write 0x00000000 0x00000007 LEVEL LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset. 0x0 0x3 read-write CPU Issue a SYSRST (CPU plus peripherals only) 0x0 BOOT Issue a BOOTRST (CPU, peripherals, and boot configuration routine) 0x1 BOOTLOADERENTRY Issue a SYSRST and enter the boot strap loader (BSL) 0x2 POR Issue a power-on reset (POR) 0x3 BOOTLOADEREXIT Issue a SYSRST and exit the boot strap loader (BSL) 0x4 SYSCTL_RESETCMD Execute an application-triggered reset command 0x1304 32 write-only 0x00000000 0xff000001 GO Execute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY. 0x0 0x1 write-only TRUE Issue reset 0x1 SYSCTL_BORTHRESHOLD BOR threshold selection 0x1308 32 read-write 0x00000000 0x00000003 LEVEL LEVEL specifies the desired BOR threshold and BOR mode. 0x0 0x2 read-write BORMIN Default minimum threshold; a BOR0- violation triggers a BOR 0x0 BORLEVEL1 A BOR1- violation generates a BORLVL interrupt 0x1 BORLEVEL2 A BOR2- violation generates a BORLVL interrupt 0x2 BORLEVEL3 A BOR3- violation generates a BORLVL interrupt 0x3 SYSCTL_BORCLRCMD Set the BOR threshold 0x130C 32 write-only 0x00000000 0xff000001 GO GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register. 0x0 0x1 write-only TRUE Issue clear 0x1 SYSCTL_SYSOSCFCLCTL SYSOSC frequency correction loop (FCL) ROSC enable 0x1310 32 write-only 0x00000000 0xff000003 SETUSEFCL Set SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST. 0x0 0x1 write-only TRUE Enable the SYSOSC FCL 0x1 SETUSEEXRES Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST. 0x1 0x1 write-only TRUE Enable the SYSOSC external Resistor 0x1 SYSCTL_LFXTCTL LFXT and LFCLK control 0x1314 32 write-only 0x00000000 0xff000003 SETUSELFXT Set SETUSELFXT to switch LFCLK to LFXT. Once set, SETUSELFXT remains set until the next BOOTRST. 0x1 0x1 write-only FALSE 0x0 TRUE Use LFXT as the LFCLK source 0x1 STARTLFXT Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set, STARTLFXT remains set until the next BOOTRST. 0x0 0x1 write-only FALSE LFXT not started 0x0 TRUE Start LFXT 0x1 SYSCTL_EXLFCTL LFCLK_IN and LFCLK control 0x1318 32 write-only 0x00000000 0xff000001 SETUSEEXLF Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set, SETUSEEXLF remains set until the next BOOTRST. 0x0 0x1 write-only TRUE Use LFCLK_IN as the LFCLK source 0x1 SYSCTL_SHDNIOREL SHUTDOWN IO release control 0x131C 32 write-only 0x00000000 0xff000001 RELEASE Set RELEASE to release the IO after a SHUTDOWN mode exit. 0x0 0x1 write-only TRUE Release IO 0x1 SYSCTL_EXRSTPIN Disable the reset function of the NRST pin 0x1320 32 write-only 0x00000000 0xff000001 DISABLE Set DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR. 0x0 0x1 write-only FALSE Reset function of NRST pin is enabled 0x0 TRUE Reset function of NRST pin is disabled 0x1 SYSCTL_SYSSTATUSCLR Clear sticky bits of SYSSTATUS 0x1324 32 write-only 0x00000000 0xff000001 ALLECC Set ALLECC to clear all ECC related SYSSTATUS indicators. 0x0 0x1 write-only CLEAR Clear ECC error state 0x1 SYSCTL_SWDCFG Disable the SWD function on the SWD pins 0x1328 32 write-only 0x00000000 0xff000001 DISABLE Set DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO. 0x0 0x1 write-only TRUE Disable SWD function on SWD pins 0x1 SYSCTL_FCCCMD Frequency clock counter start capture 0x132C 32 write-only 0x00000000 0xff000001 GO Set GO to start a capture with the frequency clock counter (FCC). 0x0 0x1 write-only TRUE 0x1 SYSCTL_SHUTDNSTORE0 Shutdown storage memory (byte 0) 0x1400 32 read-write 0x00000000 0x000003ff DATA Shutdown storage byte 0 0x0 0x8 read-write SYSCTL_SHUTDNSTORE1 Shutdown storage memory (byte 1) 0x1404 32 read-write 0x00000000 0x000003ff DATA Shutdown storage byte 1 0x0 0x8 read-write SYSCTL_SHUTDNSTORE2 Shutdown storage memory (byte 2) 0x1408 32 read-write 0x00000000 0x000003ff DATA Shutdown storage byte 2 0x0 0x8 read-write SYSCTL_SHUTDNSTORE3 Shutdown storage memory (byte 3) 0x140C 32 read-write 0x00000000 0x000003ff DATA Shutdown storage byte 3 0x0 0x8 read-write SYSCTL_MGMT_ADC12B4MSPS1_PWREN IP Enable Register 0x2800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_ADC12B4MSPS1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x2804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_ADC12B4MSPS1_CLKCFG IP Clock Configuration Register 0x2808 32 read-write 0x00000000 0xff000033 CCONSTOP Conversion Clock is ON during STOP Mode 0x5 0x1 read-write Disable 0x0 Enable 0x1 CCONRUN Conversion Clock is ON during RUN Mode 0x4 0x1 read-write Disable 0x0 Enable 0x1 SAMPCLK Sample Window Clock 0x0 0x2 read-write ULPCLK 0x0 SYSOSC 0x1 HFCLK 0x2 SYSCTL_MGMT_ADC12B4MSPS1_STAT IP State Register - Read Only 0x2814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_FWEPROTMAIN 1 Sector Write-Erase per bit starting at address 0x0 of flash 0x3000 32 read-write 0x00000000 0xffffffff SYSCTL_FWPROTMAINDATA Read-Write Protection for first 4 Sectors of Data Bank 0x3014 32 read-write 0x00000000 0x000000ff DATA 00: Both RW allowed 01: Read Only 10: No Read No Write 11: No Read No Write - Not Used 0x0 0x8 read-write SYSCTL_FRXPROTMAINSTART Flash RX Protection Start Address 0x3018 32 read-write 0x00000000 0x003fffc0 ADDR Flash RX Protection Start Address 64B granularity 0x6 0x10 read-write SYSCTL_FRXPROTMAINEND Flash RX Protection End Address 0x301C 32 read-write 0x00000000 0x003fffc0 ADDR Flash RX Protection End Address 64B granularity 0x6 0x10 read-write SYSCTL_FIPPROTMAINSTART Flash IP Protection Start Address 0x3020 32 read-write 0x00000000 0x003fffc0 ADDR Flash IP Protection Start Address 64B granularity 0x6 0x10 read-write SYSCTL_FIPPROTMAINEND Flash IP Protection End Address 0x3024 32 read-write 0x00000000 0x003fffc0 ADDR Flash IP Protection End Address 64B granularity 0x6 0x10 read-write SYSCTL_FLBANKSWPPOLICY Flash Bank Swap Policy 0x3038 32 write-only 0x00000000 0xff000001 DISABLE 1: Disables Policy To Allow Flash Bank Swapping 0x0 0x1 write-only TRUE Disallow Bank Swap 0x1 SYSCTL_FLBANKSWP Flash MAIN bank address swap 0x303C 32 write-only 0x00000000 0xff000001 USEUPPER 1: Use Upper Bank as Logical 0 0x0 0x1 write-only DISABLE Normal (default) memory map addressing scheme 0x0 ENABLE Flash upper region address space swapped with lower region 0x1 SYSCTL_FWENABLE Security Firewall Enable Register 0x3044 32 write-only 0x00000000 0xff000150 FLIPPROT 1: Flash Read IP ProtectionActive 0x6 0x1 write-only ENABLE Turn On Flash IP Protection 0x1 SRAMBOUNDARYLOCK 1: Blocks Writes from Changing SRAMBOUNDARY MMR 0x8 0x1 write-only ENABLE SRAMBOUNDARY MMR Locked 0x1 FLRXPROT 1: Flash Read Execute Protection Active 0x4 0x1 write-only ENABLE Turn On Flash Read-eXecute Protection 0x1 SYSCTL_SECSTATUS Security Configuration status 0x3048 32 read-only 0x00000000 0x00001555 FLBANKSWPPOLICY 1: Upper and Lower Banks allowed to be swapped 0xA 0x1 read-only DISABLED 0x0 ENABLED 0x1 FLIPPROT 1: Flash IP Protection Active 0x6 0x1 read-only DISABLED 0x0 ENABLED 0x1 FLBANKSWP 1: Upper and Lower Banks have been swapped 0xC 0x1 read-only SRAMBOUNDARYLOCK 1: SRAM Boundary MMR Locked 0x8 0x1 read-only DISABLED 0x0 ENABLED 0x1 FLRXPROT 1: Flash Read Execute Protection Active 0x4 0x1 read-only DISABLED 0x0 ENABLED 0x1 INITDONE 1: CSC has been completed 0x0 0x1 read-only NO INIT is not yet done 0x0 YES INIT is done 0x1 CSCEXISTS 1: CSC Exists in the system 0x2 0x1 read-only NO System does not have a CSC 0x0 YES System does have a CSC 0x1 SYSCTL_INITDONE INITCODE PASS 0x3060 32 write-only 0x00000000 0xff000001 PASS INITCODE writes 1 for PASS, left unwritten a timeout will occur if not blocked 0x0 0x1 write-only TRUE INITCODE PASS 0x1 SYSCTL_MGMT_ANACOMP0_PWREN IP Enable Register 0x8800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_ANACOMP0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x8804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_ANACOMP0_CLKCFG IP Clock Configuration Register 0x8808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_ANACOMP0_STAT IP State Register - Read Only 0x8814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_ANACOMP1_PWREN IP Enable Register 0xA800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_ANACOMP1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0xA804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_ANACOMP1_CLKCFG IP Clock Configuration Register 0xA808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_ANACOMP1_STAT IP State Register - Read Only 0xA814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_ANACOMP2_PWREN IP Enable Register 0xC800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_ANACOMP2_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0xC804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_ANACOMP2_CLKCFG IP Clock Configuration Register 0xC808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_ANACOMP2_STAT IP State Register - Read Only 0xC814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_DAC12B0_PWREN IP Enable Register 0x18800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_DAC12B0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x18804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_DAC12B0_STAT IP State Register - Read Only 0x18814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_VREF_PWREN IP Enable Register 0x30800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_VREF_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x30804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_VREF_STAT IP State Register - Read Only 0x30814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_WWDTLP0_PWREN IP Enable Register 0x80800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_WWDTLP0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x80804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_WWDTLP0_STAT IP State Register - Read Only 0x80814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_WWDTLP1_PWREN IP Enable Register 0x82800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_WWDTLP1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x82804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_WWDTLP1_STAT IP State Register - Read Only 0x82814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN IP Enable Register 0x84800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x84804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT IP State Register - Read Only 0x84814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN IP Enable Register 0x90800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x90804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT IP State Register - Read Only 0x90814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPTIMER16B2CCQEILP1_PWREN IP Enable Register 0x92800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16B2CCQEILP1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x92804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER16B2CCQEILP1_STAT IP State Register - Read Only 0x92814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_RTC_CLKCFG IP Clock Configuration Register 0x94808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16B2CCLP4_PWREN IP Enable Register 0x96800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16B2CCLP4_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x96804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER16B2CCLP4_STAT IP State Register - Read Only 0x96814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPIO0_PWREN IP Enable Register 0xA0800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPIO0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0xA0804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPIO0_STAT IP State Register - Read Only 0xA0814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPIO1_PWREN IP Enable Register 0xA2800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPIO1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0xA2804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPIO1_STAT IP State Register - Read Only 0xA2814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPIO2_PWREN IP Enable Register 0xA4800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPIO2_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0xA4804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPIO2_STAT IP State Register - Read Only 0xA4814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_I2C0_PWREN IP Enable Register 0xF0800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_I2C0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0xF0804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_I2C0_CLKCFG IP Clock Configuration Register 0xF0808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_I2C0_STAT IP State Register - Read Only 0xF0814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_I2C1_PWREN IP Enable Register 0xF2800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_I2C1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0xF2804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_I2C1_CLKCFG IP Clock Configuration Register 0xF2808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_I2C1_STAT IP State Register - Read Only 0xF2814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_I2C2_PWREN IP Enable Register 0xF4800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_I2C2_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0xF4804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_I2C2_CLKCFG IP Clock Configuration Register 0xF4808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_I2C2_STAT IP State Register - Read Only 0xF4814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_UARTLP0_PWREN IP Enable Register 0x100800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UARTLP0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x100804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_UARTLP0_CLKCFG IP Clock Configuration Register 0x100808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UARTLP0_STAT IP State Register - Read Only 0x100814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_UARTADVLP0_PWREN IP Enable Register 0x108800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UARTADVLP0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x108804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_UARTADVLP0_CLKCFG IP Clock Configuration Register 0x108808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UARTADVLP0_STAT IP State Register - Read Only 0x108814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_UARTADVLP1_PWREN IP Enable Register 0x10A800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UARTADVLP1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x10A804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_UARTADVLP1_CLKCFG IP Clock Configuration Register 0x10A808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UARTADVLP1_STAT IP State Register - Read Only 0x10A814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_MATHACL_PWREN IP Enable Register 0x410800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_MATHACL_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x410804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_MATHACL_STAT IP State Register - Read Only 0x410814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_CRC0_PWREN IP Enable Register 0x440800 32 read-write 0x00000001 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_CRC0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x440804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_CRC0_STAT IP State Register - Read Only 0x440814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_AES_PWREN IP Enable Register 0x442800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_AES_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x442804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_AES_STAT IP State Register - Read Only 0x442814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_TRNG_PWREN IP Enable Register 0x444800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_TRNG_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x444804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_TRNG_STAT IP State Register - Read Only 0x444814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_SPI0_PWREN IP Enable Register 0x468800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_SPI0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x468804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_SPI0_CLKCFG IP Clock Configuration Register 0x468808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_SPI0_STAT IP State Register - Read Only 0x468814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_SPI1_PWREN IP Enable Register 0x46A800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_SPI1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x46A804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_SPI1_CLKCFG IP Clock Configuration Register 0x46A808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_SPI1_STAT IP State Register - Read Only 0x46A814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_SPI2_PWREN IP Enable Register 0x46C800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_SPI2_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x46C804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_SPI2_CLKCFG IP Clock Configuration Register 0x46C808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_SPI2_STAT IP State Register - Read Only 0x46C814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_UART0_PWREN IP Enable Register 0x500800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UART0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x500804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_UART0_CLKCFG IP Clock Configuration Register 0x500808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UART0_STAT IP State Register - Read Only 0x500814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_UART1_PWREN IP Enable Register 0x502800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UART1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x502804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_UART1_CLKCFG IP Clock Configuration Register 0x502808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UART1_STAT IP State Register - Read Only 0x502814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_UART2_PWREN IP Enable Register 0x504800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UART2_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x504804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_UART2_CLKCFG IP Clock Configuration Register 0x504808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UART2_STAT IP State Register - Read Only 0x504814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_UART3_PWREN IP Enable Register 0x506800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UART3_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x506804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_UART3_CLKCFG IP Clock Configuration Register 0x506808 32 read-write 0x00000000 0xff000100 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_UART3_STAT IP State Register - Read Only 0x506814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_MCAN0_PWREN IP Enable Register 0x50E800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_MCAN0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x50E804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_MCAN0_STAT IP State Register - Read Only 0x50E814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_MCAN1_PWREN IP Enable Register 0x516800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_MCAN1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x516804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_MCAN1_STAT IP State Register - Read Only 0x516814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN IP Enable Register 0x860800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x860804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT IP State Register - Read Only 0x860814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPTIMER16BADV2CC0_PWREN IP Enable Register 0x862800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16BADV2CC0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x862804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER16BADV2CC0_STAT IP State Register - Read Only 0x862814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPTIMER16B2CCSP0_PWREN IP Enable Register 0x868800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16B2CCSP0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x868804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER16B2CCSP0_STAT IP State Register - Read Only 0x868814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPTIMER16B2CCSP1_PWREN IP Enable Register 0x86A800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER16B2CCSP1_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x86A804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER16B2CCSP1_STAT IP State Register - Read Only 0x86A814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 SYSCTL_MGMT_GPTIMER32B2CC0_PWREN IP Enable Register 0x870800 32 read-write 0x00000000 0xff000001 ENABLE IP Enable 0x0 0x1 read-write Disable 0x0 Enable 0x1 SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL Power Control Register - Write Only Register, Always Read as 0 0x870804 32 write-only 0x00000000 0xff000003 RESETSTKYCLR Clear the RESET STICKY Bit 0x1 0x1 write-only Clear 0x1 RESETASSERT Assert Reset to IP Domain. 0x0 0x1 write-only Do 0x1 SYSCTL_MGMT_GPTIMER32B2CC0_STAT IP State Register - Read Only 0x870814 32 read-only 0x00000000 0x00010000 RESETSTKY IP has been Reset 0x10 0x1 read-only clear 0x0 Set 0x1 ADC0 ADC 1.0 PERIPHERALREGION 0x40000000 0x0 0x2000 registers ADC0_FSUB_0 Subscriber Configuration Register. 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 ADC0_FPUB_1 Publisher Configuration Register. 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 ADC0_GPRCM[%s] 0x800 ADC0_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 ADC0_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 ADC0_CLKCFG ADC clock configuration Register 0x8 32 read-write 0x00000000 SAMPCLK ADC sample clock source selection. 0x0 0x2 ULPCLK ULPCLK is the source of ADC sample clock. 0x0 SYSOSC SYSOSC is the source of ADC sample clock. 0x1 HFCLK HFCLK clock is the source of ADC sample clock. Note : HFCLK may not be available on all the devices. 0x2 CCONRUN CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source. 0x4 0x1 DISABLE ADC conversion clock source is not kept continuously on during RUN mode. 0x0 ENABLE ADC conversion clock source kept continuously on during RUN mode. 0x1 CCONSTOP CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source. 0x5 0x1 DISABLE ADC conversion clock source is not kept continuously on during STOP mode. 0x0 ENABLE ADC conversion clock source kept continuously on during STOP mode. 0x1 ADC0_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 1 44 0 ADC0_CPU_INT[%s] 0x1020 ADC0_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0xA read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 OVIFG MEMRESx overflow interrupt 0x1 TOVIFG Sequence Conversion time overflow interrupt 0x2 HIGHIFG High threshold compare interrupt 0x3 LOWIFG Low threshold compare interrupt 0x4 INIFG Primary Sequence In range comparator interrupt 0x5 DMADONE DMA done interrupt, generated on DMA transfer completion, 0x6 UVIFG MEMRESx underflow interrupt 0x7 MEMRESIFG0 MEMRES0 data loaded interrupt 0x9 MEMRESIFG1 MEMRES1 data loaded interrupt 0xA MEMRESIFG2 MEMRES2 data loaded interrupt 0xB MEMRESIFG3 MEMRES3 data loaded interrupt 0xC MEMRESIFG4 MEMRES4 data loaded interrupt 0xD MEMRESIFG5 MEMRES5 data loaded interrupt 0xE MEMRESIFG6 MEMRES6 data loaded interrupt 0xF MEMRESIFG7 MEMRES7 data loaded interrupt 0x10 MEMRESIFG8 MEMRES8 data loaded interrupt 0x11 MEMRESIFG9 MEMRES9 data loaded interrupt 0x12 MEMRESIFG10 MEMRES10 data loaded interrupt 0x13 MEMRESIFG11 MEMRES11 data loaded interrupt 0x14 MEMRESIFG12 MEMRES12 data loaded interrupt 0x15 MEMRESIFG13 MEMRES13 data loaded interrupt 0x16 MEMRESIFG14 MEMRES14 data loaded interrupt 0x17 MEMRESIFG15 MEMRES15 data loaded interrupt 0x18 MEMRESIFG16 MEMRES16 data loaded interrupt 0x19 MEMRESIFG17 MEMRES17 data loaded interrupt 0x1A MEMRESIFG18 MEMRES18 data loaded interrupt 0x1B MEMRESIFG19 MEMRES19 data loaded interrupt 0x1C MEMRESIFG20 MEMRES20 data loaded interrupt 0x1D MEMRESIFG21 MEMRES21 data loaded interrupt 0x1E MEMRESIFG22 MEMRES22 data loaded interrupt 0x1F MEMRESIFG23 MEMRES23 data loaded interrupt 0x20 ADC0_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x6 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x6 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 1 44 0 ADC0_GEN_EVENT[%s] 0x1050 ADC0_GEN_EVENT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0xA read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 HIGHIFG High threshold compare interrupt 0x3 LOWIFG Low threshold compare interrupt 0x4 INIFG Primary Sequence In range comparator interrupt 0x5 MEMRESIFG0 MEMRES0 data loaded interrupt 0x9 ADC0_GEN_EVENT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_GEN_EVENT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_GEN_EVENT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_GEN_EVENT_ISET Interrupt set 0x20 32 write-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_GEN_EVENT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 1 44 0 ADC0_DMA_TRIG[%s] 0x1080 ADC0_DMA_TRIG_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0xA read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 MEMRESIFG0 MEMRES0 data loaded interrupt 0x9 MEMRESIFG1 MEMRES1 data loaded interrupt 0xA MEMRESIFG2 MEMRES2 data loaded interrupt 0xB MEMRESIFG3 MEMRES3 data loaded interrupt 0xC MEMRESIFG4 MEMRES4 data loaded interrupt 0xD MEMRESIFG5 MEMRES5 data loaded interrupt 0xE MEMRESIFG6 MEMRES6 data loaded interrupt 0xF MEMRESIFG7 MEMRES7 data loaded interrupt 0x10 MEMRESIFG8 MEMRES8 data loaded interrupt 0x11 MEMRESIFG9 MEMRES9 data loaded interrupt 0x12 MEMRESIFG10 MEMRES10 data loaded interrupt 0x13 MEMRESIFG11 MEMRES11 data loaded interrupt 0x14 MEMRESIFG12 MEMRES12 data loaded interrupt 0x15 MEMRESIFG13 MEMRES13 data loaded interrupt 0x16 MEMRESIFG14 MEMRES14 data loaded interrupt 0x17 MEMRESIFG15 MEMRES15 data loaded interrupt 0x18 MEMRESIFG16 MEMRES16 data loaded interrupt 0x19 MEMRESIFG17 MEMRES17 data loaded interrupt 0x1A MEMRESIFG18 MEMRES18 data loaded interrupt 0x1B MEMRESIFG19 MEMRES19 data loaded interrupt 0x1C MEMRESIFG20 MEMRES20 data loaded interrupt 0x1D MEMRESIFG21 MEMRES21 data loaded interrupt 0x1E MEMRESIFG22 MEMRES22 data loaded interrupt 0x1F MEMRESIFG23 MEMRES23 data loaded interrupt 0x20 ADC0_DMA_TRIG_IMASK Interrupt mask extension 0x8 32 read-write 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_DMA_TRIG_RIS Raw interrupt status extension 0x10 32 read-only 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_DMA_TRIG_MIS Masked interrupt status extension 0x18 32 read-only 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_DMA_TRIG_ISET Interrupt set extension 0x20 32 write-only 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC0_DMA_TRIG_ICLR Interrupt clear extension 0x28 32 write-only 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 ADC0_EVT_MODE Event Mode 0x10E0 32 read-only INT0_CFG Event line mode select for event corresponding to CPU_INT 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to GEN_EVENT 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 ADC0_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 read-only MAJREV Major rev of the IP 0x4 0x4 read-only INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 read-only FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only ADC0_CTL0 Control Register 0 0x1100 32 read-write 0x00000000 ENC Enable conversion 0x0 0x1 read-write OFF Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx. 0x0 ON Conversion enabled. ADC sequencer waits for valid trigger (software or hardware). 0x1 PWRDN Power down policy 0x10 0x1 read-write AUTO ADC is powered down on completion of a conversion if there is no pending trigger 0x0 MANUAL ADC remains powered on as long as it is enabled through software. 0x1 SCLKDIV Sample clock divider 0x18 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_4 Divide clock source by 4 0x2 DIV_BY_8 Divide clock source by 8 0x3 DIV_BY_16 Divide clock source by 16 0x4 DIV_BY_24 Divide clock source by 24 0x5 DIV_BY_32 Divide clock source by 32 0x6 DIV_BY_48 Divide clock source by 48 0x7 ADC0_CTL1 Control Register 1 0x1104 32 read-write 0x00000000 TRIGSRC Sample trigger source 0x0 0x1 read-write SOFTWARE Software trigger 0x0 EVENT Hardware event trigger 0x1 SC Start of conversion 0x8 0x1 read-write STOP When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start. When SAMPMODE is set to AUTO, writing 0 has no effect. 0x0 START When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set. When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time. 0x1 CONSEQ Conversion sequence mode 0x10 0x2 read-write SINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted once 0x0 SEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted once 0x1 REPEATSINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly 0x2 REPEATSEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly 0x3 SAMPMODE Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger. 0x14 0x1 read-write AUTO Sample timer high phase is used as sample signal 0x0 MANUAL Software trigger is used as sample signal 0x1 AVGN Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx. 0x18 0x3 read-write DISABLE Disables averager 0x0 AVG_2 Averages 2 conversions before storing in MEMRESx register 0x1 AVG_4 Averages 4 conversions before storing in MEMRESx register 0x2 AVG_8 Averages 8 conversions before storing in MEMRESx register 0x3 AVG_16 Averages 16 conversions before storing in MEMRESx register 0x4 AVG_32 Averages 32 conversions before storing in MEMRESx register 0x5 AVG_64 Averages 64 conversions before storing in MEMRESx register 0x6 AVG_128 Averages 128 conversions before storing in MEMRESx register 0x7 AVGD Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated. 0x1C 0x3 read-write SHIFT0 No shift 0x0 SHIFT1 1 bit shift 0x1 SHIFT2 2 bit shift 0x2 SHIFT3 3 bit shift 0x3 SHIFT4 4 bit shift 0x4 SHIFT5 5 bit shift 0x5 SHIFT6 6 bit shift 0x6 SHIFT7 7 bit shift 0x7 ADC0_CTL2 Control Register 2 0x1108 32 read-write 0x00000000 DF Data read-back format. Data is always stored in binary unsigned format. 0x0 0x1 read-write UNSIGNED Digital result reads as Binary Unsigned. 0x0 SIGNED Digital result reads Signed Binary. (2s complement), left aligned. 0x1 RES Resolution. These bits define the resolution of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution. 0x1 0x2 read-write BIT_12 12-bits resolution 0x0 BIT_10 10-bits resolution 0x1 BIT_8 8-bits resolution 0x2 STARTADD Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23. 0x10 0x5 read-write ADDR_00 MEMCTL0 is selected as start address of a sequence or for a single conversion. 0x0 ADDR_01 MEMCTL1 is selected as start address of a sequence or for a single conversion. 0x1 ADDR_02 MEMCTL2 is selected as start address of a sequence or for a single conversion. 0x2 ADDR_03 MEMCTL3 is selected as start address of a sequence or for a single conversion. 0x3 ADDR_04 MEMCTL4 is selected as start address of a sequence or for a single conversion. 0x4 ADDR_05 MEMCTL5 is selected as start address of a sequence or for a single conversion. 0x5 ADDR_06 MEMCTL6 is selected as start address of a sequence or for a single conversion. 0x6 ADDR_07 MEMCTL7 is selected as start address of a sequence or for a single conversion. 0x7 ADDR_08 MEMCTL8 is selected as start address of a sequence or for a single conversion. 0x8 ADDR_09 MEMCTL9 is selected as start address of a sequence or for a single conversion. 0x9 ADDR_10 MEMCTL10 is selected as start address of a sequence or for a single conversion. 0xA ADDR_11 MEMCTL11 is selected as start address of a sequence or for a single conversion. 0xB ADDR_12 MEMCTL12 is selected as start address of a sequence or for a single conversion. 0xC ADDR_13 MEMCTL13 is selected as start address of a sequence or for a single conversion. 0xD ADDR_14 MEMCTL14 is selected as start address of a sequence or for a single conversion. 0xE ADDR_15 MEMCTL15 is selected as start address of a sequence or for a single conversion. 0xF ADDR_16 MEMCTL16 is selected as start address of a sequence or for a single conversion. 0x10 ADDR_17 MEMCTL17 is selected as start address of a sequence or for a single conversion. 0x11 ADDR_18 MEMCTL18 is selected as start address of a sequence or for a single conversion. 0x12 ADDR_19 MEMCTL19 is selected as start address of a sequence or for a single conversion. 0x13 ADDR_20 MEMCTL20 is selected as start address of a sequence or for a single conversion. 0x14 ADDR_21 MEMCTL21 is selected as start address of a sequence or for a single conversion. 0x15 ADDR_22 MEMCTL22 is selected as start address of a sequence or for a single conversion. 0x16 ADDR_23 MEMCTL23 is selected as start address of a sequence or for a single conversion. 0x17 ENDADD Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23. 0x18 0x5 read-write ADDR_00 MEMCTL0 is selected as end address of sequence. 0x0 ADDR_01 MEMCTL1 is selected as end address of sequence. 0x1 ADDR_02 MEMCTL2 is selected as end address of sequence. 0x2 ADDR_03 MEMCTL3 is selected as end address of sequence. 0x3 ADDR_04 MEMCTL4 is selected as end address of sequence. 0x4 ADDR_05 MEMCTL5 is selected as end address of sequence. 0x5 ADDR_06 MEMCTL6 is selected as end address of sequence. 0x6 ADDR_07 MEMCTL7 is selected as end address of sequence. 0x7 ADDR_08 MEMCTL8 is selected as end address of sequence. 0x8 ADDR_09 MEMCTL9 is selected as end address of sequence. 0x9 ADDR_10 MEMCTL10 is selected as end address of sequence. 0xA ADDR_11 MEMCTL11 is selected as end address of sequence. 0xB ADDR_12 MEMCTL12 is selected as end address of sequence. 0xC ADDR_13 MEMCTL13 is selected as end address of sequence. 0xD ADDR_14 MEMCTL14 is selected as end address of sequence. 0xE ADDR_15 MEMCTL15 is selected as end address of sequence. 0xF ADDR_16 MEMCTL16 is selected as end address of sequence. 0x10 ADDR_17 MEMCTL17 is selected as end address of sequence. 0x11 ADDR_18 MEMCTL18 is selected as end address of sequence. 0x12 ADDR_19 MEMCTL19 is selected as end address of sequence. 0x13 ADDR_20 MEMCTL20 is selected as end address of sequence. 0x14 ADDR_21 MEMCTL21 is selected as end address of sequence. 0x15 ADDR_22 MEMCTL22 is selected as end address of sequence. 0x16 ADDR_23 MEMCTL23 is selected as end address of sequence. 0x17 DMAEN Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers. 0x8 0x1 read-write DISABLE DMA trigger not enabled 0x0 ENABLE DMA trigger enabled 0x1 SAMPCNT Number of ADC converted samples to be transferred on a DMA trigger 0xB 0x5 read-write MIN Minimum value 0x0 MAX Maximum value 0x18 FIFOEN Enable FIFO based operation 0xA 0x1 DISABLE Disable 0x0 ENABLE Enable 0x1 RSTSAMPCAPEN 0: Sample and hold capacitor is not explicitly discharged at the end of conversion. 1: Sample and hold capacitor is discharged at the end of conversion. This incurs one additional conversion clock cycle. 0x4 0x1 read-write DISABLE Disable sample capacitor discharge feature. 0x0 ENABLE Enable sample capacitor discharge feature. 0x1 ADC0_CLKFREQ Sample Clock Frequency Range Register 0x1110 32 read-write 0x00000000 FRANGE Frequency Range. 0x0 0x3 RANGE1TO4 1 to 4 MHz 0x0 RANGE4TO8 >4 to 8 MHz 0x1 RANGE8TO16 >8 to 16 MHz 0x2 RANGE16TO20 >16 to 20 MHz 0x3 RANGE20TO24 >20 to 24 MHz 0x4 RANGE24TO32 >24 to 32 MHz 0x5 RANGE32TO40 >32 to 40 MHz 0x6 RANGE40TO48 >40 to 48 MHz 0x7 ADC0_SCOMP0 Sample Time Compare 0 Register 0x1114 32 read-write 0x00000000 VAL Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. 0x0 0xA read-write ADC0_SCOMP1 Sample Time Compare 1 Register 0x1118 32 read-write 0x00000000 VAL Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. 0x0 0xA read-write ADC0_WCLOW Window Comparator Low Threshold Register 0x1148 32 read-write 0x00000000 DATA If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s. 0x0 0x10 read-write ADC0_WCHIGH Window Comparator High Threshold Register 0x1150 32 read-write 0x00000000 DATA If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s. 0x0 0x10 read-write 24 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 ADC0_MEMCTL[%s] Conversion Memory Control Register 0x1180 32 read-write 0x00000000 CHANSEL Input channel select. 0x0 0x5 read-write CHAN_0 Selects channel 0 0x0 CHAN_1 Selects channel 1 0x1 CHAN_2 Selects channel 2 0x2 CHAN_3 Selects channel 3 0x3 CHAN_4 Selects channel 4 0x4 CHAN_5 Selects channel 5 0x5 CHAN_6 Selects channel 6 0x6 CHAN_7 Selects channel 7 0x7 CHAN_8 Selects channel 8 0x8 CHAN_9 Selects channel 9 0x9 CHAN_10 Selects channel 10 0xA CHAN_11 Selects channel 11 0xB CHAN_12 Selects channel 12 0xC CHAN_13 Selects channel 13 0xD CHAN_14 Selects channel 14 0xE CHAN_15 Selects channel 15 0xF CHAN_16 Selects channel 16 0x10 CHAN_17 Selects channel 17 0x11 CHAN_18 Selects channel 18 0x12 CHAN_19 Selects channel 19 0x13 CHAN_20 Selects channel 20 0x14 CHAN_21 Selects channel 21 0x15 CHAN_22 Selects channel 22 0x16 CHAN_23 Selects channel 23 0x17 CHAN_24 Selects channel 24 0x18 CHAN_25 Selects channel 25 0x19 CHAN_26 Selects channel 26 0x1A CHAN_27 Selects channel 27 0x1B CHAN_28 Selects channel 28 0x1C CHAN_29 Selects channel 29 0x1D CHAN_30 Selects channel 30 0x1E CHAN_31 Selects channel 31 0x1F TRIG Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions. 0x18 0x1 read-write AUTO_NEXT Next conversion is automatic 0x0 TRIGGER_NEXT Next conversion requires a trigger 0x1 VRSEL Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF. 0x8 0x3 read-write VDDA_VSSA VDDA reference 0x0 EXTREF_VREFM External reference from pin 0x1 INTREF_VSSA Internal reference 0x2 VDDA_VREFM VDDA and VREFM connected to VREF+ and VREF- of ADC 0x3 INTREF_VREFM INTREF and VREFM connected to VREF+ and VREF- of ADC 0x4 WINCOMP Enable window comparator. 0x1C 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 BCSEN Enable burn out current source. 0x14 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 AVGEN Enable hardware averaging. 0x10 0x1 read-write DISABLE Averaging disabled. 0x0 ENABLE Averaging enabled. 0x1 STIME Selects the source of sample timer period between SCOMP0 and SCOMP1. 0xC 0x1 SEL_SCOMP0 Select SCOMP0 0x0 SEL_SCOMP1 Select SCOMP1 0x1 ADC0_STATUS Status Register 0x1340 32 read-only 0x00000000 BUSY Busy. This bit indicates that an active ADC sample or conversion operation is in progress. 0x0 0x1 read-only IDLE No ADC sampling or conversion in progress. 0x0 ACTIVE ADC sampling or conversion is in progress. 0x1 REFBUFRDY Indicates reference buffer is powered up and ready. 0x1 0x1 NOTREADY Not ready 0x0 READY Ready 0x1 ADC0_SVT ADC 1.0 PERIPHERALREGIONSVT 0x40556000 0x0 0x1000 registers ADC0_SVT_FIFODATA FIFO Data Register 0x556160 32 read-only 24 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 ADC0_SVT_MEMRES[%s] Memory Result Register 0x556280 32 read-only DATA MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. 0x0 0x10 ADC1 ADC 1.0 PERIPHERALREGION 0x40002000 0x0 0x2000 registers ADC1_FSUB_0 Subscriber Configuration Register. 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 ADC1_FPUB_1 Publisher Configuration Register. 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 ADC1_GPRCM[%s] 0x800 ADC1_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 ADC1_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 ADC1_CLKCFG ADC clock configuration Register 0x8 32 read-write 0x00000000 SAMPCLK ADC sample clock source selection. 0x0 0x2 ULPCLK ULPCLK is the source of ADC sample clock. 0x0 SYSOSC SYSOSC is the source of ADC sample clock. 0x1 HFCLK HFCLK clock is the source of ADC sample clock. Note : HFCLK may not be available on all the devices. 0x2 CCONRUN CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source. 0x4 0x1 DISABLE ADC conversion clock source is not kept continuously on during RUN mode. 0x0 ENABLE ADC conversion clock source kept continuously on during RUN mode. 0x1 CCONSTOP CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source. 0x5 0x1 DISABLE ADC conversion clock source is not kept continuously on during STOP mode. 0x0 ENABLE ADC conversion clock source kept continuously on during STOP mode. 0x1 ADC1_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 1 44 0 ADC1_CPU_INT[%s] 0x1020 ADC1_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0xA read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 OVIFG MEMRESx overflow interrupt 0x1 TOVIFG Sequence Conversion time overflow interrupt 0x2 HIGHIFG High threshold compare interrupt 0x3 LOWIFG Low threshold compare interrupt 0x4 INIFG Primary Sequence In range comparator interrupt 0x5 DMADONE DMA done interrupt, generated on DMA transfer completion, 0x6 UVIFG MEMRESx underflow interrupt 0x7 MEMRESIFG0 MEMRES0 data loaded interrupt 0x9 MEMRESIFG1 MEMRES1 data loaded interrupt 0xA MEMRESIFG2 MEMRES2 data loaded interrupt 0xB MEMRESIFG3 MEMRES3 data loaded interrupt 0xC MEMRESIFG4 MEMRES4 data loaded interrupt 0xD MEMRESIFG5 MEMRES5 data loaded interrupt 0xE MEMRESIFG6 MEMRES6 data loaded interrupt 0xF MEMRESIFG7 MEMRES7 data loaded interrupt 0x10 MEMRESIFG8 MEMRES8 data loaded interrupt 0x11 MEMRESIFG9 MEMRES9 data loaded interrupt 0x12 MEMRESIFG10 MEMRES10 data loaded interrupt 0x13 MEMRESIFG11 MEMRES11 data loaded interrupt 0x14 MEMRESIFG12 MEMRES12 data loaded interrupt 0x15 MEMRESIFG13 MEMRES13 data loaded interrupt 0x16 MEMRESIFG14 MEMRES14 data loaded interrupt 0x17 MEMRESIFG15 MEMRES15 data loaded interrupt 0x18 MEMRESIFG16 MEMRES16 data loaded interrupt 0x19 MEMRESIFG17 MEMRES17 data loaded interrupt 0x1A MEMRESIFG18 MEMRES18 data loaded interrupt 0x1B MEMRESIFG19 MEMRES19 data loaded interrupt 0x1C MEMRESIFG20 MEMRES20 data loaded interrupt 0x1D MEMRESIFG21 MEMRES21 data loaded interrupt 0x1E MEMRESIFG22 MEMRES22 data loaded interrupt 0x1F MEMRESIFG23 MEMRES23 data loaded interrupt 0x20 ADC1_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x6 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x6 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 1 44 0 ADC1_GEN_EVENT[%s] 0x1050 ADC1_GEN_EVENT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0xA read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 HIGHIFG High threshold compare interrupt 0x3 LOWIFG Low threshold compare interrupt 0x4 INIFG Primary Sequence In range comparator interrupt 0x5 MEMRESIFG0 MEMRES0 data loaded interrupt 0x9 ADC1_GEN_EVENT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_GEN_EVENT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_GEN_EVENT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 CLR Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_GEN_EVENT_ISET Interrupt set 0x20 32 write-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 NO_EFFECT Interrupt is not pending. 0x0 SET Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_GEN_EVENT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 INIFG Mask INIFG in MIS_EX register. 0x4 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 NO_EFFECT Interrupt is not pending. 0x0 CLR Interrupt is pending. 0x1 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 1 44 0 ADC1_DMA_TRIG[%s] 0x1080 ADC1_DMA_TRIG_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0xA read-only NO_INTR No bit is set means there is no pending interrupt request 0x0 MEMRESIFG0 MEMRES0 data loaded interrupt 0x9 MEMRESIFG1 MEMRES1 data loaded interrupt 0xA MEMRESIFG2 MEMRES2 data loaded interrupt 0xB MEMRESIFG3 MEMRES3 data loaded interrupt 0xC MEMRESIFG4 MEMRES4 data loaded interrupt 0xD MEMRESIFG5 MEMRES5 data loaded interrupt 0xE MEMRESIFG6 MEMRES6 data loaded interrupt 0xF MEMRESIFG7 MEMRES7 data loaded interrupt 0x10 MEMRESIFG8 MEMRES8 data loaded interrupt 0x11 MEMRESIFG9 MEMRES9 data loaded interrupt 0x12 MEMRESIFG10 MEMRES10 data loaded interrupt 0x13 MEMRESIFG11 MEMRES11 data loaded interrupt 0x14 MEMRESIFG12 MEMRES12 data loaded interrupt 0x15 MEMRESIFG13 MEMRES13 data loaded interrupt 0x16 MEMRESIFG14 MEMRES14 data loaded interrupt 0x17 MEMRESIFG15 MEMRES15 data loaded interrupt 0x18 MEMRESIFG16 MEMRES16 data loaded interrupt 0x19 MEMRESIFG17 MEMRES17 data loaded interrupt 0x1A MEMRESIFG18 MEMRES18 data loaded interrupt 0x1B MEMRESIFG19 MEMRES19 data loaded interrupt 0x1C MEMRESIFG20 MEMRES20 data loaded interrupt 0x1D MEMRESIFG21 MEMRES21 data loaded interrupt 0x1E MEMRESIFG22 MEMRES22 data loaded interrupt 0x1F MEMRESIFG23 MEMRES23 data loaded interrupt 0x20 ADC1_DMA_TRIG_IMASK Interrupt mask extension 0x8 32 read-write 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_DMA_TRIG_RIS Raw interrupt status extension 0x10 32 read-only 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_DMA_TRIG_MIS Masked interrupt status extension 0x18 32 read-only 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 CLR No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_DMA_TRIG_ISET Interrupt set extension 0x20 32 write-only 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 NO_EFFECT No new data ready. 0x0 SET A new data is ready to be read. 0x1 ADC1_DMA_TRIG_ICLR Interrupt clear extension 0x28 32 write-only 0x00000000 MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG4 Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. Reading MEMRES4 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xC 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG5 Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. Reading MEMRES5 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xD 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG6 Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. Reading MEMRES6 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xE 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG7 Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. Reading MEMRES7 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xF 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG9 Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. Reading MEMRES9 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x11 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG10 Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. Reading MEMRES10 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x12 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG11 Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. Reading MEMRES11 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x13 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG12 Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. Reading MEMRES12 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x14 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG13 Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. Reading MEMRES13 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x15 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG14 Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. Reading MEMRES14 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x16 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG15 Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. Reading MEMRES15 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x17 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG16 Raw interrupt status for MEMRES16. This bit is set to 1 when MEMRES16 is loaded with a new conversion result. Reading MEMRES16 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x18 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG17 Raw interrupt status for MEMRES17. This bit is set to 1 when MEMRES17 is loaded with a new conversion result. Reading MEMRES17 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x19 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG18 Raw interrupt status for MEMRES18. This bit is set to 1 when MEMRES18 is loaded with a new conversion result. Reading MEMRES18 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1A 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG19 Raw interrupt status for MEMRES19. This bit is set to 1 when MEMRES19 is loaded with a new conversion result. Reading MEMRES19 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1B 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG20 Raw interrupt status for MEMRES20. This bit is set to 1 when MEMRES20 is loaded with a new conversion result. Reading MEMRES20 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1C 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG22 Raw interrupt status for MEMRES22. This bit is set to 1 when MEMRES22 is loaded with a new conversion result. Reading MEMRES22 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1E 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG23 Raw interrupt status for MEMRES23. This bit is set to 1 when MEMRES23 is loaded with a new conversion result. Reading MEMRES23 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1F 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG8 Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. Reading MEMRES8 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x10 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 MEMRESIFG21 Raw interrupt status for MEMRES21. This bit is set to 1 when MEMRES21 is loaded with a new conversion result. Reading MEMRES21 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x1D 0x1 NO_EFFECT No new data ready. 0x0 CLR A new data is ready to be read. 0x1 ADC1_EVT_MODE Event Mode 0x10E0 32 read-only INT0_CFG Event line mode select for event corresponding to CPU_INT 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to GEN_EVENT 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 ADC1_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 read-only MAJREV Major rev of the IP 0x4 0x4 read-only INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 read-only FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only ADC1_CTL0 Control Register 0 0x1100 32 read-write 0x00000000 ENC Enable conversion 0x0 0x1 read-write OFF Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx. 0x0 ON Conversion enabled. ADC sequencer waits for valid trigger (software or hardware). 0x1 PWRDN Power down policy 0x10 0x1 read-write AUTO ADC is powered down on completion of a conversion if there is no pending trigger 0x0 MANUAL ADC remains powered on as long as it is enabled through software. 0x1 SCLKDIV Sample clock divider 0x18 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_4 Divide clock source by 4 0x2 DIV_BY_8 Divide clock source by 8 0x3 DIV_BY_16 Divide clock source by 16 0x4 DIV_BY_24 Divide clock source by 24 0x5 DIV_BY_32 Divide clock source by 32 0x6 DIV_BY_48 Divide clock source by 48 0x7 ADC1_CTL1 Control Register 1 0x1104 32 read-write 0x00000000 TRIGSRC Sample trigger source 0x0 0x1 read-write SOFTWARE Software trigger 0x0 EVENT Hardware event trigger 0x1 SC Start of conversion 0x8 0x1 read-write STOP When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start. When SAMPMODE is set to AUTO, writing 0 has no effect. 0x0 START When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set. When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time. 0x1 CONSEQ Conversion sequence mode 0x10 0x2 read-write SINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted once 0x0 SEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted once 0x1 REPEATSINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly 0x2 REPEATSEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly 0x3 SAMPMODE Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger. 0x14 0x1 read-write AUTO Sample timer high phase is used as sample signal 0x0 MANUAL Software trigger is used as sample signal 0x1 AVGN Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx. 0x18 0x3 read-write DISABLE Disables averager 0x0 AVG_2 Averages 2 conversions before storing in MEMRESx register 0x1 AVG_4 Averages 4 conversions before storing in MEMRESx register 0x2 AVG_8 Averages 8 conversions before storing in MEMRESx register 0x3 AVG_16 Averages 16 conversions before storing in MEMRESx register 0x4 AVG_32 Averages 32 conversions before storing in MEMRESx register 0x5 AVG_64 Averages 64 conversions before storing in MEMRESx register 0x6 AVG_128 Averages 128 conversions before storing in MEMRESx register 0x7 AVGD Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated. 0x1C 0x3 read-write SHIFT0 No shift 0x0 SHIFT1 1 bit shift 0x1 SHIFT2 2 bit shift 0x2 SHIFT3 3 bit shift 0x3 SHIFT4 4 bit shift 0x4 SHIFT5 5 bit shift 0x5 SHIFT6 6 bit shift 0x6 SHIFT7 7 bit shift 0x7 ADC1_CTL2 Control Register 2 0x1108 32 read-write 0x00000000 DF Data read-back format. Data is always stored in binary unsigned format. 0x0 0x1 read-write UNSIGNED Digital result reads as Binary Unsigned. 0x0 SIGNED Digital result reads Signed Binary. (2s complement), left aligned. 0x1 RES Resolution. These bits define the resolution of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution. 0x1 0x2 read-write BIT_12 12-bits resolution 0x0 BIT_10 10-bits resolution 0x1 BIT_8 8-bits resolution 0x2 STARTADD Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23. 0x10 0x5 read-write ADDR_00 MEMCTL0 is selected as start address of a sequence or for a single conversion. 0x0 ADDR_01 MEMCTL1 is selected as start address of a sequence or for a single conversion. 0x1 ADDR_02 MEMCTL2 is selected as start address of a sequence or for a single conversion. 0x2 ADDR_03 MEMCTL3 is selected as start address of a sequence or for a single conversion. 0x3 ADDR_04 MEMCTL4 is selected as start address of a sequence or for a single conversion. 0x4 ADDR_05 MEMCTL5 is selected as start address of a sequence or for a single conversion. 0x5 ADDR_06 MEMCTL6 is selected as start address of a sequence or for a single conversion. 0x6 ADDR_07 MEMCTL7 is selected as start address of a sequence or for a single conversion. 0x7 ADDR_08 MEMCTL8 is selected as start address of a sequence or for a single conversion. 0x8 ADDR_09 MEMCTL9 is selected as start address of a sequence or for a single conversion. 0x9 ADDR_10 MEMCTL10 is selected as start address of a sequence or for a single conversion. 0xA ADDR_11 MEMCTL11 is selected as start address of a sequence or for a single conversion. 0xB ADDR_12 MEMCTL12 is selected as start address of a sequence or for a single conversion. 0xC ADDR_13 MEMCTL13 is selected as start address of a sequence or for a single conversion. 0xD ADDR_14 MEMCTL14 is selected as start address of a sequence or for a single conversion. 0xE ADDR_15 MEMCTL15 is selected as start address of a sequence or for a single conversion. 0xF ADDR_16 MEMCTL16 is selected as start address of a sequence or for a single conversion. 0x10 ADDR_17 MEMCTL17 is selected as start address of a sequence or for a single conversion. 0x11 ADDR_18 MEMCTL18 is selected as start address of a sequence or for a single conversion. 0x12 ADDR_19 MEMCTL19 is selected as start address of a sequence or for a single conversion. 0x13 ADDR_20 MEMCTL20 is selected as start address of a sequence or for a single conversion. 0x14 ADDR_21 MEMCTL21 is selected as start address of a sequence or for a single conversion. 0x15 ADDR_22 MEMCTL22 is selected as start address of a sequence or for a single conversion. 0x16 ADDR_23 MEMCTL23 is selected as start address of a sequence or for a single conversion. 0x17 ENDADD Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23. 0x18 0x5 read-write ADDR_00 MEMCTL0 is selected as end address of sequence. 0x0 ADDR_01 MEMCTL1 is selected as end address of sequence. 0x1 ADDR_02 MEMCTL2 is selected as end address of sequence. 0x2 ADDR_03 MEMCTL3 is selected as end address of sequence. 0x3 ADDR_04 MEMCTL4 is selected as end address of sequence. 0x4 ADDR_05 MEMCTL5 is selected as end address of sequence. 0x5 ADDR_06 MEMCTL6 is selected as end address of sequence. 0x6 ADDR_07 MEMCTL7 is selected as end address of sequence. 0x7 ADDR_08 MEMCTL8 is selected as end address of sequence. 0x8 ADDR_09 MEMCTL9 is selected as end address of sequence. 0x9 ADDR_10 MEMCTL10 is selected as end address of sequence. 0xA ADDR_11 MEMCTL11 is selected as end address of sequence. 0xB ADDR_12 MEMCTL12 is selected as end address of sequence. 0xC ADDR_13 MEMCTL13 is selected as end address of sequence. 0xD ADDR_14 MEMCTL14 is selected as end address of sequence. 0xE ADDR_15 MEMCTL15 is selected as end address of sequence. 0xF ADDR_16 MEMCTL16 is selected as end address of sequence. 0x10 ADDR_17 MEMCTL17 is selected as end address of sequence. 0x11 ADDR_18 MEMCTL18 is selected as end address of sequence. 0x12 ADDR_19 MEMCTL19 is selected as end address of sequence. 0x13 ADDR_20 MEMCTL20 is selected as end address of sequence. 0x14 ADDR_21 MEMCTL21 is selected as end address of sequence. 0x15 ADDR_22 MEMCTL22 is selected as end address of sequence. 0x16 ADDR_23 MEMCTL23 is selected as end address of sequence. 0x17 DMAEN Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers. 0x8 0x1 read-write DISABLE DMA trigger not enabled 0x0 ENABLE DMA trigger enabled 0x1 SAMPCNT Number of ADC converted samples to be transferred on a DMA trigger 0xB 0x5 read-write MIN Minimum value 0x0 MAX Maximum value 0x18 FIFOEN Enable FIFO based operation 0xA 0x1 DISABLE Disable 0x0 ENABLE Enable 0x1 RSTSAMPCAPEN 0: Sample and hold capacitor is not explicitly discharged at the end of conversion. 1: Sample and hold capacitor is discharged at the end of conversion. This incurs one additional conversion clock cycle. 0x4 0x1 read-write DISABLE Disable sample capacitor discharge feature. 0x0 ENABLE Enable sample capacitor discharge feature. 0x1 ADC1_CLKFREQ Sample Clock Frequency Range Register 0x1110 32 read-write 0x00000000 FRANGE Frequency Range. 0x0 0x3 RANGE1TO4 1 to 4 MHz 0x0 RANGE4TO8 >4 to 8 MHz 0x1 RANGE8TO16 >8 to 16 MHz 0x2 RANGE16TO20 >16 to 20 MHz 0x3 RANGE20TO24 >20 to 24 MHz 0x4 RANGE24TO32 >24 to 32 MHz 0x5 RANGE32TO40 >32 to 40 MHz 0x6 RANGE40TO48 >40 to 48 MHz 0x7 ADC1_SCOMP0 Sample Time Compare 0 Register 0x1114 32 read-write 0x00000000 VAL Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. 0x0 0xA read-write ADC1_SCOMP1 Sample Time Compare 1 Register 0x1118 32 read-write 0x00000000 VAL Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. 0x0 0xA read-write ADC1_WCLOW Window Comparator Low Threshold Register 0x1148 32 read-write 0x00000000 DATA If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s. 0x0 0x10 read-write ADC1_WCHIGH Window Comparator High Threshold Register 0x1150 32 read-write 0x00000000 DATA If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s. 0x0 0x10 read-write 24 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 ADC1_MEMCTL[%s] Conversion Memory Control Register 0x1180 32 read-write 0x00000000 CHANSEL Input channel select. 0x0 0x5 read-write CHAN_0 Selects channel 0 0x0 CHAN_1 Selects channel 1 0x1 CHAN_2 Selects channel 2 0x2 CHAN_3 Selects channel 3 0x3 CHAN_4 Selects channel 4 0x4 CHAN_5 Selects channel 5 0x5 CHAN_6 Selects channel 6 0x6 CHAN_7 Selects channel 7 0x7 CHAN_8 Selects channel 8 0x8 CHAN_9 Selects channel 9 0x9 CHAN_10 Selects channel 10 0xA CHAN_11 Selects channel 11 0xB CHAN_12 Selects channel 12 0xC CHAN_13 Selects channel 13 0xD CHAN_14 Selects channel 14 0xE CHAN_15 Selects channel 15 0xF CHAN_16 Selects channel 16 0x10 CHAN_17 Selects channel 17 0x11 CHAN_18 Selects channel 18 0x12 CHAN_19 Selects channel 19 0x13 CHAN_20 Selects channel 20 0x14 CHAN_21 Selects channel 21 0x15 CHAN_22 Selects channel 22 0x16 CHAN_23 Selects channel 23 0x17 CHAN_24 Selects channel 24 0x18 CHAN_25 Selects channel 25 0x19 CHAN_26 Selects channel 26 0x1A CHAN_27 Selects channel 27 0x1B CHAN_28 Selects channel 28 0x1C CHAN_29 Selects channel 29 0x1D CHAN_30 Selects channel 30 0x1E CHAN_31 Selects channel 31 0x1F TRIG Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions. 0x18 0x1 read-write AUTO_NEXT Next conversion is automatic 0x0 TRIGGER_NEXT Next conversion requires a trigger 0x1 VRSEL Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF. 0x8 0x3 read-write VDDA_VSSA VDDA reference 0x0 EXTREF_VREFM External reference from pin 0x1 INTREF_VSSA Internal reference 0x2 VDDA_VREFM VDDA and VREFM connected to VREF+ and VREF- of ADC 0x3 INTREF_VREFM INTREF and VREFM connected to VREF+ and VREF- of ADC 0x4 WINCOMP Enable window comparator. 0x1C 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 BCSEN Enable burn out current source. 0x14 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 AVGEN Enable hardware averaging. 0x10 0x1 read-write DISABLE Averaging disabled. 0x0 ENABLE Averaging enabled. 0x1 STIME Selects the source of sample timer period between SCOMP0 and SCOMP1. 0xC 0x1 SEL_SCOMP0 Select SCOMP0 0x0 SEL_SCOMP1 Select SCOMP1 0x1 ADC1_STATUS Status Register 0x1340 32 read-only 0x00000000 BUSY Busy. This bit indicates that an active ADC sample or conversion operation is in progress. 0x0 0x1 read-only IDLE No ADC sampling or conversion in progress. 0x0 ACTIVE ADC sampling or conversion is in progress. 0x1 REFBUFRDY Indicates reference buffer is powered up and ready. 0x1 0x1 NOTREADY Not ready 0x0 READY Ready 0x1 ADC1_SVT ADC 1.0 PERIPHERALREGIONSVT 0x40558000 0x0 0x1000 registers ADC1_SVT_FIFODATA FIFO Data Register 0x556160 32 read-only 24 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 ADC1_SVT_MEMRES[%s] Memory Result Register 0x556280 32 read-only DATA MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. 0x0 0x10 CRCP0 CRCP 1.0 PERIPHERALREGION 0x40440000 0x0 0x2000 registers 1 24 0 CRCP0_GPRCM[%s] 0x800 CRCP0_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 CRCP0_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 CRCP0_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 CRCP0_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CRCP0_CRCCTRL CRC Control Register 0x1100 32 read-write 0x00000000 0x00000007 POLYSIZE This bit indicates which CRC calculation is performed by the generator. 0x0 0x1 read-write CRC32 CRC-32 ISO-3309 calulation is performed 0x0 CRC16 CRC-16 CCITT is performed 0x1 BITREVERSE CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT. 0x1 0x1 read-write NOT_REVERSED Bit order is not reversed. 0x0 REVERSED Bit order is reversed. 0x1 INPUT_ENDIANNESS CRC Endian. This bit indicates the byte order within a word or half word of input data. 0x2 0x1 read-write LITTLE_ENDIAN LSB is lowest memory address and first to be processed. 0x0 BIG_ENDIAN LSB is highest memory address and last to be processed. 0x1 OUTPUT_BYTESWAP CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0 0x4 0x1 read-write DISABLE Output byteswapping is disabled 0x0 ENABLE Output byteswapping is enabled. 0x1 CRCP0_CRCSEED CRC Seed Register 0x1104 32 write-only 0x00000000 0xffffffff SEED Seed Data 0x0 0x20 write-only CRCP0_CRCIN CRC Input Data Register 0x1108 32 write-only 0x00000000 0xffffffff DATA Input Data 0x0 0x20 write-only CRCP0_CRCOUT CRC Output Result Register 0x110C 32 read-only 0x00000000 0xffffffff RESULT Result 0x0 0x20 read-only CRCP0_CRCPOLY CRC Polynomial configuration register 0x1110 32 512 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511 CRCP0_CRCIN_IDX[%s] CRC Input Data Array Register 0x1800 32 write-only 0x00000000 0xffffffff DATA Input Data 0x0 0x20 write-only TIMG8 TIMG 1.0 PERIPHERALREGION 0x40090000 0x0 0x1F00 registers TIMG8_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG8_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG8_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG8_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMG8_GPRCM[%s] 0x800 TIMG8_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMG8_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMG8_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMG8_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMG8_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMG8_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMG8_INT_EVENT[%s] 0x1020 TIMG8_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMG8_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 DC Direction Change Event mask 0x1B 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 QEIERR QEIERR Event mask 0x1C 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TIMG8_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 DC Direction Change 0x1B 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 QEIERR QEIERR, set on an incorrect state transition on the encoder interface. 0x1C 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG8_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 DC Direction Change 0x1B 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 QEIERR QEIERR 0x1C 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG8_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 DC Direction Change event SET 0x1B 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 QEIERR QEIERR event SET 0x1C 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMG8_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 DC Direction Change event CLEAR 0x1B 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 QEIERR QEIERR event CLEAR 0x1C 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMG8_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMG8_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 32 0 TIMG8_COMMONREGS[%s] 0x1100 TIMG8_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMG8_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 TIMG8_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMG8_CPS Clock Prescale Register 0xC 32 read-write PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write TIMG8_CPSV Clock prescale count status register 0x10 32 read-only CPSVAL Current Prescale Count Value 0x0 0x8 read-only TIMG8_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMG8_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 1 192 0 TIMG8_COUNTERREGS[%s] 0x1800 TIMG8_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x10 read-write TIMG8_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMG8_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x10 read-write 2 4 0,1 TIMG8_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMG8_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMG8_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMG8_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 2 4 0,1 TIMG8_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMG8_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 TIMG8_QDIR Count Direction Register 0xBC 32 read-only DIR Direction of count 0x0 0x1 DOWN Down (Phase B leads Phase A) 0x0 UP Up (Phase A leads Phase B) 0x1 TIMG9 TIMG 1.0 PERIPHERALREGION 0x40092000 0x0 0x1F00 registers TIMG9_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG9_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG9_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG9_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMG9_GPRCM[%s] 0x800 TIMG9_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMG9_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMG9_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMG9_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMG9_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMG9_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMG9_INT_EVENT[%s] 0x1020 TIMG9_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMG9_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 DC Direction Change Event mask 0x1B 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 QEIERR QEIERR Event mask 0x1C 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 TIMG9_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 DC Direction Change 0x1B 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 QEIERR QEIERR, set on an incorrect state transition on the encoder interface. 0x1C 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG9_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 DC Direction Change 0x1B 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 QEIERR QEIERR 0x1C 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG9_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 DC Direction Change event SET 0x1B 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 QEIERR QEIERR event SET 0x1C 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMG9_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 DC Direction Change event CLEAR 0x1B 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 QEIERR QEIERR event CLEAR 0x1C 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMG9_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMG9_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 32 0 TIMG9_COMMONREGS[%s] 0x1100 TIMG9_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMG9_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 TIMG9_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMG9_CPS Clock Prescale Register 0xC 32 read-write PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write TIMG9_CPSV Clock prescale count status register 0x10 32 read-only CPSVAL Current Prescale Count Value 0x0 0x8 read-only TIMG9_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMG9_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 1 192 0 TIMG9_COUNTERREGS[%s] 0x1800 TIMG9_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x10 read-write TIMG9_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMG9_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x10 read-write 2 4 0,1 TIMG9_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMG9_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMG9_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMG9_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 2 4 0,1 TIMG9_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMG9_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 TIMG9_QDIR Count Direction Register 0xBC 32 read-only DIR Direction of count 0x0 0x1 DOWN Down (Phase B leads Phase A) 0x0 UP Up (Phase A leads Phase B) 0x1 TIMG14 TIMG 1.0 PERIPHERALREGION 0x40096000 0x0 0x1F00 registers TIMG14_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG14_FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG14_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 TIMG14_FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 1 24 0 TIMG14_GPRCM[%s] 0x800 TIMG14_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 TIMG14_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 TIMG14_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 TIMG14_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 TIMG14_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 TIMG14_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 3 44 0,1,2 TIMG14_INT_EVENT[%s] 0x1020 TIMG14_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 Z Interrupt Source: Zero event 0x1 L REPLACE THIS WITH AN ACTUAL IRQ NAME 0x2 CCD0 Interrupt Source: Capture or compare down event (CCD0) 0x5 CCD1 Interrupt Source: Capture or compare down event (CCD1) 0x6 CCD2 Interrupt Source: Capture or compare down event (CCD2) 0x7 CCD3 Interrupt Source: Capture or compare down event (CCD3) 0x8 CCU0 Interrupt Source: Capture or compare up event (CCU0) 0x9 CCU1 Interrupt Source: Capture or compare up event (CCU1) 0xA CCU2 Interrupt Source: Capture or compare up event (CCU2) 0xB CCU3 Interrupt Source: Capture or compare up event (CCU3) 0xC CCD4 Interrupt Source: Compare down event (CCD4) 0xD CCD5 Interrupt Source: Compare down event (CCD5) 0xE CCU4 Interrupt Source: Compare down event (CCU4) 0xF CCU5 Interrupt Source: Compare down event (CCU5) 0x10 F Interrupt Source: Fault Event generated an interrupt. 0x19 TOV Interrupt Source: Trigger overflow 0x1A REPC Repeat Counter Zero 0x1B DC Interrupt Source: Direction Change 0x1C QEIERR QEI Incorrect state transition error 0x1D TIMG14_IMASK Interrupt mask 0x8 32 read-write Z Zero Event mask 0x0 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 L Load Event mask 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TOV Trigger Overflow Event mask 0x19 0x1 CLR Disable Event 0x0 SET Enable Event 0x1 CCD2 Capture or Compare DN event mask CCP2 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCD3 Capture or Compare DN event mask CCP3 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU2 Capture or Compare UP event mask CCP2 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CCU3 Capture or Compare UP event mask CCP3 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TIMG14_RIS Raw interrupt status 0x10 32 read-only 0x00000000 0xffffffff Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD2 Capture or compare down event generated an interrupt CCP2 0x6 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD3 Capture or compare down event generated an interrupt CCP3 0x7 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU2 Capture or compare up event generated an interrupt CCP2 0xA 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU3 Capture or compare up event generated an interrupt CCP3 0xB 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG14_MIS Masked interrupt status 0x18 32 read-only 0x00000000 Z Zero event generated an interrupt. 0x0 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 L Load event generated an interrupt. 0x1 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TOV Trigger overflow 0x19 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD2 Capture or compare down event generated an interrupt CCP2 0x6 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCD3 Capture or compare down event generated an interrupt CCP3 0x7 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU2 Capture or compare up event generated an interrupt CCP2 0xA 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 CCU3 Capture or compare up event generated an interrupt CCP3 0xB 0x1 CLR Event Cleared 0x0 SET Event Set 0x1 TIMG14_ISET Interrupt set 0x20 32 write-only 0x00000000 Z Zero event SET 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 L Load event SET 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD0 Capture or compare down event SET 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD1 Capture or compare down event SET 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU0 Capture or compare up event SET 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU1 Capture or compare up event SET 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TOV Trigger Overflow event SET 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD2 Capture or compare down event SET 0x6 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCD3 Capture or compare down event SET 0x7 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU2 Capture or compare up event SET 0xA 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 CCU3 Capture or compare up event SET 0xB 0x1 NO_EFFECT Writing 0 has no effect. 0x0 SET Event Set 0x1 TIMG14_ICLR Interrupt clear 0x28 32 write-only 0x00000000 Z Zero event CLEAR 0x0 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 L Load event CLEAR 0x1 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD0 Capture or compare down event CLEAR 0x4 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD1 Capture or compare down event CLEAR 0x5 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU0 Capture or compare up event CLEAR 0x8 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU1 Capture or compare up event CLEAR 0x9 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TOV Trigger Overflow event CLEAR 0x19 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD2 Capture or compare down event CLEAR 0x6 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCD3 Capture or compare down event CLEAR 0x7 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU2 Capture or compare up event CLEAR 0xA 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 CCU3 Capture or compare up event CLEAR 0xB 0x1 NO_EFFECT Writing 0 has no effect. 0x0 CLR Event Clear 0x1 TIMG14_EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 TIMG14_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 1 32 0 TIMG14_COMMONREGS[%s] 0x1100 TIMG14_CCPD CCP Direction 0x0 32 read-write C0CCP0 Counter CCP0 0x0 0x1 INPUT Input 0x0 OUTPUT Output 0x1 C0CCP1 Counter CCP1 0x1 0x1 INPUT Input 0x0 OUTPUT Output 0x1 TIMG14_ODIS Output Disable 0x4 32 read-write C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[0]. 0x0 CCP_OUTPUT_LOW CCP output occpout[0] is forced low. 0x1 C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write CCP_OUTPUT_OCTL Output function as selected by the OCTL register CCPO field are provided to occpout[1]. 0x0 CCP_OUTPUT_LOW CCP output occpout[1] is forced low. 0x1 TIMG14_CCLKCTL Counter Clock Control Register 0x8 32 read-write CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write DISABLED Clock is disabled. 0x0 ENABLED Clock is enabled 0x1 TIMG14_CPS Clock Prescale Register 0xC 32 read-write PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write TIMG14_CPSV Clock prescale count status register 0x10 32 read-only CPSVAL Current Prescale Count Value 0x0 0x8 read-only TIMG14_CTTRIGCTL Timer Cross Trigger Control Register 0x14 32 read-write CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write DISABLED Cross trigger generation disabled. 0x0 ENABLE Cross trigger generation enabled 0x1 EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write FSUB0 Use FSUB0 as cross trigger source. 0x0 FSUB1 Use FSUB1 as cross trigger source. 0x1 Z Use Zero event as cross trigger source. 0x2 L Use Load event as cross trigger source. 0x3 CCD0 Use CCD0 event as cross trigger source. 0x4 CCD1 Use CCD1 event as cross trigger source. 0x5 CCD2 Use CCD2 event as cross trigger source. 0x6 CCD3 Use CCD3 event as cross trigger source. 0x7 CCU0 Use CCU0 event as cross trigger source. 0x8 CCU1 Use CCU1 event as cross trigger source. 0x9 CCU2 Use CCU2 event as cross trigger source. 0xA CCU3 Use CCU3 event as cross trigger source. 0xB TIMG14_CTTRIG Timer Cross Trigger Register 0x1C 32 write-only TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only DISABLED Cross trigger generation disabled 0x0 GENERATE Generate Cross trigger pulse 0x1 1 180 0 TIMG14_COUNTERREGS[%s] 0x1800 TIMG14_CTR Counter Register 0x0 32 read-write 0x00000000 0xffffffff CCTR Current Counter value 0x0 0x10 read-write TIMG14_CTRCTL Counter Control Register 0x4 32 read-write 0x0000ff80 0xffffffff EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write REPEAT_0 Does not automatically advance following a zero event. 0x0 REPEAT_1 Continues to advance following a zero event. 0x1 REPEAT_2 Reserved 0x2 REPEAT_3 Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 0x3 REPEAT_4 Reserved 0x4 CM Count Mode 0x4 0x2 read-write DOWN Down 0x0 UP_DOWN Up/Down 0x1 UP Counter counts up. 0x2 CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write LDVAL The counter is set to the LOAD register value 0x0 NOCHANGE The counter value is unchanged from its current value which could have been initialized by software 0x1 ZEROVAL The counter is set to zero 0x2 DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write RESUME Resume counting 0x0 CVAE_ACTION Perform the action as specified by the CVAE field. 0x1 CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CCCTL0_LCOND CCCTL_0 LCOND 0x0 CCCTL1_LCOND CCCTL_1 LCOND 0x1 CCCTL2_LCOND CCCTL_2 LCOND This value exists when there are 4 channels. 0x2 CCCTL3_LCOND CCCTL_3 LCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2 input QEI mode. This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3 input QEI mode. This value exists when gptimer support QEI feature. 0x5 CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CCCTL0_ACOND CCCTL_0 ACOND 0x0 CCCTL1_ACOND CCCTL_1 ACOND 0x1 CCCTL2_ACOND CCCTL_2 ACOND This value exists when there are 4 channels. 0x2 CCCTL3_ACOND CCCTL_3 ACOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CCCTL0_ZCOND CCCTL_0 ZCOND 0x0 CCCTL1_ZCOND CCCTL_1 ZCOND 0x1 CCCTL2_ZCOND CCCTL_2 ZCOND This value exists when there are 4 channels. 0x2 CCCTL3_ZCOND CCCTL_3 ZCOND This value exists when there are 4 channels. 0x3 QEI_2INP Controlled by 2-input QEI mode This value exists when gptimer support QEI feature. 0x4 QEI_3INP Controlled by 3-input QEI mode This value exists when gptimer support QEI feature. 0x5 TIMG14_LOAD Load Register 0x8 32 read-write 0x00000000 0xffffffff LD Load Value 0x0 0x10 read-write 2 4 0,1 TIMG14_CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x10 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMG14_CC_23[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x18 32 read-write 0x00000000 0xffffffff CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 TIMG14_CCCTL_01[%s] Capture or Compare Control Registers 0x30 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACT register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMG14_CCCTL_23[%s] Capture or Compare Control Registers 0x38 32 read-write 0x00000000 0xffffffff CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write NOCAPTURE None (never captures) 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write TIMCLK Each TIMCLK 0x0 CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 CC_TRIG_HIGH CCP High or Trigger assertion (level) 0x5 LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CC_TRIG_RISE Rising edge of CCP or trigger assertion edge 0x1 CC_TRIG_FALL Falling edge of CCP or trigger de-assertion edge 0x2 CC_TRIG_EDGE Either edge of CCP or trigger change (assertion/de-assertion edge) 0x3 COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write COMPARE Compare 0x0 CAPTURE Capture 0x1 CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write Immediately Value written to the CCACTx_y register has immediate effect. 0x0 Zero_EVT Following a zero event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 0x1 Compare_Down_EVT Following a compare (down) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x2 Compare_UP_EVT Following a compare (up) event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 0x3 ZERO_LOAD_EVT Following a zero or load event Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 0x4 ZERO_RC_ZERO_EVT Following a zero event with repeat count also zero. Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 0x5 TRIG On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. 0x6 CC2SELU Selects the source second CCU event. 0x16 0x3 SEL_CCU0 Selects CCU from CC0. 0x0 SEL_CCU1 Selects CCU from CC1. 0x1 SEL_CCU2 Selects CCU from CC2. 0x2 SEL_CCU3 Selects CCU from CC3. 0x3 SEL_CCU4 Selects CCU from CC4. 0x4 SEL_CCU5 Selects CCU from CC5. 0x5 CC2SELD Selects the source second CCD event. 0x1D 0x3 SEL_CCD0 Selects CCD from CC0. 0x0 SEL_CCD1 Selects CCD from CC1. 0x1 SEL_CCD2 Selects CCD from CC2. 0x2 SEL_CCD3 Selects CCD from CC3. 0x3 SEL_CCD4 Selects CCD from CC4. 0x4 SEL_CCD5 Selects CCD from CC5. 0x5 2 4 0,1 TIMG14_OCTL_01[%s] CCP Output Control Registers 0x50 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMG14_OCTL_23[%s] CCP Output Control Registers 0x58 32 read-write 0x00000000 0xffffffff CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write NOINV No inversion 0x0 INV Invert 0x1 CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write LOW Low 0x0 HIGH High 0x1 CCPO CCP Output Source 0x0 0x4 read-write FUNCVAL Signal generator value (for example, PWM, triggered PWM) 0x0 LOAD Load condition 0x1 CMPVAL Compare value = counter condition 0x2 ZERO Zero condition 0x4 CAPCOND Capture condition 0x5 FAULTCOND Fault Condition 0x6 CC0_MIRROR_ALL Mirror CCP of first capture and compare register in counter group 0x8 CC1_MIRROR_ALL Mirror CCP of second capture and compare register in counter group 0x9 DEADBAND Deadband Inserted Output 0xC CNTDIR Counter direction 0xD 2 4 0,1 TIMG14_CCACT_01[%s] Capture or Compare Action Registers 0x70 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 2 4 0,1 TIMG14_CCACT_23[%s] Capture or Compare Action Registers 0x78 32 read-write 0x00000000 0xffffffff ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 CCP_TOGGLE CCP output value is toggled 0x3 SWFRCACT CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write DISABLED This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 0x0 CCP_HIGH CCP output value is set high 0x1 CCP_LOW CCP output value is set low 0x2 2 4 0,1 TIMG14_IFCTL_01[%s] Input Filter Control Register 0x80 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 2 4 0,1 TIMG14_IFCTL_23[%s] Input Filter Control Register 0x88 32 read-write 0x00000000 0xffffffff ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write CCPX_INPUT CCP of the corresponding capture compare unit 0x0 CCPX_INPUT_PAIR Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 0x1 CCP0_INPUT CCP0 of the counter 0x2 TRIG_INPUT Trigger 0x3 CCP_XOR XOR of CCP inputs as input source. 0x4 FSUB0 subscriber 0 event as input source. 0x5 FSUB1 subscriber 1 event as input source. 0x6 COMP0 Comparator 0 output. 0x7 COMP1 Comparator 1 output. 0x8 COMP2 Comparator 2 output. 0x9 INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write NOINVERT Noninverted 0x0 INVERT Inverted 0x1 FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write _3 The division factor is 3 0x0 _5 The division factor is 5 0x1 _8 The division factor is 8 0x2 CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write Consecutive Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 0x0 Voting Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. 0x1 FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write DISABLED Bypass. 0x0 ENABLED Filtered. 0x1 TIMG14_TSEL Trigger Select 0xB0 32 read-write 0x00000000 0xffffffff ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TRIG0 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x0 TRIG1 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x1 TRIG2 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x2 TRIG3 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x3 TRIG4 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x4 TRIG5 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x5 TRIG6 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x6 TRIG7 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x7 TRIG8 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x8 TRIG9 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0x9 TRIG10 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xA TRIG11 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xB TRIG12 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xC TRIG13 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xD TRIG14 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xE TRIG15 TRIGx = External trigger input from timer x (if available) in the same power domain as the current timer. 0xF TRIG_SUB0 TRIG_SUBx = External trigger input from subscriber port x. 0x10 TRIG_SUB1 TRIG_SUBx = External trigger input from subscriber port x. 0x11 TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write DISABLED Triggers are not used. 0x0 ENABLED Triggers are used as selected by the IE, ITSEL and ETSEL fields. 0x1 UART5 UART 1.0 PERIPHERALREGION 0x40504000 0x0 0x1F00 registers 1 24 0 UART5_GPRCM[%s] 0x800 UART5_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 UART5_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 UART5_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 UART5_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 UART5_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 UART5_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 UART5_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 UART5_CPU_INT[%s] 0x1020 UART5_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 FEFG UART framing error interrupt; Interrupt Flag: FE 0x2 PEFG UART parity error interrupt; Interrupt Flag: PE 0x3 BEFG UART break error interrupt; Interrupt Flag: BE 0x4 OEFG UART receive overrun error interrupt; Interrupt Flag: OE 0x5 RXNE Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE 0x6 RXPE Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE 0x7 LINC0 LIN capture 0 / match interrupt; Interrupt Flag: LINC0 0x8 LINC1 LIN capture 1 interrupt; Interrupt Flag: LINC1 0x9 LINOVF LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF 0xA RXIFG UART receive interrupt; Interrupt Flag: RX 0xB TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC EOT UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT 0xD MODE_9B 9-bit mode address match interrupt; Interrupt Flag: MODE_9B 0xE CTS UART Clear to Send Modem interrupt; Interrupt Flag: CTS 0xF DMA_DONE_RX DMA DONE on RX 0x10 DMA_DONE_TX DMA DONE on TX 0x11 NERR_EVT Noise Error Event 0x12 UART5_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PARERR Enable UART Parity Error Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 BRKERR Enable UART Break Error Interrupt. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTS Enable UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX Enable DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX Enable DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART5_CPU_INT_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_RX DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_TX DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART5_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR Masked UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR Masked UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS Masked UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_RX Masked DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_TX Masked DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART5_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 FRMERR Set UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PARERR Set UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 BRKERR Set UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTS Set UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing this has no effect 0x0 SET Set the interrupt 0x1 UART5_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PARERR Clear UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 BRKERR Clear UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTS Clear UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART5_DMA_TRIG_RX[%s] 0x1050 UART5_DMA_TRIG_RX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 RXIFG UART receive interrupt; Interrupt Flag: RX 0xB UART5_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART5_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART5_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART5_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART5_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART5_DMA_TRIG_TX[%s] 0x1080 UART5_DMA_TRIG_TX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC UART5_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART5_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART5_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART5_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART5_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 UART5_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 UART5_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 UART5_CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write DISABLE Disable Module 0x0 ENABLE Enable module 0x1 HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write OVS16 16x oversampling. 0x0 OVS8 8x oversampling. 0x1 OVS3 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled. 0x2 LBE UART Loop Back Enable 0x2 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The UARTxTX path is fed through the UARTxRX path internally. 0x1 RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write DISABLE The receive section of the UART is disabled. 0x0 ENABLE The receive section of the UART is enabled. 0x1 TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write DISABLE The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled. 0x0 ENABLE The transmit section of the UART is enabled. 0x1 RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CLR Signal not RTS 0x0 SET Signal RTS 0x1 RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write DISABLE RTS hardware flow control is disabled. 0x0 ENABLE RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries. 0x1 CTSEN Enable Clear To Send 0xE 0x1 read-write DISABLE CTS hardware flow control is disabled. 0x0 ENABLE CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted. 0x1 MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write UART Normal operation 0x0 RS485 RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data. 0x1 IDLELINE The UART operates in IDLE Line Mode 0x2 ADDR9BIT The UART operates in 9 Bit Address mode 0x3 SMART ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. 0x4 DALI DALI Mode: 0x5 FEN UART Enable FIFOs 0x11 0x1 read-write DISABLE The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 0x0 ENABLE The transmit and receive FIFO buffers are enabled (FIFO mode). 0x1 TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write LOW TXD pin is low 0x0 HIGH TXD pin is high 0x1 TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 0x5 0x1 read-write DISABLE TXD pin can not be controlled by TXD_OUT 0x0 ENABLE TXD pin can be controlled by TXD_OUT 0x1 MAJVOTE Majority Vote Enable When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (i.e. all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set. Oversampling of 16 : bits 7, 8, 9 are used Oversampling of 8 : bits 3, 4, 5 are used Disabled : Single sample value (center value) used 0x12 0x1 read-write DISABLE Majority voting is disabled 0x0 ENABLE Majority voting is enabled 0x1 MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write DISABLE Least significant bit is sent first in the protocol packet 0x0 ENABLE Most significant bit is sent first in the protocol packet 0x1 UART5_LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write DISABLE Normal use. 0x0 ENABLE A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0x1 PEN UART Parity Enable 0x1 0x1 read-write DISABLE Parity is disabled and no parity bit is added to the data frame. 0x0 ENABLE Parity checking and generation is enabled. 0x1 EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write ODD Odd parity is performed, which checks for an odd number of 1s. 0x0 EVEN Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0x1 STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write DISABLE One stop bit is transmitted at the end of a frame. 0x0 ENABLE Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid. 0x1 WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write DATABIT5 5 bits (default) 0x0 DATABIT6 6 bits 0x1 DATABIT7 7 bits 0x2 DATABIT8 8 bits 0x3 SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write DISABLE Disable Stick Parity 0x0 ENABLE Enable Stick Parity 0x1 SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write DISABLE Disable Send Idle Pattern 0x0 ENABLE Enable Send Idle Pattern 0x1 EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write UART5_STAT UART Status Register 0x1108 32 read-only BUSY UART Busy This bit is set as soon as the transmit FIFO or TXDATA register becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only CLEARED The UART is not busy. 0x0 SET The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register. 0x1 TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only CLEARED The transmitter is not full. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0x1 RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only CLEARED The receiver can receive data. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0x1 TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only CLEARED The transmitter has data to transmit. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0x1 CTS Clear To Send 0x8 0x1 read-only CLEARED The CTS signal is not asserted (high). 0x0 SET The CTS signal is asserted (low). 0x1 IDLE IDLE mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only CLEARED IDLE has not been detected before last received character. (In idle-line multiprocessor mode). 0x0 SET IDLE has been detected before last received character. (In idle-line multiprocessor mode). 0x1 RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only CLEARED The receiver is not empty. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0x1 UART5_IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_EMPTY TX FIFO is empty 0x5 LVL_1 TX FIFO >= 1 entry free Note: esp. required for DMA Trigger 0x7 RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write LVL_1_4_RES RX FIFO >= 1/4 full Note: For ULP Domain 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_FULL_RES RX FIFO is full Note: For ULP Domain 0x4 LVL_FULL RX FIFO is full 0x5 LVL_1 RX FIFO >= 1 entry available Note: esp. required for DMA Trigger 0x7 RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write UART5_IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write UART5_FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write UART5_GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb CHAIN Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0xB 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 UART5_TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write UART5_RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff DATA Received Data. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only CLR No framing error has occurred 0x0 SET The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1). 0x1 PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only CLR No parity error has occurred 0x0 SET The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0x1 BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only CLR No break condition has occurred 0x0 SET A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0x1 OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only CLR No data has been lost due to a receive overrun. 0x0 SET New data was received but could not be stored, because the previous data was not read (resulting in data loss). 0x1 NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only CLR No noise error occured 0x0 SET Noise error occured during majority voting 0x1 UART5_AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff MSK Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register must match. 0x0 0x8 read-write UART5_ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh. 0x0 0x8 read-write UART6 UART 1.0 PERIPHERALREGION 0x40506000 0x0 0x1F00 registers 1 24 0 UART6_GPRCM[%s] 0x800 UART6_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 UART6_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 UART6_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write Disable 0x0 Enable 0x1 UART6_GPRCM_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 UART6_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 UART6_CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 UART6_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 UART6_CPU_INT[%s] 0x1020 UART6_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 FEFG UART framing error interrupt; Interrupt Flag: FE 0x2 PEFG UART parity error interrupt; Interrupt Flag: PE 0x3 BEFG UART break error interrupt; Interrupt Flag: BE 0x4 OEFG UART receive overrun error interrupt; Interrupt Flag: OE 0x5 RXNE Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE 0x6 RXPE Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE 0x7 LINC0 LIN capture 0 / match interrupt; Interrupt Flag: LINC0 0x8 LINC1 LIN capture 1 interrupt; Interrupt Flag: LINC1 0x9 LINOVF LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF 0xA RXIFG UART receive interrupt; Interrupt Flag: RX 0xB TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC EOT UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT 0xD MODE_9B 9-bit mode address match interrupt; Interrupt Flag: MODE_9B 0xE CTS UART Clear to Send Modem interrupt; Interrupt Flag: CTS 0xF DMA_DONE_RX DMA DONE on RX 0x10 DMA_DONE_TX DMA DONE on TX 0x11 NERR_EVT Noise Error Event 0x12 UART6_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 PARERR Enable UART Parity Error Interrupt. 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 BRKERR Enable UART Break Error Interrupt. 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTS Enable UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_RX Enable DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 DMA_DONE_TX Enable DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART6_CPU_INT_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_RX DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 DMA_DONE_TX DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART6_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 PARERR Masked UART Parity Error Interrupt. 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 BRKERR Masked UART Break Error Interrupt. 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTS Masked UART Clear to Send Modem Interrupt. 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_RX Masked DMA Done on RX Event Channel Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 DMA_DONE_TX Masked DMA Done on TX Event Channel Interrupt 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART6_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 FRMERR Set UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 PARERR Set UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 BRKERR Set UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTS Set UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 DMA_DONE_RX Set DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 DMA_DONE_TX Set DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing this has no effect 0x0 SET Set the interrupt 0x1 UART6_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 PARERR Clear UART Parity Error Interrupt. 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 BRKERR Clear UART Break Error Interrupt. 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTS Clear UART Clear to Send Modem Interrupt. 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 DMA_DONE_RX Clear DMA Done on RX Event Channel Interrupt 0xF 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 DMA_DONE_TX Clear DMA Done on TX Event Channel Interrupt 0x10 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART6_DMA_TRIG_RX[%s] 0x1050 UART6_DMA_TRIG_RX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTFG UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0x1 RXIFG UART receive interrupt; Interrupt Flag: RX 0xB UART6_DMA_TRIG_RX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 RXINT Enable UART Receive Interrupt. 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART6_DMA_TRIG_RX_RIS Raw interrupt status 0x10 32 read-only RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART6_DMA_TRIG_RX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 RXINT Masked UART Receive Interrupt. 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART6_DMA_TRIG_RX_ISET Interrupt set 0x20 32 write-only 0x00000000 RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 RXINT Set UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART6_DMA_TRIG_RX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 RXINT Clear UART Receive Interrupt. 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 1 44 0 UART6_DMA_TRIG_TX[%s] 0x1080 UART6_DMA_TRIG_TX_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 TXIFG UART transmit interrupt; Interrupt Flag: TX 0xC UART6_DMA_TRIG_TX_IMASK Interrupt mask 0x8 32 read-write 0x00000000 TXINT Enable UART Transmit Interrupt. 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 UART6_DMA_TRIG_TX_RIS Raw interrupt status 0x10 32 read-only TXINT UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART6_DMA_TRIG_TX_MIS Masked interrupt status 0x18 32 read-only 0x00000000 TXINT Masked UART Transmit Interrupt. 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 UART6_DMA_TRIG_TX_ISET Interrupt set 0x20 32 write-only 0x00000000 TXINT Set UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 UART6_DMA_TRIG_TX_ICLR Interrupt clear 0x28 32 write-only 0x00000000 TXINT Clear UART Transmit Interrupt. 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 UART6_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 UART6_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 UART6_CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write DISABLE Disable Module 0x0 ENABLE Enable module 0x1 HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write OVS16 16x oversampling. 0x0 OVS8 8x oversampling. 0x1 OVS3 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled. 0x2 LBE UART Loop Back Enable 0x2 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The UARTxTX path is fed through the UARTxRX path internally. 0x1 RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write DISABLE The receive section of the UART is disabled. 0x0 ENABLE The receive section of the UART is enabled. 0x1 TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write DISABLE The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled. 0x0 ENABLE The transmit section of the UART is enabled. 0x1 RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CLR Signal not RTS 0x0 SET Signal RTS 0x1 RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write DISABLE RTS hardware flow control is disabled. 0x0 ENABLE RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries. 0x1 CTSEN Enable Clear To Send 0xE 0x1 read-write DISABLE CTS hardware flow control is disabled. 0x0 ENABLE CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted. 0x1 MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write UART Normal operation 0x0 RS485 RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data. 0x1 IDLELINE The UART operates in IDLE Line Mode 0x2 ADDR9BIT The UART operates in 9 Bit Address mode 0x3 SMART ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. 0x4 DALI DALI Mode: 0x5 FEN UART Enable FIFOs 0x11 0x1 read-write DISABLE The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 0x0 ENABLE The transmit and receive FIFO buffers are enabled (FIFO mode). 0x1 TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write LOW TXD pin is low 0x0 HIGH TXD pin is high 0x1 TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 0x5 0x1 read-write DISABLE TXD pin can not be controlled by TXD_OUT 0x0 ENABLE TXD pin can be controlled by TXD_OUT 0x1 MAJVOTE Majority Vote Enable When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (i.e. all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set. Oversampling of 16 : bits 7, 8, 9 are used Oversampling of 8 : bits 3, 4, 5 are used Disabled : Single sample value (center value) used 0x12 0x1 read-write DISABLE Majority voting is disabled 0x0 ENABLE Majority voting is enabled 0x1 MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write DISABLE Least significant bit is sent first in the protocol packet 0x0 ENABLE Most significant bit is sent first in the protocol packet 0x1 UART6_LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write DISABLE Normal use. 0x0 ENABLE A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0x1 PEN UART Parity Enable 0x1 0x1 read-write DISABLE Parity is disabled and no parity bit is added to the data frame. 0x0 ENABLE Parity checking and generation is enabled. 0x1 EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write ODD Odd parity is performed, which checks for an odd number of 1s. 0x0 EVEN Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0x1 STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write DISABLE One stop bit is transmitted at the end of a frame. 0x0 ENABLE Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid. 0x1 WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write DATABIT5 5 bits (default) 0x0 DATABIT6 6 bits 0x1 DATABIT7 7 bits 0x2 DATABIT8 8 bits 0x3 SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write DISABLE Disable Stick Parity 0x0 ENABLE Enable Stick Parity 0x1 SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write DISABLE Disable Send Idle Pattern 0x0 ENABLE Enable Send Idle Pattern 0x1 EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write UART6_STAT UART Status Register 0x1108 32 read-only BUSY UART Busy This bit is set as soon as the transmit FIFO or TXDATA register becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only CLEARED The UART is not busy. 0x0 SET The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register. 0x1 TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only CLEARED The transmitter is not full. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0x1 RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only CLEARED The receiver can receive data. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0x1 TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only CLEARED The transmitter has data to transmit. 0x0 SET If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0x1 CTS Clear To Send 0x8 0x1 read-only CLEARED The CTS signal is not asserted (high). 0x0 SET The CTS signal is asserted (low). 0x1 IDLE IDLE mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only CLEARED IDLE has not been detected before last received character. (In idle-line multiprocessor mode). 0x0 SET IDLE has been detected before last received character. (In idle-line multiprocessor mode). 0x1 RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only CLEARED The receiver is not empty. 0x0 SET If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0x1 UART6_IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write LVL_3_4 TX FIFO <= 3/4 empty 0x1 LVL_1_2 TX FIFO <= 1/2 empty (default) 0x2 LVL_1_4 TX FIFO <= 1/4 empty 0x3 LVL_EMPTY TX FIFO is empty 0x5 LVL_1 TX FIFO >= 1 entry free Note: esp. required for DMA Trigger 0x7 RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write LVL_1_4_RES RX FIFO >= 1/4 full Note: For ULP Domain 0x0 LVL_1_4 RX FIFO >= 1/4 full 0x1 LVL_1_2 RX FIFO >= 1/2 full (default) 0x2 LVL_3_4 RX FIFO >= 3/4 full 0x3 LVL_FULL_RES RX FIFO is full Note: For ULP Domain 0x4 LVL_FULL RX FIFO is full 0x5 LVL_1 RX FIFO >= 1 entry available Note: esp. required for DMA Trigger 0x7 RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write UART6_IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write UART6_FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write UART6_GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb CHAIN Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0xB 0x1 read-write DISABLED Disabled 0x0 ENABLED Enabled 0x1 UART6_TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write UART6_RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff DATA Received Data. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only CLR No framing error has occurred 0x0 SET The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1). 0x1 PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only CLR No parity error has occurred 0x0 SET The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0x1 BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only CLR No break condition has occurred 0x0 SET A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0x1 OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only CLR No data has been lost due to a receive overrun. 0x0 SET New data was received but could not be stored, because the previous data was not read (resulting in data loss). 0x1 NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only CLR No noise error occured 0x0 SET Noise error occured during majority voting 0x1 UART6_AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff MSK Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register must match. 0x0 0x8 read-write UART6_ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh. 0x0 0x8 read-write FLASHCTL FLASHCTL 1.0 NVMNW_A2512 0x400CD000 0x0 0x2000 registers FLASHCTL_IIDX Interrupt Index Register 0x1020 32 read-only 0x00000000 STAT Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt. 0x0 0x1 read-only NO_INTR No Interrupt Pending 0x0 DONE DONE Interrupt Pending 0x1 FLASHCTL_IMASK Interrupt Mask Register 0x1028 32 read-write DONE Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register 0x0 0x1 read-write DISABLED Interrupt is masked out 0x0 ENABLED Interrupt will request an interrupt service routine and corresponding bit in [IPSTANDARD.MIS] will be set 0x1 FLASHCTL_RIS Raw Interrupt Status Register 0x1030 32 read-only DONE Flash wrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority. 0x0 0x1 read-only CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 FLASHCTL_MIS Masked Interrupt Status Register 0x1038 32 read-only DONE Flash wrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits. 0x0 0x1 read-only CLR Masked interrupt did not occur 0x0 SET Masked interrupt occurred 0x1 FLASHCTL_ISET Interrupt Set Register 0x1040 32 write-only DONE 0: No effect 1: Set the DONE interrupt in the RIS register 0x0 0x1 write-only NO_EFFECT Writing a 0 has no effect 0x0 SET Set [IPSTANDARD.RIS] bit 0x1 FLASHCTL_ICLR Interrupt Clear Register 0x1048 32 write-only DONE 0: No effect 1: Clear the DONE interrupt in the RIS register 0x0 0x1 write-only NO_EFFECT Writing a 0 has no effect 0x0 CLR Clear [IPSTANDARD.RIS] bit 0x1 FLASHCTL_EVT_MODE Event Mode 0x10E0 32 read-only INT0_CFG Event line mode select for peripheral event 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. Hardware must clear the RIS. 0x2 FLASHCTL_DESC Hardware Version Description Register 0x10FC 32 read-only MINREV Minor Revision 0x0 0x4 read-only MAJREV Major Revision 0x4 0x4 read-only INSTNUM Instance number 0x8 0x4 read-only FEATUREVER Feature set 0xC 0x4 read-only MODULEID Module ID 0x10 0x10 read-only FLASHCTL_CMDEXEC Command Execute Register 0x1100 32 read-write VAL Command Execute value Initiates execution of the command specified in the CMDTYPE register. 0x0 0x1 read-write NOEXECUTE Command will not execute or is not executing in flash wrapper 0x0 EXECUTE Command will execute or is executing in flash wrapper 0x1 FLASHCTL_CMDTYPE Command Type Register 0x1104 32 read-write COMMAND Command type 0x0 0x3 read-write NOOP No Operation 0x0 PROGRAM Program 0x1 ERASE Erase 0x2 READVERIFY ReadVerify - Perform a standalone ReadVerify operation. 0x3 MODECHANGE Mode Change - Perform a mode change only, no other operation. 0x4 CLEARSTATUS Clear Status - Clear status bits in FW_SMSTAT only. 0x5 BLANKVERIFY Blank Verify - Check whether a flash word is in the erased state. This command may only be used with CMDTYPE.SIZE = ONEWORD 0x6 SIZE Command size 0x4 0x3 read-write ONEWORD Operate on 1 flash word 0x0 TWOWORD Operate on 2 flash words 0x1 FOURWORD Operate on 4 flash words 0x2 EIGHTWORD Operate on 8 flash words 0x3 SECTOR Operate on a flash sector 0x4 BANK Operate on an entire flash bank 0x5 FLASHCTL_CMDCTL Command Control Register 0x1108 32 read-write MODESEL Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly through the NW hardware. 0x0 0x4 read-write READ Read Mode 0x0 RDMARG0 Read Margin 0 Mode 0x2 RDMARG1 Read Margin 1 Mode 0x4 RDMARG0B Read Margin 0B Mode 0x6 RDMARG1B Read Margin 1B Mode 0x7 PGMVER Program Verify Mode 0x9 PGMSW Program Single Word 0xA ERASEVER Erase Verify Mode 0xB ERASESECT Erase Sector 0xC PGMMW Program Multiple Word 0xE ERASEBNK Erase Bank 0xF BANKSEL Bank Select A specific Bank ID can be written to this field to indicate to which bank an operation is to be applied if CMDCTL.ADDRXLATEOVR is set. 0x4 0x5 read-write BANK0 Bank 0 0x1 BANK1 Bank 1 0x2 BANK2 Bank 2 0x4 BANK3 Bank 3 0x8 BANK4 Bank 4 0x10 REGIONSEL Bank Region A specific region ID can be written to this field to indicate to which region an operation is to be applied if CMDCTL.ADDRXLATEOVR is set. 0x9 0x4 read-write MAIN Main Region 0x1 NONMAIN Non-Main Region 0x2 TRIM Trim Region 0x4 ENGR Engr Region 0x8 ECCGENOVR Override hardware generation of ECC data for program. Use data written to CMDDATAECC*. 0x11 0x1 read-write NOOVERRIDE Do not override 0x0 OVERRIDE Override 0x1 ADDRXLATEOVR Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID. 0x10 0x1 read-write NOOVERRIDE Do not override 0x0 OVERRIDE Override 0x1 SSERASEDIS Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired. 0x14 0x1 read-write ENABLE Enable 0x0 DISABLE Disable 0x1 DATAVEREN Enable invalid data verify. This checks for 0->1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without executing the program. 0x15 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FLASHCTL_CMDADDR Command Address Register 0x1120 32 read-write VAL Address value 0x0 0x20 read-write FLASHCTL_CMDBYTEN Command Program Byte Enable Register 0x1124 32 read-write VAL Command Byte Enable value. A 1-bit per flash word byte value is placed in this register. 0x0 0x12 read-write FLASHCTL_CMDDATAINDEX Command Data Index Register 0x112C 32 read-write VAL Data register index 0x0 0x3 read-write FLASHCTL_CMDDATA0 Command Data Register 0 0x1130 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA1 Command Data Register 1 0x1134 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA2 Command Data Register 2 0x1138 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA3 Command Data Register Bits 127:96 0x113C 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA4 Command Data Register 4 0x1140 32 read-write VAL A 32-bit data value is placed in this field. T 0x0 0x20 read-write FLASHCTL_CMDDATA5 Command Data Register 5 0x1144 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA6 Command Data Register 6 0x1148 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA7 Command Data Register 7 0x114C 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA8 Command Data Register 8 0x1150 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA9 Command Data Register 9 0x1154 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA10 Command Data Register 10 0x1158 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA11 Command Data Register 11 0x115C 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA12 Command Data Register 12 0x1160 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA13 Command Data Register 13 0x1164 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA14 Command Data Register 14 0x1168 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA15 Command Data Register 15 0x116C 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA16 Command Data Register 16 0x1170 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA17 Command Data Register 17 0x1174 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA18 Command Data Register 18 0x1178 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA19 Command Data Register 19 0x117C 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA20 Command Data Register 20 0x1180 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA21 Command Data Register 21 0x1184 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA22 Command Data Register 22 0x1188 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA23 Command Data Register 23 0x118C 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA24 Command Data Register 24 0x1190 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA25 Command Data Register 25 0x1194 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA26 Command Data Register 26 0x1198 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA27 Command Data Register 27 0x119C 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA28 Command Data Register 28 0x11A0 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA29 Command Data Register 29 0x11A4 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA30 Command Data Register 30 0x11A8 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATA31 Command Data Register 31 0x11AC 32 read-write VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write FLASHCTL_CMDDATAECC0 Command Data Register ECC 0 0x11B0 32 read-write VAL0 ECC data for bits 63:0 of the data is placed here. 0x0 0x8 read-write VAL1 ECC data for bits 127:64 of the data is placed here. 0x8 0x8 read-write FLASHCTL_CMDDATAECC1 Command Data Register ECC 1 0x11B4 32 read-write VAL0 ECC data for bits 63:0 of the data is placed here. 0x0 0x8 read-write VAL1 ECC data for bits 127:64 of the data is placed here. 0x8 0x8 read-write FLASHCTL_CMDDATAECC2 Command Data Register ECC 2 0x11B8 32 read-write VAL0 ECC data for bits 63:0 of the data is placed here. 0x0 0x8 read-write VAL1 ECC data for bits 127:64 of the data is placed here. 0x8 0x8 read-write FLASHCTL_CMDDATAECC3 Command Data Register ECC 3 0x11BC 32 read-write VAL0 ECC data for bits 63:0 of the data is placed here. 0x0 0x8 read-write VAL1 ECC data for bits 127:64 of the data is placed here. 0x8 0x8 read-write FLASHCTL_CMDDATAECC4 Command Data Register ECC 4 0x11C0 32 read-write VAL0 ECC data for bits 63:0 of the data is placed here. 0x0 0x8 read-write VAL1 ECC data for bits 127:64 of the data is placed here. 0x8 0x8 read-write FLASHCTL_CMDDATAECC5 Command Data Register ECC 5 0x11C4 32 read-write VAL0 ECC data for bits 63:0 of the data is placed here. 0x0 0x8 read-write VAL1 ECC data for bits 127:64 of the data is placed here. 0x8 0x8 read-write FLASHCTL_CMDDATAECC6 Command Data Register ECC 6 0x11C8 32 read-write VAL0 ECC data for bits 63:0 of the data is placed here. 0x0 0x8 read-write VAL1 ECC data for bits 127:64 of the data is placed here. 0x8 0x8 read-write FLASHCTL_CMDDATAECC7 Command Data Register ECC 7 0x11CC 32 read-write VAL0 ECC data for bits 63:0 of the data is placed here. 0x0 0x8 read-write VAL1 ECC data for bits 127:64 of the data is placed here. 0x8 0x8 read-write FLASHCTL_CMDWEPROTA Command Write Erase Protect A Register 0x11D0 32 read-write VAL Each bit protects 1 sector. bit [0]: When 1, sector 0 of the flash memory will be protected from program and erase. bit [1]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit [31]: When 1, sector 31 of the flash memory will be protected from program and erase. 0x0 0x20 read-write FLASHCTL_CMDWEPROTB Command Write Erase Protect B Register 0x11D4 32 read-write VAL Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register. 0x0 0x20 read-write FLASHCTL_CMDWEPROTC Command Write Erase Protect C Register 0x11D8 32 read-write VAL Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. Note that the sectors protected with this register start at sector 256 in the flash, where the sectors protected by the CMDWEPROTB register end. 0x0 0x20 read-write FLASHCTL_CMDWEPROTNM Command Write Erase Protect Non-Main Register 0x1210 32 read-write VAL Each bit protects 1 sector. bit [0]: When 1, sector 0 of the non-main region will be protected from program and erase. bit [1]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the non-main will be protected from program and erase. 0x0 0x20 read-write FLASHCTL_CMDWEPROTTR Command Write Erase Protect Trim Register 0x1214 32 read-write VAL Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase. 0x0 0x20 read-write FLASHCTL_CMDWEPROTEN Command Write Erase Protect Engr Register 0x1218 32 read-write VAL Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase. 0x0 0x20 read-write FLASHCTL_CFGCMD Command Configuration Register 0x13B0 32 read-write WAITSTATE Wait State setting for verify reads 0x0 0x4 read-write RDCLKSTREN Enable pulse stretching when generating a read clock to the flash bank from the flash wrapper. This effectively divides the read clock driven to the bank in order to avoid minimum pulse width requirements at the bank. 0x4 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 CTRLCLKSTREN Enable pulse stretching when generating a control clock to the flash bank from the flash wrapper. This effectively divides the control clock driven to the bank in order to avoid minimum pulse width requirements at the bank. 0x5 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 HOLDCLKSTREN Enable pulse stretching for the clocking of the hold latches for inputs to the flash bank. This effectively divides the flash controller internal clock in order to create a 50/50 duty cycle clock for hold latching. 0x6 0x1 read-write DISABLE Disable 0x0 ENABLE Enable 0x1 FLASHCTL_CFGPCNT Pulse Counter Configuration Register 0x13B4 32 read-write MAXPCNTOVR Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used. 0x0 0x1 read-write DEFAULT Use hard-wired (default) value for maximum pulse count 0x0 OVERRIDE Use value from MAXPCNTVAL field as maximum puse count 0x1 MAXPCNTVAL Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}. 0x4 0x8 read-write MAXERSPCNTOVR Override hard-wired maximum pulse count for erase. If set, then the value in MAXERSPCNTVAL will be used as the max pulse count for erase operations. By default, this bit is 0, and a hard-wired max pulse count is used. 0x10 0x1 read-write DEFAULT Use hard-wired (default) value for maximum pulse count 0x0 OVERRIDE Use value from MAXERSPCNTVAL field as maximum erase pulse count 0x1 MAXERSPCNTVAL Override maximum pulse count for erase with this value. If MAXERSPCNTOVR = 0, then this field is ignored. If MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for erase. 0x14 0xC read-write FLASHCTL_STATCMD Command Status Register 0x13D0 32 read-only CMDDONE Command Done 0x0 0x1 read-only STATNOTDONE Not Done 0x0 STATDONE Done 0x1 CMDPASS Command Pass - valid when CMD_DONE field is 1 0x1 0x1 read-only STATFAIL Fail 0x0 STATPASS Pass 0x1 CMDINPROGRESS Command In Progress 0x2 0x1 read-only STATCOMPLETE Complete 0x0 STATINPROGRESS In Progress 0x1 FAILWEPROT Command failed due to Write/Erase Protect Sector Violation 0x4 0x1 read-only STATNOFAIL No Fail 0x0 STATFAIL Fail 0x1 FAILVERIFY Command failed due to verify error 0x5 0x1 read-only STATNOFAIL No Fail 0x0 STATFAIL Fail 0x1 FAILMISC Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit. 0xC 0x1 read-only STATNOFAIL No Fail 0x0 STATFAIL Fail 0x1 FAILILLADDR Command failed due to the use of an illegal address 0x6 0x1 read-only STATNOFAIL No Fail 0x0 STATFAIL Fail 0x1 FAILMODE Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode. 0x7 0x1 read-only STATNOFAIL No Fail 0x0 STATFAIL Fail 0x1 FAILINVDATA Program command failed because an attempt was made to program a stored 0 value to a 1. 0x8 0x1 read-only STATNOFAIL No Fail 0x0 STATFAIL Fail 0x1 FLASHCTL_STATADDR Address Status Register 0x13D4 32 read-only BANKADDR Current Bank Address A bank offset address is stored in this register. 0x0 0x10 read-only BANKID Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank. 0x15 0x5 read-only BANK0 Bank 0 0x1 BANK1 Bank 1 0x2 BANK2 Bank 2 0x4 BANK3 Bank 3 0x8 BANK4 Bank 4 0x10 REGIONID Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating. 0x10 0x5 read-only MAIN Main Region 0x1 NONMAIN Non-Main Region 0x2 TRIM Trim Region 0x4 ENGR Engr Region 0x8 FLASHCTL_STATPCNT Pulse Count Status Register 0x13D8 32 read-only PULSECNT Current Pulse Counter Value 0x0 0xC read-only FLASHCTL_STATMODE Mode Status Register 0x13DC 32 read-only BANKNOTINRD Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank. 0x0 0x5 read-only BANK0 Bank 0 0x1 BANK1 Bank 1 0x2 BANK2 Bank 2 0x4 BANK3 Bank 3 0x8 BANK4 Bank 4 0x10 BANKMODE Indicates mode of bank(s) that are not in READ mode 0x8 0x4 read-only READ Read Mode 0x0 RDMARG0 Read Margin 0 Mode 0x2 RDMARG1 Read Margin 1 Mode 0x4 RDMARG0B Read Margin 0B Mode 0x6 RDMARG1B Read Margin 1B Mode 0x7 PGMVER Program Verify Mode 0x9 PGMSW Program Single Word 0xA ERASEVER Erase Verify Mode 0xB ERASESECT Erase Sector 0xC PGMMW Program Multiple Word 0xE ERASEBNK Erase Bank 0xF BANK2TRDY Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s). 0x10 0x1 read-only FALSE Not ready 0x0 TRUE Ready 0x1 BANK1TRDY Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed. 0x11 0x1 read-only FALSE Not ready 0x0 TRUE Ready 0x1 FLASHCTL_GBLINFO0 Global Information Register 0 0x13F0 32 read-only SECTORSIZE Sector size in bytes 0x0 0x10 read-only ONEKB Sector size is ONEKB 0x400 TWOKB Sector size is TWOKB 0x800 NUMBANKS Number of banks instantiated Minimum: 1 Maximum: 5 0x10 0x3 read-only FLASHCTL_GBLINFO1 Global Information Register 1 0x13F4 32 read-only DATAWIDTH Data width in bits 0x0 0x8 read-only W64BIT Data width is 64 bits 0x40 W128BIT Data width is 128 bits 0x80 ECCWIDTH ECC data width in bits 0x8 0x5 read-only W0BIT ECC data width is 0. ECC not used. 0x0 W8BIT ECC data width is 8 bits 0x8 W16BIT ECC data width is 16 bits 0x10 REDWIDTH Redundant data width in bits 0x10 0x3 read-only W0BIT Redundant data width is 0. Redundancy/Repair not present. 0x0 W2BIT Redundant data width is 2 bits 0x2 W4BIT Redundant data width is 4 bits 0x4 FLASHCTL_GBLINFO2 Global Information Register 2 0x13F8 32 read-only DATAREGISTERS Number of data registers present. 0x0 0x4 read-only FLASHCTL_BANK0INFO0 Bank Information Register 0 for Bank 0 0x1400 32 read-only MAINSIZE Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512) 0x0 0xC read-only MINSECTORS Minimum value of [MAINSIZE] 0x8 MAXSECTORS Maximum value of [MAINSIZE] 0x200 FLASHCTL_BANK0INFO1 Bank Information Register 1 for Bank 0 0x1404 32 read-only NONMAINSIZE Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0x0 0x8 read-only MINSECTORS Minimum value of [NONMAINSIZE] 0x0 MAXSECTORS Maximum value of [NONMAINSIZE] 0x20 TRIMSIZE Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0x8 0x8 read-only MINSECTORS Minimum value of [TRIMSIZE] 0x0 MAXSECTORS Maximum value of [TRIMSIZE] 0x20 ENGRSIZE Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0x10 0x8 read-only MINSECTORS Minimum value of [ENGRSIZE] 0x0 MAXSECTORS Maximum value of [ENGRSIZE] 0x20 FLASHCTL_BANK1INFO0 Bank Information Register 0 for Bank 1 0x1410 32 read-only MAINSIZE Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512) 0x0 0xC read-only MINSECTORS Minimum value of [MAINSIZE] 0x8 MAXSECTORS Maximum value of [MAINSIZE] 0x200 FLASHCTL_BANK1INFO1 Bank Information Register 1 for Bank 1 0x1414 32 read-only NONMAINSIZE Non-main region size in sectors 0x0 0x8 read-only MINSECTORS Minimum value of [NONMAINSIZE] 0x0 MAXSECTORS Maximum value of [NONMAINSIZE] 0x20 TRIMSIZE Trim region size in sectors 0x8 0x8 read-only MINSECTORS Minimum value of [TRIMSIZE] 0x0 MAXSECTORS Maximum value of [TRIMSIZE] 0x20 ENGRSIZE Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0x10 0x8 read-only MINSECTORS Minimum value of [ENGRSIZE] 0x0 MAXSECTORS Maximum value of [ENGRSIZE] 0x20 FLASHCTL_BANK2INFO0 Bank Information Register 0 for Bank 2 0x1420 32 read-only MAINSIZE Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512) 0x0 0xC read-only MINSECTORS Minimum value of [MAINSIZE] 0x8 MAXSECTORS Maximum value of [MAINSIZE] 0x200 FLASHCTL_BANK2INFO1 Bank Information Register 1 for Bank 2 0x1424 32 read-only NONMAINSIZE Non-main region size in sectors 0x0 0x8 read-only MINSECTORS Minimum value of [NONMAINSIZE] 0x0 MAXSECTORS Maximum value of [NONMAINSIZE] 0x20 TRIMSIZE Trim region size in sectors 0x8 0x8 read-only MINSECTORS Minimum value of [TRIMSIZE] 0x0 MAXSECTORS Maximum value of [TRIMSIZE] 0x20 ENGRSIZE Engr region size in sectors 0x10 0x8 read-only MINSECTORS Minimum value of [ENGRSIZE] 0x0 MAXSECTORS Maximum value of [ENGRSIZE] 0x20 FLASHCTL_BANK3INFO0 Bank Information Register 0 for Bank 3 0x1430 32 read-only MAINSIZE Main region size in sectors 0x0 0xC read-only MINSECTORS Minimum value of [MAINSIZE] 0x8 MAXSECTORS Maximum value of [MAINSIZE] 0x200 FLASHCTL_BANK3INFO1 Bank Information Register 1 for Bank 3 0x1434 32 read-only NONMAINSIZE Non-main region size in sectors 0x0 0x8 read-only MINSECTORS Minimum value of [NONMAINSIZE] 0x0 MAXSECTORS Maximum value of [NONMAINSIZE] 0x20 TRIMSIZE Trim region size in sectors 0x8 0x8 read-only MINSECTORS Minimum value of [TRIMSIZE] 0x0 MAXSECTORS Maximum value of [TRIMSIZE] 0x20 ENGRSIZE Engr region size in sectors 0x10 0x8 read-only MINSECTORS Minimum value of [ENGRSIZE] 0x0 MAXSECTORS Maximum value of [ENGRSIZE] 0x20 FLASHCTL_BANK4INFO0 Bank Information Register 0 for Bank 4 0x1440 32 read-only MAINSIZE Main region size in sectors 0x0 0xC read-only MINSECTORS Minimum value of [MAINSIZE] 0x8 MAXSECTORS Maximum value of [MAINSIZE] 0x200 FLASHCTL_BANK4INFO1 Bank Information Register 1 for Bank 4 0x1444 32 read-only NONMAINSIZE Non-main region size in sectors 0x0 0x8 read-only MINSECTORS Minimum value of [NONMAINSIZE] 0x0 MAXSECTORS Maximum value of [NONMAINSIZE] 0x20 TRIMSIZE Trim region size in sectors 0x8 0x8 read-only MINSECTORS Minimum value of [TRIMSIZE] 0x0 MAXSECTORS Maximum value of [TRIMSIZE] 0x20 ENGRSIZE Engr region size in sectors 0x10 0x8 read-only MINSECTORS Minimum value of [ENGRSIZE] 0x0 MAXSECTORS Maximum value of [ENGRSIZE] 0x20 LFSS LFSS 1.0 PERIPHERALREGION 0x40094000 0x0 0x1600 registers LFSS_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 LFSS_FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 LFSS_CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-only LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-only DISABLE LFCLK is disabled 0x0 ENABLE LFCLK is enabled 0x1 1 44 0 LFSS_CPU_INT[%s] 0x1020 LFSS_CPU_INT_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTCRDY RTC ready 0x1 RTCTEV RTC time event 0x2 RTCA1 RTC alarm 1 0x3 RTCA2 RTC alarm 2 0x4 RT0PS RTC prescale timer 0 0x5 RT1PS RTC prescale timer 1 0x6 RT2PS RTC prescale timer 2 0x7 TSEVT Time stamp event 0x8 TIO0 Tamper I/O 0 event 0x9 TIO1 Tamper I/O 1 event 0xA TIO2 Tamper I/O 2 event 0xB TIO3 Tamper I/O 3 event 0xC TIO4 Tamper I/O 4 event 0xD TIO5 Tamper I/O 5 event 0xE TIO6 Tamper I/O 6 event 0xF TIO7 Tamper I/O 7 event 0x10 TIO8 Tamper I/O 8 event 0x11 TIO9 Tamper I/O 9 event 0x12 TIO10 Tamper I/O 10 event 0x13 TIO11 Tamper I/O 11 event 0x14 TIO12 Tamper I/O 12 event 0x15 TIO13 Tamper I/O 13 event 0x16 TIO14 Tamper I/O 14 event 0x17 TIO15 Tamper I/O 15 event 0x18 LFSS_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTCRDY RTC ready 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RTCTEV RTC time event 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RTCA1 RTC alarm 1 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RTCA2 RTC alarm 2 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RT0PS RTC prescale timer 0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RT1PS RTC prescale timer 1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RT2PS RTC prescale timer 2 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TSEVT Time stamp event 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 read-write CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 LFSS_CPU_INT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 RTCRDY RTC ready 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTCTEV RTC time event 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTCA1 RTC alarm 1 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTCA2 RTC alarm 2 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RT0PS RTC prescale timer 0 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RT1PS RTC prescale timer 1 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RT2PS RTC prescale timer 2 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TSEVT Time stamp event 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 LFSS_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTCRDY RTC ready 0x0 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RTCTEV RTC time event 0x1 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RTCA1 RTC alarm 1 0x2 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RTCA2 RTC alarm 2 0x3 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RT0PS RTC prescale timer 0 0x4 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RT1PS RTC prescale timer 1 0x5 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RT2PS RTC prescale timer 2 0x6 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TSEVT Time stamp event 0x7 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 LFSS_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 RTCRDY RTC ready 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RTCTEV RTC time event 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RTCA1 RTC alarm 1 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RTCA2 RTC alarm 2 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RT0PS RTC prescale timer 0 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RT1PS RTC prescale timer 1 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RT2PS RTC prescale timer 2 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TSEVT Time stamp event 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 LFSS_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTCRDY RTC ready 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RTCTEV RTC time event 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RTCA1 RTC alarm 1 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RTCA2 RTC alarm 2 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RT0PS RTC prescale timer 0 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RT1PS RTC prescale timer 1 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RT2PS RTC prescale timer 2 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TSEVT Time stamp event 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 1 44 0 LFSS_GEN_EVENT[%s] 0x1050 LFSS_GEN_EVENT_IIDX Interrupt Index Register 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 RTCRDY RTC ready 0x1 RTCTEV RTC time event 0x2 RTCA1 RTC alarm 1 0x3 RTCA2 RTC alarm 2 0x4 RT0PS RTC prescale timer 0 0x5 RT1PS RTC prescale timer 1 0x6 RT2PS RTC prescale timer 2 0x7 TSEVT Time stamp event 0x8 TIO0 Tamper I/O 0 event 0x9 TIO1 Tamper I/O 1 event 0xA TIO2 Tamper I/O 2 event 0xB TIO3 Tamper I/O 3 event 0xC TIO4 Tamper I/O 4 event 0xD TIO5 Tamper I/O 5 event 0xE TIO6 Tamper I/O 6 event 0xF TIO7 Tamper I/O 7 event 0x10 TIO8 Tamper I/O 8 event 0x11 TIO9 Tamper I/O 9 event 0x12 TIO10 Tamper I/O 10 event 0x13 TIO11 Tamper I/O 11 event 0x14 TIO12 Tamper I/O 12 event 0x15 TIO13 Tamper I/O 13 event 0x16 TIO14 Tamper I/O 14 event 0x17 TIO15 Tamper I/O 15 event 0x18 LFSS_GEN_EVENT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 RTCRDY RTC ready 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RTCTEV RTC time event 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RTCA1 RTC alarm 1 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RTCA2 RTC alarm 2 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RT0PS RTC prescale timer 0 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RT1PS RTC prescale timer 1 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 RT2PS RTC prescale timer 2 0x6 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TSEVT Time stamp event 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 read-write CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrrupt Mask 0x1 LFSS_GEN_EVENT_RIS Raw interrupt status 0x10 32 read-only 0x00000000 RTCRDY RTC ready 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTCTEV RTC time event 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTCA1 RTC alarm 1 0x2 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RTCA2 RTC alarm 2 0x3 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RT0PS RTC prescale timer 0 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RT1PS RTC prescale timer 1 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 RT2PS RTC prescale timer 2 0x6 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TSEVT Time stamp event 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occurred 0x1 LFSS_GEN_EVENT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 RTCRDY RTC ready 0x0 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RTCTEV RTC time event 0x1 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RTCA1 RTC alarm 1 0x2 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RTCA2 RTC alarm 2 0x3 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RT0PS RTC prescale timer 0 0x4 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RT1PS RTC prescale timer 1 0x5 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 RT2PS RTC prescale timer 2 0x6 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TSEVT Time stamp event 0x7 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 CLR Interrupt did not occur or is masked out 0x0 SET Interrupt occurred 0x1 LFSS_GEN_EVENT_ISET Interrupt set 0x20 32 write-only 0x00000000 RTCRDY RTC ready 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RTCTEV RTC time event 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RTCA1 RTC alarm 1 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RTCA2 RTC alarm 2 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RT0PS RTC prescale timer 0 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RT1PS RTC prescale timer 1 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 RT2PS RTC prescale timer 2 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TSEVT Time stamp event 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 LFSS_GEN_EVENT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 RTCRDY RTC ready 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RTCTEV RTC time event 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RTCA1 RTC alarm 1 0x2 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RTCA2 RTC alarm 2 0x3 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RT0PS RTC prescale timer 0 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RT1PS RTC prescale timer 1 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 RT2PS RTC prescale timer 2 0x6 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TSEVT Time stamp event 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO0 Tamper I/O 0 event 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO1 Tamper I/O 1 event 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO2 Tamper I/O 2 event 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO3 Tamper I/O 3 event 0xB 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO4 Tamper I/O 4 event 0xC 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO5 Tamper I/O 5 event 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO6 Tamper I/O 6 event 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO7 Tamper I/O 7 event 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO8 Tamper I/O 8 event 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO9 Tamper I/O 9 event 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO10 Tamper I/O 10 event 0x12 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO11 Tamper I/O 11 event 0x13 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO12 Tamper I/O 12 event 0x14 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO13 Tamper I/O 13 event 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO14 Tamper I/O 14 event 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TIO15 Tamper I/O 15 event 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 LFSS_EVT_MODE Event Mode 0x10E0 32 read-only EVT0_CFG Event line mode 0 select 0x0 0x2 read-only SOFTWARE The interrupt or event line is in software mode. The software ISR clears the associated RIS flag. 0x1 EVT1_CFG Event line mode 1 select 0x2 0x2 read-only HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 LFSS_DESC LFSS Descriptor Register 0x10FC 32 read-only MINREV Minor revision. This number holds the module revision and is incremented by the module developers. n = Minor module revision (see device-specific data sheet) 0x0 0x4 read-only MAJREV Major revision. This number holds the module revision and is incremented by the module developers. n = Major version (see device-specific data sheet) 0x4 0x4 read-only INSTNUM Instantiated version. Describes which instance of the module accessed. 0x8 0x4 read-only INST0 This is the default, if there is only one instance - like for SSIM 0x0 FEATUREVER Feature set of this module. Differentiates the complexity of the actually instantiated module if there are differences. 0xC 0x4 read-only MODULEID Module identifier. This ID is unique for each module. 0x2911 = Module ID of the LFSS Module 0x10 0x10 read-only LFSS_CLKCTL RTC Clock Control Register 0x1100 32 read-write 0x00000000 0xffffffff MODCLKEN This bit enables the supply of the 32kHz clock to the RTC. It will not power-up the 32kHz crystal oscillator this needs to be done in the Clock System Module. 0x1F 0x1 read-write DISABLE 32kHz clock is not supplied to the RTC. 0x0 ENABLE 32kHz clock is supplied to the RTC. 0x1 LFSS_DBGCTL RTC Module Debug Control Register 0x1104 32 read-write 0x00000000 0xffffffff DBGRUN Debug Run. 0x0 0x1 read-write HALT Counter is halted if CPU is in debug state. 0x0 RUN Continue to operate normally ignoring the debug state of the CPU. 0x1 DBGINT Debug Interrupt Enable. 0x1 0x1 read-write OFF Interrupts of the module will not be captured anymore if CPU is in debug state. Which means no update to the RTCRIS, RTCMISC and RTCIIDX register. 0x0 ON Interrupts are enabled in debug mode. Interrupt requests are signaled to the interrupt controller. If the flags are required by software (polling mode) the DGBINT bit need to be set to 1. 0x1 LFSS_CTL RTC Control Register 0x1108 32 read-write 0x00000000 0xffffffff RTCTEVTX Real-time clock time event 0x0 = Minute changed 0x1 = Hour changed 0x2 = Every day at midnight (00:00) 0x3 = Every day at noon (12:00) 0x0 0x2 read-write MINUTE Generate RTC event every minute. 0x0 HOUR Generate RTC event every hour. 0x1 MIDNIGHT Generate RTC event at midnight. 0x2 NOON Generate RTC event at noon. 0x3 RTCBCD Real-time clock BCD select. Selects BCD counting for real-time clock. 0x7 0x1 read-write BINARY Binary code selected 0x0 BCD Binary coded decimal (BCD) code selected 0x1 LFSS_STA RTC Status Register 0x110C 32 read-only 0x00000000 0xffffffff RTCRDY Real-time clock ready. This bit indicates when the real-time clock time values are safe for reading. 0x0 0x1 read-only NOT_READY RTC time values in transition 0x0 READY RTC time values safe for reading. 0x1 RTCTCRDY Real-time clock temperature compensation ready. This is a read only bit that indicates when the RTCTCMPx can be written. Write to RTCTCMPx should be avoided when RTCTCRDY is reset. 0x1 0x1 read-only NOT_READY RTC temperature compensation in transition 0x0 READY RTC temperature compensation ready 0x1 RTCTCOK Real-time clock temperature compensation write OK. This is a read-only bit that indicates if the write to RTCTCMP is successful or not. 0x2 0x1 read-only NOT_OK Write to RTCTCMPx is unsuccessful 0x0 OK Write to RTCTCMPx is successful 0x1 LFSS_CAL RTC Clock Offset Calibration Register 0x1110 32 read-write 0x00000000 0xffffffff RTCOCALX Real-time clock offset error calibration. Each LSB represents approximately +1ppm (RTCOCALXS = 1) or -1ppm (RTCOCALXS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will be ignored by hardware. 0x0 0x8 read-write RTCOCALS Real-time clock offset error calibration sign. This bit decides the sign of offset error calibration. 0xF 0x1 read-write DOWN Down calibration. Frequency adjusted down. 0x0 UP Up calibration. Frequency adjusted up. 0x1 RTCCALFX Real-time clock calibration frequency. Selects frequency output to RTCCLK pin for calibration measurement. The corresponding port must be configured for the peripheral module function. 0x10 0x2 read-write F32KHZ 32 kHz 0x0 F512HZ 512 Hz 0x1 F256HZ 256 Hz 0x2 F1HZ 1 Hz 0x3 LFSS_TCMP RTC Temperature Compensation Register 0x1114 32 read-write 0x00000000 0xffffffff RTCTCMPX Real-time clock temperature compensation. Value written into this register is used for temperature compensation of RTC. Each LSB represents approximately +1ppm (RTCTCMPS = 1) or -1ppm (RTCTCMPS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm are ignored by hardware. Reading from RTCTCMP register at any time returns the cumulative value which is the signed addition of RTCOCALx and RTCTCMPX values, and the updated sign bit (RTCTCMPS) of the addition result. 0x0 0x8 read-write RTCTCMPS Real-time clock temperature compensation sign. This bit decides the sign of temperature compensation. 0xF 0x1 read-write DOWN Down calibration. Frequency adjusted down. 0x0 UP Up calibration. Frequency adjusted up. 0x1 LFSS_SEC RTC Seconds Register - Calendar Mode With Binary / BCD Format 0x1118 32 read-write 0x00000000 0xffff80c0 SECBIN Seconds Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x6 read-write SECLOWBCD Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write SECHIGHBCD Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x3 read-write LFSS_MIN RTC Minutes Register - Calendar Mode With Binary / BCD Format 0x111C 32 read-write 0x00000000 0xffff80c0 MINBIN Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x6 read-write MINLOWBCD Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write MINHIGHBCD Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x3 read-write LFSS_HOUR RTC Hours Register - Calendar Mode With Binary / BCD Format 0x1120 32 read-write 0x00000000 0xffffc0e0 HOURBIN Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x5 read-write HOURLOWBCD Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write HOURHIGHBCD Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x2 read-write LFSS_DAY RTC Day Of Week / Month Register - Calendar Mode With Binary / BCD Format 0x1124 32 read-write 0x00000000 0xffc0e0f8 DOW Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0. 0x0 0x3 read-write DOMBIN Day of month Binary (1 to 28, 29, 30, 31). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x8 0x5 read-write DOMLOWBCD Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x10 0x4 read-write DOMHIGHBCD Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x14 0x2 read-write LFSS_MON RTC Month Register - Calendar Mode With Binary / BCD Format 0x1128 32 read-write 0x00000000 0xffffe0f0 MONBIN Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x4 read-write MONLOWBCD Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write MONHIGHBCD Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x1 read-write LFSS_YEAR RTC Year Register - Calendar Mode With Binary / BCD Format 0x112C 32 read-write 0x00000000 0x8000f000 YEARLOWBIN Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x8 read-write YEARHIGHBIN Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write YEARLOWESTBCD Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x10 0x4 read-write DECADEBCD Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x14 0x4 read-write CENTLOWBCD Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x18 0x4 read-write CENTHIGHBCD Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x1C 0x3 read-write LFSS_A1MIN RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format 0x1130 32 read-write 0x00000000 0xffff80c0 AMINBIN Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x6 read-write AMINAEBIN Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0x7 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 AMINLOWBCD Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write AMINHIGHBCD Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x3 read-write AMINAEBCD Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0xF 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 LFSS_A1HOUR RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format 0x1134 32 read-write 0x00000000 0xffffc0f0 AHOURBIN Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x5 read-write AHOURAEBIN Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0x7 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 AHOURLOWBCD Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write AHOURHIGHBCD Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.. 0xC 0x2 read-write AHOURAEBCD Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0xF 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 LFSS_A1DAY RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format 0x1138 32 read-write 0x00000000 0xffc0e0f8 ADOW Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0. 0x0 0x3 read-write ADOWAE Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0. 0x7 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 ADOMBIN Alarm Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x8 0x5 read-write ADOMAEBIN Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0xF 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 ADOMLOWBCD Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x10 0x4 read-write ADOMHIGHBCD Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x14 0x2 read-write ADOMAEBCD Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0x17 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 LFSS_A2MIN RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format 0x113C 32 read-write 0x00000000 0xffff80c0 AMINBIN Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x6 read-write AMINAEBIN Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0x7 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 AMINLOWBCD Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write AMINHIGHBCD Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x3 read-write AMINAEBCD Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0xF 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 LFSS_A2HOUR RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format 0x1140 32 read-write 0x00000000 0xffffc0f0 AHOURBIN Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x5 read-write AHOURAEBIN Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0x7 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 AHOURLOWBCD Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-write AHOURHIGHBCD Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.. 0xC 0x2 read-write AHOURAEBCD Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0xF 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 LFSS_A2DAY RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format 0x1144 32 read-write 0x00000000 0xffc0e0f8 ADOW Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0. 0x0 0x3 read-write ADOWAE Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0. 0x7 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 ADOMBIN Alarm Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x8 0x5 read-write ADOMAEBIN Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0xF 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 ADOMLOWBCD Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x10 0x4 read-write ADOMHIGHBCD Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x14 0x2 read-write ADOMAEBCD Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled. 0x17 0x1 read-write DISABLE No alarm 0x0 ENABLE Alarm enabled 0x1 LFSS_PSCTL RTC Prescale Timer 0/1 Control Register 0x1148 32 read-write 0x00000008 0xffffffff RT0IP Prescale timer 0 interrupt interval 0x2 0x3 read-write INT244US Interval every 244 microsecond 0x2 INT488US Interval every 488 microsecond 0x3 INT0P98MS Interval every 0.98 milisecond 0x4 INT1P95MS Interval every 1.95 milisecond 0x5 INT3P91MS Interval every 3.91 milisecond 0x6 INT7P81MS Interval every 7.81 milisecond 0x7 RT1IP Prescale timer 1 interrupt interval 0x12 0x3 read-write INT15P6MS Interval every 15.6 milisecond 0x0 INT31P3MS Interval every 31.3 milisecond 0x1 INT62P5MS Interval every 62.5 milisecond 0x2 INT125MS Interval every 125 milisecond 0x3 INT250MS Interval every 250 milisecond 0x4 INT500MS Interval every 500 milisecond 0x5 INT1S Interval every 1 second 0x6 INT2S Interval every 2 second 0x7 LFSS_EXTPSCTL RTC Prescale Timer 2 Control Register 0x114C 32 read-write 0x00000000 0xffffffff RT2PS Prescale timer 2 interrupt interval 0x2 0x2 read-write INT4S Interval every 4 second 0x0 INT8S Interval every 8 second 0x1 INT16S Interval every 16 second 0x2 LFSS_TSSEC Time Stamp Seconds Register - Calendar Mode With Binary / BCD Format 0x1150 32 read-only 0x00000000 0xffffffff SECBIN Time Stamp Second Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x6 SECLOWBCD Time Stamp Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 SECHIGHBCD Time Stamp Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x3 LFSS_TSMIN Time Stamp Minutes Register - Calendar Mode With Binary / BCD Format 0x1154 32 read-only 0x00000000 0xffffffff MINBIN Time Stamp Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x6 read-only MINLOWBCD Time Stamp Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-only MINHIGHBCD Time Stamp Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x3 read-only LFSS_TSHOUR Time Stamp Hours Register - Calendar Mode With Binary / BCD Format 0x1158 32 read-only 0x00000000 0xffffffff HOURBIN Time Stamp Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x5 read-only HOURLOWBCD Time Stamp Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-only HOURHIGHBCD Time Stamp Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x2 read-only LFSS_TSDAY Time Stamp Day Of Week / MonthRegister - Calendar Mode With Binary / BCD Format 0x115C 32 read-only 0x00000000 0xffffffff DOW Time Stamp Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0. 0x0 0x3 read-only DOMBIN Time Stamp Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x8 0x5 read-only DOMLOWBCD Time Stamp Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x10 0x4 read-only DOMHIGHBCD Time Stamp Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x14 0x2 read-only LFSS_TSMON Time Stamp Month Register - Calendar Mode With Binary / BCD Format 0x1160 32 read-only 0x00000000 0xffffffff MONBIN Time Stamp Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x4 read-only MONLOWBCD Time Stamp Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-only MONHIGHBCD Time Stamp Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0xC 0x1 read-only LFSS_TSYEAR Time Stamp Years Register - Calendar Mode With Binary / BCD Format 0x1164 32 read-only 0x00000000 0xffffffff YEARLOWBIN Time Stamp Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x0 0x8 read-only YEARHIGHBIN Time Stamp Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0. 0x8 0x4 read-only YERARLOWESTBCD Time Stamp Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x10 0x4 read-only DECADEBCD Time Stamp Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x14 0x4 read-only CENTLOWBCD Time Stamp Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x18 0x4 read-only CENTHIGHBCD Time Stamp Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0. 0x1C 0x3 read-only LFSS_TSSTAT Time Stamp Status Register 0x1168 32 read-only 0x00000000 0xffffffff TSTIOEVT0 Tamper I/O 0 caused time stamp event 0x0 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT1 Tamper I/O 1 caused time stamp event 0x1 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT2 Tamper I/O 2 caused time stamp event 0x2 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT3 Tamper I/O 3 caused time stamp event 0x3 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT4 Tamper I/O 4 caused time stamp event 0x4 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT5 Tamper I/O 5 caused time stamp event 0x5 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT6 Tamper I/O 6 caused time stamp event 0x6 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT7 Tamper I/O 7 caused time stamp event 0x7 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT8 Tamper I/O 8 caused time stamp event 0x8 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT9 Tamper I/O 9 caused time stamp event 0x9 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT10 Tamper I/O 10 caused time stamp event 0xA 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT11 Tamper I/O 11 caused time stamp event 0xB 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT12 Tamper I/O 12 caused time stamp event 0xC 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT13 Tamper I/O 13 caused time stamp event 0xD 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT14 Tamper I/O 14 caused time stamp event 0xE 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSTIOEVT15 Tamper I/O 15 caused time stamp event 0xF 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 TSVDDEVT Loss of VDD caused time stamp event 0x10 0x1 read-only CLR no event detected 0x0 SET event detected 0x1 LFSS_TSCTL Time Stamp Control Register 0x116C 32 read-write 0x00000000 0xffffffff TSTIOEN0 Time Stamp by Tamper I/O 0 enable 0x0 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN1 Time Stamp by Tamper I/O 1 enable 0x1 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN2 Time Stamp by Tamper I/O 2 enable 0x2 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN3 Time Stamp by Tamper I/O 3 enable 0x3 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN4 Time Stamp by Tamper I/O 4 enable 0x4 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN5 Time Stamp by Tamper I/O 5 enable 0x5 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN6 Time Stamp by Tamper I/O 6 enable 0x6 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN7 Time Stamp by Tamper I/O 7 enable 0x7 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN8 Time Stamp by Tamper I/O 8 enable 0x8 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN9 Time Stamp by Tamper I/O 9 enable 0x9 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN10 Time Stamp by Tamper I/O 10 enable 0xA 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN11 Time Stamp by Tamper I/O 11 enable 0xB 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN12 Time Stamp by Tamper I/O 12 enable 0xC 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN13 Time Stamp by Tamper I/O 13 enable 0xD 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN14 Time Stamp by Tamper I/O 14 enable 0xE 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSTIOEN15 Time Stamp by Tamper I/O 15 enable 0xF 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSVDDEN Time Stamp by VDD Loss detection enable 0x10 0x1 read-write DISABLE function disabled 0x0 ENABLE function enabled 0x1 TSCAPTURE Defines the capture method of the RTC timestamp when a time stamp event occurens. 0x14 0x1 read-write FIRST Time stamp holds RTC capture at first occurrence of time stamp event. 0x0 LAST Time stamp holds RTC capture at last occurrence of time stamp event. 0x1 LFSS_TSCLR Time Stamp Clear Register 0x1170 32 write-only 0x00000000 0xffffffff CLR Clear time stamp and status register. 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR clear time stamp event 0x1 LFSS_LFSSRST Low frequency sub-system reset request 0x11F0 32 read-write 0x00000000 0xffffffff VBATPOR If set, the register bit will request a power on reset to the PMU of the LFSS. 0x0 0x1 read-write NO_EFFECT Writing this value has no effect. 0x0 SET Request power on reset to the LFSS. 0x1 LFSS_RTCLOCK Real time clock lock register 0x11FC 32 read-write 0x00000000 0xffffffff PROTECT If set, the register bit will protect the CLKCTL, SEC, MIN, HOUR, DAY, MON, YEAR and LFSSRST from accidental writes. 0x0 0x1 read-write CLR RTC counter is writable. 0x0 SET RTC counter is read only access. 0x1 16 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 LFSS_TIOCTL[%s] Tamper I/O Control Register 0x1200 32 read-write 0x00000000 0xffffffff IOMUX tamper I/O is controlled by SoC IOMUX module 0x0 0x1 read-write IOMUX The tamper I/O is controlled by the IOMUX of the SoC and does allow assignment to a peripheral function. In the case the main supply (VDD) is lost, this I/O will go into a Hi-Z state. 0x0 TAMPER The tamper I/O is controlled by the TIOCTL register and stays functional during loss of the main supply (VDD). 0x1 PIPD pull down enable 0x10 0x1 read-write DISABLE The pull-down function is disabled. 0x0 ENABLE The pull-down function is enabled. 0x1 PIPU pull up enable 0x11 0x1 DISABLE The pull-up function is disabled. 0x0 ENABLE The pull-up function is enabled. 0x1 INENA input enable 0x12 0x1 read-write DISABLE The input path is disabled. 0x0 ENABLE The input path is enabled. 0x1 POLARITY Enables and configures edge detection polarity for TIO 0x8 0x2 DISABLE Edge detection disabled 0x0 RISE Detects rising edge of input event 0x1 FALL Detects falling edge of input event 0x2 BOTH Detects both rising and falling edge of input event 0x3 FILTEREN Programmable counter length of digital glitch filter for TIO0 0xC 0x2 NO_FLT no filter on the tamper I/O beyond CDC synchronization sample 0x0 FLT_1 1 FLCLK minimum sample (30us) 0x1 FLT_2 3 LFCLK minimum sample (100us) 0x2 FLT_3 6 LFCLK minimum sample (200us) 0x3 TOUTSEL Selects the source for TOUT control 0x4 0x2 TOUT The TOUT register is the source for TOUT 0x0 LFCLKEXT The LFCLK is the source for TOUT 0x1 HEARTBEAT The heart beat generatore is the source for TOUT 0x2 TSEVTSTAT The time stamp event status is the source for TOUT 0x3 OUTINV Output inversion enable 0x13 0x1 DISBALE The output inversion is disabled. 0x0 ENABLE The output inversion is enabled. 0x1 LFSS_TOUT3_0 Tamper Output 3 to 0 0x1280 32 read-write 0x00000000 0xffffffff TIO0 This bit sets the value of the pin tamper I/O 0 (TIO0) when the output is enabled through TOE0 register. 0x0 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO1 This bit sets the value of the pin tamper I/O 1 (TIO1) when the output is enabled through TOE1 register. 0x8 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO2 This bit sets the value of the pin tamper I/O 2 (TIO0) when the output is enabled through TOE2 register. 0x10 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO3 This bit sets the value of the pin tamper I/O 3 (TIO3) when the output is enabled through TOE3 register. 0x18 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 LFSS_TOUT7_4 Tamper Output 7 to 4 0x1284 32 read-write 0x00000000 0xffffffff TIO4 This bit sets the value of the pin tamper I/O 4 (TIO4) when the output is enabled through TOE4 register. 0x0 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO5 This bit sets the value of the pin tamper I/O 5 (TIO5) when the output is enabled through TOE5 register. 0x8 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO6 This bit sets the value of the pin tamper I/O 2 (TIO6) when the output is enabled through TOE6 register. 0x10 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO7 This bit sets the value of the pin tamper I/O 7 (TIO7) when the output is enabled through TOE7 register. 0x18 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 LFSS_TOUT11_8 Tamper Output 11 to 8 0x1288 32 read-write 0x00000000 0xffffffff TIO8 This bit sets the value of the pin tamper I/O 8 (TIO8) when the output is enabled through TOE8 register. 0x0 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO9 This bit sets the value of the pin tamper I/O 9 (TIO9) when the output is enabled through TOE9 register. 0x8 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO10 This bit sets the value of the pin tamper I/O 10 (TIO10) when the output is enabled through TOE10 register. 0x10 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO11 This bit sets the value of the pin tamper I/O 11 (TIO11) when the output is enabled through TOE11 register. 0x18 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 LFSS_TOUT15_12 Tamper Output 15 to 12 0x128C 32 read-write 0x00000000 0xffffffff TIO12 This bit sets the value of the pin tamper I/O 12 (TIO12) when the output is enabled through TOE12 register. 0x0 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO13 This bit sets the value of the pin tamper I/O 13 (TIO13) when the output is enabled through TOE13 register. 0x8 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO14 This bit sets the value of the pin tamper I/O 14 (TIO14) when the output is enabled through TOE14 register. 0x10 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 TIO15 This bit sets the value of the pin tamper I/O 15 (TIO15) when the output is enabled through TOE15 register. 0x18 0x1 read-write ZERO Output is set to 0 0x0 ONE Output is set to 1 0x1 LFSS_TOE3_0 Tamper Output Enable 3 to 0 0x1290 32 read-write 0x00000000 0xffffffff TIO0 Enables data output for tamper I/O 0 0x0 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO1 Enables data output for tamper I/O 1 0x8 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO2 Enables data output for tamper I/O 2 0x10 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO3 Enables data output for tamper I/O 3 0x18 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 LFSS_TOE7_4 Tamper Output Enable 7 to 4 0x1294 32 read-write 0x00000000 0xffffffff TIO4 Enables data output for tamper I/O 4 0x0 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO5 Enables data output for tamper I/O 5 0x8 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO6 Enables data output for tamper I/O 6 0x10 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO7 Enables data output for tamper I/O 7 0x18 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 LFSS_TOE11_8 Tamper Output Enable 7 to 4 0x1298 32 read-write 0x00000000 0xffffffff TIO8 Enables data output for tamper I/O 8 0x0 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO9 Enables data output for tamper I/O 9 0x8 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO10 Enables data output for tamper I/O 10 0x10 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO11 Enables data output for tamper I/O 11 0x18 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 LFSS_TOE15_12 Tamper Output Enable 7 to 4 0x129C 32 read-write 0x00000000 0xffffffff TIO12 Enables data output for tamper I/O 12 0x0 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO13 Enables data output for tamper I/O 13 0x8 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO14 Enables data output for tamper I/O 14 0x10 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 TIO15 Enables data output for tamper I/O 15 0x18 0x1 read-write DISABLE output disabled 0x0 ENABLE output enabled 0x1 LFSS_TIN3_0 Tamper Input Register 0x12A0 32 read-only 0x00000000 0xffffffff TIO0 This bit reads the data input value of tamper I/O 0. 0x0 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO1 This bit reads the data input value of tamper I/O 1. 0x8 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO2 This bit reads the data input value of tamper I/O 2. 0x10 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO3 This bit reads the data input value of tamper I/O 3. 0x18 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 LFSS_TIN7_4 Tamper Input Register 0x12A4 32 read-only 0x00000000 0xffffffff TIO4 This bit reads the data input value of tamper I/O 4. 0x0 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO5 This bit reads the data input value of tamper I/O 5. 0x8 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO6 This bit reads the data input value of tamper I/O 6. 0x10 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO7 This bit reads the data input value of tamper I/O 7. 0x18 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 LFSS_TIN11_8 Tamper Input Register 0x12A8 32 read-only 0x00000000 0xffffffff TIO8 This bit reads the data input value of tamper I/O 8. 0x0 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO9 This bit reads the data input value of tamper I/O 9. 0x8 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO10 This bit reads the data input value of tamper I/O 10. 0x10 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO11 This bit reads the data input value of tamper I/O 11. 0x18 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 LFSS_TIN15_12 Tamper Input Register 0x12AC 32 read-only 0x00000000 0xffffffff TIO12 This bit reads the data input value of tamper I/O 12. 0x0 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO13 This bit reads the data input value of tamper I/O 13. 0x8 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO14 This bit reads the data input value of tamper I/O 14. 0x10 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 TIO15 This bit reads the data input value of tamper I/O 15. 0x18 0x1 ZERO Input value is 0 0x0 ONE Input value is 1 0x1 LFSS_HEARTBEAT Heartbeat Register 0x12C0 32 read-write 0x00000000 0xffffffff HBINTERVAL Heart beat interval 0x0 0x3 HBINT0P125 Heart beat interval 0.125 sec 0x0 HBINT0P25 Heart beat interval 0.25 sec 0x1 HBINT0P5 Heart beat interval 0.5 sec 0x2 HBINT1 Heart beat interval 1 sec 0x3 HBINT2 Heart beat interval 2 sec 0x4 HBINT4 Heart beat interval 4 sec 0x5 HBINT8 Heart beat interval 8 sec 0x6 HBINT16 Heart beat interval 16 sec 0x7 HBWIDTH Heart beat interval width 0x8 0x3 HBPWDTH1 Heart beat pulse width 1 msec 0x0 HBPWDTH2 Heart beat pulse width 2 msec 0x1 HBPWDTH4 Heart beat pulse width 4 msec 0x2 HBPWDTH8 Heart beat pulse width 8 msec 0x3 HBPWDTH16 Heart beat pulse width 16 msec 0x4 HBPWDTH32 Heart beat pulse width 32 msec 0x5 HBPWDTH64 Heart beat pulse width 64 msec 0x6 HBPWDTH128 Heart beat pulse width 128 msec 0x7 HBMODE Heart beat mode 0x10 0x2 HB_DIS Heart beat disabled 0x0 HB_ALLWAYS Heart beat allways enabled 0x1 HB_TS Heart beat enabled when time stamp event detected 0x2 HB_VDDFAIL Heart beat when VDD has fail condition 0x3 LFSS_TIOLOCK Tamper I/O lock register 0x12FC 32 read-write 0x00000000 0xffffffff PROTECT If set, the register bit will protect the TIOCTL and HEARTBEAT from accidental writes. 0x0 0x1 read-write CLR Tamper I/O control is writable. 0x0 SET Tamper I/O control is read only access. 0x1 LFSS_WDTEN Watchdog Timer Enable Register 0x1300 32 read-write 0x00000000 0xffffffff ENABLE Enable bit for the WDT. 0x0 0x1 read-write CLR Disable WDT 0x0 SET Enable WDT 0x1 LFSS_WDTDBGCTL Watchdog Timer Debug Control Register 0x1304 32 read-write 0x00000000 0xffffffff FREE Free run control 0x0 0x1 STOP The WDT freezes functionality while the CPU is Halted during debug and resumes when the CPU is active. 0x0 RUN The WDT ignores the state of the CPU Halted debug state. 0x1 LFSS_WDTCTL Watchdog Timer Control Register 0x1308 32 read-write 0x00000043 0xffffffff CLKDIV Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. 0x0 0x3 read-write MIN Minimum value 0x0 MAX Maximum value 0x7 PER Timer Period of the WDT. These bits select the total watchdog timer count. 0x4 0x3 read-write PER_EN_25 Total timer count is 2^25 0x0 PER_EN_21 Total timer count is 2^21 0x1 PER_EN_18 Total timer count is 2^18 0x2 PER_EN_15 Total timer count is 2^15 0x3 PER_EN_12 Total timer count is 2^12 (default) 0x4 PER_EN_10 Total timer count is 2^10 0x5 PER_EN_8 Total timer count is 2^8 0x6 PER_EN_6 Total timer count is 2^6 0x7 LFSS_WDTCNTRST Watchdog Timer Counter Reset Register 0x130C 32 write-only 0x00000000 0xffffffff RESTART Writing 03A7h to this register restarts the WDT Counter. Writing any other value causes a POR level reset. Read as 0x0h. 0x0 0x20 write-only VALUE VALUE to restart the WDT counter 0x3A7 LFSS_WDTSTAT Watchdog Timer Status Register 0x1310 32 read-only 0x00000000 0xffffffff RUN Watchdog running status flag. 0x0 0x1 read-only STOP Watchdog counter stopped. 0x0 RUN Watchdog running. 0x1 LFSS_WDTLOCK Watchdog timer lock register 0x13FC 32 read-write 0x00000000 0xffffffff PROTECT If set, the register bit will protect the WDTEN and WDTCTL from accidental writes. 0x0 0x1 read-write CLR Watchdog timer control is writable. 0x0 SET Watchdog timer control is read only access. 0x1 32 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 LFSS_SPMEM[%s] Scratch Pad Memory Data Register 0x1400 32 read-write 0x00000000 0xffffffff DATA3 memory data byte 3 0x18 0x8 read-write DATA2 memory data byte 2 0x10 0x8 read-write DATA1 memory data byte 1 0x8 0x8 read-write DATA0 memory data byte 0 0x0 0x8 read-write LFSS_SPMWPROT0 Scratch Pad Memory Write Protect Register 0 0x1500 32 read-write 0x00000000 0xffffffff WP_3_3 write protect SPMEM3 - DATA3 0xF 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_3_2 write protect SPMEM3 - DATA2 0xE 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_3_1 write protect SPMEM3 - DATA1 0xD 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_3_0 write protect SPMEM3 - DATA0 0xC 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_2_3 write protect SPMEM2 - DATA3 0xB 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_2_2 write protect SPMEM2 - DATA2 0xA 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_2_1 write protect SPMEM2 - DATA1 0x9 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_2_0 write protect SPMEM2 - DATA0 0x8 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_1_3 write protect SPMEM1 - DATA3 0x7 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_1_2 write protect SPMEM1 - DATA2 0x6 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_1_1 write protect SPMEM1 - DATA1 0x5 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_1_0 write protect SPMEM1 - DATA0 0x4 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_0_3 write protect SPMEM0 - DATA3 0x3 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_0_2 write protect SPMEM0 - DATA2 0x2 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_0_1 write protect SPMEM0 - DATA1 0x1 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_0_0 write protect SPMEM0 - DATA0 0x0 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 LFSS_SPMWPROT1 Scratch Pad Memory Write Protect Register 1 0x1504 32 read-write 0x00000000 0xffffffff WP_7_3 write protect SPMEM7 - DATA3 0xF 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_7_2 write protect SPMEM7 - DATA2 0xE 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_7_1 write protect SPMEM7 - DATA1 0xD 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_7_0 write protect SPMEM7 - DATA0 0xC 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_6_3 write protect SPMEM6 - DATA3 0xB 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_6_2 write protect SPMEM6 - DATA2 0xA 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_6_1 write protect SPMEM6 - DATA1 0x9 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_6_0 write protect SPMEM6 - DATA0 0x8 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_5_3 write protect SPMEM5 - DATA3 0x7 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_5_2 write protect SPMEM5 - DATA2 0x6 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_5_1 write protect SPMEM5 - DATA1 0x5 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_5_0 write protect SPMEM5 - DATA0 0x4 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_4_3 write protect SPMEM4 - DATA3 0x3 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_4_2 write protect SPMEM4 - DATA2 0x2 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_4_1 write protect SPMEM4 - DATA1 0x1 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_4_0 write protect SPMEM4 - DATA0 0x0 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 LFSS_SPMWPROT2 Scratch Pad Memory Write Protect Register 2 0x1508 32 read-write 0x00000000 0xffffffff WP_11_3 write protect SPMEM11 - DATA3 0xF 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_11_2 write protect SPMEM11 - DATA2 0xE 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_11_1 write protect SPMEM11 - DATA1 0xD 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_11_0 write protect SPMEM11 - DATA0 0xC 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_10_3 write protect SPMEM10 - DATA3 0xB 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_10_2 write protect SPMEM610- DATA2 0xA 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_10_1 write protect SPMEM10 - DATA1 0x9 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_10_0 write protect SPMEM10 - DATA0 0x8 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_9_3 write protect SPMEM9 - DATA3 0x7 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_9_2 write protect SPMEM9 - DATA2 0x6 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_9_1 write protect SPMEM9 - DATA1 0x5 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_9_0 write protect SPMEM9 - DATA0 0x4 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_8_3 write protect SPMEM8 - DATA3 0x3 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_8_2 write protect SPMEM8 - DATA2 0x2 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_8_1 write protect SPMEM8 - DATA1 0x1 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_8_0 write protect SPMEM8 - DATA0 0x0 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 LFSS_SPMWPROT3 Scratch Pad Memory Write Protect Register 3 0x150C 32 read-write 0x00000000 0xffffffff WP_15_3 write protect SPMEM15 - DATA3 0xF 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_15_2 write protect SPMEM15 - DATA2 0xE 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_15_1 write protect SPMEM15 - DATA1 0xD 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_15_0 write protect SPMEM15 - DATA0 0xC 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_14_3 write protect SPMEM14 - DATA3 0xB 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_14_2 write protect SPMEM14- DATA2 0xA 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_14_1 write protect SPMEM14 - DATA1 0x9 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_14_0 write protect SPMEM14 - DATA0 0x8 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_13_3 write protect SPMEM13 - DATA3 0x7 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_13_2 write protect SPMEM13 - DATA2 0x6 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_13_1 write protect SPMEM13 - DATA1 0x5 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_13_0 write protect SPMEM13 - DATA0 0x4 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_12_3 write protect SPMEM12 - DATA3 0x3 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_12_2 write protect SPMEM12 - DATA2 0x2 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_12_1 write protect SPMEM12 - DATA1 0x1 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_12_0 write protect SPMEM12 - DATA0 0x0 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 LFSS_SPMWPROT4 Scratch Pad Memory Write Protect Register 4 0x1510 32 read-write 0x00000000 0xffffffff WP_19_3 write protect SPMEM19 - DATA3 0xF 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_19_2 write protect SPMEM19 - DATA2 0xE 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_19_1 write protect SPMEM19 - DATA1 0xD 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_19_0 write protect SPMEM19 - DATA0 0xC 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_18_3 write protect SPMEM18 - DATA3 0xB 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_18_2 write protect SPMEM18- DATA2 0xA 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_18_1 write protect SPMEM18 - DATA1 0x9 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_18_0 write protect SPMEM18 - DATA0 0x8 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_17_3 write protect SPMEM17 - DATA3 0x7 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_17_2 write protect SPMEM17 - DATA2 0x6 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_17_1 write protect SPMEM17 - DATA1 0x5 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_17_0 write protect SPMEM17 - DATA0 0x4 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_16_3 write protect SPMEM16 - DATA3 0x3 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_16_2 write protect SPMEM16 - DATA2 0x2 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_16_1 write protect SPMEM16 - DATA1 0x1 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_16_0 write protect SPMEM16 - DATA0 0x0 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 LFSS_SPMWPROT5 Scratch Pad Memory Write Protect Register 5 0x1514 32 read-write 0x00000000 0xffffffff WP_23_3 write protect SPMEM23 - DATA3 0xF 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_23_2 write protect SPMEM23 - DATA2 0xE 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_23_1 write protect SPMEM23 - DATA1 0xD 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_23_0 write protect SPMEM23 - DATA0 0xC 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_22_3 write protect SPMEM22 - DATA3 0xB 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_22_2 write protect SPMEM22- DATA2 0xA 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_22_1 write protect SPMEM22 - DATA1 0x9 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_22_0 write protect SPMEM22 - DATA0 0x8 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_21_3 write protect SPMEM21 - DATA3 0x7 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_21_2 write protect SPMEM21 - DATA2 0x6 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_21_1 write protect SPMEM21 - DATA1 0x5 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_21_0 write protect SPMEM21 - DATA0 0x4 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_20_3 write protect SPMEM20 - DATA3 0x3 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_20_2 write protect SPMEM20 - DATA2 0x2 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_20_1 write protect SPMEM20 - DATA1 0x1 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_20_0 write protect SPMEM20 - DATA0 0x0 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 LFSS_SPMWPROT6 Scratch Pad Memory Write Protect Register 6 0x1518 32 read-write 0x00000000 0xffffffff WP_27_3 write protect SPMEM27 - DATA3 0xF 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_27_2 write protect SPMEM27 - DATA2 0xE 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_27_1 write protect SPMEM27 - DATA1 0xD 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_27_0 write protect SPMEM27 - DATA0 0xC 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_26_3 write protect SPMEM26 - DATA3 0xB 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_26_2 write protect SPMEM26- DATA2 0xA 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_26_1 write protect SPMEM26 - DATA1 0x9 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_26_0 write protect SPMEM26 - DATA0 0x8 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_25_3 write protect SPMEM25 - DATA3 0x7 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_25_2 write protect SPMEM25 - DATA2 0x6 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_25_1 write protect SPMEM25 - DATA1 0x5 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_25_0 write protect SPMEM25 - DATA0 0x4 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_24_3 write protect SPMEM24 - DATA3 0x3 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_24_2 write protect SPMEM24 - DATA2 0x2 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_24_1 write protect SPMEM24 - DATA1 0x1 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_24_0 write protect SPMEM24 - DATA0 0x0 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 LFSS_SPMWPROT7 Scratch Pad Memory Write Protect Register 7 0x151C 32 read-write 0x00000000 0xffffffff WP_31_3 write protect SPMEM31 - DATA3 0xF 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_31_2 write protect SPMEM31 - DATA2 0xE 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_31_1 write protect SPMEM31 - DATA1 0xD 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_31_0 write protect SPMEM31 - DATA0 0xC 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_30_3 write protect SPMEM30 - DATA3 0xB 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_30_2 write protect SPMEM30- DATA2 0xA 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_30_1 write protect SPMEM30 - DATA1 0x9 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_30_0 write protect SPMEM30 - DATA0 0x8 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_29_3 write protect SPMEM29 - DATA3 0x7 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_29_2 write protect SPMEM29 - DATA2 0x6 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_29_1 write protect SPMEM29 - DATA1 0x5 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_29_0 write protect SPMEM29 - DATA0 0x4 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_28_3 write protect SPMEM28 - DATA3 0x3 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_28_2 write protect SPMEM28 - DATA2 0x2 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_28_1 write protect SPMEM28 - DATA1 0x1 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 WP_28_0 write protect SPMEM28 - DATA0 0x0 0x1 read-write READWRITE SPMEM is read and write access 0x0 READONLY SPMEM is read only access 0x1 LFSS_SPMTERASE0 Scratch Pad Memory Tamper Erase Register 0 0x1540 32 read-write 0x00000000 0xffffffff TE_3_3 tamper erase enable SPMEM3 - DATA3 0xF 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_3_2 tamper erase enable SPMEM3 - DATA2 0xE 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_3_1 tamper erase enable SPMEM3 - DATA1 0xD 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_3_0 tamper erase enable SPMEM3 - DATA0 0xC 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_2_3 tamper erase enable SPMEM2 - DATA3 0xB 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_2_2 tamper erase enable SPMEM2 - DATA2 0xA 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_2_1 tamper erase enable SPMEM2 - DATA1 0x9 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_2_0 tamper erase enable SPMEM2 - DATA0 0x8 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_1_3 tamper erase enable SPMEM1 - DATA3 0x7 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_1_2 tamper erase enable SPMEM1 - DATA2 0x6 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_1_1 tamper erase enable SPMEM1 - DATA1 0x5 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_1_0 tamper erase enable SPMEM1 - DATA0 0x4 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_0_3 tamper erase enable SPMEM0 - DATA3 0x3 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_0_2 tamper erase enable SPMEM0 - DATA2 0x2 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_0_1 tamper erase enable SPMEM0 - DATA1 0x1 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_0_0 tamper erase enable SPMEM0 - DATA0 0x0 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 LFSS_SPMTERASE1 Scratch Pad Memory Tamper Erase Register 1 0x1544 32 read-write 0x00000000 0xffffffff TE_7_3 tamper erase enable SPMEM7 - DATA3 0xF 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_7_2 tamper erase enable SPMEM7 - DATA2 0xE 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_7_1 tamper erase enable SPMEM7 - DATA1 0xD 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_7_0 tamper erase enable SPMEM7 - DATA0 0xC 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_6_3 tamper erase enable SPMEM6 - DATA3 0xB 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_6_2 tamper erase enable SPMEM6 - DATA2 0xA 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_6_1 tamper erase enable SPMEM6 - DATA1 0x9 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_6_0 tamper erase enable SPMEM6 - DATA0 0x8 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_5_3 tamper erase enable SPMEM5 - DATA3 0x7 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_5_2 tamper erase enable SPMEM5 - DATA2 0x6 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_5_1 tamper erase enable SPMEM5 - DATA1 0x5 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_5_0 tamper erase enable SPMEM5 - DATA0 0x4 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_4_3 tamper erase enable SPMEM4 - DATA3 0x3 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_4_2 tamper erase enable SPMEM4 - DATA2 0x2 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_4_1 tamper erase enable SPMEM4 - DATA1 0x1 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_4_0 tamper erase enable SPMEM4 - DATA0 0x0 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 LFSS_SPMTERASE2 Scratch Pad Memory Tamper Erase Register 2 0x1548 32 read-write 0x00000000 0xffffffff TE_11_3 tamper erase enable SPMEM11 - DATA3 0xF 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_11_2 tamper erase enable SPMEM11 - DATA2 0xE 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_11_1 tamper erase enable SPMEM11 - DATA1 0xD 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_11_0 tamper erase enable SPMEM11 - DATA0 0xC 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_10_3 tamper erase enable SPMEM10 - DATA3 0xB 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_10_2 tamper erase enable SPMEM10 - DATA2 0xA 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_10_1 tamper erase enable SPMEM10 - DATA1 0x9 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_10_0 tamper erase enable SPMEM10 - DATA0 0x8 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_9_3 tamper erase enable SPMEM9 - DATA3 0x7 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_9_2 tamper erase enable SPMEM9 - DATA2 0x6 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_9_1 tamper erase enable SPMEM9 - DATA1 0x5 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_9_0 tamper erase enable SPMEM9 - DATA0 0x4 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_8_3 tamper erase enable SPMEM8 - DATA3 0x3 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_8_2 tamper erase enable SPMEM8 - DATA2 0x2 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_8_1 tamper erase enable SPMEM8 - DATA1 0x1 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_8_0 tamper erase enable SPMEM8 - DATA0 0x0 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 LFSS_SPMTERASE3 Scratch Pad Memory Tamper Erase Register 3 0x154C 32 read-write 0x00000000 0xffffffff TE_15_3 tamper erase enable SPMEM15 - DATA3 0xF 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_15_2 tamper erase enable SPMEM15 - DATA2 0xE 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_15_1 tamper erase enable SPMEM15 - DATA1 0xD 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_15_0 tamper erase enable SPMEM15 - DATA0 0xC 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_14_3 tamper erase enable SPMEM14 - DATA3 0xB 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_14_2 tamper erase enable SPMEM14 - DATA2 0xA 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_14_1 tamper erase enable SPMEM14 - DATA1 0x9 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_14_0 tamper erase enable SPMEM14 - DATA0 0x8 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_13_3 tamper erase enable SPMEM13 - DATA3 0x7 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_13_2 tamper erase enable SPMEM13 - DATA2 0x6 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_13_1 tamper erase enable SPMEM13 - DATA1 0x5 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_13_0 tamper erase enable SPMEM13 - DATA0 0x4 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_12_3 tamper erase enable SPMEM12 - DATA3 0x3 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_12_2 tamper erase enable SPMEM12 - DATA2 0x2 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_12_1 tamper erase enable SPMEM12 - DATA1 0x1 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_12_0 tamper erase enable SPMEM12 - DATA0 0x0 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 LFSS_SPMTERASE4 Scratch Pad Memory Tamper Erase Register 4 0x1550 32 read-write 0x00000000 0xffffffff TE_19_3 tamper erase enable SPMEM19 - DATA3 0xF 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_19_2 tamper erase enable SPMEM19 - DATA2 0xE 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_19_1 tamper erase enable SPMEM19 - DATA1 0xD 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_19_0 tamper erase enable SPMEM19 - DATA0 0xC 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_18_3 tamper erase enable SPMEM18 - DATA3 0xB 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_18_2 tamper erase enable SPMEM18 - DATA2 0xA 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_18_1 tamper erase enable SPMEM18 - DATA1 0x9 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_18_0 tamper erase enable SPMEM18 - DATA0 0x8 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_17_3 tamper erase enable SPMEM17 - DATA3 0x7 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_17_2 tamper erase enable SPMEM17 - DATA2 0x6 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_17_1 tamper erase enable SPMEM17 - DATA1 0x5 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_17_0 tamper erase enable SPMEM17 - DATA0 0x4 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_16_3 tamper erase enable SPMEM16 - DATA3 0x3 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_16_2 tamper erase enable SPMEM16 - DATA2 0x2 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_16_1 tamper erase enable SPMEM16 - DATA1 0x1 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_16_0 tamper erase enable SPMEM16 - DATA0 0x0 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 LFSS_SPMTERASE5 Scratch Pad Memory Tamper Erase Register 5 0x1554 32 read-write 0x00000000 0xffffffff TE_23_3 tamper erase enable SPMEM23 - DATA3 0xF 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_23_2 tamper erase enable SPMEM23 - DATA2 0xE 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_23_1 tamper erase enable SPMEM23 - DATA1 0xD 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_23_0 tamper erase enable SPMEM23 - DATA0 0xC 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_22_3 tamper erase enable SPMEM22 - DATA3 0xB 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_22_2 tamper erase enable SPMEM22 - DATA2 0xA 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_22_1 tamper erase enable SPMEM22 - DATA1 0x9 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_22_0 tamper erase enable SPMEM22 - DATA0 0x8 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_21_3 tamper erase enable SPMEM21 - DATA3 0x7 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_21_2 tamper erase enable SPMEM21 - DATA2 0x6 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_21_1 tamper erase enable SPMEM21 - DATA1 0x5 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_21_0 tamper erase enable SPMEM21 - DATA0 0x4 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_20_3 tamper erase enable SPMEM20 - DATA3 0x3 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_20_2 tamper erase enable SPMEM20 - DATA2 0x2 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_20_1 tamper erase enable SPMEM20 - DATA1 0x1 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_20_0 tamper erase enable SPMEM20 - DATA0 0x0 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 LFSS_SPMTERASE6 Scratch Pad Memory Tamper Erase Register 6 0x1558 32 read-write 0x00000000 0xffffffff TE_27_3 tamper erase enable SPMEM27 - DATA3 0xF 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_27_2 tamper erase enable SPMEM27 - DATA2 0xE 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_27_1 tamper erase enable SPMEM27 - DATA1 0xD 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_27_0 tamper erase enable SPMEM27 - DATA0 0xC 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_26_3 tamper erase enable SPMEM26 - DATA3 0xB 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_26_2 tamper erase enable SPMEM26 - DATA2 0xA 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_26_1 tamper erase enable SPMEM26 - DATA1 0x9 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_26_0 tamper erase enable SPMEM26 - DATA0 0x8 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_25_3 tamper erase enable SPMEM25 - DATA3 0x7 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_25_2 tamper erase enable SPMEM25 - DATA2 0x6 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_25_1 tamper erase enable SPMEM25 - DATA1 0x5 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_25_0 tamper erase enable SPMEM25 - DATA0 0x4 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_24_3 tamper erase enable SPMEM24 - DATA3 0x3 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_24_2 tamper erase enable SPMEM24 - DATA2 0x2 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_24_1 tamper erase enable SPMEM24 - DATA1 0x1 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_24_0 tamper erase enable SPMEM24 - DATA0 0x0 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 LFSS_SPMTERASE7 Scratch Pad Memory Tamper Erase Register 7 0x155C 32 read-write 0x00000000 0xffffffff TE_31_3 tamper erase enable SPMEM31 - DATA3 0xF 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_31_2 tamper erase enable SPMEM31 - DATA2 0xE 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_31_1 tamper erase enable SPMEM31 - DATA1 0xD 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_31_0 tamper erase enable SPMEM31 - DATA0 0xC 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_30_3 tamper erase enable SPMEM30 - DATA3 0xB 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_30_2 tamper erase enable SPMEM30 - DATA2 0xA 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_30_1 tamper erase enable SPMEM30 - DATA1 0x9 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_30_0 tamper erase enable SPMEM30 - DATA0 0x8 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_29_3 tamper erase enable SPMEM29 - DATA3 0x7 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_29_2 tamper erase enable SPMEM29 - DATA2 0x6 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_29_1 tamper erase enable SPMEM29 - DATA1 0x5 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_29_0 tamper erase enable SPMEM29 - DATA0 0x4 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_28_3 tamper erase enable SPMEM28 - DATA3 0x3 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_28_2 tamper erase enable SPMEM28 - DATA2 0x2 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_28_1 tamper erase enable SPMEM28 - DATA1 0x1 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 TE_28_0 tamper erase enable SPMEM28 - DATA0 0x0 0x1 read-write DISABLE SPMEM is unmodified during tamper event 0x0 ENABLE SPMEM will be erased with tamper event 0x1 I2C1 I2C 1.0 PERIPHERALREGION 0x400F2000 0x0 0x1F00 registers 1 24 0 I2C1_GPRCM[%s] 0x800 I2C1_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 I2C1_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 I2C1_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write DISABLE Not block async clock request 0x0 ENABLE Block async clock request 0x1 I2C1_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 I2C1_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 I2C1_CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 I2C1_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 I2C1_CPU_INT[%s] 0x1020 I2C1_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXDONEFG Controller data received 0x1 CTXDONEFG Controller data transmitted 0x2 CRXFIFOTRG Controller receive FIFO Trigger Level 0x3 CTXFIFOTRG Controller transmit FIFO Trigger level 0x4 CRXFIFOFULL RX FIFO FULL Event/interrupt pending 0x5 CTX_EMPTY Transmit FIFO/Buffer Empty Event/interrupt pending 0x6 CNACKFG Address/Data NACK 0x8 CSTARTFG Start Event 0x9 CSTOPFG Stop Event 0xA CARBLOSTFG Arbitration Lost 0xB CDMA_DONE_TX DMA DONE on Channel TX 0xC CDMA_DONE_RX DMA DONE on Channel RX 0xD CPEC_RX_ERR Controller PEC Receive Error Event 0xE TIMEOUTA Timeout A Event 0xF TIMEOUTB Timeout B Event 0x10 TRXDONEFG Target Data Event 0x11 TTXDONEFG Target Data Event 0x12 TRXFIFOTRG Target receive FIFO Trigger Level 0x13 TTXFIFOTRG Target transmit FIFO Trigger level 0x14 TRXFIFOFULL RX FIFO FULL Event/interrupt pending 0x15 TTXEMPTY Transmit FIFO/Buffer Empty Event/interrupt pending 0x16 TSTARTFG Start Event 0x17 TSTOPFG Stop Event 0x18 TGENCALL General Call Event 0x19 TDMA_DONE_TX DMA DONE on Channel TX 0x1A TDMA_DONE_RX DMA DONE on Channel RX 0x1B TPEC_RX_ERR Target PEC receive error event 0x1C TTX_UNFL Target TX FIFO underflow 0x1D TRX_OVFL Target RX FIFO overflow event 0x1E TARBLOST Target arbitration lost event 0x1F INTR_OVFL Interrupt overflow event 0x20 I2C1_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXDONE Controller Receive Transaction completed Interrupt 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXEMPTY Target Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an Target RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TSTART Start Condition Interrupt 0x16 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TDMA_DONE_TX Target DMA Done on Event Channel TX 0x19 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TDMA_DONE_RX Target DMA Done on Event Channel RX 0x1A 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Clear Set Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 INTR_OVFL Interrupt Overflow Interrupt Mask 0x1F 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_CPU_INT_RIS Raw interrupt status 0x10 32 read-only CRXDONE Controller Receive Transaction completed Interrupt 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TSTART Start Condition Interrupt 0x16 0x1 CLR Clear interrupt 0x0 SET Set Interrupt 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 CLR Clear Interrupt 0x0 SET Set interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 CLR Clear interrupt 0x0 SET Set interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 CLR Clear interrupt 0x0 SET Set interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt Occured 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Interrupt did not occur 0x0 SET Interrupt ocuured 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Interrupt did not occur 0x0 SET Interrupt Occured 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INTR_OVFL Interrupt overflow interrupt It is set when CSTART or CSTOP interrupts overflow i.e. occur twice without being serviced 0x1F 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 I2C1_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXDONE Controller Receive Data Interrupt 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if the RX FIFO is full. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TSTART Target START Detection Interrupt 0x16 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TSTOP Target STOP Detection Interrupt 0x17 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 I2C1_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXDONE Controller Receive Data Interrupt Signals that a byte has been received 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TIMEOUTA Timeout A interrupt 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CSTART START Detection Interrupt 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CRXFIFOFULL RXFIFO full event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TGENCALL General Call Interrupt 0x18 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TSTART Start Condition Interrupt 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 NO_EFFECT No effect 0x0 SET Set interrupt 0x1 I2C1_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXDONE Controller Receive Data Interrupt Signals that a byte has been received 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TIMEOUTA Timeout A interrupt 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CSTART START Detection Interrupt 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CRXFIFOFULL RXFIFO full event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TGENCALL General Call Interrupt 0x18 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TSTART Target START Detection Interrupt 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TSTOP Target STOP Detection Interrupt 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clear interrupt 0x1 1 44 0 I2C1_DMA_TRIG1[%s] 0x1050 I2C1_DMA_TRIG1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXFIFOTRG Controller receive FIFO Trigger Level 0x1 CTXFIFOTRG Controller transmit FIFO Trigger level 0x2 TRXFIFOTRG Target receive FIFO Trigger Level 0x3 TTXFIFOTRG Target transmit FIFO Trigger level 0x4 I2C1_DMA_TRIG1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_DMA_TRIG1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_DMA_TRIG1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_DMA_TRIG1_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_DMA_TRIG1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 1 44 0 I2C1_DMA_TRIG0[%s] 0x1080 I2C1_DMA_TRIG0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXFIFOTRG Controller receive FIFO Trigger Level 0x1 CTXFIFOTRG Controller transmit FIFO Trigger level 0x2 TRXFIFOTRG Target receive FIFO Trigger Level 0x3 TTXFIFOTRG Target transmit FIFO Trigger level 0x4 I2C1_DMA_TRIG0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_DMA_TRIG0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_DMA_TRIG0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_DMA_TRIG0_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C1_DMA_TRIG0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 I2C1_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG0] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 I2C1_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 I2C1_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 I2C1_GFCTL I2C Glitch Filter Control 0x1200 32 read-write AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only) 0x9 0x2 read-write AGLIT_5 Pulses shorter then 5ns length are filtered. 0x0 AGLIT_10 Pulses shorter then 10ns length are filtered. 0x1 AGLIT_25 Pulses shorter then 25ns length are filtered. 0x2 AGLIT_50 Pulses shorter then 50ns length are filtered. 0x3 DGFSEL Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only) 0x0 0x3 read-write DISABLED Bypass 0x0 CLK_1 1 clock 0x1 CLK_2 2 clocks 0x2 CLK_3 3 clocks 0x3 CLK_4 4 clocks 0x4 CLK_8 8 clocks 0x5 CLK_16 16 clocks 0x6 CLK_31 31 clocks 0x7 AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write DISABLE Analog Glitch Filter disable 0x0 ENABLE Analog Glitch Filter enable 0x1 CHAIN Analog and digital noise filters chaining enable. 0xB 0x1 DISABLE When 0, chaining is disabled and only digital filter output is available to IP logic for oversampling 0x0 ENABLE When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for oversampling 0x1 I2C1_TIMEOUT_CTL I2C Timeout Count Control Register 0x1204 32 read-write 0x00020002 0xffffffff TCNTLA Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us. 0x0 0x8 read-write TCNTAEN Timeout Counter A Enable 0xF 0x1 read-write DISABLE Disable Timeout Counter B 0x0 ENABLE Enable Timeout Counter B 0x1 TCNTLB Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns. 0x10 0x8 read-write TCNTBEN Timeout Counter B Enable 0x1F 0x1 read-write DISABLE Disable Timeout Counter B 0x0 ENABLE Enable Timeout Counter B 0x1 I2C1_TIMEOUT_CNT I2C Timeout Count Register 0x1208 32 read-only 0x00020002 0xffffffff TCNTA Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A 0x0 0x8 read-only TCNTB Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B 0x10 0x8 1 56 0 I2C1_CONTROLLER[%s] 0x1210 I2C1_CSA I2C Controller Target Address Register 0x0 32 read-write 0x00000000 DIR Receive/Send The DIR bit specifies if the next Controller operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive 0x0 0x1 TRANSMIT The Controller is in transmit mode. 0x0 RECEIVE The Controller is in receive mode. 0x1 TADDR I2C Target Address This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care 0x1 0xA CMODE This bit selects the adressing mode to be used in Controller mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 MODE7 7-bit addressing mode 0x0 MODE10 10-bit addressing mode 0x1 I2C1_CCTR I2C Controller Control Register 0x4 32 read-write 0x00000000 0xffffffff BURSTRUN I2C Controller Enable and start transaction 0x0 0x1 read-write DISABLE In standard mode, this encoding means the Controller is unable to transmit or receive data. 0x0 ENABLE The Controller is able to transmit or receive data. 0x1 START Generate START 0x1 0x1 read-write DISABLE The controller does not generate the START condition. 0x0 ENABLE The controller generates the START or repeated START condition. 0x1 STOP Generate STOP 0x2 0x1 read-write DISABLE The controller does not generate the STOP condition. 0x0 ENABLE The controller generates the STOP condition. 0x1 ACK Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. 0x3 0x1 read-write DISABLE The last received data byte of a transaction is not acknowledged automatically by the Controller. 0x0 ENABLE The last received data byte of a transaction is acknowledged automatically by the Controller. 0x1 CBLEN I2C transaction length This field contains the programmed length of bytes of the Transaction. 0x10 0xC read-write CACKOEN Controller ACK overrride Enable 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When 1 and the Controller is receiving data and the number of bytes indicated in MBLEN have been received, the state machine will generate an rxdone interrupt and wait at the start of the ACK for FW to indicate if an ACK or NACK should be sent. The ACK or NACK is selected by writing the MCTR register and setting ACK accordingly. The other fields in this register can also be written at this time to continue on with the transaction. If a NACK is sent the state machine will automatically send a Stop. 0x1 RD_ON_TXEMPTY Read on TX Empty 0x5 0x1 DISABLE No special behavior 0x0 ENABLE When 1 the Controller will transmit all bytes from the TX FIFO before continuing with the programmed Burst Run Read. If the DIR is not set to Read in the MSA then this bit is ignored. The Start must be set in the MCTR for proper I2C protocol. The Controller will first send the Start Condition, I2C Address with R/W bit set to write, before sending the bytes in the TX FIFO. When the TX FIFO is empty, the I2C transaction will continue as programmed in MTCR and MSA without sending a Stop Condition. This is intended to be used to perform simple I2C command based reads transition that will complete after initiating them without having to get an interrupt to turn the bus around. 0x1 I2C1_CSR I2C Controller Status Register 0x8 32 read-only BUSY I2C Controller FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction. 0x0 0x1 read-only CLEARED The controller is idle. 0x0 SET The controller is busy. 0x1 ERR Error The error can be from the Target address not being acknowledged or the transmit data not being acknowledged. 0x1 0x1 read-only CLEARED No error was detected on the last operation. 0x0 SET An error occurred on the last operation. 0x1 ADRACK Acknowledge Address 0x2 0x1 read-only CLEARED The transmitted address was acknowledged 0x0 SET The transmitted address was not acknowledged. 0x1 DATACK Acknowledge Data 0x3 0x1 read-only CLEARED The transmitted data was acknowledged 0x0 SET The transmitted data was not acknowledged. 0x1 ARBLST Arbitration Lost 0x4 0x1 read-only CLEARED The I2C controller won arbitration. 0x0 SET The I2C controller lost arbitration. 0x1 IDLE I2C Idle 0x5 0x1 read-only CLEARED The I2C controller is not idle. 0x0 SET The I2C controller is idle. 0x1 BUSBSY I2C Bus is Busy Controller State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0x6 0x1 read-only CLEARED The I2C bus is idle. 0x0 SET 'This Status bit is set on a START or when SCL goes low. It is cleared on a STOP, or when a SCL high bus busy timeout occurs and SCL and SDA are both high. This status is cleared when the ACTIVE bit is low. Note that the Controller State Machine will wait until this bit is cleared before starting an I2C transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0x1 CBCNT I2C Controller Transaction Count This field contains the current count-down value of the transaction. 0x10 0xC read-only I2C1_CRXDATA I2C Controller RXData 0xC 32 read-only 0x00000000 0xffffffff VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only I2C1_CTXDATA I2C Controller TXData 0x10 32 read-write 0x00000000 0xffffffff VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write I2C1_CTPR I2C Controller Timer Period 0x14 32 read-write 0x00000001 0xffffffff TPR Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns. 0x0 0x7 read-write I2C1_CCR I2C Controller Configuration 0x18 32 read-write 0x00000000 0xffffffff LPBK I2C Loopback 0x8 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The controller in a test mode loopback configuration. 0x1 MCTL MultiController mode. In MultiController mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller. 0x1 0x1 read-write DISABLE Disable MultiController mode. 0x0 ENABLE Enable MultiController mode. 0x1 ACTIVE Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0x0 0x1 read-write DISABLE Disables the I2C Controller operation. 0x0 ENABLE Enables the I2C Controller operation. 0x1 CLKSTRETCH Clock Stretching. This bit controls the support for clock stretching of the I2C bus. 0x2 0x1 read-write DISABLE Disables the clock stretching detection. This can be disabled if no Target on the bus does support clock stretching, so that the maximum speed on the bus can be reached. 0x0 ENABLE Enables the clock stretching detection. Enabling the clock stretching ensures compliance to the I2C standard but could limit the speed due the clock stretching. 0x1 I2C1_CBMON I2C Controller Bus Monitor 0x24 32 read-only 0x00000003 0xffffffff SCL I2C SCL Status 0x0 0x1 read-only CLEARED The I2CSCL signal is low. 0x0 SET The I2CSCL signal is high. Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations. 0x1 SDA I2C SDA Status 0x1 0x1 read-only CLEARED The I2CSDA signal is low. 0x0 SET The I2CSDA signal is high. Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations. 0x1 I2C1_CFIFOCTL I2C Controller FIFO Control 0x28 32 read-write 0x00000000 TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 EMPTY Trigger when the TX FIFO is empty. 0x0 LEVEL_1 Trigger when TX FIFO contains 1 byte 0x1 LEVEL_2 Trigger when TX FIFO contains 2 byte 0x2 LEVEL_3 Trigger when TX FIFO contains 3 byte 0x3 LEVEL_4 Trigger when TX FIFO contains 4 byte 0x4 LEVEL_5 Trigger when TX FIFO contains 5 byte 0x5 LEVEL_6 Trigger when TX FIFO contains 6 byte 0x6 LEVEL_7 Trigger when TX FIFO contains 7 byte 0x7 TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 LEVEL_1 Trigger when RX FIFO contains >= 1 byte 0x0 LEVEL_2 Trigger when RX FIFO contains >= 2 byte 0x1 LEVEL_3 Trigger when RX FIFO contains >= 3 byte 0x2 LEVEL_4 Trigger when RX FIFO contains >= 4 byte 0x3 LEVEL_5 Trigger when RX FIFO contains >= 5 byte 0x4 LEVEL_6 Trigger when RX FIFO contains >= 6 byte 0x5 LEVEL_7 Trigger when RX FIFO contains >= 7 byte 0x6 LEVEL_8 Trigger when RX FIFO contains >= 8 byte 0x7 RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 I2C1_CFIFOSR I2C Controller FIFO Status Register 0x2C 32 read-only 0x00000800 RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 I2C1_CONTROLLER_I2CPECCTL I2C Controller PEC control register 0x30 32 read-write 0x00000000 0xffffffff PECCNT PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Controller use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Target Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the Controller_I2CPECCTL Register will clear the current PEC Byte Count in the Controller State Machine. 0x0 0x9 PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits except the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 DISABLE PEC is disabled in Controller mode 0x0 ENABLE PEC is enabled in Controller mode 0x1 I2C1_CONTROLLER_PECSR I2C Controller PEC status register 0x34 32 read-only 0x00000000 0xffffffff PECBYTECNT PEC Byte Count This is the current PEC Byte Count of the Controller State Machine. 0x0 0x9 PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 CLEARED Indicates PEC was not checked in the transaction that occurred before the last Stop 0x0 SET Indicates if the PEC was checked in the transaction that occurred before the last Stop 0x1 PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 CLEARED Indicates PEC check error did not occurr in the transaction that occurred before the last Stop 0x0 SET Indicates if a PEC check error occurred in the transaction that occurred before the last Stop 0x1 1 44 0 I2C1_TARGET[%s] 0x1250 I2C1_TOAR I2C Target Own Address 0x0 32 read-write 0x00004000 0xffffffff OAR I2C Target Own Address: This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care 0x0 0xA read-write OAREN I2C Target Own Address Enable 0xE 0x1 DISABLE Disable OAR address 0x0 ENABLE Enable OAR address 0x1 TMODE This bit selects the adressing mode to be used in Target mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 MODE7 Enable 7-bit addressing 0x0 MODE10 Enable 10-bit addressing 0x1 I2C1_TOAR2 I2C Target Own Address 2 0x4 32 read-write 0x00000000 0xffffffff OAR2 I2C Target Own Address 2 This field specifies the alternate OAR2 address. 0x0 0x7 read-write OAR2EN I2C Target Own Address 2 Enable 0x7 0x1 read-write DISABLE The alternate address is disabled. 0x0 ENABLE Enables the use of the alternate address in the OAR2 field. 0x1 OAR2_MASK I2C Target Own Address 2 Mask: This field specifies bits A6 through A0 of the Target address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care. 0x10 0x7 I2C1_TCTR I2C Target Control Register 0x8 32 read-write 0x00000404 0xffffffff ACTIVE Device Active. Setting this bit enables the Target functionality. 0x0 0x1 read-write DISABLE Disables the I2C Target operation. 0x0 ENABLE Enables the I2C Target operation. 0x1 GENCALL General call response enable Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call 0x1 0x1 read-write DISABLE Do not respond to a general call 0x0 ENABLE Respond to a general call 0x1 TCLKSTRETCH Target Clock Stretch Enable 0x2 0x1 DISABLE Target clock stretching is disabled 0x0 ENABLE Target clock stretching is enabled 0x1 TXEMPTY_ON_TREQ Tx Empty Interrupt on TREQ 0x3 0x1 DISABLE When 0, RIS:TTXEMPTY will be set when only the Target TX FIFO is empty. This allows the TTXEMPTY interrupt to be used to indicate that the I2C bus is being clock stretched and that Target TX data is required. 0x0 ENABLE When 1, RIS:TTXEMPTY will be set when the Target State Machine is in the TX_WAIT state which occurs when the TX FIFO is empty AND the I2C transaction is clock stretched waiting for the FIFO to receive data. 0x1 TXTRIG_TXMODE Tx Trigger when Target FSM is in Tx Mode 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When 1, RIS:TXFIFOTRG will be set when the Target TX FIFO has reached the trigger level AND the Target State Machine is in the TXMODE as defined in the SSR register. When cleared RIS:TXFIFOTRG will be set when the Target TX FIFO is at or above the trigger level. This setting can be used to hold off the TX DMA until a transaction starts. This allows the DMA to be configured when the I2C is idle but have it wait till the transaction starts to load the Target TX FIFO, so it can load from a memory buffer that might be changing over time. 0x1 TXWAIT_STALE_TXFIFO Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Target State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale. 0x5 0x1 DISABLE When 0, the TX FIFO empty signal to the Target State Machine indicates that the TX FIFO is empty. 0x0 ENABLE When 1, the TX FIFO empty signal to the Target State Machine will indicate that the TX FIFO is empty or that the TX FIFO data is stale. The TX FIFO data is determined to be stale when there is data in the TX FIFO when the Target State Machine leaves the TXMODE as defined in the SSR register. This can occur is a Stop or timeout occur when there are bytes left in the TX FIFO. 0x1 RXFULL_ON_RREQ Rx full interrupt generated on RREQ condition as indicated in SSR 0x6 0x1 DISABLE When 0, RIS:TRXFULL will be set when only the Target RX FIFO is full. This allows the TRXFULL interrupt to be used to indicate that the I2C bus is being clock stretched and that the FW must either read the RX FIFO or ACK/NACK the current Rx byte. 0x0 ENABLE When 1, RIS:TRXFULL will be set when the Target State Machine is in the RX_WAIT or RX_ACK_WAIT states which occurs when the I2C transaction is clock stretched because the RX FIFO is full or the ACKOEN has been set and the state machine is waiting for FW to ACK/NACK the current byte. 0x1 EN_DEFHOSTADR Enable Default Host Address 0x7 0x1 DISABLE When this bit is 0, the default host address is not matched NOTE: it may still be matched if programmed inside SOAR/SOAR2 0x0 ENABLE When this bit is 1, default host address of 7h000_1000 is always matched by the Target address match logic. 0x1 EN_ALRESPADR Enable Alert Response Address 0x8 0x1 DISABLE When this bit is 0, the alert response address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2 0x0 ENABLE When this bit is 1, alert response address of 7h000_1100 is always matched by the Target address match logic. 0x1 EN_DEFDEVADR Enable Deault device address 0x9 0x1 DISABLE When this bit is 0, the default device address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2. 0x0 ENABLE When this bit is 1, default device address of 7h110_0001 is always matched by the Target address match logic. 0x1 TWUEN Target Wakeup Enable 0xA 0x1 DISABLE When 0, the Target is not allowed to clock stretch on START detection 0x0 ENABLE When 1, the Target is allowed to clock stretch on START detection and wait for faster clock to be abvailable. This allows clean wake up support for I2C in low power mode use cases 0x1 I2C1_TSR I2C Target Status Register 0xC 32 read-only 0x00000000 0xffffffff RREQ Receive Request 0x0 0x1 read-only CLEARED No outstanding receive data. 0x0 SET The I2C controller has outstanding receive data from the I2C Controller and is using clock stretching to delay the Controller until the data has been read from the TRXDATA FIFO (Target RX FIFO is full). 0x1 TREQ Transmit Request 0x1 0x1 read-only CLEARED No outstanding transmit request. 0x0 SET The I2C controller has been addressed as a Target transmitter and is using clock stretching to delay the Controller until data has been written to the TTXDATA FIFO (Target TX FIFO is empty). 0x1 OAR2SEL OAR2 Address Matched This bit gets reevaluated after every address comparison. 0x3 0x1 read-only CLEARED Either the OAR2 address is not matched or the match is in legacy mode. 0x0 SET OAR2 address matched and ACKed by the Target. 0x1 QCMDST Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction 0x4 0x1 read-only CLEARED The last transaction was a normal transaction or a transaction has not occurred. 0x0 SET The last transaction was a Quick Command transaction. 0x1 QCMDRW Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read 0x5 0x1 read-only CLEARED Quick command was a write 0x0 SET Quick command was a read 0x1 RXMODE Target FSM is in Rx MODE 0x2 0x1 CLEARED The Target State Machine is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. 0x0 SET The Target State Machine is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. 0x1 BUSBSY I2C bus is busy 0x6 0x1 CLEARED The I2C Bus is not busy 0x0 SET The I2C Bus is busy. This is cleared on a timeout. 0x1 TXMODE Target FSM is in TX MODE 0x7 0x1 CLEARED The Target State Machine is not in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. 0x0 SET The Target State Machine is in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. 0x1 STALE_TXFIFO Stale Tx FIFO 0x8 0x1 CLEARED Tx FIFO is not stale 0x0 SET The TX FIFO is stale. This occurs when the TX FIFO was not emptied during the previous I2C transaction. 0x1 ADDRMATCH Indicates the address for which Target address match happened 0x9 0xA I2C1_TRXDATA I2C Target RXData 0x10 32 read-only 0x00000000 0xffffffff VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only I2C1_TTXDATA I2C Target TXData 0x14 32 read-write 0x00000000 0xffffffff VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write I2C1_TACKCTL I2C Target ACK Control 0x18 32 read-write 0x00000000 0xffffffff ACKOEN I2C Target ACK Override Enable 0x0 0x1 read-write DISABLE A response in not provided. 0x0 ENABLE An ACK or NACK is sent according to the value written to the ACKOVAL bit. 0x1 ACKOVAL I2C Target ACK Override Value Note: for General Call this bit will be ignored if set to NACK and Target continues to receive data. 0x1 0x1 read-write DISABLE An ACK is sent indicating valid data or command. 0x0 ENABLE A NACK is sent indicating invalid data or command. 0x1 ACKOEN_ON_START When set this bit will automatically turn on the Target ACKOEN field following a Start Condition. 0x2 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following a Start Condition. 0x1 ACKOEN_ON_PECNEXT When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing Target_SACKCTL. 0x3 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing Target_SACKCTL. 0x1 ACKOEN_ON_PECDONE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte. 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte. 0x1 I2C1_TFIFOCTL I2C Target FIFO Control 0x1C 32 read-write 0x00000000 TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 LEVEL_4 Trigger when TX FIFO contains 4 byte 0x4 LEVEL_5 Trigger when TX FIFO contains 5 byte 0x5 LEVEL_6 Trigger when TX FIFO contains 6 byte 0x6 LEVEL_7 Trigger when TX FIFO contains 7 byte 0x7 TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 LEVEL_5 Trigger when RX FIFO contains >= 5 byte 0x4 LEVEL_6 Trigger when RX FIFO contains >= 6 byte 0x5 LEVEL_7 Trigger when RX FIFO contains >= 7 byte 0x6 LEVEL_8 Trigger when RX FIFO contains >= 8 byte 0x7 I2C1_TFIFOSR I2C Target FIFO Status Register 0x20 32 read-only 0x00000800 RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 INACTIVE FIFOFlush not active 0x0 ACTIVE FIFO Flush active 0x1 I2C1_TARGET_PECCTL I2C Target PEC control register 0x24 32 read-write 0x00000000 0xffffffff PECCNT When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Target use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction 0x0 0x9 PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits except the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 DISABLE PEC transmission and check is disabled 0x0 ENABLE PEC transmission and check is enabled 0x1 I2C1_TARGET_PECSR I2C Target PEC status register 0x28 32 read-only 0x00000000 0xffffffff PECBYTECNT This is the current PEC Byte Count of the Target State Machine. 0x0 0x9 PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 CLEARED Indicates PEC was not checked in the transaction that occurred before the last Stop 0x0 SET Indicates PEC was checked in the transaction that occurred before the last Stop 0x1 PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 CLEARED Indicates PEC check error did not occurr in the transaction that occurred before the last Stop 0x0 SET Indicates PEC check error occurred in the transaction that occurred before the last Stop 0x1 I2C2 I2C 1.0 PERIPHERALREGION 0x400F4000 0x0 0x1F00 registers 1 24 0 I2C2_GPRCM[%s] 0x800 I2C2_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 I2C2_RSTCTL Reset Control 0x4 32 write-only 0x00000000 RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 I2C2_CLKCFG Peripheral Clock Configuration Register 0x8 32 read-write 0x00000000 BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write DISABLE Not block async clock request 0x0 ENABLE Block async clock request 0x1 I2C2_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 I2C2_CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 RATIO Selects divide ratio of module clock 0x0 0x3 DIV_BY_1 Do not divide clock source 0x0 DIV_BY_2 Divide clock source by 2 0x1 DIV_BY_3 Divide clock source by 3 0x2 DIV_BY_4 Divide clock source by 4 0x3 DIV_BY_5 Divide clock source by 5 0x4 DIV_BY_6 Divide clock source by 6 0x5 DIV_BY_7 Divide clock source by 7 0x6 DIV_BY_8 Divide clock source by 8 0x7 I2C2_CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DISABLE Does not select this clock as a source 0x0 ENABLE Select this clock as a source 0x1 I2C2_PDBGCTL Peripheral Debug Control 0x1018 32 read-write FREE Free run control 0x0 0x1 read-write STOP The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 0x0 RUN The peripheral ignores the state of the Core Halted input 0x1 SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write IMMEDIATE The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 0x0 DELAYED The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption 0x1 1 44 0 I2C2_CPU_INT[%s] 0x1020 I2C2_CPU_INT_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXDONEFG Controller data received 0x1 CTXDONEFG Controller data transmitted 0x2 CRXFIFOTRG Controller receive FIFO Trigger Level 0x3 CTXFIFOTRG Controller transmit FIFO Trigger level 0x4 CRXFIFOFULL RX FIFO FULL Event/interrupt pending 0x5 CTX_EMPTY Transmit FIFO/Buffer Empty Event/interrupt pending 0x6 CNACKFG Address/Data NACK 0x8 CSTARTFG Start Event 0x9 CSTOPFG Stop Event 0xA CARBLOSTFG Arbitration Lost 0xB CDMA_DONE_TX DMA DONE on Channel TX 0xC CDMA_DONE_RX DMA DONE on Channel RX 0xD CPEC_RX_ERR Controller PEC Receive Error Event 0xE TIMEOUTA Timeout A Event 0xF TIMEOUTB Timeout B Event 0x10 TRXDONEFG Target Data Event 0x11 TTXDONEFG Target Data Event 0x12 TRXFIFOTRG Target receive FIFO Trigger Level 0x13 TTXFIFOTRG Target transmit FIFO Trigger level 0x14 TRXFIFOFULL RX FIFO FULL Event/interrupt pending 0x15 TTXEMPTY Transmit FIFO/Buffer Empty Event/interrupt pending 0x16 TSTARTFG Start Event 0x17 TSTOPFG Stop Event 0x18 TGENCALL General Call Event 0x19 TDMA_DONE_TX DMA DONE on Channel TX 0x1A TDMA_DONE_RX DMA DONE on Channel RX 0x1B TPEC_RX_ERR Target PEC receive error event 0x1C TTX_UNFL Target TX FIFO underflow 0x1D TRX_OVFL Target RX FIFO overflow event 0x1E TARBLOST Target arbitration lost event 0x1F INTR_OVFL Interrupt overflow event 0x20 I2C2_CPU_INT_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXDONE Controller Receive Transaction completed Interrupt 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Set Interrupt Mask 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXEMPTY Target Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an Target RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TSTART Start Condition Interrupt 0x16 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TDMA_DONE_TX Target DMA Done on Event Channel TX 0x19 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TDMA_DONE_RX Target DMA Done on Event Channel RX 0x1A 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Clear Set Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 INTR_OVFL Interrupt Overflow Interrupt Mask 0x1F 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_CPU_INT_RIS Raw interrupt status 0x10 32 read-only CRXDONE Controller Receive Transaction completed Interrupt 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TSTART Start Condition Interrupt 0x16 0x1 CLR Clear interrupt 0x0 SET Set Interrupt 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 CLR Clear Interrupt 0x0 SET Set interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 CLR Clear interrupt 0x0 SET Set interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 CLR Clear interrupt 0x0 SET Set interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Interrupt did not occur 0x0 SET Interrupt Occured 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Interrupt did not occur 0x0 SET Interrupt ocuured 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Interrupt did not occur 0x0 SET Interrupt Occured 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 INTR_OVFL Interrupt overflow interrupt It is set when CSTART or CSTOP interrupts overflow i.e. occur twice without being serviced 0x1F 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 I2C2_CPU_INT_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXDONE Controller Receive Data Interrupt 0x0 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TIMEOUTA Timeout A Interrupt 0xE 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTART START Detection Interrupt 0x8 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOFULL RXFIFO full event. This interrupt is set if the RX FIFO is full. 0x4 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 CLR Interrupt disabled 0x0 SET Interrupt occured 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TGENCALL General Call Interrupt 0x18 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 CLR Clear Interrupt Mask 0x0 SET Interrupt occured 0x1 TSTART Target START Detection Interrupt 0x16 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TSTOP Target STOP Detection Interrupt 0x17 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 CLR Clear MIS 0x0 SET Set MIS 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 CLR Clear interrupt mask 0x0 SET Set interrupt mask 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 CLR Interrupt did not occur 0x0 SET Interrupt occured 0x1 I2C2_CPU_INT_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXDONE Controller Receive Data Interrupt Signals that a byte has been received 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TIMEOUTA Timeout A interrupt 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CSTART START Detection Interrupt 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CRXFIFOFULL RXFIFO full event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 NO_EFFECT Interrupt disabled 0x0 SET Set Interrupt 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TGENCALL General Call Interrupt 0x18 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set Interrupt 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt 0x1 TSTART Start Condition Interrupt 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TSTOP Stop Condition Interrupt 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 NO_EFFECT Writing 0 has no effect 0x0 SET Set interrupt 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 NO_EFFECT No effect 0x0 SET Set interrupt 0x1 I2C2_CPU_INT_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXDONE Controller Receive Data Interrupt Signals that a byte has been received 0x0 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TIMEOUTA Timeout A interrupt 0xE 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CNACK Address/Data NACK Interrupt 0x7 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CSTART START Detection Interrupt 0x8 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CSTOP STOP Detection Interrupt 0x9 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CARBLOST Arbitration Lost Interrupt 0xA 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTXDONE Controller Transmit Transaction completed Interrupt 0x1 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CRXFIFOFULL RXFIFO full event. 0x4 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 CDMA_DONE_TX DMA Done on Event Channel TX 0xB 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 CDMA_DONE_RX DMA Done on Event Channel RX 0xC 0x1 NO_EFFECT Interrupt disabled 0x0 CLR Clear Interrupt 0x1 TRXDONE Target Receive Data Interrupt Signals that a byte has been received 0x10 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTXDONE Target Transmit Transaction completed Interrupt 0x11 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TGENCALL General Call Interrupt 0x18 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x12 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x13 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Clear Interrupt 0x1 TSTART Target START Detection Interrupt 0x16 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TSTOP Target STOP Detection Interrupt 0x17 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TDMA_DONE_TX DMA Done on Event Channel TX 0x19 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 TDMA_DONE_RX DMA Done on Event Channel RX 0x1A 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear interrupt 0x1 CPEC_RX_ERR Controller RX Pec Error Interrupt 0xD 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TIMEOUTB Timeout B Interrupt 0xF 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TPEC_RX_ERR Target RX Pec Error Interrupt 0x1B 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TTX_UNFL Target TX FIFO underflow 0x1C 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TRX_OVFL Target RX FIFO overflow 0x1D 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 TARBLOST Target Arbitration Lost 0x1E 0x1 NO_EFFECT Writing 0 has no effect 0x0 CLR Clear Interrupt 0x1 INTR_OVFL Interrupt overflow 0x1F 0x1 NO_EFFECT No effect 0x0 CLR Clear interrupt 0x1 1 44 0 I2C2_DMA_TRIG1[%s] 0x1050 I2C2_DMA_TRIG1_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXFIFOTRG Controller receive FIFO Trigger Level 0x1 CTXFIFOTRG Controller transmit FIFO Trigger level 0x2 TRXFIFOTRG Target receive FIFO Trigger Level 0x3 TTXFIFOTRG Target transmit FIFO Trigger level 0x4 I2C2_DMA_TRIG1_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_DMA_TRIG1_RIS Raw interrupt status 0x10 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_DMA_TRIG1_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_DMA_TRIG1_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_DMA_TRIG1_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 1 44 0 I2C2_DMA_TRIG0[%s] 0x1080 I2C2_DMA_TRIG0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only NO_INTR No interrupt pending 0x0 CRXFIFOTRG Controller receive FIFO Trigger Level 0x1 CTXFIFOTRG Controller transmit FIFO Trigger level 0x2 TRXFIFOTRG Target receive FIFO Trigger Level 0x3 TTXFIFOTRG Target transmit FIFO Trigger level 0x4 I2C2_DMA_TRIG0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_DMA_TRIG0_RIS Raw interrupt status 0x10 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_DMA_TRIG0_MIS Masked interrupt status 0x18 32 read-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 CLR Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_DMA_TRIG0_ISET Interrupt set 0x20 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 SET Set Interrupt Mask 0x1 I2C2_DMA_TRIG0_ICLR Interrupt clear 0x28 32 write-only 0x00000000 CRXFIFOTRG Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 CTXFIFOTRG Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TRXFIFOTRG Target Receive FIFO Trigger 0x2 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 TTXFIFOTRG Target Transmit FIFO Trigger 0x3 0x1 NO_EFFECT Clear Interrupt Mask 0x0 CLR Set Interrupt Mask 0x1 I2C2_EVT_MODE Event Mode 0x10E0 32 read-write INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.CPU_INT] 0x0 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG1] 0x2 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG0] 0x4 0x2 read-only DISABLE The interrupt or event line is disabled. 0x0 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS. 0x1 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. 0x2 I2C2_INTCTL Interrupt control register 0x10E4 32 read-write INTEVAL Writing a 1 to this field re-evaluates the interrupt sources. 0x0 0x1 write-only DISABLE The interrupt or event line is disabled. 0x0 EVAL The interrupt or event line is in software mode. Software must clear the RIS. 0x1 I2C2_DESC Module Description 0x10FC 32 read-only MINREV Minor rev of the IP 0x0 0x4 MAJREV Major rev of the IP 0x4 0x4 INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 FEATUREVER Feature Set for the module *instance* 0xC 0x4 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 I2C2_GFCTL I2C Glitch Filter Control 0x1200 32 read-write AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only) 0x9 0x2 read-write AGLIT_5 Pulses shorter then 5ns length are filtered. 0x0 AGLIT_10 Pulses shorter then 10ns length are filtered. 0x1 AGLIT_25 Pulses shorter then 25ns length are filtered. 0x2 AGLIT_50 Pulses shorter then 50ns length are filtered. 0x3 DGFSEL Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only) 0x0 0x3 read-write DISABLED Bypass 0x0 CLK_1 1 clock 0x1 CLK_2 2 clocks 0x2 CLK_3 3 clocks 0x3 CLK_4 4 clocks 0x4 CLK_8 8 clocks 0x5 CLK_16 16 clocks 0x6 CLK_31 31 clocks 0x7 AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write DISABLE Analog Glitch Filter disable 0x0 ENABLE Analog Glitch Filter enable 0x1 CHAIN Analog and digital noise filters chaining enable. 0xB 0x1 DISABLE When 0, chaining is disabled and only digital filter output is available to IP logic for oversampling 0x0 ENABLE When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for oversampling 0x1 I2C2_TIMEOUT_CTL I2C Timeout Count Control Register 0x1204 32 read-write 0x00020002 0xffffffff TCNTLA Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us. 0x0 0x8 read-write TCNTAEN Timeout Counter A Enable 0xF 0x1 read-write DISABLE Disable Timeout Counter B 0x0 ENABLE Enable Timeout Counter B 0x1 TCNTLB Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns. 0x10 0x8 read-write TCNTBEN Timeout Counter B Enable 0x1F 0x1 read-write DISABLE Disable Timeout Counter B 0x0 ENABLE Enable Timeout Counter B 0x1 I2C2_TIMEOUT_CNT I2C Timeout Count Register 0x1208 32 read-only 0x00020002 0xffffffff TCNTA Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A 0x0 0x8 read-only TCNTB Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B 0x10 0x8 1 56 0 I2C2_CONTROLLER[%s] 0x1210 I2C2_CSA I2C Controller Target Address Register 0x0 32 read-write 0x00000000 DIR Receive/Send The DIR bit specifies if the next Controller operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive 0x0 0x1 TRANSMIT The Controller is in transmit mode. 0x0 RECEIVE The Controller is in receive mode. 0x1 TADDR I2C Target Address This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care 0x1 0xA CMODE This bit selects the adressing mode to be used in Controller mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 MODE7 7-bit addressing mode 0x0 MODE10 10-bit addressing mode 0x1 I2C2_CCTR I2C Controller Control Register 0x4 32 read-write 0x00000000 0xffffffff BURSTRUN I2C Controller Enable and start transaction 0x0 0x1 read-write DISABLE In standard mode, this encoding means the Controller is unable to transmit or receive data. 0x0 ENABLE The Controller is able to transmit or receive data. 0x1 START Generate START 0x1 0x1 read-write DISABLE The controller does not generate the START condition. 0x0 ENABLE The controller generates the START or repeated START condition. 0x1 STOP Generate STOP 0x2 0x1 read-write DISABLE The controller does not generate the STOP condition. 0x0 ENABLE The controller generates the STOP condition. 0x1 ACK Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. 0x3 0x1 read-write DISABLE The last received data byte of a transaction is not acknowledged automatically by the Controller. 0x0 ENABLE The last received data byte of a transaction is acknowledged automatically by the Controller. 0x1 CBLEN I2C transaction length This field contains the programmed length of bytes of the Transaction. 0x10 0xC read-write CACKOEN Controller ACK overrride Enable 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When 1 and the Controller is receiving data and the number of bytes indicated in MBLEN have been received, the state machine will generate an rxdone interrupt and wait at the start of the ACK for FW to indicate if an ACK or NACK should be sent. The ACK or NACK is selected by writing the MCTR register and setting ACK accordingly. The other fields in this register can also be written at this time to continue on with the transaction. If a NACK is sent the state machine will automatically send a Stop. 0x1 RD_ON_TXEMPTY Read on TX Empty 0x5 0x1 DISABLE No special behavior 0x0 ENABLE When 1 the Controller will transmit all bytes from the TX FIFO before continuing with the programmed Burst Run Read. If the DIR is not set to Read in the MSA then this bit is ignored. The Start must be set in the MCTR for proper I2C protocol. The Controller will first send the Start Condition, I2C Address with R/W bit set to write, before sending the bytes in the TX FIFO. When the TX FIFO is empty, the I2C transaction will continue as programmed in MTCR and MSA without sending a Stop Condition. This is intended to be used to perform simple I2C command based reads transition that will complete after initiating them without having to get an interrupt to turn the bus around. 0x1 I2C2_CSR I2C Controller Status Register 0x8 32 read-only BUSY I2C Controller FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction. 0x0 0x1 read-only CLEARED The controller is idle. 0x0 SET The controller is busy. 0x1 ERR Error The error can be from the Target address not being acknowledged or the transmit data not being acknowledged. 0x1 0x1 read-only CLEARED No error was detected on the last operation. 0x0 SET An error occurred on the last operation. 0x1 ADRACK Acknowledge Address 0x2 0x1 read-only CLEARED The transmitted address was acknowledged 0x0 SET The transmitted address was not acknowledged. 0x1 DATACK Acknowledge Data 0x3 0x1 read-only CLEARED The transmitted data was acknowledged 0x0 SET The transmitted data was not acknowledged. 0x1 ARBLST Arbitration Lost 0x4 0x1 read-only CLEARED The I2C controller won arbitration. 0x0 SET The I2C controller lost arbitration. 0x1 IDLE I2C Idle 0x5 0x1 read-only CLEARED The I2C controller is not idle. 0x0 SET The I2C controller is idle. 0x1 BUSBSY I2C Bus is Busy Controller State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0x6 0x1 read-only CLEARED The I2C bus is idle. 0x0 SET 'This Status bit is set on a START or when SCL goes low. It is cleared on a STOP, or when a SCL high bus busy timeout occurs and SCL and SDA are both high. This status is cleared when the ACTIVE bit is low. Note that the Controller State Machine will wait until this bit is cleared before starting an I2C transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0x1 CBCNT I2C Controller Transaction Count This field contains the current count-down value of the transaction. 0x10 0xC read-only I2C2_CRXDATA I2C Controller RXData 0xC 32 read-only 0x00000000 0xffffffff VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only I2C2_CTXDATA I2C Controller TXData 0x10 32 read-write 0x00000000 0xffffffff VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write I2C2_CTPR I2C Controller Timer Period 0x14 32 read-write 0x00000001 0xffffffff TPR Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns. 0x0 0x7 read-write I2C2_CCR I2C Controller Configuration 0x18 32 read-write 0x00000000 0xffffffff LPBK I2C Loopback 0x8 0x1 read-write DISABLE Normal operation. 0x0 ENABLE The controller in a test mode loopback configuration. 0x1 MCTL MultiController mode. In MultiController mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller. 0x1 0x1 read-write DISABLE Disable MultiController mode. 0x0 ENABLE Enable MultiController mode. 0x1 ACTIVE Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0x0 0x1 read-write DISABLE Disables the I2C Controller operation. 0x0 ENABLE Enables the I2C Controller operation. 0x1 CLKSTRETCH Clock Stretching. This bit controls the support for clock stretching of the I2C bus. 0x2 0x1 read-write DISABLE Disables the clock stretching detection. This can be disabled if no Target on the bus does support clock stretching, so that the maximum speed on the bus can be reached. 0x0 ENABLE Enables the clock stretching detection. Enabling the clock stretching ensures compliance to the I2C standard but could limit the speed due the clock stretching. 0x1 I2C2_CBMON I2C Controller Bus Monitor 0x24 32 read-only 0x00000003 0xffffffff SCL I2C SCL Status 0x0 0x1 read-only CLEARED The I2CSCL signal is low. 0x0 SET The I2CSCL signal is high. Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations. 0x1 SDA I2C SDA Status 0x1 0x1 read-only CLEARED The I2CSDA signal is low. 0x0 SET The I2CSDA signal is high. Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations. 0x1 I2C2_CFIFOCTL I2C Controller FIFO Control 0x28 32 read-write 0x00000000 TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 EMPTY Trigger when the TX FIFO is empty. 0x0 LEVEL_1 Trigger when TX FIFO contains 1 byte 0x1 LEVEL_2 Trigger when TX FIFO contains 2 byte 0x2 LEVEL_3 Trigger when TX FIFO contains 3 byte 0x3 LEVEL_4 Trigger when TX FIFO contains 4 byte 0x4 LEVEL_5 Trigger when TX FIFO contains 5 byte 0x5 LEVEL_6 Trigger when TX FIFO contains 6 byte 0x6 LEVEL_7 Trigger when TX FIFO contains 7 byte 0x7 TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 LEVEL_1 Trigger when RX FIFO contains >= 1 byte 0x0 LEVEL_2 Trigger when RX FIFO contains >= 2 byte 0x1 LEVEL_3 Trigger when RX FIFO contains >= 3 byte 0x2 LEVEL_4 Trigger when RX FIFO contains >= 4 byte 0x3 LEVEL_5 Trigger when RX FIFO contains >= 5 byte 0x4 LEVEL_6 Trigger when RX FIFO contains >= 6 byte 0x5 LEVEL_7 Trigger when RX FIFO contains >= 7 byte 0x6 LEVEL_8 Trigger when RX FIFO contains >= 8 byte 0x7 RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 I2C2_CFIFOSR I2C Controller FIFO Status Register 0x2C 32 read-only 0x00000800 RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 I2C2_CONTROLLER_I2CPECCTL I2C Controller PEC control register 0x30 32 read-write 0x00000000 0xffffffff PECCNT PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Controller use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Target Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the Controller_I2CPECCTL Register will clear the current PEC Byte Count in the Controller State Machine. 0x0 0x9 PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits except the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 DISABLE PEC is disabled in Controller mode 0x0 ENABLE PEC is enabled in Controller mode 0x1 I2C2_CONTROLLER_PECSR I2C Controller PEC status register 0x34 32 read-only 0x00000000 0xffffffff PECBYTECNT PEC Byte Count This is the current PEC Byte Count of the Controller State Machine. 0x0 0x9 PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 CLEARED Indicates PEC was not checked in the transaction that occurred before the last Stop 0x0 SET Indicates if the PEC was checked in the transaction that occurred before the last Stop 0x1 PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 CLEARED Indicates PEC check error did not occurr in the transaction that occurred before the last Stop 0x0 SET Indicates if a PEC check error occurred in the transaction that occurred before the last Stop 0x1 1 44 0 I2C2_TARGET[%s] 0x1250 I2C2_TOAR I2C Target Own Address 0x0 32 read-write 0x00004000 0xffffffff OAR I2C Target Own Address: This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care 0x0 0xA read-write OAREN I2C Target Own Address Enable 0xE 0x1 DISABLE Disable OAR address 0x0 ENABLE Enable OAR address 0x1 TMODE This bit selects the adressing mode to be used in Target mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 MODE7 Enable 7-bit addressing 0x0 MODE10 Enable 10-bit addressing 0x1 I2C2_TOAR2 I2C Target Own Address 2 0x4 32 read-write 0x00000000 0xffffffff OAR2 I2C Target Own Address 2 This field specifies the alternate OAR2 address. 0x0 0x7 read-write OAR2EN I2C Target Own Address 2 Enable 0x7 0x1 read-write DISABLE The alternate address is disabled. 0x0 ENABLE Enables the use of the alternate address in the OAR2 field. 0x1 OAR2_MASK I2C Target Own Address 2 Mask: This field specifies bits A6 through A0 of the Target address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care. 0x10 0x7 I2C2_TCTR I2C Target Control Register 0x8 32 read-write 0x00000404 0xffffffff ACTIVE Device Active. Setting this bit enables the Target functionality. 0x0 0x1 read-write DISABLE Disables the I2C Target operation. 0x0 ENABLE Enables the I2C Target operation. 0x1 GENCALL General call response enable Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call 0x1 0x1 read-write DISABLE Do not respond to a general call 0x0 ENABLE Respond to a general call 0x1 TCLKSTRETCH Target Clock Stretch Enable 0x2 0x1 DISABLE Target clock stretching is disabled 0x0 ENABLE Target clock stretching is enabled 0x1 TXEMPTY_ON_TREQ Tx Empty Interrupt on TREQ 0x3 0x1 DISABLE When 0, RIS:TTXEMPTY will be set when only the Target TX FIFO is empty. This allows the TTXEMPTY interrupt to be used to indicate that the I2C bus is being clock stretched and that Target TX data is required. 0x0 ENABLE When 1, RIS:TTXEMPTY will be set when the Target State Machine is in the TX_WAIT state which occurs when the TX FIFO is empty AND the I2C transaction is clock stretched waiting for the FIFO to receive data. 0x1 TXTRIG_TXMODE Tx Trigger when Target FSM is in Tx Mode 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When 1, RIS:TXFIFOTRG will be set when the Target TX FIFO has reached the trigger level AND the Target State Machine is in the TXMODE as defined in the SSR register. When cleared RIS:TXFIFOTRG will be set when the Target TX FIFO is at or above the trigger level. This setting can be used to hold off the TX DMA until a transaction starts. This allows the DMA to be configured when the I2C is idle but have it wait till the transaction starts to load the Target TX FIFO, so it can load from a memory buffer that might be changing over time. 0x1 TXWAIT_STALE_TXFIFO Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Target State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale. 0x5 0x1 DISABLE When 0, the TX FIFO empty signal to the Target State Machine indicates that the TX FIFO is empty. 0x0 ENABLE When 1, the TX FIFO empty signal to the Target State Machine will indicate that the TX FIFO is empty or that the TX FIFO data is stale. The TX FIFO data is determined to be stale when there is data in the TX FIFO when the Target State Machine leaves the TXMODE as defined in the SSR register. This can occur is a Stop or timeout occur when there are bytes left in the TX FIFO. 0x1 RXFULL_ON_RREQ Rx full interrupt generated on RREQ condition as indicated in SSR 0x6 0x1 DISABLE When 0, RIS:TRXFULL will be set when only the Target RX FIFO is full. This allows the TRXFULL interrupt to be used to indicate that the I2C bus is being clock stretched and that the FW must either read the RX FIFO or ACK/NACK the current Rx byte. 0x0 ENABLE When 1, RIS:TRXFULL will be set when the Target State Machine is in the RX_WAIT or RX_ACK_WAIT states which occurs when the I2C transaction is clock stretched because the RX FIFO is full or the ACKOEN has been set and the state machine is waiting for FW to ACK/NACK the current byte. 0x1 EN_DEFHOSTADR Enable Default Host Address 0x7 0x1 DISABLE When this bit is 0, the default host address is not matched NOTE: it may still be matched if programmed inside SOAR/SOAR2 0x0 ENABLE When this bit is 1, default host address of 7h000_1000 is always matched by the Target address match logic. 0x1 EN_ALRESPADR Enable Alert Response Address 0x8 0x1 DISABLE When this bit is 0, the alert response address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2 0x0 ENABLE When this bit is 1, alert response address of 7h000_1100 is always matched by the Target address match logic. 0x1 EN_DEFDEVADR Enable Deault device address 0x9 0x1 DISABLE When this bit is 0, the default device address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2. 0x0 ENABLE When this bit is 1, default device address of 7h110_0001 is always matched by the Target address match logic. 0x1 TWUEN Target Wakeup Enable 0xA 0x1 DISABLE When 0, the Target is not allowed to clock stretch on START detection 0x0 ENABLE When 1, the Target is allowed to clock stretch on START detection and wait for faster clock to be abvailable. This allows clean wake up support for I2C in low power mode use cases 0x1 I2C2_TSR I2C Target Status Register 0xC 32 read-only 0x00000000 0xffffffff RREQ Receive Request 0x0 0x1 read-only CLEARED No outstanding receive data. 0x0 SET The I2C controller has outstanding receive data from the I2C Controller and is using clock stretching to delay the Controller until the data has been read from the TRXDATA FIFO (Target RX FIFO is full). 0x1 TREQ Transmit Request 0x1 0x1 read-only CLEARED No outstanding transmit request. 0x0 SET The I2C controller has been addressed as a Target transmitter and is using clock stretching to delay the Controller until data has been written to the TTXDATA FIFO (Target TX FIFO is empty). 0x1 OAR2SEL OAR2 Address Matched This bit gets reevaluated after every address comparison. 0x3 0x1 read-only CLEARED Either the OAR2 address is not matched or the match is in legacy mode. 0x0 SET OAR2 address matched and ACKed by the Target. 0x1 QCMDST Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction 0x4 0x1 read-only CLEARED The last transaction was a normal transaction or a transaction has not occurred. 0x0 SET The last transaction was a Quick Command transaction. 0x1 QCMDRW Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read 0x5 0x1 read-only CLEARED Quick command was a write 0x0 SET Quick command was a read 0x1 RXMODE Target FSM is in Rx MODE 0x2 0x1 CLEARED The Target State Machine is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. 0x0 SET The Target State Machine is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. 0x1 BUSBSY I2C bus is busy 0x6 0x1 CLEARED The I2C Bus is not busy 0x0 SET The I2C Bus is busy. This is cleared on a timeout. 0x1 TXMODE Target FSM is in TX MODE 0x7 0x1 CLEARED The Target State Machine is not in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. 0x0 SET The Target State Machine is in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. 0x1 STALE_TXFIFO Stale Tx FIFO 0x8 0x1 CLEARED Tx FIFO is not stale 0x0 SET The TX FIFO is stale. This occurs when the TX FIFO was not emptied during the previous I2C transaction. 0x1 ADDRMATCH Indicates the address for which Target address match happened 0x9 0xA I2C2_TRXDATA I2C Target RXData 0x10 32 read-only 0x00000000 0xffffffff VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only I2C2_TTXDATA I2C Target TXData 0x14 32 read-write 0x00000000 0xffffffff VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write I2C2_TACKCTL I2C Target ACK Control 0x18 32 read-write 0x00000000 0xffffffff ACKOEN I2C Target ACK Override Enable 0x0 0x1 read-write DISABLE A response in not provided. 0x0 ENABLE An ACK or NACK is sent according to the value written to the ACKOVAL bit. 0x1 ACKOVAL I2C Target ACK Override Value Note: for General Call this bit will be ignored if set to NACK and Target continues to receive data. 0x1 0x1 read-write DISABLE An ACK is sent indicating valid data or command. 0x0 ENABLE A NACK is sent indicating invalid data or command. 0x1 ACKOEN_ON_START When set this bit will automatically turn on the Target ACKOEN field following a Start Condition. 0x2 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following a Start Condition. 0x1 ACKOEN_ON_PECNEXT When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing Target_SACKCTL. 0x3 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing Target_SACKCTL. 0x1 ACKOEN_ON_PECDONE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte. 0x4 0x1 DISABLE No special behavior 0x0 ENABLE When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte. 0x1 I2C2_TFIFOCTL I2C Target FIFO Control 0x1C 32 read-write 0x00000000 TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 LEVEL_4 Trigger when TX FIFO contains 4 byte 0x4 LEVEL_5 Trigger when TX FIFO contains 5 byte 0x5 LEVEL_6 Trigger when TX FIFO contains 6 byte 0x6 LEVEL_7 Trigger when TX FIFO contains 7 byte 0x7 TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 NOFLUSH Do not Flush FIFO 0x0 FLUSH Flush FIFO 0x1 RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 LEVEL_5 Trigger when RX FIFO contains >= 5 byte 0x4 LEVEL_6 Trigger when RX FIFO contains >= 6 byte 0x5 LEVEL_7 Trigger when RX FIFO contains >= 7 byte 0x6 LEVEL_8 Trigger when RX FIFO contains >= 8 byte 0x7 I2C2_TFIFOSR I2C Target FIFO Status Register 0x20 32 read-only 0x00000800 RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 INACTIVE FIFO Flush not active 0x0 ACTIVE FIFO Flush active 0x1 RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 INACTIVE FIFOFlush not active 0x0 ACTIVE FIFO Flush active 0x1 I2C2_TARGET_PECCTL I2C Target PEC control register 0x24 32 read-write 0x00000000 0xffffffff PECCNT When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Target use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction 0x0 0x9 PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits except the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 DISABLE PEC transmission and check is disabled 0x0 ENABLE PEC transmission and check is enabled 0x1 I2C2_TARGET_PECSR I2C Target PEC status register 0x28 32 read-only 0x00000000 0xffffffff PECBYTECNT This is the current PEC Byte Count of the Target State Machine. 0x0 0x9 PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 CLEARED Indicates PEC was not checked in the transaction that occurred before the last Stop 0x0 SET Indicates PEC was checked in the transaction that occurred before the last Stop 0x1 PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 CLEARED Indicates PEC check error did not occurr in the transaction that occurred before the last Stop 0x0 SET Indicates PEC check error occurred in the transaction that occurred before the last Stop 0x1