//###############################################################################
//
// FILE:   cyclone_can.h
//
// TITLE:  Cyclone CAN Interface Register Definitions.
//
// NOTES:
//  1) Bitfields have been defined for big-endian only.
//###############################################################################
//
//  Ver  | dd mmm yyyy | Who  | Description of changes
// ======|=============|======|==============================================
//  1.00 | 19 Aug 2008 | CMF  | Started with Spartan_Pmbus.h.
//       |             |      | Updated for 1.0 Memory map document.
//       |             |      |
//
//  Texas Instruments, Inc
//  Copyright Texas Instruments 2009. All rights reserved.
//###############################################################################

#ifndef CYCLONE_CAN_H
#define CYCLONE_CAN_H

#ifdef __cplusplus
extern "C" {
#endif

  //=============================================================================
  // CAN Interface Individual Register Bit Definitions
  //=============================================================================

  //-----------------------------------------------------------------------------
  // CAN Control Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANCTRL_BITS {             // bits   description
    Uint32 rsvd0:22;                // 31:10  reserved
    Uint32 CONFIG_REQ:1;            // 9      Configuration Mode (0-> Normal Mode, 1-> Config Mode Request)
    Uint32 DATA_BYTE_ORDER:1;       // 8      Mailbox Byte Config(0-> 1st Byte MSB, 1-> 1st Byte LSB)
    Uint32 CHANGE_DATA_REQ:1;       // 7      Allows the CPU to write to the MBOX if high 
    Uint32 AUTO_BUS_MODE:1;         // 6      Auto Bus Mode EN (Prevents tx errors from putting the CAN module into config mode)     
    Uint32 SELF_TEST:1;             // 5      Self Test Mode EN     
    Uint32 CAN_RESET:1;             // 4      CAN Reset (Active High)     
    Uint32 MBOX_NUMBER:4;           // 3:0    MBOX Number for CPU Access      
  };
  union CANCTRL_REG {
    Uint32                   all;
    struct CANCTRL_BITS     bit;
  };
  
  //-----------------------------------------------------------------------------
  // CAN Baud Control Register bit definitions
  // Bits are only writable in Configuration Mode 
  //-----------------------------------------------------------------------------
  struct CANBAUDCTRL_BITS {         // bits   description
    Uint32 rsvd0:8;                 // 31:24  reserved
    Uint32 BAUD_PRESCALER:8;        // 23:16  Configuration Mode (0-> Normal Mode, 1-> Config Mode Request)
    Uint32 rsvd1:5;                 // 15:11  reserved
    Uint32 SYNC_EDGE_SEL:1;         // 10     CAN Bus Timing Edge Sync
    Uint32 SJW:2;                   // 9:8    Sampling counter will be re-locked to a received edge within this time quanta.
    Uint32 MAJ_SAMPLE:1;            // 7      Majority Sampling EN
    Uint32 TSEG1:4;                 // 6:3    Prescaler Ticks in Sampling Section #1
    Uint32 TSEG2:3;                 // 2:0    Prescaler Ticks in Sampling Section #2
  };
  union CANBAUDCTRL_REG {
    Uint32                   all;
    struct CANBAUDCTRL_BITS     bit;
  };

  //-----------------------------------------------------------------------------
  // CAN TX IO Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANTXIOCTRL_BITS {             // bits   description
    Uint32 rsvd0:24;                    // 31:8   reserved
    Uint32 TX_DATA_EN_N_FUNC:1;         // 7      Functional Mode Enable (0->Manual, 1->Functional)
    Uint32 TX_DATA_EN_N_GPIO_DIR:1;     // 6      Pin Direction in GPIO Mode (Input/Output)
    Uint32 TX_DATA_EN_N_GPIO_VAL:1;     // 5      TX Enable_N Pin Output in GPIO Mode 
    Uint32 TX_DATA_EN_N_IN:1;           // 4      TX Enable_N Pin Value
    Uint32 TX_DATA_VAL_FUNC:1;          // 3      Functional Mode Enable (0->Manual, 1->Functional)
    Uint32 TX_DATA_VAL_GPIO_DIR:1;      // 2      Pin Direction in GPIO Mode (Input/Output)
    Uint32 TX_DATA_VAL_GPIO_VAL:1;      // 1      TX Data Pin Output in GPIO Mode 
    Uint32 TX_DATA_VAL_IN:1;            // 0      TX Data Pin Value
  };
  union CANTXIOCTRL_REG {
    Uint32                   all;
    struct CANTXIOCTRL_BITS     bit;
  };


  //-----------------------------------------------------------------------------
  // CAN RX IO Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANRXIOCTRL_BITS {        // bits   description
    Uint32 rsvd0:28;               // 31:4   reserved
    Uint32 RX_DATA_VAL_FUNC:1;         // 3      Functional Mode Enable (0->Manual, 1->Functional)
    Uint32 RX_DATA_VAL_GPIO_DIR:1;     // 2      Pin Direction in GPIO Mode (Input/Output)
    Uint32 RX_DATA_VAL_GPIO_VAL:1;     // 1      RX Data Pin Output in GPIO Mode
    Uint32 RX_DATA_VAL_IN:1;           // 0      Pin Value
  };
  union CANRXIOCTRL_REG {
    Uint32                   all;
    struct CANRXIOCTRL_BITS     bit;
  };
  
  //-----------------------------------------------------------------------------
  // CAN MBOX Enable Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANMBOXEN_BITS {          // bits   description
    Uint32 rsvd0:16;               // 31:16   reserved
    Uint32 MBOX_EN:16;             // 15:0   Mailbox Enable 
  };
  union CANMBOXEN_REG {
    Uint32                all;
    struct CANMBOXEN_BITS    bit;
  };
  
  //-----------------------------------------------------------------------------
  // CAN MBOX DIR Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANMBOXDIR_BITS {         // bits  Description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 MBOX_DIR:16;            // 15:0   Mailbox Direction (0-> Transmit, 1-> Receive)
  };
  union CANMBOXDIR_REG {
    Uint32                 all;
    struct CANMBOXDIR_BITS      bit;
  };

  //-----------------------------------------------------------------------------
  // CAN MBOX Transmit Request Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANTXREQSET_BITS {        // bits   description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 TX_REQ_SET:16;          // 15:0   Mailbox Transmit Request (Self-Clears after TX complete)
  };
  union CANTXREQSET_REG {
    Uint32                  all;
    struct CANTXREQSET_BITS     bit;
  };

  //-----------------------------------------------------------------------------
  // CAN MBOX Transmit Request Reset Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANTXREQRESET_BITS {      // bits   description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 TX_REQ_RESET:16;        // 15:0   Mailbox Transmit Request Reset (Self-Clears after TX resets)
  };
  union CANTXREQRESET_REG {
    Uint32                  all;
    struct CANTXREQRESET_BITS     bit;
  };

  //-----------------------------------------------------------------------------
  // CAN TX ACK Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANTXACK_BITS {           // bits   description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 TX_ACK:16;              // 15:0   Mailbox Transmit ACK (Write 1 to Clear)
  };
  union CANTXACK_REG {
    Uint32                   all;
    struct CANTXACK_BITS     bit;
  };
  
  //-----------------------------------------------------------------------------
  // CAN TX Abort ACK Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANTXABORTACK_BITS {      // bits   description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 ABORT_ACK:16;           // 15:0   Mailbox Transmit Abort ACK (Write 1 to Clear)
  };
  union CANTXABORTACK_REG {
    Uint32                   all;
    struct CANTXABORTACK_BITS     bit;
  };
  
  //-----------------------------------------------------------------------------
  // CAN RX Message Pending Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANRXMSGPEND_BITS {       // bits   description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 RX_MSG_PEND:16;         // 15:0   Mailbox Receive Message Pending (Write 1 to Clear)
  };
  union CANRXMSGPEND_REG {
    Uint32                   all;
    struct CANRXMSGPEND_BITS     bit;
  };

  //-----------------------------------------------------------------------------
  // CAN RX Message Lost Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANRXMSGLOST_BITS {           // bits   description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 RX_MSG_LOST:16;         // 15:0   Mailbox Receive Message Lost Pending (Last MSG overwritten) (Write 1 to Clear)
  };
  union CANRXMSGLOST_REG {
    Uint32                 all;
    struct CANRXMSGLOST_BITS   bit;
  };
  
  //-----------------------------------------------------------------------------
  // CAN Remote Frame Pending Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANREMOTEFRAMEPEND_BITS { // bits   description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 REMOTE_FRAME_PEND:16;   // 15:0   Mailbox Remote Frame Pending (Write 1 to Clear)
  };
  union CANREMOTEFRAMEPEND_REG {
    Uint32                 all;
    struct CANREMOTEFRAMEPEND_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN Over Write Protection Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANOVERWRITEPROT_BITS {   // bits   description
    Uint32 rsvd0:16;               // 31:16  reserved
    Uint32 OVER_WRITE_PROT:16;     // 15:0   Mailbox RX Overwrite protection (RX MSG will not overwrite current data)
  };
  union CANOVERWRITEPROT_REG {
    Uint32                 all;
    struct CANOVERWRITEPROT_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN Mailbox Interrupt Mask Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANMBOXINTENABLE_BITS {    // bits   description
    Uint32 rsvd0:16;              // 31:16  reserved
    Uint32 MBOX_INT_ENABLE:16;      // 15:0   Mailbox Interrupt Mask (0-> Interrupt will not be generated, 1-> Interrupt will be generated)
  };
  union CANMBOXINTENABLE_REG {
    Uint32                 all;
    struct CANMBOXINTENABLE_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN Mailbox Interrupt Level Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANMBOXINTLEVEL_BITS {   // bits   description
    Uint32 rsvd0:16;              // 31:16  reserved
    Uint32 MBOX_INT_LEVEL:16;     // 15:0   Mailbox Interrupt Level
  };
  union CANMBOXINTLEVEL_REG {
    Uint32                 all;
    struct CANMBOXINTLEVEL_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN Status Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANSTAT_BITS {           // bits   description
    Uint32 rsvd0:7;               // 31:25 reserved
    Uint32 FORM_ERROR:1;          // 24   Form Error (Write '1' to Clear)
    Uint32 BIT_ERROR:1;           // 23   Bit Error (Write '1' to Clear)
    Uint32 BIT_STUCK:1;           // 22   Bit Stuck (Write '1' to Clear)
    Uint32 CRC_ERROR:1;           // 21   CRC Error (Write '1' to Clear)
    Uint32 STUFF_ERROR:1;         // 20   STUFF Error (Write '1' to Clear)
    Uint32 ACK_ERROR:1;           // 19   ACK Error (Write '1' to Clear)
    Uint32 BUS_OFF_ERROR:1;       // 18   BUS OFF Error (Write '1' to Clear)
    Uint32 PASSIVE_ERROR:1;       // 17   Passive Error (Write '1' to Clear)
    Uint32 WARNING:1;             // 16   Warning (Write '1' to Clear)
    Uint32 rsvd1:13;              // 15:3  reserved
    Uint32 CONFIG_MODE:1;         // 2    Config Mode Status Flag
    Uint32 RX_EN:1;               // 1    RX Mode Status Flag
    Uint32 TX_EN:1;               // 0    TX Mode Status Flag
  };
  union CANSTAT_REG {
    Uint32                 all;
    struct CANSTAT_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN TX Error Count Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANTXERRCOUNT_BITS {    // bits   description
    Uint32 rsvd0:24;             // 31:8  reserved
    Uint32 TX_ERR_COUNT:8;       // 7:0   Transmit Error Counter (Read-Only)
  };
  union CANTXERRCOUNT_REG {
    Uint32                 all;
    struct CANTXERRCOUNT_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN RX Error Count Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANRXERRCOUNT_BITS {    // bits   description
    Uint32 rsvd0:24;             // 31:8  reserved
    Uint32 RX_ERR_COUNT:8;       // 7:0   Receive Error Counter (Read-Only)
  };
  union CANRXERRCOUNT_REG {
    Uint32                 all;
    struct CANRXERRCOUNT_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN Global Interrupt Mask Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANGLBINTENABLE_BITS {       // bits   description
    Uint32 rsvd0:17;                // 31:15  reserved
    Uint32 CAN_ERRORS_INT_EN:1;     // 14     CAN ERRORS INT EN
    Uint32 ABORT_ACK_INT_EN:1;      // 13     Abort ACK INT EN
    Uint32 RAM_WRITE_INT_EN:1;      // 12     RAM Write INT EN
    Uint32 RX_MSG_LOST_INT_EN:1;    // 11     RX MSG Lost INT EN
    Uint32 BUS_OFF_ERROR_INT_EN:1;  // 10     BUS OFF Error INT EN
    Uint32 PASSIVE_ERROR_INT_EN:1;  // 9      PASSIVE Error INT EN
    Uint32 WARNING_ERROR_INT_EN:1;  // 8      Warning INT EN
    Uint32 rsvd1:5;                 // 7:3    reserved
    Uint32 GLB_INT_LVL:1;           // 2      GLB INT LEVEL
    Uint32 LVL1_INT_EN:1;           // 1      Level 1 Interrupts
    Uint32 LVL0_INT_EN:1;           // 0      Level 0 Interrupts
  };
  union CANGLBINTENABLE_REG {
    Uint32                 all;
    struct CANGLBINTENABLE_BITS   bit;
  };


  //-----------------------------------------------------------------------------
  // CAN Global Interrupt Level Flag Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANGLBINTLVLFLAG_BITS {                // bits   description
    Uint32 rsvd0:17;                             // 31:15  reserved
    Uint32 CAN_ERRORS_INT:1;                     // 14     CAN ERRORS INT
    Uint32 ABORT_ACK_INT:1;                      // 13     Abort ACK INT
    Uint32 RAM_WRITE_INT:1;                      // 12     RAM Write INT
    Uint32 RX_MSG_LOST_INT:1;                    // 11     RX MSG Lost INT
    Uint32 BUS_OFF_ERROR_INT:1;                  // 10     BUS OFF Error INT
    Uint32 PASSIVE_ERROR_INT:1;                  // 9      PASSIVE Error INT
    Uint32 WARNING_ERROR_INT:1;                  // 8      Warning INT
    Uint32 rsvd1:3;                              // 7:5    reserved
    Uint32 MBOX_TX_ACK_OR_RX_MSG_PEND:1;         // 4     Mailbox INT
    Uint32 MBOX_INT_VEC:4;                       // 3:0    Mailbox Interrupt Vector
  };
  union CANGLBINTLVLFLAG_REG {
    Uint32                 all;
    struct CANGLBINTLVLFLAG_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN Address Mask Register bit definitions
  //-----------------------------------------------------------------------------
  struct CANADDRMASK_BITS {                  // bits   description
    Uint32 IDE_MASK:1;                           // 31     IDE Mask
    Uint32 rsvd0:2;                              // 30:29  Reserved
    Uint32 STDID_MASK:11;                        // 28:18  STDID Mask
    Uint32 EXTID_MASK:18;                        // 17:0   EXTID Mask
  };
  union CANADDRMASK_REG {
    Uint32                 all;
    struct CANADDRMASK_BITS   bit;
  };

  //-----------------------------------------------------------------------------
  // CAN Reserved Registers bit definitions
  //-----------------------------------------------------------------------------
  struct CANRSVD_BITS {                  // bits   description
    Uint32 rsvd0:32;                     // 31:0  Reserved
  };
  union CANRSVD_REG {
    Uint32                 all;
    struct CANRSVD_BITS   bit;
  };

  //=============================================================================
  // CAN Interface Register File
  //=============================================================================
  struct CAN_REGS {
    union  CANCTRL_REG                  CANCTRL;
    union  CANBAUDCTRL_REG              CANBAUDCTRL;
    union  CANTXIOCTRL_REG              CANTXIOCTRL;
    union  CANRXIOCTRL_REG              CANRXIOCTRL;
    union  CANMBOXEN_REG                CANMBOXEN;
    union  CANMBOXDIR_REG               CANMBOXDIR;
    union  CANTXREQSET_REG              CANTXREQSET;
    union  CANTXREQRESET_REG            CANTXREQRESET;
    union  CANTXACK_REG                 CANTXACK;
    union  CANTXABORTACK_REG            CANTXABORTACK;
    union  CANRXMSGPEND_REG             CANRXMSGPEND;
    union  CANRXMSGLOST_REG             CANRXMSGLOST;
    union  CANREMOTEFRAMEPEND_REG       CANREMOTEFRAMEPEND;
    union  CANOVERWRITEPROT_REG         CANOVERWRITEPROT;
    union  CANMBOXINTENABLE_REG         CANMBOXINTENABLE;
    union  CANMBOXINTLEVEL_REG          CANMBOXINTLEVEL;
    union  CANSTAT_REG                  CANSTAT;
    union  CANTXERRCOUNT_REG            CANTXERRCOUNT;
    union  CANRXERRCOUNT_REG            CANRXERRCOUNT;
    union  CANGLBINTENABLE_REG          CANGLBINTENABLE;
    union  CANGLBINTLVLFLAG_REG         CANGLBINTLVL0FLAG;
    union  CANGLBINTLVLFLAG_REG         CANGLBINTLVL1FLAG;
    union  CANADDRMASK_REG              CANADDRMASK_0_2;
    union  CANADDRMASK_REG              CANADDRMASK_3_5;
    union  CANADDRMASK_REG              CANADDRMASK_6_15;
    union  CANRSVD_REG                  CANRSVD_0;
    union  CANRSVD_REG                  CANRSVD_1;
    union  CANRSVD_REG                  CANRSVD_2;
    union  CANRSVD_REG                  CANRSVD_3;
  };
  
  //---------------------------------------------------------------------------
  // CAN Interface External References & Function Declarations:
  //
  extern volatile struct CAN_REGS CanRegs;
  
  //===========================================================================
#ifdef __cplusplus
}       // end of extern "C"
#endif

#endif  // end of CYCLONE_CAN_H definition

//===========================================================================
// End of file
//===========================================================================
