# Physical Constraint Data Sheets

This chapter provides detailed descriptions of every physical constraint, grouped by constraint family, as they appear in the Physical worksheet of Constraint Manager. Each data sheet includes the following information about the constraints:

| descriptions, with corresponding property override names

| domain

| tier restrictions

| legal values

| applicable objects

| applicable DRC codes (see Dictionary of DRC Error Marker Codes)

| notes

Note: You can specify Physical constraints on both Xnets and Nets.

|  | You must enable design rule checks individually using the Modes and Options tabs of the Analysis Modes dialog box. See the Analyze - Analysis Modes command in Constraint Manager.

### Negative Plane

#### Negative plane islands

Flags electrically disconnected areas (islands) formed by overlapping thermal reliefs or antipads on a negative layer shape.

#### Negative plane islands oversize

Scales up the pad geometry before the check for Negative plane islands. (Design Options pane)

#### Negative plane sliver

Flags "slivers" or small undesired webs of copper between two objects, usually formed by placing antipads or thermal pads of pins or vias spaced too close to other padstack items or the negative plane boundary.

#### Negative plane sliver spacing

Specifies spacing checks for Negative plane sliver spacing (Design Options pane)

NEGATIVE_PLANE_SLIVER_SPACING

Domain: | Design
Restricted To: | None
Legal Values: | Design units
Applicable Objects: | Design
Applicable DRC Codes: | D - I, N - S
Notes: | Negative Plane Islands

| For Negative plane islands, DRC errors are reported between the shape and pins or vias forming the island.

| For Negative plane islands oversize, enter a value that takes into account inaccuracies that may be introduced in the manufacturing process.

Negative Plane Slivers

| For Negative plane slivers oversize, enter a value that takes into account conducting slivers that are created during the etching process often become detached and may produce shorts on circuit boards.

| Mostly produced on negative plane layers and are caused by antipads and thermal pads of pins and vias spaced too close to the other padstack referencing items or the conducting plane boundary.

### Line Width & Neck Width

| Specify the range of the width of a cline segment.

#### Line Width - Min

The minimum width for the cline segments

MIN_LINE_WIDTH

#### Line Width - Max

The maximum width for the cline segments

MAX_LINE_WIDTH

#### Neck - Min Width

The minimum line width of a cline segment when in neck mode.

MIN_NECK_WIDTH

#### Neck - Max Length

The maximum neck length allowed for neck mode.

MAXIMUM_NECK_LENGTH

Domain: | Physical
Restricted To: | None
Legal Values: | Design units
Applicable Objects: | Design, Net Class, Bus, Diffpair, Xnet, Net, PinPair, Region, Region Class
Applicable DRC Codes: | L - W
Notes: |

| The value for MIN_LINE_WIDTH must be less than the value for MAX_LINE_WIDTH.

| If you enter a value for MAX_LINE_WIDTH that is less than MIN_LINE_WIDTH, a message will be issued indicating the line width values are incompatible.

| These constraints are also used by the Differential Pair DRC. See the Primary data sheet for additional information.

### BB Via Stagger

| Specify the range of the center-to-center distance allowed between the connect point of one pin or blind/buried via (x, y location) and the connect point of the other, where the two pins or blind/buried vias are on the same net and have a single cline connecting them.

#### BB Via Stagger - Min

Specifies the minimum center-to-center distance between the connect point of one pin or via (the x,y location of the pin or via) and the connect point of the other, where the two pins or vias are on the same net and have a single connect line joining them.

MIN_BVIA_STAGGER

#### BB Via Stagger - Max

Specifies the maximum center-to-center distance between the connect point of one pin or blind/buried via (the pin or via's x, y location) and the connect point of the other, where the two pins or vias are on the same net and have a single connect line joining them.

MAX_BVIA_STAGGER

Domain: | Physical
Restricted To: | None
Legal Values: | Design units
Applicable Objects: | Design, Net Class, Bus, Diffpair, Xnet, Net, PinPair, Region, Region Class
Applicable DRC Codes: | V - G
Notes: | None

### Allow - Etch

Specifies whether clines and shapes are allowed on this etch subclass.

ALLOW_ON_ETCH_SUBCLASS

Domain: | Physical
Restricted To: | None
Legal Values: | True, False
Applicable Objects: | Design, Region
Applicable DRC Codes: | S - N
Notes: | The use of Layer Sets is recommended for layer-based routing rules.

### Allow - Ts

Specifies whether T-junctions of cline segments are allowed and where they may form.

TS_ALLOWED

Domain: | Physical
Restricted To: | None
Legal Values: | Anywhere - Specifies that T junctions can form at a pin, via, or on a connect line (cline). Pins Only - Allows T junctions to only form at a pin. The net schedule controls whether T junctions are legal at a pin. Pins Vias Only - Allows T junctions only at a pin or via.

Not Allowed - Prohibits T junctions.

Applicable Objects: | Design, Net Class, Bus, Diffpair, Xnet, Net, PinPair, Region, Region Class
Applicable DRC Codes: | J - N
Notes: | None

### Allow - Pad-Pad Connect

Specifies whether a pin/via whose connect point lies within the extents of another pin/via forms a direct connection without the presence of an intermediate cline.

PAD_PAD_DIRECT_CONNECT

Domain: | Physical
Restricted To: | None
Legal Values: | ALL_ALLOWED - Specifies that direct connections can form anywhere. VIAS_PINS_ONLY - Specifies that only pin-via and pin-microvia direct connections can be formed. VIAS_VIAS_ONLY - Specifies that only via-via and via-microvia direct connections can be formed.

MICROVIAS_MICROVIAS_ONLY - Specifies that only microvia-microvia direct connections can be formed.

MICROVIAS_MICROVIAS_COINCIDENT_ONLY - Specifies that microvia-microvia direct connections can be formed, only if the microvias are co-incident.

NOT_ALLOWED - Prohibits direct connections everywhere.

Applicable Objects: | Design, Net Class, Bus, Diffpair, Xnet, Net, PinPair, Region, Region Class
Applicable DRC Codes: | V - G
Notes: | Use for conditions where one or both of the pads, vias, or microvias that should be overlapping or coincident is a surface mount device pad. For example, this allows symbol surface mount device pads to embed associated fan-outs without the need to draw a connect line.

### Via List

#### Vias

Lists the padstacks in the database of the current design which are allowed for routing.

VIA_LIST

Domain: | Physical
Restricted To: | None
Legal Values: | Padstack names separated by ;
Applicable Objects: | Design, Net Class, Bus, Diffpair, Xnet, Net, PinPair, Region, Region Class
Applicable DRC Codes: | V - N
Notes: |

| The via list is verified by the Vialist DRC. A DRC error is reported if the via is not present in the VIA_LIST property.

| The following items are excluded from the Vialist DRC:

|  | Top and Bottom test vias

|  | Bondfingers

|  | Vias with NODRC_VIALIST property

|  | Vias associated with symbol instances or definitions that contain the NODRC_VIALIST property