# SMD Pin Data Sheets

This chapter provides detailed descriptions of SMD pin constraints. You can access them through the Analysis Modes dialog box of Constraint Manager (choose Analyze -- Analysis Modes).

Each data sheet includes the following information about the constraints:

| Descriptions

| Domain

| Tier restrictions

| Legal values

| Applicable objects

| Applicable DRC codes (see Dictionary of DRC Error Marker Codes)

| Notes

|  | You must enable design rule checks individually using the Modes and Options tabs of the Analysis Modes dialog box. See the Analyze - Analysis Modes command in Constraint Manager.

### Via at SMD pin
#### Via at SMD fit | This constraint is attached to components/component pins, or symbols/symbol pins. Property values are on or off. When on, it specifies that a via is allowed inside an SMD pin, but only if it is completely covered by the pin. When off, just the center of the via needs to be inside the pin. In cases where the property is attached to a symbol, the property is extended to all instances of the symbol. VIA_AT_SMD_FIT
#### Via at SMD thru | This constraint is attached to components/component pins, or symbols/symbol pins. Property values are on or off. When on, it specifies that a through hole via, blind via, or microvia is allowed inside an SMD pin. When off, only partial vias are allowed. In cases where the property is attached to a symbol, the property is extended to all instances of the symbol. VIA_AT_SMD_THRU
Domain: | Same Net Spacing
Restricted To: | None
Legal Values: | Boolean
Applicable Objects: | Symbol Definition, Symbol Instance
Applicable DRC Codes: | F - P, T- P
Notes: | Via at SMD Pin is a toggle that enables the following subordinate constraints
| Via at SMD Fit
| Via at SMD thru
These constraints reflect how via-SMD pin geometry conditions are considered in determining if a DRC error condition exists. Their default state is OFF. #### Via at SMD Fit When the ON state is active, the VIA conducting pin is constrained to lie within or tangent to the internal sides of the SMD PIN conductor pad. When the OFF state is active, a more liberal criterion is employed in determining design errors. In this case, the VIA conductor pin may lie partially outside of the SMD conductor pad geometry, up to the point where the center of the pad contacts the pin conductor boundaries. Note: When a VIA_AT_SMD_FIT property is attached to a symbol (instance or definition) or to a pin, it always overrides the global control state.
Notes (continued) Floating via - Fit ON The via is allowed to float within an SMD pad up to the point where the edge of the via intersects the edge of the pad. Floating via - Fit OFF The via is allowed to bubble outside the edge of a pad up to the point where the center of the via is still inside the pad. | #### Via at SMD Thru When enabled, thru vias--as opposed to blind and buried vias--at SMD pads are marked as errors. Note: When a VIA_AT_SMD_THRU property is attached to a symbol (instance or definition) or to a pin, it always overrides the global control state, where TRUE marks errors at the pad and FALSE instructs error checking to ignore pad/thru via overlaps.

### Etch turn under SMD pin
#### Etch turn under SMD pin | When ON this constraint checks multi-segment bends within a pad boundary. The check is limited to nets containing electrical pin-pair constraints. To suppress the Etch turn under SMD pin DRC on pins or symbols you can set the pin/symbol property ETCH_TURN_UNDER_PAD = FALSE This symbol/pin property suppresses individual Etch turn under SMD pin DRCs when set to FALSE. When this property is set to TRUE it does not suppress the DRC but let you override a FALSE setting on a child object. For example, for a pin the property value is FALSE and for the symbol the value is TRUE. In this case a pin DRC is generated. If this property is attached to a symbol definition, the property is extended to all instances of the symbol. To suppress the Etch turn under SMD pin DRC on SMD pins within nets/Xnets you can set the property ETCH_TURN_UNDER_PAD_EXEMPT = TRUE Note: This setting overrides the pin or symbol property ETCH_TURN_UNDER_PAD = TRUE For checking all SMD pins to be checked for Etch turn under SMD pin constraint you can set the design level property ETCH_TURN_UNDER_ALL_PADS = TRUE
Domain: | Global
Restricted To: | None
Legal Values: | Boolean
Applicable Objects: | Pins
Applicable DRC Codes: | E - P
Notes: | The Etch turns under SMD pin constraint detects etch compensation buried within the pad. Driven by concern that etch segments within pad boundaries adversely affect timing rules, the checker reports if three or more turns exist within the pad boundary. By default, this check only applies to nets with etch length or propagation constraints. Note: The enable state of this constraint is independent of the Via at SMD Pin state. The default mode for this constraint is OFF.