void DRV8x_Analog_Init(void)
{
    /*
     * CTRL2 Register
     * DIR, STEP, SPI_DIR, SPI_STEP, MICROSTEP_MODE [3:0]
     */
    switch (P1IN&0x07) {                    // 1 , 2 , 3
        case 0x00:                          // On, On, On
            SPI_Write(0x05, 0x000A);        // 1/256
            break;
        case 0x01:                          // Off, On, On
            SPI_Write(0x05, 0x0009);        // 1/128
            break;
        case 0x02:                          // On, Off, On
            SPI_Write(0x05, 0x0008);        // 1/64
            break;
        case 0x03:                          // Off, Off, On
            SPI_Write(0x05, 0x0007);        // 1/32
            break;
        case 0x04:                          // On, On, Off
            SPI_Write(0x05, 0x0006);        // 1/16
            break;
        case 0x05:                          // Off, On, Off
            SPI_Write(0x05, 0x0005);        // 1/8
            break;
        case 0x06:                          // On, Off, Off
            SPI_Write(0x05, 0x0004);        // 1/4
            break;
        case 0x07:                          // Off, Off, Off
            SPI_Write(0x05, 0x0003);        // 1/2
            break;
        default:
            SPI_Write(0x05, 0x0003);        // 1/2
            break;
    }
    delay_1ms(1);

    /*
     * CTRL3 Register
     * CLR_FLT, LOCK [2:0] (UL=011b, L=110b), TOCP, OCP_MODE, OTSD_MODE, TW_REP
     */
    SPI_Write(0x06, 0x00B9);
    delay_1ms(1);

    /*
     * CTRL4 Register
     * TBLANK_TIME [1:0], STL_LRN, EN_STL, STL_REP, FRQ_CHG, STEP_FRQ_TOL [1:0]
     */
    SPI_Write(0x07, 0x0004);
    delay_1ms(1);

    /*
     * CTRL5 Register
     * STALL_TH [7:0]
     */
    SPI_Write(0x08, 0x0000);
    delay_1ms(1);

    /*
     * CTRL6 Register
     * RC_RIPPLE [1:0], DIS_SSC, TRQ_SCALE, STALL_TH [11:8]
     */
    SPI_Write(0x09, 0x0000);
    delay_1ms(1);

    /* CTRL7 & CTRL8 are read only*/

    /*
     * CTRL9 Register
     * EN_OL, OL_MODE, OL_T [1:0], STEP_EDGE, RES_AUTO [1:0], EN_AUTO
     */
    SPI_Write(0x0C, 0x0001);        // Enable auto-resolution 1/256
    delay_1ms(1);


    uint8_t fs_curr_setting = ((P1IN&BIT5)>>5) + (P2IN&(BIT1|BIT2));
    uint16_t TRQ_DAC_SET = 0;
    // TRQ_DAC = 25.6 * I_FS
    switch (fs_curr_setting) {              // 6 , 7 , 8
        case 0x00:                          // On, On, On
            TRQ_DAC_SET = 0x008F;           // 5.6 A
            break;
        case 0x01:                          // Off, On, On
            TRQ_DAC_SET = 0x007D;        // 4.9 A
            break;
        case 0x02:                          // On, Off, On
            TRQ_DAC_SET = 0x006E;        // 4.3 A
            break;
        case 0x03:                          // Off, Off, On
            TRQ_DAC_SET = 0x0061;        // 3.8 A
            break;
        case 0x04:                          // On, On, Off
            TRQ_DAC_SET = 0x0052;        // 3.2 A
            break;
        case 0x05:                          // Off, On, Off
            TRQ_DAC_SET = 0x0045;        // 2.7 A
            break;
        case 0x06:                          // On, Off, Off
            TRQ_DAC_SET = 0x0036;        // 2.1 A
            break;
        case 0x07:                          // Off, Off, Off
            TRQ_DAC_SET = 0x0024;        // 1.4 A
            break;
        default:
            TRQ_DAC_SET = 0x0024;        // 1.4 A
            break;
    }
    
    /*
     * CTRL10 Register
     * ISTSL [7:0],
     * Default = 10000000b = 128/256 x 100%
     */
   SPI_Write(0x0D, TRQ_DAC_SET>>1);     // I_HOLD = 10 * (X/256)
   delay_1ms(1);

    /*
     * CTRL11 Register
     * TRQ_DAC [7:0]
     */
    SPI_Write(0x0E, TRQ_DAC_SET);
    delay_1ms(1);

    /*
     * CTRL12 Register
     * EN_STSL, TSTSL_FALL [3:0], RSVD
     */
    if(P1IN&BIT3)
        SPI_Write(0x0F, 0x0000);        // Disable I_Hold current
    else
        SPI_Write(0x0F, 0x00F8);        // Enable I_Hold current
    delay_1ms(1);

    /*
     * CTRL13 Register
     * TSTSL_DLY [5:0], VREF_INT_EN, RSVD
     */
    SPI_Write(0x10, 0x00FE);
    delay_1ms(1);

    /*
     * CTRL14 Register
     * VM_ADC [4:0], RSVD
     * Read Only
     */

    /*
     * SS_CTRL1 Register
     * SS_SMPL_SEL [7:6], RSVD [5:4], SS_PWM_FREQ [3:2], RSVD, EN_SS
     */

     // (20.10.2025) SILENT STEP REVIZYON - BARIS **********
    if(P1IN&BIT4)
        SPI_Write(0x31, 0x0000);        // Disable Silent Step Mode 
    else
        SPI_Write(0x31, 0x0001);        // Enable Silent Step Mode //SILENT STEP OPENING MANUEL
    delay_1ms(1);

    /*
     * SS_CTRL2 Register
     * RSVD, SS_KP [6:0]
     */
    SPI_Write(0x32, 0x5B);
    delay_1ms(1);

    /*
     * SS_CTRL3 Register
     * RSVD, SS_KI [6:0]
     */
    SPI_Write(0x33, 0x01);
    delay_1ms(1);

    /*
     * SS_CTRL4 Register
     * RSVD, SS_KI_DIV_SEL [6:4], RSVD, SS_KP_DIV_SEL [2:0]
     */
    SPI_Write(0x34, 0x11);
    delay_1ms(1);

    /*
     * SS_CTRL5 Register
     * SS_THR [7:0]
     */
    SPI_Write(0x35, 0xFF);
    delay_1ms(1);

    // (20.10.2025) SILENT STEP REVIZYON - BARIS **********

    /*
     * AUTO-TOURQUE Settings Section
     */
     
    switch (flashBuffer[0]) {
        case ATQ_LRN_STATE_DONE:                // All settings are done, enable auto-torque
        case ATQ_LRN_STATE_CONSTS:              // Only CONST1 and CONST2 are known
            SPI_Write(0x20, flashBuffer[ATQ_LRN_CONST1_ADDRESS_H]);
            SPI_Write(0x21, flashBuffer[ATQ_LRN_CONST1_ADDRESS_L]);
            SPI_Write(0x22, flashBuffer[ATQ_LRN_CONST2_ADDRESS_H]);
            SPI_Write(0x23, flashBuffer[ATQ_LRN_CONST2_ADDRESS_L]);
            SPI_Write(0x2D, flashBuffer[ATQ_ERR_TURNC_LRN_STEP_ADDRESS]);
            break;
        default:
            break;
    }
    
    /*
     * CTRL1 Register
     * EN_OUT, SR (rise/fall time), IDX_RST, TOFF1:0, DECAY2:0
     */
    SPI_Write(0x04, 0x00C7);
    delay_1ms(1);
}