# First power down the outputs changing R51 0x00333e & 0x00003e # APLL1/DPLL1 Registers R90 0x005a03 R91 0x005b03 R92 0x005c33 R93 0x005d0f R94 0x005e17 R95 0x005f05 R102 0x006600 R103 0x006732 R104 0x006800 R105 0x006900 R106 0x006a00 R107 0x006b00 R108 0x006c00 R109 0x006d03 R110 0x006e00 R111 0x006f01 R112 0x007000 R113 0x007100 R114 0x007200 R115 0x007300 R116 0x007400 R117 0x007500 R118 0x0076ff R119 0x0077ff R120 0x0078ff R121 0x0079ff R122 0x007aff R123 0x007b02 R124 0x007c02 R125 0x007d00 R126 0x007e01 R127 0x007f01 R128 0x008077 R158 0x009e03 R159 0x009f0d R160 0x00a029 R295 0x012700 R296 0x012803 R302 0x012e2f R303 0x012f0a R304 0x013000 R305 0x013100 R306 0x013200 R307 0x013301 R308 0x013400 R309 0x013500 R310 0x013600 R311 0x013700 R312 0x013800 R313 0x013900 R314 0x013a00 R315 0x013b00 R316 0x013c00 R317 0x013d00 R318 0x013e06 R319 0x013f8b R320 0x014000 R321 0x014100 R322 0x014200 R323 0x014361 R324 0x0144a8 R325 0x0145a0 R326 0x014604 R327 0x014700 R328 0x014803 R329 0x014984 R330 0x014a00 R331 0x014b00 R332 0x014c00 R333 0x014d1c R334 0x014e00 R335 0x014f00 R336 0x015002 R337 0x015100 R338 0x015200 R339 0x015301 R340 0x015400 R341 0x015500 R342 0x015600 R343 0x015700 R344 0x015800 R345 0x0159e0 R346 0x015a00 R347 0x015ba1 R348 0x015c03 R349 0x015d01 R350 0x015e09 R351 0x015f01 R352 0x016000 R353 0x01612c R354 0x01620f R355 0x016302 R356 0x016406 R357 0x016501 R358 0x016600 R359 0x01670e R360 0x016818 R361 0x016902 R362 0x016a0f R363 0x016b04 R364 0x016c35 R365 0x016d17 R366 0x016e4b R367 0x016f4b R368 0x01704b R369 0x01714b R370 0x01724b R371 0x01734b R372 0x0174ff R373 0x0175ff R374 0x0176ff R375 0x0177ff R376 0x0178ff R377 0x017924 R378 0x017a00 R379 0x017b64 R380 0x017c00 R381 0x017d00 R382 0x017e00 R383 0x017f01 R384 0x018005 R385 0x0181f5 R386 0x0182e1 R387 0x018300 R388 0x018400 R389 0x01856e R390 0x018600 R391 0x018700 R392 0x018800 R393 0x018901 R394 0x018a05 R395 0x018bf5 R396 0x018ce1 R397 0x018d00 R398 0x018e00 R399 0x018f00 R400 0x019000 R401 0x019100 R402 0x019200 R403 0x019300 R404 0x019402 R405 0x019500 R406 0x019600 R407 0x019700 R408 0x01988c R409 0x019950 R410 0x019a02 R411 0x019b03 R412 0x019c37 R413 0x019d00 R414 0x019e00 R415 0x019f0d R416 0x01a00f R417 0x01a102 R418 0x01a208 R419 0x01a30b R420 0x01a409 R421 0x01a508 R422 0x01a608 R423 0x01a701 R424 0x01a875 R425 0x01a900 R426 0x01aa00 R427 0x01ab10 R428 0x01ac0d R429 0x01ad01 R430 0x01ae07 R431 0x01af00 R432 0x01b000 R433 0x01b100 R434 0x01b20d R435 0x01b355 R436 0x01b455 R437 0x01b555 R438 0x01b655 R439 0x01b755 R440 0x01b824 R594 0x025200 R595 0x025300 R596 0x025400 R597 0x025500 R598 0x025600 R599 0x025700 R600 0x025800 R601 0x025900 R602 0x025a2c R603 0x025bc4 R604 0x025c55 R605 0x025d4c R606 0x025e49 R607 0x025f49 R608 0x026082 R609 0x02612d R626 0x027200 R627 0x027300 R628 0x027400 R629 0x027500 R630 0x027600 R631 0x027705 R632 0x027801 R633 0x027900 R634 0x027a00 R635 0x027b00 R636 0x027c01 # APLL1/DPLL1 mux Registers # output channel 1 Registers R58 0x003a18 R59 0x003b00 R60 0x003c00 R61 0x003d01 R30 0x001e00 & 0x000000c R51 0x00333e & 0x0000002 R83 0x005300 & 0x0000002 R85 0x005512 & 0x0000038 R88 0x00583f & 0x0000002 # output channel 2 and 3 Registers R64 0x004000 R65 0x004100 R66 0x004201 R51 0x00333e & 0x0000004 R83 0x005300 & 0x0000004 R86 0x005612 & 0x0000007 R88 0x00583f & 0x0000004 # output channel 2 only Registers R62 0x003e18 R30 0x001e00 & 0x0000030 # output channel 3 only Registers R63 0x003f18 R30 0x001e00 & 0x00000c0 # output channel 4 and 5 Registers R69 0x004500 R70 0x004600 R71 0x004778 R51 0x00333e & 0x0000008 R83 0x005300 & 0x0000008 R86 0x005612 & 0x0000038 R88 0x00583f & 0x0000008 # output channel 4 only Registers R67 0x004318 R31 0x001f00 & 0x0000003 # output channel 5 only Registers R68 0x004418 R31 0x001f00 & 0x000000c # output channel 6 Registers R72 0x004818 R73 0x004900 R74 0x004a00 R75 0x004b78 R31 0x001f00 & 0x0000030 R51 0x00333e & 0x0000010 R83 0x005300 & 0x0000010 R87 0x005712 & 0x0000007 R88 0x00583f & 0x0000010 # output channel 7 Registers R76 0x004c18 R77 0x004d00 R78 0x004e00 R79 0x004f00 R80 0x005000 R81 0x005178 R31 0x001f00 & 0x00000c0 R51 0x00333e & 0x0000020 R83 0x005300 & 0x0000020 R87 0x005712 & 0x0000038 R88 0x00583f & 0x0000020 # Other APLL1/DPLL1 Registers R17 0x001100 # LOPL_DPLL1_MASK, LOFL_DPLL1_MASK, HIST1_MASK, HLDOVR1_MASK, REFSWITCH1_MASK, LOR_MISSCLK1_MASK, LOR_FREQ1_MASK, LOR_AMP1_MASK R20 0x001400 # LOPL_DPLL1_POL, LOFL_DPLL1_POL, HIST1_POL, HLDOVR1_POL, REFSWITCH1_POL, LOR_MISSCLK1_POL, LOR_FREQ1_POL, LOR_AMP1_POL R583 0x024700 # DPLL1_FDEV[31:24] R584 0x024800 # DPLL1_FDEV[23:16] R585 0x024900 # DPLL1_FDEV[15:8] R586 0x024a00 # DPLL1_FDEV R16 0x001000 & 0x0000004 # LOL_PLL1_MASK R19 0x001300 & 0x0000004 # LOL_PLL1_POL R50 0x003200 & 0x0000003 # GPIO6_FDEV_EN, GPIO5_FDEV_EN R82 0x00525a & 0x000000f # PLL1_SEC_CH47_SYNC_BNK, PLL1_SEC_CH03_SYNC_BNK, PLL1_PRI_CH47_SYNC_BNK, PLL1_PRI_CH03_SYNC_BNK R176 0x00b009 & 0x000000a # REF_A_DPLL1_EN, REF_B_DPLL1_EN R182 0x00b633 & 0x000000f # MUTE_DPLL1_TCXO, MUTE_DPLL1_PHLOCK, MUTE_DPLL1_LOCK, MUTE_APLL1_LOCK R580 0x024402 & 0x0000007 # DPLL1_DCO_SEL_REF_TCXOB, DPLL1_IGNORE_GPIO_PIN, DPLL1_FDEV_EN R582 0x024600 & 0x000003f # DPLL1_FDEV[37:32] # General Registers R40 0x0028ce # RESERVED R42 0x002abf # RESERVED R170 0x00aa00 # MEMDAR R172 0x00acfe # RAMDAT R174 0x00ae00 # NVMUNLK R184 0x00b8f0 # GPIO_OUT, GPIO6_STAT_POL, GPIO5_STAT_POL, STAT1_POL, STAT0_POL R12 0x000c3b & 0x00000fb # RESET_SW, SYNC_SW, SYNC_AUTO_APLL, SYNC_MUTE, PLLSTRTMODE, AUTOSTRT R16 0x001000 & 0x0000033 # LOS_FDET_TCXO_MASK, LOS_FDET_XO_MASK, LOS_TCXO_MASK, LOS_XO_MASK R19 0x001300 & 0x0000033 # LOS_FDET_TCXO_POL, LOS_FDET_XO_POL, LOS_TCXO_POL, LOS_XO_POL R25 0x001900 & 0x0000003 # INT_AND_OR, INT_EN R32 0x002000 & 0x0000003 # RESERVED R33 0x002105 & 0x000000f # RESERVED R34 0x002205 & 0x000000f # RESERVED, LVL_SEL_XO_DIFF R36 0x002403 & 0x000000f # XO_FDET_BYP, XO_DETECT_BYP, XO_BUFSEL R38 0x002610 & 0x000000f # RESERVED R46 0x002e40 & 0x000007f # STAT0_SEL R47 0x002f41 & 0x000007f # STAT1_SEL R48 0x00304a & 0x000007f # GPIO5_STAT_SEL R49 0x003150 & 0x000007f # GPIO6_STAT_SEL R84 0x005401 & 0x000003f # O_CH4_7_ZERODLY_EN, O_CH0_3_ZERODLY_EN R89 0x005900 & 0x0000003 # REF_BYPASS_MUX R164 0x00a424 & 0x000003f # REF_1P2V_LDO_TRIM, LDO_TRIM R167 0x00a700 & 0x0000010 # RESERVED R169 0x00a900 & 0x000001f # MEMADR[12:8] R175 0x00af00 & 0x000000f # REGCOMMIT_PG R185 0x00b900 & 0x000009f # DPLL_TCXO_MDIV_DBLR, DPLL_TCXO_MDIV R186 0x00ba11 & 0x0000037 # TCXO_DETECT_MODE, TCXO_FDET_BYP, TCXO_DETECT_BYP, TCXO_BUFSEL R187 0x00bb95 & 0x000000f # LVL_SEL_REF1, LVL_SEL_REF0 R188 0x00bc15 & 0x000000f # LVL_SEL_REF3, LVL_SEL_REF2 R205 0x00cd02 & 0x00000f0 # RESERVED R218 0x00da00 & 0x0000001 # SET_HOLD_CLK R678 0x02a640 & 0x00000e0 # RESERVED R736 0x02e000 & 0x0000018 # OCXO_MDIV_STATUS_OUT_SEL # APLL1/DPLL1 Reset R677 0x02a501 & 0x000001 R677 0x02a500 & 0x000001 # Last power up the outputs R51 0x00333e & 0x00003e