# First power down the outputs changing
R51	0x00333f	 &	 0x000001

# APLL2/DPLL2 Registers
R96	0x006002
R97	0x006103
R98	0x006244
R99	0x00630f
R100	0x006417
R101	0x006505
R129	0x008100
R130	0x008239
R131	0x00834a
R132	0x0084aa
R133	0x0085aa
R134	0x0086aa
R135	0x0087ab
R136	0x008803
R137	0x008900
R138	0x008a01
R139	0x008b00
R140	0x008c00
R141	0x008d00
R142	0x008e00
R143	0x008f00
R144	0x009000
R145	0x00914a
R146	0x0092bc
R147	0x0093ae
R148	0x0094a9
R149	0x009580
R150	0x009600
R151	0x009702
R152	0x009800
R153	0x009901
R154	0x009a01
R155	0x009b77
R161	0x00a100
R162	0x00a20d
R163	0x00a329
R300	0x012c00
R301	0x012d03
R441	0x01b92f
R442	0x01ba0a
R443	0x01bb00
R444	0x01bc00
R445	0x01bd00
R446	0x01be01
R447	0x01bf00
R448	0x01c000
R449	0x01c100
R450	0x01c200
R451	0x01c300
R452	0x01c400
R453	0x01c500
R454	0x01c600
R455	0x01c700
R456	0x01c800
R457	0x01c906
R458	0x01ca8b
R459	0x01cb00
R460	0x01cc00
R461	0x01cd00
R462	0x01ce00
R463	0x01cf00
R464	0x01d0b0
R465	0x01d107
R466	0x01d200
R467	0x01d302
R468	0x01d4a9
R469	0x01d500
R470	0x01d600
R471	0x01d700
R472	0x01d81d
R473	0x01d91f
R474	0x01da1d
R475	0x01db00
R476	0x01dc00
R477	0x01dd00
R478	0x01de00
R479	0x01df00
R480	0x01e000
R481	0x01e100
R482	0x01e200
R483	0x01e300
R484	0x01e4a1
R485	0x01e500
R486	0x01e6a0
R487	0x01e700
R488	0x01e820
R489	0x01e909
R490	0x01ea01
R491	0x01eb00
R492	0x01ec2c
R493	0x01ed06
R494	0x01ee02
R495	0x01ef06
R496	0x01f001
R497	0x01f100
R498	0x01f20d
R499	0x01f317
R500	0x01f402
R501	0x01f50f
R502	0x01f603
R503	0x01f7db
R504	0x01f855
R505	0x01f95a
R506	0x01fa5a
R507	0x01fb5a
R508	0x01fc5a
R509	0x01fd5a
R510	0x01fe5a
R511	0x01ffff
R512	0x0200ff
R513	0x0201ff
R514	0x0202ff
R515	0x0203ff
R516	0x020424
R517	0x020500
R518	0x02060a
R519	0x020700
R520	0x020800
R521	0x020900
R522	0x020a01
R523	0x020b06
R524	0x020cd4
R525	0x020d67
R526	0x020e25
R527	0x020f00
R528	0x021014
R529	0x021100
R530	0x021200
R531	0x021300
R532	0x021401
R533	0x021506
R534	0x0216d4
R535	0x021767
R536	0x021825
R537	0x021900
R538	0x021a00
R539	0x021b00
R540	0x021c00
R541	0x021d00
R542	0x021e00
R543	0x021f02
R544	0x022000
R545	0x022104
R546	0x02224c
R547	0x02238f
R548	0x022450
R549	0x022501
R550	0x022602
R551	0x02276f
R552	0x022800
R553	0x022900
R554	0x022a0c
R555	0x022b0d
R556	0x022c04
R557	0x022d08
R558	0x022e0d
R559	0x022f0c
R560	0x023008
R561	0x023108
R562	0x023200
R563	0x023378
R564	0x023400
R565	0x023500
R566	0x023612
R567	0x023710
R568	0x023801
R569	0x023901
R570	0x023a00
R571	0x023b00
R572	0x023c00
R573	0x023d24
R574	0x023eaa
R575	0x023faa
R576	0x0240aa
R577	0x0241aa
R578	0x0242ab
R579	0x024324
R610	0x026245
R611	0x026345
R612	0x026440
R613	0x026500
R614	0x026600
R615	0x026700
R616	0x02686e
R617	0x026900
R618	0x026ac0
R619	0x026b44
R620	0x026c16
R621	0x026d0e
R622	0x026e83
R623	0x026f10
R624	0x02700c
R625	0x027109
R637	0x027d00
R638	0x027e00
R639	0x027f00
R640	0x028000
R641	0x028100
R642	0x028205
R643	0x028301
R644	0x028400
R645	0x028500
R646	0x028600
R647	0x028701

# Input0 Registers
R193	0x00c100
R194	0x00c200
R195	0x00c342
R206	0x00ce00
R207	0x00cf00
R208	0x00d03c
R219	0x00db00
R220	0x00dc6e
R221	0x00dd00
R222	0x00de78
R236	0x00ec00
R237	0x00ed06
R238	0x00ee5b
R239	0x00ef72
R240	0x00f000
R241	0x00f11e
R242	0x00f284
R243	0x00f385
R268	0x010c0e
R272	0x011000
R273	0x011198
R274	0x011296
R275	0x011380
R288	0x01203f

# More Input Registers.  Inputs = [0]
R43	0x002b0f	 &	 0x0000001
R44	0x002c88	 &	 0x000000f
R183	0x00b755	 &	 0x0000003
R189	0x00bd19	 &	 0x000003f
R205	0x00cd02	 &	 0x0000001
R235	0x00eb00	 &	 0x0000003
R292	0x012400	 &	 0x0000007
R297	0x012901	 &	 0x0000007

# APLL2/DPLL2 mux Registers


# output channel 0 Registers
R52	0x00343e
R53	0x003502
R54	0x003600
R55	0x003700
R56	0x003800
R57	0x00396e
R30	0x001e00	 &	 0x0000003
R51	0x00333e	 &	 0x0000001
R83	0x005300	 &	 0x0000001
R85	0x005512	 &	 0x0000007
R88	0x00583f	 &	 0x0000001

# Other APLL2/DPLL2 Registers
R18	0x001200				 # LOPL_DPLL2_MASK, LOFL_DPLL2_MASK, HIST2_MASK, HLDOVR2_MASK, REFSWITCH2_MASK, LOR_MISSCLK2_MASK, LOR_FREQ2_MASK, LOR_AMP2_MASK
R21	0x001500				 # LOPL_DPLL2_POL, LOFL_DPLL2_POL, HIST2_POL, HLDOVR2_POL, REFSWITCH2_POL, LOR_MISSCLK2_POL, LOR_FREQ2_POL, LOR_AMP2_POL
R589	0x024d00				 # DPLL2_FDEV[31:24]
R590	0x024e00				 # DPLL2_FDEV[23:16]
R591	0x024f00				 # DPLL2_FDEV[15:8]
R592	0x02500a				 # DPLL2_FDEV
R16	0x001000	 &	 0x0000008		 # LOL_PLL2_MASK
R19	0x001300	 &	 0x0000008		 # LOL_PLL2_POL
R50	0x003200	 &	 0x00000c0		 # GPIO4_FDEV_EN, GPIO3_FDEV_EN
R19	0x001300	 &	 0x00000f0		 # PLL2_SEC_CH47_SYNC_BNK, PLL2_SEC_CH03_SYNC_BNK, PLL2_PRI_CH47_SYNC_BNK, PLL2_PRI_CH03_SYNC_BNK
R176	0x00b009	 &	 0x0000005		 # REF_A_DPLL2_EN, REF_B_DPLL2_EN
R182	0x00b633	 &	 0x00000f0		 # MUTE_DPLL2_TCXO, MUTE_DPLL2_PHLOCK, MUTE_DPLL2_LOCK, MUTE_APLL2_LOCK
R581	0x024500	 &	 0x0000007		 # DPLL2_DCO_SEL_REF_TCXOB, DPLL2_IGNORE_GPIO_PIN, DPLL2_FDEV_EN
R588	0x024c00	 &	 0x000003f		 # DPLL2_FDEV[37:32]

# General Registers
R40	0x0028ce				 # RESERVED
R42	0x002abf				 # RESERVED
R170	0x00aa00				 # MEMDAR
R172	0x00acfe				 # RAMDAT
R174	0x00ae00				 # NVMUNLK
R184	0x00b8f0				 # GPIO_OUT, GPIO6_STAT_POL, GPIO5_STAT_POL, STAT1_POL, STAT0_POL
R12	0x000c3b	 &	 0x00000fb		 # RESET_SW, SYNC_SW, SYNC_AUTO_APLL, SYNC_MUTE, PLLSTRTMODE, AUTOSTRT
R16	0x001000	 &	 0x0000033		 # LOS_FDET_TCXO_MASK, LOS_FDET_XO_MASK, LOS_TCXO_MASK, LOS_XO_MASK
R19	0x001300	 &	 0x0000033		 # LOS_FDET_TCXO_POL, LOS_FDET_XO_POL, LOS_TCXO_POL, LOS_XO_POL
R25	0x001900	 &	 0x0000003		 # INT_AND_OR, INT_EN
R32	0x002000	 &	 0x0000003		 # RESERVED
R33	0x002105	 &	 0x000000f		 # RESERVED
R34	0x002205	 &	 0x000000f		 # RESERVED, LVL_SEL_XO_DIFF
R36	0x002403	 &	 0x000000f		 # XO_FDET_BYP, XO_DETECT_BYP, XO_BUFSEL
R38	0x002610	 &	 0x000000f		 # RESERVED
R46	0x002e40	 &	 0x000007f		 # STAT0_SEL
R47	0x002f41	 &	 0x000007f		 # STAT1_SEL
R48	0x00304a	 &	 0x000007f		 # GPIO5_STAT_SEL
R49	0x003150	 &	 0x000007f		 # GPIO6_STAT_SEL
R84	0x005401	 &	 0x000003f		 # O_CH4_7_ZERODLY_EN, O_CH0_3_ZERODLY_EN
R89	0x005900	 &	 0x0000003		 # REF_BYPASS_MUX
R164	0x00a424	 &	 0x000003f		 # REF_1P2V_LDO_TRIM, LDO_TRIM
R167	0x00a700	 &	 0x0000010		 # RESERVED
R169	0x00a900	 &	 0x000001f		 # MEMADR[12:8]
R175	0x00af00	 &	 0x000000f		 # REGCOMMIT_PG
R185	0x00b900	 &	 0x000009f		 # DPLL_TCXO_MDIV_DBLR, DPLL_TCXO_MDIV
R186	0x00ba11	 &	 0x0000037		 # TCXO_DETECT_MODE, TCXO_FDET_BYP, TCXO_DETECT_BYP, TCXO_BUFSEL
R187	0x00bb95	 &	 0x000000f		 # LVL_SEL_REF1, LVL_SEL_REF0
R188	0x00bc15	 &	 0x000000f		 # LVL_SEL_REF3, LVL_SEL_REF2
R205	0x00cd02	 &	 0x00000f0		 # RESERVED
R218	0x00da00	 &	 0x0000001		 # SET_HOLD_CLK
R678	0x02a640	 &	 0x00000e0		 # RESERVED
R736	0x02e000	 &	 0x0000018		 # OCXO_MDIV_STATUS_OUT_SEL

# APLL2/DPLL2 Reset
R677	0x02a502	 &	 0x000002
R677	0x02a500	 &	 0x000002

# Last power up the outputs
R51	0x00333e	 &	 0x000001