--R0 (address(4..0) = "00000") - clk_out_0
						register_array(0)(4 downto 0)		<= (others => '0'); -- address
						register_array(0)(31)				<= '0';	-- clk_out_0 - power up
						register_array(0)(30 downto 28)	<= (others => '0');	-- analog delay off
						register_array(0)(27 downto 18)	<= std_logic_vector(to_unsigned(DDLY_0,10)); --(p.56) digital delay 120 VCO clk periods 0-522
						register_array(0)(17)				<= '0';	-- reset turn off
						register_array(0)(16) 				<= '1';	-- digital delay HS0 (Even) - ref to p.38(table 8)
						register_array(0)(15 downto 5)	<= std_logic_vector(to_unsigned(140,11));	-- for clk_out_0 = 17.5MHz (ADC1) (VCO 2450/140) p.58
						--R1 (address(4..0) = "00001") - clk_out_1
						register_array(1)(4 downto 0)		<= std_logic_vector(to_unsigned(1,5)); -- address
						register_array(1)(31) 				<= '0';	-- clk_out_1 - power up
						register_array(1)(30 downto 28)	<= (others => '0');	-- analog delay off
						register_array(1)(27 downto 18) 	<= std_logic_vector(to_unsigned(DDLY_1,10)); --(p.56) digital delay 120 VCO clk periods 0-522
						register_array(1)(17) 				<= '0';	-- powerdown turn off
						register_array(1)(16) 				<= '1';	-- digital delay HS1 - ref to p.38(table 8)
						register_array(1)(15 downto 5)	<= std_logic_vector(to_unsigned(140,11));	-- for clk_out_1 = 17.5MHz (VCO 2450/140) p.58
						--R2 (address(4..0) = "00010") - clk_out_2
						register_array(2)(4 downto 0)		<= std_logic_vector(to_unsigned(2,5)); -- address
						register_array(2)(31) 				<= '0';	-- clk_out_2 - power up because of SYNC_QUAL requirements p.63(Ethernet output clk)
						register_array(2)(30 downto 28)	<= (others => '0');	-- analog delay off
						register_array(2)(27 downto 18) 	<= std_logic_vector(to_unsigned(DDLY_2,10)); --(p.56) digital delay 120 VCO clk periods 0-522
						register_array(2)(17) 				<= '0';	-- must be 0
						register_array(2)(16) 				<= '1';	-- digital delay HS2 - ref to p.38(table 8)
						register_array(2)(15 downto 5)	<= std_logic_vector(to_unsigned(98,11));	-- for clk_out_2 = 25 MHz (VCO 2450/98) p.58
						--R3 (address(4..0) = "00011") - clk_out_3
						register_array(3)(4 downto 0)		<= std_logic_vector(to_unsigned(3,5)); -- address
						register_array(3)(31) 				<= '0';	-- clk_out_3 - power up
						register_array(3)(30) 				<= '1';	-- OSCin source
						register_array(3)(29 downto 28) 	<= (others => '0');	-- analog delay off
						register_array(3)(27 downto 18) 	<= std_logic_vector(to_unsigned(DDLY_3,10)); --(p.56) digital delay 120 VCO clk periods 0-522
						register_array(3)(17) 				<= '0';	-- must be 0
						register_array(3)(16) 				<= '0';	-- digital delay HS3 (DIV Odd) - ref to p.39(table 8)
						register_array(3)(15 downto 5)	<= std_logic_vector(to_unsigned(1,11));	-- for clk_out_3 = 100MHz (OSCin/1) p.58
						--R4 (address(4..0) = "00100") - clk_out_4
						register_array(4)(4 downto 0)		<= std_logic_vector(to_unsigned(4,5)); -- address
						register_array(4)(31) 				<= '0';	-- clk_out_4 - power up
						register_array(4)(30) 				<= '1';	-- OSCin source
						register_array(4)(29 downto 28) 	<= (others => '0');	-- analog delay off
						register_array(4)(27 downto 18) 	<= std_logic_vector(to_unsigned(DDLY_4,10)); --(p.56) digital delay 120 VCO clk periods 0-522
						register_array(4)(17) 				<= '0';	-- must be 0
						register_array(4)(16) 				<= '0';	-- digital delay HS4 (DIV Odd) - ref to p.38(table 8)
						register_array(4)(15 downto 5)	<= std_logic_vector(to_unsigned(1,11));	-- for clk_out_4 = 100MHz (OSCin 100/1) p.58
						--R5 (address(4..0) = "00101") - clk_out_5
						register_array(5)(4 downto 0)		<= std_logic_vector(to_unsigned(5,5)); -- address
						register_array(5)(31) 				<= '1';	-- clk_out_5 - power down
						register_array(5)(30 downto 28) 	<= (others => '0');	-- analog delay off
						register_array(5)(27 downto 18) 	<= std_logic_vector(to_unsigned(120,10)); --(p.56) digital delay 120 VCO clk periods 0-522
						register_array(5)(17) 				<= '0';	-- must be 0
						register_array(5)(16) 				<= '1';	-- digital delay HS5 - ref to p.38(table 8)
						register_array(5)(15 downto 5)	<= std_logic_vector(to_unsigned(50,11));	-- for clk_out_5 (VCO/10) p.58
						--R6 (address(4..0) = "00110")
						register_array(6)(4 downto 0)		<= std_logic_vector(to_unsigned(6,5)); -- address
						register_array(6)(31 downto 28)	<= (others => '0');	-- must be 0
						register_array(6)(27 downto 24)	<= std_logic_vector(to_unsigned(1,4)); --(p.58) clk_out_1 type - LVDS
						register_array(6)(23 downto 20)	<= std_logic_vector(to_unsigned(1,4)); --(p.58) clk_out_0 type - LVDS
						register_array(6)(19 downto 16)	<= (others => '0');	-- must be 0
						register_array(6)(15 downto 11)	<= (others => '0');	-- analog delay clk_out_1 = 500ps + no delay
						register_array(6)(10)				<= '0';					-- must be 0
						register_array(6)(9 downto 5) 	<= (others => '0');	-- analog delay clk_out_0 = 500ps + no delay
						--R7 (address(4..0) = "00111")
						register_array(7)(4 downto 0)		<= std_logic_vector(to_unsigned(7,5)); -- address
						register_array(7)(31 downto 28)	<= (others => '0');	-- must be 0
						register_array(7)(27 downto 24)	<= std_logic_vector(to_unsigned(2,4)); -- clk_out_3 type - LVPECL p.58
						---change----------------
						-- register_array(7)(23 downto 20)	<= std_logic_vector(to_unsigned(8,4));	-- clk_out_2 type - LVCMOS (Norm/Norm) p.58
						register_array(7)(23 downto 20)	<= (others => '0'); -- clk_out_2 type - logic low
						---change----------------
						register_array(7)(19 downto 16)	<= (others => '0');	-- must be 0
						register_array(7)(15 downto 11)	<= (others => '0');	-- analog delay clk_out_3 = 500ps + no delay
						register_array(7)(10)				<= '0';					-- must be 0
						register_array(7)(9 downto 5) 	<= (others => '0');	-- analog delay clk_out_2 = 500ps + no delay
						--R8 (address(4..0) = "01000")
						register_array(8)(4 downto 0)		<= std_logic_vector(to_unsigned(8,5)); -- address
						register_array(8)(31 downto 28) 	<= (others => '0');	-- must be 0
						register_array(8)(27 downto 24)	<= (others => '0');	-- clk_out_5 type - powerdown
						register_array(8)(23 downto 20) 	<= (others => '0');	-- must be 0
						register_array(8)(19 downto 16) 	<= std_logic_vector(to_unsigned(2,4)); --(p.58) clk_out_4 type - LVPECL
						register_array(8)(15 downto 11) 	<= (others => '0');	-- analog delay clk_out_5 = 500ps + no delay
						register_array(8)(10)				<= '0';					-- must be 0
						register_array(8)(9 downto 5) 	<= (others => '0');	-- analog delay clk_out_4 = 500ps + no delay
						--R9 (address(4..0) = "01001")
						register_array(9)(4 downto 0)	<= std_logic_vector(to_unsigned(9,5)); -- address
						register_array(9)(30)	<= '1';
						register_array(9)(28)	<= '1';
						register_array(9)(26)	<= '1';
						register_array(9)(24)	<= '1';
						register_array(9)(22)	<= '1';
						register_array(9)(20)	<= '1';
						register_array(9)(18)	<= '1';
						register_array(9)(16)	<= '1';
						register_array(9)(14)	<= '1';
						register_array(9)(12)	<= '1';
						register_array(9)(10)	<= '1';
						register_array(9)(8)		<= '1';
						register_array(9)(6)		<= '1';
						--R10 (address(4..0) = "01010")
						register_array(10)(4 downto 0)	<= std_logic_vector(to_unsigned(10,5)); -- address
						register_array(10)(31 downto 28) <= std_logic_vector(to_unsigned(1,4)); -- must be 1
						register_array(10)(27 downto 24) <= std_logic_vector(to_unsigned(1,4));	--(p.59) OSC_out type - LVDS
						register_array(10)(23)				<= '0';	-- must be 0
						register_array(10)(22)				<= '1';	-- OSC_out - enable (p.60)
						register_array(10)(21)				<= '0';	-- must be 0
						register_array(10)(20)				<= '0';	-- bypass divider OSC_out (p.60)
						register_array(10)(19)				<= '0';	-- normal operation OSC_out (p.60)
						register_array(10)(18 downto 16)	<= (others =>'0');	-- OSC_out divider = 8(but it was bypassed)
						register_array(10)(15)				<= '0';	-- must be 0
						register_array(10)(14)				<= '1';	-- must be 1
						register_array(10)(13)				<= '0';	-- must be 0
						register_array(10)(12)				<= '0';	-- no divide VCO (p.61)
						register_array(10)(11)				<= '1';	-- must be 1 because of using dinamic digital delay
						register_array(10)(10 downto 8)	<= (others =>'0');	-- VCO devider = 8(but it was bypassed)
						--change---------------- qualifying clock - clk_out_1
						register_array(10)(7 downto 5)	<= std_logic_vector(to_unsigned(1,3)); -- CLK_out_1 is selected as a reference output clock
						--change----------------
						
						--R11 (address(4..0) = "01011")
						register_array(11)(4 downto 0)	<= std_logic_vector(to_unsigned(11,5)); -- address
						register_array(11)(31 downto 27) <= std_logic_vector(to_unsigned(6,5));	-- (p.62) Single PLL mode, internal VCO
						register_array(11)(26)				<= '1';	-- SYNC - enable, required for dinamic d.d. (p.62)
						register_array(11)(25)				<= '1';	-- clk_out_5 will not be synchronized (p.63)
						register_array(11)(24)				<= '1';	-- clk_out_4 will not be synchronized (p.63)
						register_array(11)(23)				<= '1';	-- clk_out_3 will not be synchronized (p.63)
						register_array(11)(22)				<= '1';	-- clk_out_2 will not be synchronized (p.63)
						--change----------------
						register_array(11)(21)				<= '0';--'0';	-- clk_out_1 will be synchronized (p.63)
						register_array(11)(20)				<= '0';--'0';	-- clk_out_0 will be synchronized (p.63)
						--change----------------
						register_array(11)(19 downto 18)	<= (others =>'0');	-- should be logic low (p.63)
						register_array(11)(17)				<= '1';	-- sync_qual - qualification by selected reference clock (clk_out_3)
						register_array(11)(16)				<= '1';	-- SYNC is active low
						register_array(11)(15)				<= '0';	-- SYNC auto off - manual mode
						register_array(11)(14 downto 12) <= std_logic_vector(to_unsigned(0,3));	-- SYNC IO pin type (input)
						register_array(11)(11 downto 6)	<= (others =>'0');	-- must be 0
						register_array(11)(5)				<= '0';	-- XTAL disabled (p.73)
						--R12 (address(4..0) = "01100")
						register_array(12)(4 downto 0)	<= std_logic_vector(to_unsigned(12,5)); -- address
						register_array(12)(31 downto 27)	<= std_logic_vector(to_unsigned(2,5));	-- PLL2 DLD (digital lock detect selection for LD pin)
						register_array(12)(26 downto 24)	<= std_logic_vector(to_unsigned(3,3));	-- status_LD - output type
						register_array(12)(23)				<= '0';	-- turning off as we use SYNC_QUAL = 1
						register_array(12)(22)				<= '0';	-- turning off as we use SYNC_QUAL = 1
						register_array(12)(21 downto 20) <= (others => '0');	-- must be 0
						register_array(12)(19 downto 18) <= "11";	-- must be ones
						register_array(12)(17 downto 9)	<= (others => '0');	-- must be 0
						register_array(12)(8)				<= '0';	-- disable DAC for PLL1 tuning voltage
						register_array(12)(7 downto 6)	<= std_logic_vector(to_unsigned(1,2));	-- holdover disabled (p.67)
						register_array(12)(5)				<= '1';	-- must be 1
						--R13 (address(4..0) = "01101")
						register_array(13)(4 downto 0)	<= std_logic_vector(to_unsigned(13,5)); -- address
						register_array(13)(31 downto 27)	<= std_logic_vector(to_unsigned(4,5));	-- asserting status_HO pin as "holdover status"
						register_array(13)(26 downto 24)	<= std_logic_vector(to_unsigned(3,3));	-- asserting status_HO pin as output
						register_array(13)(23)				<= '0';	-- must be 0
						register_array(13)(22 downto 20)	<= (others => '0');	-- status_CLKin1 - logic low
						register_array(13)(19)				<= '0';	-- must be 0
						register_array(13)(18 downto 16)	<= std_logic_vector(to_unsigned(3,3));	-- asserting status_CLKin0 as output push-pull
						register_array(13)(15)				<= '1';	-- diables the holdover mode from being activated because of PLL1 (p.68)
						register_array(13)(14 downto 12)	<= std_logic_vector(to_unsigned(6,3));	-- status_CLKin0 - uWire readback
						register_array(13)(11 downto 9)	<= (others => '0');	-- Clkin_select - CLKin0
						register_array(13)(8)				<= '0';	-- status_CLKin0/status_CLKin1 is "active high"
						register_array(13)(7 downto 5)	<= (others => '0');	-- CLKin0|1|2 are disabled (p.70)
						--R14 (address(4..0) = "01110")
						register_array(14)(4 downto 0)	<= std_logic_vector(to_unsigned(14,5)); -- address
						register_array(14)(31 downto 30)	<= (others => '0');	-- setting time before loss-of-signal asserts (1200 ns)
						register_array(14)(29)				<= '0';	-- must be 0
						register_array(14)(28)				<= '0';	-- disable LOS detect (because this is for CLKin that we don't use)
						register_array(14)(27)				<= '0';	-- must be 0
						register_array(14)(26 downto 24)	<= std_logic_vector(to_unsigned(3,3));	-- status_CLKin1 type - output push-pull
						register_array(14)(23)				<= '0';	-- must be 0
						register_array(14)(22 downto 20)	<= (others => '0');	--	asserting CLKin buffers to be "Bipolar" for LVDS (p.71)
						register_array(14)(19 downto 14)	<= std_logic_vector(to_unsigned(63,6));	-- high threshold of the voltage at which "Holdover mode" is entered
						register_array(14)(13 downto 12)	<= (others => '0');	-- must be 0
						register_array(14)(11 downto 6)	<= (others => '0');	-- low threshold of the voltage at which "Holdover mode" is entered
						register_array(14)(5)				<= '0';	-- disables entering holdover mode dependency on DAC Vtune
						--R15 (address(4..0) = "01111")
						register_array(15)(4 downto 0)	<= std_logic_vector(to_unsigned(15,5)); -- address
						register_array(15)(31 downto 22)	<= (others => '0');	-- asserting DAC value to 3.2 mV if in manual mode (p.72)
						register_array(15)(21)				<= '0';	-- must be 0
						register_array(15)(20)				<= '1';	-- selection of the DAC manual mode
						register_array(15)(19 downto 6)	<= std_logic_vector(to_unsigned(512,14));	-- clocks before holdover mode (but holdover mode was disabled)
						register_array(15)(5)				<= '0';	-- force holdover - disable
						--R16 (address(4..0) = "10000")
						register_array(16)(4 downto 0)	<= std_logic_vector(to_unsigned(16,5)); -- address
						register_array(16)(31 downto 30)	<= (others => '0');	--	confirm that XTAL lvl is 1.65 Vpp (XTAL was disabled in R11)
						register_array(16)(24)				<= '1';	-- must be 1
						register_array(16)(22)				<= '1';	-- must be 1
						register_array(16)(20)				<= '1';	-- must be 1
						register_array(16)(18)				<= '1';	-- must be 1
						register_array(16)(16)				<= '1';	-- must be 1
						register_array(16)(10)				<= '1';	-- must be 1
						--R24 (address(4..0) = "11000")
						register_array(17)(4 downto 0)	<= std_logic_vector(to_unsigned(24,5));	-- address
						register_array(17)(31 downto 28)	<= std_logic_vector(to_unsigned(0,4));		-- PLL2_C4_LF capacity (p.73)
						register_array(17)(27 downto 24)	<= std_logic_vector(to_unsigned(0,4));		-- PLL2_C3_LF capacity (p.74)
						register_array(17)(23)				<= '0';	-- must be 0
						register_array(17)(22 downto 20)	<= std_logic_vector(to_unsigned(0,3));		-- PLL2_R4_LF resistance
						register_array(17)(19)				<= '0';	-- must be 0
						register_array(17)(18 downto 16)	<= std_logic_vector(to_unsigned(0,3));		-- PLL2_R3_LF resistance
						register_array(17)(15)				<= '0';	-- must be 0
						register_array(17)(14 downto 12)	<= (others => '0');	-- PLL1_N digital delay - 0 ps
						register_array(17)(11)				<= '0';	-- must be 0
						register_array(17)(10 downto 8)	<= (others => '0');	-- PLL1_R digital delay - 0 ps
						register_array(17)(7 downto 6)	<= std_logic_vector(to_unsigned(3,2));	-- window size used for digital lock detect for PLL1 (p.76) 40ns - same as reset value
						register_array(17)(5)				<= '0';	-- must be 0
						--R26 (address(4..0) = "11010")
						register_array(18)(4 downto 0)	<= std_logic_vector(to_unsigned(26,5));	-- address
						register_array(18)(31 downto 30)	<= std_logic_vector(to_unsigned(2,2));		-- window size DLD must be 2
						register_array(18)(29)				<= '0';	-- reference frecuency doubler bypassed (f_OSCin * 1)
						register_array(18)(28)				<= '0';	-- internal VCO requires the negative charge pump polarity to be selected (p.77)
						register_array(18)(27 downto 26)	<= (others => '0');	-- never mind as we are selecting TRI-STATE at PLL2_CP_gain
						register_array(18)(25 downto 23)	<= (others => '1');	-- must be 1
						register_array(18)(22)				<= '0';	-- must be 0
						register_array(18)(21)				<= '1';	-- must be 1
						register_array(18)(20)				<= '0';	-- must be 0
						register_array(18)(19 downto 6)	<= std_logic_vector(to_unsigned(8192,14));	-- Number of PDF cycles which phase error must be within DLD window before LD state is asserted (p.78)
						register_array(18)(5)				<= '0';	-- Enabling PLL2_CP (loop filter)
						--R27 (address(4..0) = "11011")
						register_array(19)(4 downto 0)	<= std_logic_vector(to_unsigned(27,5));	-- address
						register_array(19)(31 downto 29)	<= (others => '0');	-- must be 0
						register_array(19)(28)				<= '1';	-- Many VCXOs use positive slope (p.78)
						register_array(19)(27 downto 26)	<= (others => '0');	-- never mind as we are selecting TRI-STATE at PLL1_CP_gain
						register_array(19)(25 downto 20)	<= (others => '0');	-- pre divider CLKinX = 1
						register_array(19)(19 downto 6)	<= std_logic_vector(to_unsigned(96,14));	-- PLL1 divider (p.79)
						register_array(19)(5)				<= '1';	-- Entering TRI-STATE at PLL1_CP (loop filter)
						--R28 (address(4..0) = "11100")
						register_array(20)(4 downto 0)	<= std_logic_vector(to_unsigned(28,5));	-- address
						register_array(20)(31 downto 20)	<= std_logic_vector(to_unsigned(2,12));	-- PLL2_R = 2 - reference frecuency will be 50MHz (OSCin/2)
						register_array(20)(19 downto 6)	<= std_logic_vector(to_unsigned(50,14));	-- PLL1 N devider
						register_array(20)(5)				<= '0';	-- must be 0
						--R29 (address(4..0) = "11101")
						register_array(21)(4 downto 0)	<= std_logic_vector(to_unsigned(29,5));	-- address
						register_array(21)(31 downto 27)	<= (others => '0');	-- must be 0
						register_array(21)(26 downto 24)	<= "001";	-- OSCin freq >63 to 127 MHz (100MHz)
						register_array(21)(23)				<= '0';	-- phase detector frecuency <= 100MHz
						register_array(21)(22 downto 5)	<= std_logic_vector(to_unsigned(7,18));	-- PLL2_N_cal = PLL2_N = 7 (to reach PDF = 50MHz)
						--R30 (address(4..0) = "11110")
						register_array(22)(4 downto 0)	<= std_logic_vector(to_unsigned(30,5));	-- address
						register_array(22)(31 downto 27)	<= (others => '0');	-- must be 0
						register_array(22)(26 downto 24)	<= std_logic_vector(to_unsigned(7,3));	-- PLL2_P (prescale divider) = 7
						register_array(22)(23)				<= '0';	-- must be 0
						register_array(22)(22 downto 5)	<= std_logic_vector(to_unsigned(7,18));	-- PLL2_N = PLL2_N_cal = 7 (to reach PDF = 50MHz)
						--R31 (address(4..0) = "11111")
						register_array(23)(4 downto 0)	<= std_logic_vector(to_unsigned(31,5));	-- address
						register_array(23)(31 downto 22)	<= (others => '0');	-- must be 0
						register_array(23)(21)				<= '0';	-- LEuWire must be low for readback
						register_array(23)(20 downto 16) <= std_logic_vector(to_unsigned(readback_addr,5));
						register_array(23)(15 downto 6)	<= (others => '0');	-- must be 0
						register_array(23)(5)				<= uWire_lock;	-- 1: R0-R30 locked| 0: R0-R30 unlocked