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[FLEX]
btnScan_I2C=Scan I2C
st_save_info=0
st_save_vco_listboxes={'VCO2_selected_index': 0, 'VCO1_selected_index': 0, 'VCO3_selected_index': 0, 'VCO1_choices': [Fraction(4900, 1), Fraction(5000, 1), Fraction(5100, 1), Fraction(5200, 1), Fraction(4800, 1)], 'VCO2_choices': [Fraction(5600, 1), Fraction(5700, 1), Fraction(5800, 1)], 'VCO3_choices': [Fraction(2500, 1)]}
LOW_POWER_DISABLE_MODE=1
MATLAB_RUNTIME_DOWNLOAD_URL=https://www.mathworks.com/products/compiler/matlab-runtime.html
bGotoStartupPage=Goto Start Page
ck_advanced_options=0
ck_enable_output_autoset=1
ck_ignore_SPI_comm_errors=0
APLL1_REF_FREQ=48.0
APLL2_REF_FREQ=1250.0
APLL3_REF_FREQ=48.0
DPLL1_FL1_EXP_ud=14
DPLL1_FL1_MANT_ud=17
DPLL1_FL2_EXP_ud=19
DPLL1_FL2_MANT_ud=3
DPLL1_LCK_EXP_ud=9
DPLL1_LCK_MANT_ud=24
DPLL2_FL1_EXP_ud=13
DPLL2_FL1_MANT_ud=21
DPLL2_FL2_EXP_ud=15
DPLL2_FL2_MANT_ud=31
DPLL2_LCK_EXP_ud=9
DPLL2_LCK_MANT_ud=24
DPLL3_FL1_EXP_ud=15
DPLL3_FL1_MANT_ud=11
DPLL3_FL2_EXP_ud=14
DPLL3_FL2_MANT_ud=31
DPLL3_LCK_EXP_ud=12
DPLL3_LCK_MANT_ud=24
MAX_TDC1=26
MAX_TDC2=26
MAX_TDC3=1
OUT0_FREQ=25.0
OUT0_TARGET_FREQ=25.0
OUT10_FREQ=250.0
OUT10_TARGET_FREQ=250.0
OUT11_FREQ=250.0
OUT11_TARGET_FREQ=250.0
OUT12_FREQ=250.0
OUT12_TARGET_FREQ=250.0
OUT13_FREQ=250.0
OUT13_TARGET_FREQ=250.0
OUT14_FREQ=500.0
OUT14_TARGET_FREQ=500.0
OUT15_FREQ=156.25
OUT15_TARGET_FREQ=156.25
OUT1_FREQ=100.0
OUT1_TARGET_FREQ=100.0
OUT2_FREQ=100.0
OUT2_TARGET_FREQ=100.0
OUT3_FREQ=0.0
OUT3_TARGET_FREQ=100.0
OUT4_FREQ=100.0
OUT4_TARGET_FREQ=100.0
OUT5_FREQ=100.0
OUT5_TARGET_FREQ=100.0
OUT6_FREQ=100.0
OUT6_TARGET_FREQ=100.0
OUT7_FREQ=100.0
OUT7_TARGET_FREQ=100.0
OUT8_FREQ=500.0
OUT8_TARGET_FREQ=500.0
OUT9_FREQ=500.0
OUT9_TARGET_FREQ=500.0
OUTx_TARGET_FREQ=156.25
PLL1_FB_REF_FREQ=1250.0
PLL1_PFD_freq=96.0
PLL2_FB_REF_FREQ=1562.5
PLL2_PFD_freq=125.0
PLL3_FB_REF_FREQ=1228.8
PLL3_PFD_freq=96.0
REF0_FREQ=125.0
REF0_PPM=4.6
REF1_FREQ=48.0
REF1_PPM=4.6
VCO1_INT=51
VCO1_NUM=349526/8388624
VCO1_PPM=0.0
VCO1_freq=4900.0
VCO2_INT=44
VCO2_NUM=6710888/8388610
VCO2_PPM=0.0
VCO2_freq=5600.0
VCO3_INT=26
VCO3_NUM=45812984491
VCO3_PPM=1.16415321827e-08
VCO3_freq=2500.0
XO_FREQ=48.0
XO_PPM=50
bModify_Apply=Apply quick set
bModify_InvertSelection=Invert
bModify_SelectAll=Select All
bModify_SelectNone=Select none
bRUN_ALL=bRUN_ALL;
bRUN_SCRIPT=RUN MATLAB;
bTICS_RESET=RESET
btnAPPLY_TO_DEVICE=Apply Output Clock Settings to Device
btnASSIGN_VCO_SETTINGS=Assign Selected VCO Settings to Device
btnCALCULATE_VCOS=Calculate VCO Frequency Options
btnCOPY_TO_OVERRIDE=Copy to Selected VCO Frequency
cbBypassMatlabRunWarning=0
cbDefault_SYSREF_operation=0
cbDisableFastlock_DPLL1=0
cbDisableFastlock_DPLL2=0
cbDisableFastlock_DPLL3=0
cbFrequencyValidation_option=1
cbOUT0_FMT=16
cbOUT0_SRC=6
cbOUT0_VCM=0
cbOUT10_FMT=1
cbOUT10_VCM=0
cbOUT11_FMT=1
cbOUT11_VCM=0
cbOUT12_FMT=1
cbOUT12_VCM=0
cbOUT13_FMT=1
cbOUT13_VCM=0
cbOUT1415_SRC=2
cbOUT14_FMT=1
cbOUT14_VCM=0
cbOUT15_FMT=1
cbOUT15_VCM=0
cbOUT1_FMT=1
cbOUT1_SRC=6
cbOUT1_VCM=0
cbOUT23_SRC=2
cbOUT2_FMT=1
cbOUT2_VCM=0
cbOUT3_FMT=0
cbOUT3_VCM=0
cbOUT4567_SRC=0
cbOUT4_FMT=9
cbOUT4_VCM=0
cbOUT5_FMT=1
cbOUT5_VCM=0
cbOUT6_FMT=1
cbOUT6_VCM=0
cbOUT7_FMT=1
cbOUT7_VCM=0
cbOUT8_FMT=1
cbOUT8_VCM=0
cbOUT8to13_SRC=1
cbOUT9_FMT=1
cbOUT9_VCM=0
cbOUTx_FMT=0
cbOUTx_SRC=9
cb_DPLL1_ZDM_option=0
cb_DPLL2_ZDM_option=0
cb_DPLL3_ZDM_option=0
chOUT0_SR=0
chOUT10_SR=0
chOUT11_SR=0
chOUT12_SR=0
chOUT13_SR=0
chOUT1_SR=0
chOUT4_SR=0
chOUT5_SR=0
chOUT6_SR=0
chOUT7_SR=0
chOUT8_SR=0
chOUT9_SR=0
ckCalcDPLL1=0
ckCalcDPLL2=0
ckCalcDPLL3=1
ckOUT0_modify=0
ckOUT10_modify=0
ckOUT11_modify=0
ckOUT12_modify=0
ckOUT13_modify=0
ckOUT14_modify=0
ckOUT15_modify=0
ckOUT1_modify=0
ckOUT2_modify=0
ckOUT3_modify=0
ckOUT4_modify=0
ckOUT5_modify=0
ckOUT6_modify=0
ckOUT7_modify=0
ckOUT8_modify=0
ckOUT9_modify=0
ckOUTx_SR=0
ckVCO_OVERRIDE_EN=0
ck_Use_DPLL1=0
ck_Use_DPLL2=0
ck_Use_DPLL3=1
opt_specify_vco1_freq=4900.0
opt_specify_vco1_freq_units=MHz
opt_specify_vco2_freq=5600.0
opt_specify_vco2_freq_units=MHz
opt_specify_vco3_freq=2500.0
opt_specify_vco3_freq_units=MHz
sDPLL1_DCO_STEP=0
sDPLL1_DCO_STEP_ACT=0
sDPLL1_PEAK=0.1
sDPLL1_PEAK_ACT=n/a
sDPLL1_PEAK_ERROR=1
sDPLL1_PEAK_ERROR_ACT=n/a
sDPLL1_REF_DEN_PROG=2^40
sDPLL1_er_fn_offset=100
sDPLL1_er_fn_value=0.35 dB
sDPLL1_tr_fn_offset=100
sDPLL1_tr_fn_value=-27.12 dB
sDPLL2_DCO_STEP=10366.604
sDPLL2_DCO_STEP_ACT=10366.6036356843
sDPLL2_PEAK=0.1
sDPLL2_PEAK_ACT=n/a
sDPLL2_PEAK_ERROR=1
sDPLL2_PEAK_ERROR_ACT=n/a
sDPLL2_REF_DEN_PROG=2^40
sDPLL2_er_fn_offset=100
sDPLL2_er_fn_value=0.41 dB
sDPLL2_tr_fn_offset=100
sDPLL2_tr_fn_value=-25.72 dB
sDPLL3_DCO_STEP=0
sDPLL3_DCO_STEP_ACT=0
sDPLL3_PEAK=0.1
sDPLL3_PEAK_ACT=n/a
sDPLL3_PEAK_ERROR=1
sDPLL3_PEAK_ERROR_ACT=n/a
sDPLL3_REF_DEN_PROG=2^40
sDPLL3_er_fn_offset=100
sDPLL3_er_fn_value=0.41 dB
sDPLL3_tr_fn_offset=100
sDPLL3_tr_fn_value=-25.72 dB
stAPLL_ref_changed_bad_VCO_note=
stDPLL1_FL1_VAL=89.13 ms
stDPLL1_FL2_VAL=503.32 ms
stDPLL1_LBW_ACT_SP=10.107
stDPLL1_LCK_VAL=3.93 ms
stDPLL2_FL1_VAL=86.02 ms
stDPLL2_FL2_VAL=507.90 ms
stDPLL2_LBW_ACT_SP=10.143
stDPLL2_LCK_VAL=6.14 ms
stDPLL3_FL1_VAL=360.45 ms
stDPLL3_FL2_VAL=507.90 ms
stDPLL3_LBW_ACT_SP=10.143
stDPLL3_LCK_VAL=98.30 ms
stDPLL_TDC1_freq=25
stDPLL_TDC2_freq=2.0
stDPLL_TDC3_freq=1.0
stOUT0_VCM=.
stOUT10_VCM=Setting 3, Vcm = 1.25 V
stOUT11_VCM=Setting 3, Vcm = 1.25 V
stOUT12_VCM=Setting 3, Vcm = 1.25 V
stOUT13_VCM=Setting 3, Vcm = 1.25 V
stOUT14_VCM=Setting 3, Vcm = 1.25 V
stOUT15_VCM=Setting 3, Vcm = 1.25 V
stOUT1_VCM=Setting 3, Vcm = 1.25 V
stOUT2_VCM=Setting 3, Vcm = 1.25 V
stOUT3_VCM=.
stOUT4_VCM=Setting 1, Vcm = 0.375 V
stOUT5_VCM=Setting 3, Vcm = 1.25 V
stOUT6_VCM=Setting 3, Vcm = 1.25 V
stOUT7_VCM=Setting 3, Vcm = 1.25 V
stOUT8_VCM=Setting 3, Vcm = 1.25 V
stOUT9_VCM=Setting 3, Vcm = 1.25 V
stOUTx_VCM=.
st_ExtraGain=
st_ZDM_NOTES=ZDM disabled
st_frequency_planning_note=Frequency plan updated.  Press Calculate VCO Frequency Options"
tcDPLL1_LBW=10
tcDPLL1_extra_gain=1
tcDPLL2_LBW=10
tcDPLL2_extra_gain=1
tcDPLL3_LBW=10
tcDPLL3_extra_gain=1
bSaveDesignReport=Save design report text to file
btnDesignReport=Generate Design Report
mtcDR_Output=--== Design Report, 2023-11-13 1658 ==--\nThe design report is a basic summary and check of device settings\n----------------------------------------------------------------------------------------------------------\n\n-= Outputs =-\n-------------\nOutput	Enabled	VOD	VCM	FREQ	SOURCE\nOUT0	1 (On)	0	1	25.0	PLL3\nOUT1	1 (On)	0	4	100.0	PLL3\nOUT2	1 (On)	0	4	100.0	0:PLL3\nOUT3	1 (On)	7	1	100.0	0:PLL3\nOUT4	1 (On)	7	1	100.0	PLL3\nOUT5	1 (On)	0	4	100.0	PLL3\nOUT6	1 (On)	0	4	100.0	PLL3\nOUT7	1 (On)	0	4	100.0	PLL3\nOUT8	1 (On)	0	4	500.0	PLL3\nOUT9	1 (On)	0	4	500.0	PLL3\nOUT10	1 (On)	0	4	250.0	PLL3\nOUT11	1 (On)	0	4	250.0	PLL3\nOUT12	1 (On)	0	4	250.0	PLL3\nOUT13	1 (On)	0	4	250.0	PLL3\nOUT14	1 (On)	0	4	500.0	0:VCO3\nOUT15	1 (On)	7	1	156.25	0:VCO3\n\n\n-= DPLL1 =-\nDPLL1_EN = 0\nDPLL1_LOOP_EN = 0\nMUTE_DPLL1_FRLOCK = 0\nMUTE_DPLL1_PHLOCK = 0\nZDM user inputs check: pass: ZDM disabled\nNot using ZDM.\n\n-= DPLL2 =-\nDPLL2_EN = 0\nDPLL2_LOOP_EN = 0\nMUTE_DPLL2_FRLOCK = 0\nMUTE_DPLL2_PHLOCK = 0\nZDM user inputs check: pass: ZDM disabled\nNot using ZDM.\n\n-= DPLL3 =-\nDPLL3_EN = 0\nDPLL3_LOOP_EN = 0\nMUTE_DPLL3_FRLOCK = 0\nMUTE_DPLL3_PHLOCK = 0\nZDM user inputs check: pass: ZDM disabled\nNot using ZDM.\n\n-= APLLs =-\n* APLL Start Priority Check: Pass\n\n\n-= APLL1 =-\nVCO1 frequency inside valid operating range (4800.0 MHz to 5350.0 MHz)\nAPLL1_EN = 0\nMUTE_APLL1_LOCK = 0\n\n-= APLL2 =-\nVCO2 frequency inside valid operating range (5595.0 MHz to 5950.0 MHz)\nAPLL2_EN = 1\nMUTE_APLL2_LOCK = 0\n\n-= APLL3 =-\nVCO3 frequency inside valid operating range (2499.75 MHz to 2500.25 MHz)\nAPLL3_EN = 1
boxRegsFormat=1
btnGenAllRegs=Generate Register Programming Sequence
btnSaveRegsFile=Save Contents to Text File
btnWriteRegs=Write Contents to Device\n(With GUI update, may\ntrigger additional writes)
btnWriteRegsDirect=Write Contents to Device\n(direct, no GUI update)
cbGenProgrammingOption=1
chkGenReducedRegs=0
prgm_Output=# The comments below are the steps for implementing glitchless device programming.\n# The function block("0==LOL_PLLx",timeout_seconds = 1) polls the status of the APLLs to determine if they are locked, max 1 s.\n# During this time, TICS Pro usage is blocked.\n# The function block("0==LOL_PLLx",timeout_seconds = 1) can be replaced with open_loop_delay(seconds=1) to delay for 1 s\n# This is as opposed to checking the APLL lock status.\n\n# Step 1: Set all outputs to static low to ensure that there are no glitches at startup.\n# Set OUT0 to static low.\nR962	0x03c230 # OUT0 L\nR963	0x03c322 # OUT0 Static DC\n# Set OUT1 to static low.\nR965	0x03c500 # OUT1 L\nR966	0x03c622 # OUT1 Static DC\n# Set OUT2 to static low.\nR1025	0x040102 # OUT2 L & OUT2 Static DC\n# Set OUT3 to static low.\nR1057	0x04210a # OUT3 Static DC\n# Set OUT4 to static low.\nR1090	0x04424a # OUT4 L & OUT4 Static DC\n# Set OUT5 to static low.\nR1092	0x04440a # OUT5 L & OUT5 Static DC\n# Set OUT6 to static low.\nR1122	0x04620a # OUT6 L & OUT6 Static DC\n# Set OUT7 to static low.\nR1124	0x04640a # OUT7 L & OUT7 Static DC\n# Set OUT8 to static low.\nR1154	0x04820a # OUT8 L & OUT8 Static DC\n# Set OUT9 to static low.\nR1156	0x04840a # OUT9 L & OUT9 Static DC\n# Set OUT10 to static low.\nR1186	0x04a20a # OUT10 L & OUT10 Static DC\n# Set OUT11 to static low.\nR1188	0x04a40a # OUT11 L & OUT11 Static DC\n# Set OUT12 to static low.\nR1218	0x04c20a # OUT12 L & OUT12 Static DC.\n# Set OUT13 to static low.\nR1220	0x04c40a # OUT13 L & OUT13 Static DC\n# Set OUT14 to static low.\nR1249	0x04e102 # OUT14 Static DC\n# Set OUT15 to static low.\nR1281	0x050102 # OUT15 Static DC\n# Finished setting all outputs to static low.\n\n# Step 2: Write all of the registers to the device EXCEPT for those that do the following:\n# 	1. Change the outputs from static low to a different state\n# 	2. Change the state of SYNC_EN or SYNC_SW\n# 	3. Change the state of SWRST\n# These registers have already been excluded from register generation via commenting.\nR19	0x001300\nR20	0x001400\nR22	0x001635\nR24	0x001806\nR26	0x001A00\nR32	0x002000\nR37	0x002500\nR38	0x0026FF\nR39	0x0027FF\nR40	0x002820\nR41	0x002900\nR42	0x002A00\nR43	0x002B00\nR44	0x002C00\nR49	0x003102\nR54	0x003620\nR55	0x003700\nR56	0x003800\nR57	0x00390C\nR58	0x003A26\nR59	0x003B0F\nR60	0x003C00\nR61	0x003D00\nR62	0x003E00\nR63	0x003F0C\nR64	0x00400B\nR67	0x004302\nR68	0x004408\nR70	0x004600\nR75	0x004B1A\nR76	0x004C1A\nR77	0x004D1A\nR78	0x004E00\nR79	0x004F2E\nR80	0x00502E\nR83	0x0053A8\nR84	0x005400\nR85	0x005500\nR86	0x00560E\nR87	0x005700\nR88	0x005800\nR89	0x00591E\nR96	0x006000\nR97	0x006100\nR98	0x006200\nR99	0x006306\nR100	0x006400\nR101	0x006500\nR102	0x006616\nR109	0x006D00\nR110	0x006E6F\nR111	0x006F00\nR112	0x007077\nR113	0x007100\nR114	0x00726F\nR115	0x007300\nR116	0x007477\nR125	0x007D00\nR126	0x007E13\nR127	0x007FDE\nR128	0x008044\nR129	0x008100\nR130	0x00821E\nR131	0x008384\nR132	0x008481\nR133	0x008500\nR134	0x00861E\nR135	0x008784\nR136	0x008880\nR137	0x008900\nR138	0x008A1E\nR139	0x008B84\nR140	0x008C80\nR157	0x009D0A\nR158	0x009E0A\nR161	0x00A100\nR162	0x00A200\nR163	0x00A300\nR164	0x00A400\nR207	0x00CF00\nR208	0x00D000\nR223	0x00DF00\nR225	0x00E100\nR226	0x00E201\nR228	0x00E400\nR229	0x00E50A\nR230	0x00E600\nR231	0x00E764\nR232	0x00E800\nR233	0x00E922\nR234	0x00EAA0\nR235	0x00EBF3\nR236	0x00EC00\nR237	0x00ED22\nR238	0x00EEA0\nR239	0x00EFF3\nR240	0x00F000\nR241	0x00F198\nR242	0x00F296\nR243	0x00F383\nR247	0x00F755\nR248	0x00F840\nR249	0x00F948\nR250	0x00FA00\nR251	0x00FB00\nR252	0x00FC00\nR253	0x00FD00\nR254	0x00FE00\nR255	0x00FF00\nR256	0x010000\nR257	0x010100\nR258	0x010200\nR259	0x010300\nR260	0x010400\nR261	0x010503\nR262	0x010600\nR263	0x010700\nR264	0x010801\nR265	0x0109A7\nR266	0x010A07\nR267	0x010B00\nR268	0x010C00\nR269	0x010D00\nR270	0x010E0A\nR271	0x010F0E\nR272	0x01100A\nR273	0x011105\nR274	0x01120D\nR275	0x011308\nR276	0x01140D\nR277	0x011508\nR278	0x01160A\nR279	0x011709\nR280	0x01180A\nR281	0x011911\nR282	0x011A10\nR283	0x011B08\nR284	0x011C42\nR285	0x011D2E\nR286	0x011E00\nR287	0x011F73\nR288	0x012001\nR289	0x012185\nR290	0x012203\nR291	0x012309\nR292	0x012401\nR293	0x012592\nR294	0x01260D\nR295	0x012742\nR296	0x012801\nR297	0x012940\nR298	0x012A00\nR299	0x012B0A\nR300	0x012C3E\nR301	0x012D0A\nR302	0x012E08\nR303	0x012F1D\nR304	0x01301F\nR305	0x013107\nR306	0x01323F\nR307	0x01330F\nR308	0x01343F\nR309	0x013500\nR314	0x013A00\nR315	0x013B00\nR316	0x013C00\nR317	0x013D00\nR318	0x013ED3\nR319	0x013F81\nR320	0x0140D7\nR321	0x0141DB\nR322	0x0142F3\nR323	0x0143FC\nR324	0x0144FF\nR325	0x0145FF\nR326	0x0146FF\nR327	0x0147FE\nR328	0x0148EC\nR329	0x014900\nR330	0x014A00\nR331	0x014B00\nR332	0x014C0F\nR333	0x014DA0\nR334	0x014E00\nR335	0x014F00\nR336	0x015000\nR337	0x015100\nR338	0x015200\nR339	0x015300\nR340	0x015400\nR341	0x015500\nR342	0x015600\nR343	0x015700\nR344	0x015800\nR345	0x015902\nR346	0x015A00\nR347	0x015B00\nR348	0x015C00\nR349	0x015D00\nR350	0x015E00\nR351	0x015F00\nR352	0x016000\nR358	0x016600\nR359	0x016700\nR360	0x016801\nR361	0x016900\nR362	0x016A01\nR367	0x016F00\nR368	0x017000\nR369	0x017100\nR370	0x017200\nR373	0x017500\nR375	0x017700\nR376	0x017801\nR378	0x017A00\nR379	0x017B0A\nR380	0x017C00\nR381	0x017D64\nR382	0x017E00\nR383	0x017F03\nR384	0x018045\nR385	0x01810E\nR386	0x018200\nR387	0x018303\nR388	0x018445\nR389	0x01850E\nR390	0x018600\nR391	0x018798\nR392	0x018896\nR393	0x01898D\nR397	0x018D55\nR398	0x018E6E\nR399	0x018F8E\nR400	0x019000\nR401	0x019100\nR402	0x019200\nR403	0x019300\nR404	0x019400\nR405	0x019500\nR406	0x019600\nR407	0x019700\nR408	0x019800\nR409	0x019900\nR410	0x019A00\nR411	0x019B03\nR412	0x019C00\nR413	0x019D00\nR414	0x019E15\nR415	0x019FE0\nR416	0x01A000\nR417	0x01A100\nR418	0x01A200\nR419	0x01A300\nR420	0x01A40B\nR421	0x01A50F\nR422	0x01A60B\nR423	0x01A708\nR424	0x01A80C\nR425	0x01A908\nR426	0x01AA0C\nR427	0x01AB08\nR428	0x01AC0A\nR429	0x01AD08\nR430	0x01AE0A\nR431	0x01AF11\nR432	0x01B00D\nR433	0x01B105\nR434	0x01B236\nR435	0x01B3AD\nR436	0x01B403\nR437	0x01B5EF\nR438	0x01B601\nR439	0x01B785\nR440	0x01B803\nR441	0x01B909\nR442	0x01BA01\nR443	0x01BB92\nR444	0x01BC0D\nR445	0x01BD42\nR446	0x01BE01\nR447	0x01BF40\nR448	0x01C000\nR449	0x01C10A\nR450	0x01C214\nR451	0x01C308\nR452	0x01C408\nR453	0x01C51F\nR454	0x01C621\nR455	0x01C707\nR456	0x01C83F\nR457	0x01C90F\nR458	0x01CA3F\nR459	0x01CB00\nR464	0x01D000\nR465	0x01D100\nR466	0x01D200\nR467	0x01D30A\nR468	0x01D4EF\nR469	0x01D5FF\nR470	0x01D6E1\nR471	0x01D781\nR472	0x01D80F\nR473	0x01D9F3\nR474	0x01DAFF\nR475	0x01DBE1\nR476	0x01DC81\nR477	0x01DD2E\nR478	0x01DE00\nR479	0x01DF00\nR480	0x01E000\nR481	0x01E100\nR482	0x01E212\nR483	0x01E3C0\nR484	0x01E400\nR485	0x01E500\nR486	0x01E600\nR487	0x01E700\nR488	0x01E800\nR489	0x01E900\nR490	0x01EA00\nR491	0x01EB00\nR492	0x01EC00\nR493	0x01ED00\nR494	0x01EE00\nR495	0x01EF02\nR496	0x01F000\nR497	0x01F19D\nR498	0x01F2A3\nR499	0x01F383\nR500	0x01F441\nR501	0x01F501\nR502	0x01F600\nR508	0x01FC00\nR509	0x01FD00\nR510	0x01FE30\nR511	0x01FF00\nR512	0x02007D\nR517	0x020500\nR518	0x020600\nR519	0x020700\nR520	0x020800\nR523	0x020B0A\nR525	0x020D00\nR526	0x020E02\nR528	0x021080\nR529	0x02110A\nR530	0x021200\nR531	0x021364\nR532	0x021400\nR533	0x021523\nR534	0x021628\nR535	0x021700\nR536	0x021800\nR537	0x021901\nR538	0x021A77\nR539	0x021B00\nR540	0x021C00\nR541	0x021D98\nR542	0x021E96\nR543	0x021F80\nR547	0x0223D5\nR548	0x022456\nR549	0x022551\nR550	0x022600\nR551	0x022700\nR552	0x022800\nR553	0x022900\nR554	0x022A00\nR555	0x022B00\nR556	0x022C00\nR557	0x022D00\nR558	0x022E00\nR559	0x022F00\nR560	0x023000\nR561	0x023103\nR562	0x023200\nR563	0x023300\nR564	0x023413\nR565	0x023588\nR566	0x023600\nR567	0x023700\nR568	0x023800\nR569	0x023900\nR570	0x023A0C\nR571	0x023B0E\nR572	0x023C0C\nR573	0x023D08\nR574	0x023E0B\nR575	0x023F08\nR576	0x02400B\nR577	0x024108\nR578	0x024209\nR579	0x024309\nR580	0x024409\nR581	0x024511\nR582	0x02460B\nR583	0x024707\nR584	0x02482D\nR585	0x02496F\nR586	0x024A03\nR587	0x024BEE\nR588	0x024C01\nR589	0x024D85\nR590	0x024E03\nR591	0x024F0C\nR592	0x025001\nR593	0x025192\nR594	0x02520D\nR595	0x025342\nR596	0x025401\nR597	0x025540\nR598	0x025600\nR599	0x02570A\nR600	0x025814\nR601	0x025908\nR602	0x025A08\nR603	0x025B1E\nR604	0x025C20\nR605	0x025D07\nR606	0x025E3F\nR607	0x025F0F\nR608	0x026000\nR609	0x026100\nR614	0x026600\nR615	0x026700\nR616	0x026800\nR617	0x026909\nR618	0x026AC4\nR619	0x026B00\nR620	0x026C00\nR621	0x026D00\nR622	0x026E00\nR623	0x026F00\nR624	0x027000\nR625	0x027100\nR626	0x027200\nR627	0x027300\nR628	0x027400\nR629	0x027500\nR630	0x027600\nR631	0x027700\nR632	0x027800\nR633	0x027968\nR634	0x027A2A\nR635	0x027BAA\nR636	0x027CAA\nR637	0x027DAA\nR638	0x027EAA\nR639	0x027FFF\nR640	0x0280FF\nR641	0x0281FF\nR642	0x0282FF\nR643	0x0283FF\nR644	0x028400\nR645	0x028502\nR646	0x028600\nR647	0x028700\nR648	0x028800\nR649	0x028900\nR650	0x028A00\nR651	0x028B00\nR652	0x028C00\nR658	0x029200\nR659	0x029300\nR660	0x02947D\nR661	0x029500\nR662	0x029630\nR667	0x029B00\nR668	0x029C00\nR669	0x029D01\nR670	0x029E01\nR707	0x02C36D\nR708	0x02C403\nR709	0x02C509\nR710	0x02C602\nR711	0x02C702\nR712	0x02C8FF\nR713	0x02C900\nR714	0x02CA0A\nR715	0x02CB1C\nR716	0x02CC00\nR717	0x02CD33\nR718	0x02CE05\nR719	0x02CF55\nR720	0x02D056\nR721	0x02D180\nR722	0x02D200\nR723	0x02D310\nR724	0x02D436\nR731	0x02DBF1\nR732	0x02DCA0\nR733	0x02DD08\nR736	0x02E000\nR745	0x02E900\nR746	0x02EA01\nR773	0x030506\nR777	0x030922\nR778	0x030A0E\nR779	0x030B07\nR780	0x030C02\nR781	0x030D02\nR782	0x030E7F\nR783	0x030F00\nR784	0x031008\nR785	0x031102\nR786	0x031200\nR787	0x03132C\nR788	0x031466\nR789	0x031566\nR790	0x031668\nR791	0x031780\nR792	0x031800\nR793	0x031902\nR794	0x031A06\nR803	0x032340\nR804	0x032438\nR805	0x032504\nR808	0x032800\nR818	0x033200\nR819	0x033301\nR840	0x034822\nR841	0x034915\nR842	0x034A01\nR843	0x034B0D\nR844	0x034C0D\nR845	0x034DFF\nR846	0x034E00\nR847	0x034F0A\nR848	0x03501C\nR849	0x035100\nR850	0x03521A\nR851	0x035305\nR852	0x03540A\nR853	0x0355AA\nR854	0x0356AA\nR855	0x0357AA\nR856	0x0358AB\nR857	0x035905\nR864	0x0360F8\nR865	0x0361BA\nR866	0x036214\nR872	0x036800\nR882	0x037200\nR967	0x03C701\nR968	0x03C800\nR969	0x03C933\nR971	0x03CB1B\nR972	0x03CC00\nR973	0x03CD3F\nR974	0x03CE00\nR975	0x03CF00\nR976	0x03D000\nR977	0x03D100\nR978	0x03D200\nR979	0x03D31C\nR980	0x03D400\nR981	0x03D507\nR982	0x03D600\nR983	0x03D705\nR984	0x03D800\nR985	0x03D900\nR986	0x03DA00\nR987	0x03DBFA\nR988	0x03DC00\nR989	0x03DD00\nR990	0x03DE00\nR991	0x03DF00\nR1026	0x04020F\nR1027	0x040308\nR1028	0x040400\nR1029	0x040500\nR1030	0x040600\nR1031	0x040719\nR1058	0x042200\nR1059	0x042308\nR1060	0x042400\nR1061	0x042500\nR1062	0x042600\nR1063	0x042719\nR1093	0x044531\nR1094	0x044603\nR1095	0x044700\nR1096	0x044800\nR1097	0x044900\nR1098	0x044A07\nR1099	0x044B00\nR1100	0x044C02\nR1101	0x044D00\nR1102	0x044E00\nR1103	0x044F00\nR1104	0x045008\nR1105	0x045100\nR1106	0x045200\nR1107	0x045300\nR1108	0x045410\nR1125	0x046531\nR1126	0x046603\nR1127	0x046700\nR1128	0x046800\nR1129	0x046900\nR1130	0x046A07\nR1131	0x046B00\nR1132	0x046C02\nR1133	0x046D00\nR1134	0x046E00\nR1135	0x046F00\nR1136	0x0470FA\nR1137	0x047100\nR1138	0x047200\nR1139	0x047300\nR1140	0x047410\nR1157	0x048531\nR1158	0x048623\nR1159	0x048700\nR1160	0x048800\nR1161	0x048900\nR1162	0x048A05\nR1163	0x048B00\nR1164	0x048C02\nR1165	0x048D00\nR1166	0x048E00\nR1167	0x048F00\nR1168	0x0490FA\nR1169	0x049100\nR1170	0x049200\nR1171	0x049300\nR1172	0x049410\nR1189	0x04A530\nR1190	0x04A621\nR1191	0x04A700\nR1192	0x04A800\nR1193	0x04A900\nR1194	0x04AA0A\nR1195	0x04AB00\nR1196	0x04AC02\nR1197	0x04AD05\nR1198	0x04AE00\nR1199	0x04AF00\nR1200	0x04B00A\nR1201	0x04B100\nR1202	0x04B200\nR1203	0x04B302\nR1204	0x04B410\nR1221	0x04C531\nR1222	0x04C623\nR1223	0x04C700\nR1224	0x04C800\nR1225	0x04C900\nR1226	0x04CA0A\nR1227	0x04CB00\nR1228	0x04CC02\nR1229	0x04CD05\nR1230	0x04CE00\nR1231	0x04CF00\nR1232	0x04D00A\nR1233	0x04D100\nR1234	0x04D200\nR1235	0x04D302\nR1236	0x04D410\nR1250	0x04E20F\nR1251	0x04E308\nR1252	0x04E400\nR1253	0x04E500\nR1254	0x04E600\nR1255	0x04E705\nR1282	0x05020F\nR1283	0x050308\nR1284	0x050400\nR1285	0x050500\nR1286	0x050600\nR1287	0x050710\n\n# Step 3. Perform a software reset (SWRST bit = 1, then SWRST bit = 0).\nR23	0x001740\nR23	0x001700\n\n# Step 4. Wait for the APLL to lock before asserting SYNC_EN and SYNC_SW.\n# Note: block("0==LOL_PLLx", timeout_seconds=1) is a function that polls for the given APLL for the locked condition.\n# The 0 above means that the APLL is locked, 1 means the APLL is unlocked.\n# The " around the condition are REQUIRED for function operation - the condition must be in quoation marks.\n# There is a one second timeout window in this function within which the APLL can lock.\n# If the APLL does not lock within this window, the write operation does not continue.\n# If implemented in an FPGA, a function would have to be created to handle this task.\n# Alternatively, instead of using block("0==LOL_PLLx", timeout_seconds=1), use open_loop_delay(seconds=1).\n# The function open_loop_delay(seconds=1) is simply a 1 second delay, after which writes continue.\n# The delay time is configurable, i.e. open_loop_delay(seconds=2) will delay for 2 seconds\n# If an APLL is not being used (eg. APLL1 disabled), then simply do not poll that LOL bit, as it will be set, but its state does not actually matter.\n# open_loop_delay(seconds=1)\nblock("0==LOL_PLL1", timeout_seconds=1)\nblock("0==LOL_PLL2", timeout_seconds=1)\n\n# Step 5: Assert SYNC by writing SYNC_EN = 1, then SYNC_SW = 1.\nR25	0x001901\nR21	0x0015e1\n\n# Step 6. Write the output registers to their proper states.\nR961	0x03c148\nR962	0x03c230\nR963	0x03c328\nR964	0x03c460\nR965	0x03c500\nR966	0x03c614\nR1024	0x040060\nR1025	0x040103\nR1056	0x04200f\nR1057	0x04210b\nR1089	0x04414f\nR1090	0x04424c\nR1091	0x044360\nR1092	0x04440c\nR1121	0x046160\nR1122	0x04620c\nR1123	0x046360\nR1124	0x04640c\nR1153	0x048160\nR1154	0x04820c\nR1155	0x048360\nR1156	0x04840c\nR1185	0x04a160\nR1186	0x04a209\nR1187	0x04a360\nR1188	0x04a409\nR1217	0x04c160\nR1218	0x04c209\nR1219	0x04c360\nR1220	0x04c40c\nR1248	0x04e060\nR1249	0x04e103\nR1280	0x050060\nR1281	0x050103\n\n# Step 7: Dessert SYNC by writing SYNC_SW = 0, then SYNC_EN = 0 (SYNC_EN = 0 not required).\nR21	0x0015a1\nR25	0x001900\n
txtStartupUpdate=
bExportTextToFile=Save Contents to File
bProgramEEPROM=Program EEPROM
bREGCOMMIT=REGCOMMIT Sequence
bSRAMDirect=SRAM Sequence
btnEE_READSTATUS=Read EE Status Registers
btnEE_TICS2EPR=Export EE Map to .epr
mtc_EEPROMdump=EEPROM programming log or programming sequence will populate here
APLL1_REF_FREQ=48.0
APLL2_REF_FREQ=1250.0
APLL3_REF_FREQ=48.0
DPLL1_REF_FREQ=25.0
DPLL1_TDC_FREQ=25.0
DPLL2_REF_FREQ=48.0
DPLL2_TDC_FREQ=2.0
DPLL3_REF_FREQ=125.0
DPLL3_TDC_FREQ=1.0
PLL1_FB_APLL_REF_FREQ=1225.0
PLL1_FB_DPLL_REF_FREQ=612.5
PLL1_PFD_freq=96.0
PLL2_FB_APLL_REF_FREQ=1400.0
PLL2_FB_DPLL_REF_FREQ=560.0
PLL2_PFD_freq=125.0
PLL3_FB_APLL_REF_FREQ=1250.0
PLL3_FB_DPLL_REF_FREQ=625.0
PLL3_PFD_freq=96.0
REF0_FREQ=125.0
REF1_FREQ=48.0
VCO1_APLL_FREQ=4900.0
VCO1_DPLL_FREQ=5287.68
VCO1_freq=4900.0
VCO2_APLL_FREQ=5600.0
VCO2_DPLL_FREQ=5599.999999
VCO2_freq=5600.0
VCO3_APLL_FREQ=~2500.000000
VCO3_DPLL_FREQ=2500.0
VCO3_freq=2500.0
XO_FREQ=48.0
stDPLL1_Reference_Message=No input selected!  Holdover!
stDPLL2_Reference_Message=No input selected!  Holdover!
stDPLL3_Reference_Message=No input selected!  Holdover!
DPLL1_OFFSET_TIME=0.000000 fs
DPLL1_PARAMETER_A=0
DPLL1_PARAMETER_B=72
DPLL1_PARAMETER_C=7
DPLL2_OFFSET_TIME=0.000000 fs
DPLL2_PARAMETER_A=0
DPLL2_PARAMETER_B=654
DPLL2_PARAMETER_C=0
DPLL3_OFFSET_TIME=0.000000 fs
DPLL3_PARAMETER_A=0
DPLL3_PARAMETER_B=593
DPLL3_PARAMETER_C=0
OUT0_FREQ=25.0
OUT0_TARGET_FREQ=25.0
OUT10_FREQ=250.0
OUT10_TARGET_FREQ=250.0
OUT4_FREQ=100.0
OUT4_TARGET_FREQ=100.0
REF0_FREQ=125.0
REF1_FREQ=48.0
VCO1_freq=4900.0
VCO2_freq=5600.0
VCO3_freq=2500.0
bGOTO_STARTPAGE=Go to Start Page
bSetZDM_DPLL1=Set ZDM DPLL_1
bSetZDM_DPLL2=Set ZDM DPLL_2
bSetZDM_DPLL3=Set ZDM DPLL_3
cbOUT0_FMT=16
cbOUT0_SRC=6
cbOUT10_FMT=1
cbOUT4567_SRC=0
cbOUT4_FMT=9
cbOUT8to13_SRC=1
cb_DPLL1_ZDM_option=0
cb_DPLL2_ZDM_option=0
cb_DPLL3_ZDM_option=0
chOUT0_SR=0
chOUT10_SR=0
chOUT4_SR=0
st_ZDM_NOTES=ZDM disabled
bClearAllSYNCEnables=_Clear all\nSYNC enables
bConfigureGPIO1_for_CMOS_SYSREF_1PPS_output=Configure GPIO1 for buffered output
bConfigureGPIO2_for_CMOS_SYSREF_1PPS_output=Configure GPIO2 for buffered output
bGenerateDividerSyncSequence=Generate Register\nProgramming Sequence
bSetAllSYNCEnables=_Set all\nSYNC enables
bSetSYSREFSYNCEnablesForDeterminism=Set SYNC enables for\nDeterministic SYSREF
bSetSYSREFSYNCEnablesForNoDisruption=Set SYNC enables for\nNon-disruptive SYSREF
boxRegsFormat=1
btnSaveSyncRegsFile=Save SYNC sequence to file
btnWriteSyncRegs=Write SYNC sequence to device
cbMaskWriteSelection=0
mtc_prgm_Output_Sync=# The generated register list will appear here.  Custom writes can also be performed by entering values into this box, seperated by a return.\n# Lines starting with the "#" character are treated as comments, and are ignored for the register write.
OUT01_CH0_CLK_IN_SEL=3
OUT01_CH1_CLK_IN_SEL=3
OUT0_FREQ=25.0
OUT10_FREQ=250.0
OUT11_FREQ=250.0
OUT12_FREQ=250.0
OUT13_FREQ=250.0
OUT14_FREQ=500.0
OUT15_FREQ=156.25
OUT1_FREQ=100.0
OUT2_FREQ=100.0
OUT3_FREQ=0.0
OUT4_FREQ=100.0
OUT5_FREQ=100.0
OUT6_FREQ=100.0
OUT7_FREQ=100.0
OUT8_FREQ=500.0
OUT9_FREQ=500.0
REF0_FREQ=125.0
REF1_FREQ=48.0
REF_2OUT01_FREQ=0.0
VCO1_freq=4900.0
VCO2_freq=5600.0
VCO3_freq=2500.0
XO_FREQ=48.0
stOUT1011_WARNING=
stOUT1213_WARNING=
stOUT1415_WARNING=
stOUT23_WARNING=
stOUT45_WARNING=
stOUT67_WARNING=
stOUT89_WARNING=
CH0_DIV2_FREQ=0.0
CH0_FREQ=0.0
CH0_SYSREF_FREQ=0.0
CH1_FREQ=0.0
CHDIV0_FREQ=25.0
CHDIV1_FREQ=100.0
OUT01_CH0_CLK_IN_SEL=3
OUT01_CH1_CLK_IN_SEL=3
OUT0_AMP_NAME=CMOS Tristate Ctrl
OUT0_CMOS_FORCE_L=Force Low:
OUT0_CMOS_POL=Invert:
OUT0_FREQ=25.0
OUT1_AMP_NAME=LVDS, Vcm = 1.25 V
OUT1_CMOS_FORCE_L=Force Low:
OUT1_CMOS_POL=Invert:
OUT1_FREQ=100.0
OUT_0_1_SR_WARNING=Warning: Invalid frequency for SYSREF ADLY
PLL1_PRI_DIV_FREQ=700.0
PLL1_SEC_DIV_FREQ=980.0
PLL2_VCO_DIV_FREQ=700.0
PLL3_VCODIV_FREQ=2500.0
REF_2OUT01_FREQ=0.0
VCO1_freq=4900.0
VCO2_freq=5600.0
VCO3_freq=2500.0
XO_FREQ=48.0
CH2_FREQ=2500.0
CH3_FREQ=0.0
CHDIV2_FREQ=100.0
CHDIV3_FREQ=0.0
OUT2_AMP_NAME=LVDS, Vcm = 1.25 V
OUT2_FREQ=100.0
OUT3_AMP_NAME=HCSL 750 mV
OUT3_FREQ=0.0
PLL1_PRI_DIV_FREQ=700.0
PLL2_VCO_DIV_FREQ=700.0
PLL3_VCODIV_FREQ=2500.0
VCO1_freq=4900.0
VCO2_freq=5600.0
VCO3_freq=2500.0
CH4_5_DIV2_FREQ=0.0
CH4_5_FREQ=0.0
CH4_5_SYSREF_FREQ=0.0
CHDIV4_5_FREQ=100.0
OUT4_AMP_NAME=HCSL 750 mV
OUT4_FREQ=100.0
OUT5_AMP_NAME=LVDS, Vcm = 1.25 V
OUT5_FREQ=100.0
OUT_4_5_SR_WARNING=Warning: ADLY out of range
PLL2_VCO_DIV_FREQ=700.0
PLL3_VCODIV_FREQ=2500.0
VCO2_freq=5600.0
VCO3_freq=2500.0
CH6_7_DIV2_FREQ=0.0
CH6_7_FREQ=0.0
CH6_7_SYSREF_FREQ=0.0
CHDIV6_7_FREQ=100.0
OUT6_AMP_NAME=LVDS, Vcm = 1.25 V
OUT6_FREQ=100.0
OUT7_AMP_NAME=LVDS, Vcm = 1.25 V
OUT7_FREQ=100.0
OUT_6_7_SR_WARNING=Warning: ADLY out of range
PLL2_VCO_DIV_FREQ=700.0
PLL3_VCODIV_FREQ=2500.0
VCO2_freq=5600.0
VCO3_freq=2500.0
CH8_9_DIV2_FREQ=0.0
CH8_9_FREQ=0.0
CH8_9_SYSREF_FREQ=0.0
CHDIV8_9_FREQ=500.0
OUT8_AMP_NAME=LVDS, Vcm = 1.25 V
OUT8_FREQ=500.0
OUT9_AMP_NAME=LVDS, Vcm = 1.25 V
OUT9_FREQ=500.0
OUT_8_9_SR_WARNING=Warning: ADLY out of range
PLL2_VCO_DIV_FREQ=700.0
PLL3_VCODIV_FREQ=2500.0
VCO2_freq=5600.0
VCO3_freq=2500.0
CH10_11_DIV2_FREQ=0.0
CH10_11_FREQ=2500.0
CH10_11_SYSREF_FREQ=250.0
CHDIV10_11_FREQ=0.0
OUT10_AMP_NAME=LVDS, Vcm = 1.25 V
OUT10_FREQ=250.0
OUT11_AMP_NAME=LVDS, Vcm = 1.25 V
OUT11_FREQ=250.0
OUT_10_11_SR_WARNING=Warning: ADLY out of range
PLL2_VCO_DIV_FREQ=700.0
PLL3_VCODIV_FREQ=2500.0
VCO2_freq=5600.0
VCO3_freq=2500.0
CH12_13_DIV2_FREQ=0.0
CH12_13_FREQ=2500.0
CH12_13_SYSREF_FREQ=250.0
CHDIV12_13_FREQ=250.0
OUT12_AMP_NAME=LVDS, Vcm = 1.25 V
OUT12_FREQ=250.0
OUT13_AMP_NAME=LVDS, Vcm = 1.25 V
OUT13_FREQ=250.0
OUT_12_13_SR_WARNING=Warning: ADLY out of range
PLL2_VCO_DIV_FREQ=700.0
PLL3_VCODIV_FREQ=2500.0
VCO2_freq=5600.0
VCO3_freq=2500.0
CH14_FREQ=2500.0
CH15_FREQ=2500.0
CHDIV14_FREQ=500.0
CHDIV15_FREQ=156.25
OUT14_AMP_NAME=LVDS, Vcm = 1.25 V
OUT14_FREQ=500.0
OUT15_AMP_NAME=HCSL 750 mV
OUT15_FREQ=156.25
PLL1_PRI_DIV_FREQ=700.0
PLL2_VCO_DIV_FREQ=700.0
PLL3_VCODIV_FREQ=2500.0
VCO1_freq=4900.0
VCO2_freq=5600.0
VCO3_freq=2500.0
btnClearLatches=Clear Latched Bits
btnReadStatus=Read Status Bits
DPLL1_AVG_ud=10
DPLL2_AVG_ud=10
DPLL3_AVG_ud=10
REF0_AVG_COUNT_ud=2
REF0_EARLY_MARGIN_ud=1
REF0_LATE_MARGIN_ud=1
REF0_LATE_ud=0
REF1_AVG_COUNT_ud=2
REF1_EARLY_MARGIN_ud=1
REF1_LATE_MARGIN_ud=1
REF1_LATE_ud=0
bUpdateValidations=Reassign All
stDPLL1_PL_LOCK_calc=181.41 ps
stDPLL1_PL_UNLK_calc=725.62 ps
stDPLL1_TMEAS_calc=n/a
stDPLL2_PL_LOCK_calc=139.80 ps
stDPLL2_PL_UNLK_calc=559.20 ps
stDPLL2_TMEAS_calc=n/a
stDPLL3_PL_LOCK_calc=345.36 ps
stDPLL3_PL_UNLK_calc=1.38 ns
stDPLL3_TMEAS_calc=96.00 ms
stREF0_EARLY_calc=4.80 ns
stREF0_LATE_calc=11.20 ns
stREF0_PH_VALID_calc=n/a; REF0 > 2 kHz
stREF0_PPM_TIMER=41.67 ms
stREF1_EARLY_calc=17.60 ns
stREF1_LATE_calc=24.00 ns
stREF1_PH_VALID_calc=n/a; REF1 > 2 kHz
stREF1_PPM_TIMER=41.67 ms
tcDPLL1_ACCURACY_PPM=1
tcDPLL1_LOCK_PPM=1
tcDPLL1_UNLK_PPM=10
tcDPLL2_ACCURACY_PPM=1
tcDPLL2_LOCK_PPM=1
tcDPLL2_UNLK_PPM=10
tcDPLL3_ACCURACY_PPM=1
tcDPLL3_LOCK_PPM=1
tcDPLL3_UNLK_PPM=10
tcREF0_ACCURACY_PPM=1
tcREF0_PPM_INVALID=59.6
tcREF0_PPM_VALID=55.6
tcREF1_ACCURACY_PPM=1
tcREF1_PPM_INVALID=59.6
tcREF1_PPM_VALID=55.6
bConfigureGPIO1_for_CMOS_SYSREF_1PPS_output=Configure GPIO1 for buffered output
bConfigureGPIO2_for_CMOS_SYSREF_1PPS_output=Configure GPIO2 for buffered output
btnREAD_TEC=Read TEC
APLL1_FREQ_SHIFT=0
APLL1_NUM_effective=0
APLL2_FREQ_SHIFT=0
APLL2_NUM_effective=0
APLL3_FREQ_SHIFT=0
APLL3_NUM_effective=0
DPLL1_FREE_RUN_relative=0
DPLL1_FREE_RUN_relative_2s_complement=0
DPLL1_HOLD_EXP_ud=2
DPLL1_HOLD_MANT_ud=10
DPLL2_FREE_RUN_relative=0
DPLL2_FREE_RUN_relative_2s_complement=0
DPLL2_HOLD_EXP_ud=2
DPLL2_HOLD_MANT_ud=10
DPLL3_FREE_RUN_relative=0
DPLL3_FREE_RUN_relative_2s_complement=0
DPLL3_HOLD_EXP_ud=2
DPLL3_HOLD_MANT_ud=10
bAPLL1_FDECR=Decrement
bAPLL1_FINCR=Increment
bAPLL2_FDECR=Decrement
bAPLL2_FINCR=Increment
bAPLL3_FDECR=Decrement
bAPLL3_FINCR=Increment
cbDCO_MODE_APLL1=0
cbDCO_MODE_APLL2=0
cbDCO_MODE_APLL3=0
sAPLL1_DCO_STEP=0.01
sAPLL1_DCO_STEP_ACT=n/a
sAPLL2_DCO_STEP=0.01
sAPLL2_DCO_STEP_ACT=n/a
sAPLL3_DCO_STEP=0.01
sAPLL3_DCO_STEP_ACT=n/a
stDPLL1_HOLD_VAL=1.60 us
stDPLL2_HOLD_VAL=1.57 us
stDPLL3_HOLD_VAL=1.60 us
APLL1_REF_FREQ=48.0
PLL1_DEN=1099511627776
PLL1_DEN_24B=8388624
PLL1_NUM_24B=349526
PLL1_PFD_freq=96.0
PLL1_PRI_DIV_FREQ=700.0
PLL1_SEC_DIV_FREQ=980.0
PLL2_FB_APLL_REF_FREQ=1400.0
PLL3_FB_APLL_REF_FREQ=1250.0
VCO1_freq=4900.0
XO_FREQ=48.0
bAPLL1_READ=Readback
stAPLL1_status=DPLL1 in holdover
APLL2_REF_FREQ=1250.0
PLL1_FB_APLL_REF_FREQ=1225.0
PLL2_DEN=1099511627776
PLL2_DEN_24B=8388610
PLL2_NUM_24B=6710888
PLL2_PFD_freq=125.0
PLL2_VCO_DIV_FREQ=700.0
PLL3_FB_APLL_REF_FREQ=1250.0
VCO2_freq=5600.0
XO_FREQ=48.0
bAPLL2_READ=Readback
stAPLL2_status=DPLL2 in holdover
APLL3_REF_FREQ=48.0
PLL1_FB_APLL_REF_FREQ=1225.0
PLL2_FB_APLL_REF_FREQ=1400.0
PLL3_DEN=1099511627776
PLL3_DEN_24B=11184811
PLL3_NUM_24B=330410
PLL3_PFD_freq=96.0
PLL3_VCODIV_FREQ=2500.0
VCO3_freq=2500.0
XO_FREQ=48.0
bAPLL3_READ=Readback
stAPLL3_status=DPLL3 in holdover
AbsDCO_ppb_error_DPLL1=0
AbsDCO_ppb_error_DPLL2=0
AbsDCO_ppb_error_DPLL3=0
DPLL1_FB_CONFIG=0
DPLL1_FREQ_SHIFT=0
DPLL1_NUM=0
DPLL1_PHS1_EXP_ud=0
DPLL1_PHS1_MANT_ud=10
DPLL1_PHS_SLOPE=42.55158
DPLL1_PHS_SLOPE_ACT=42.551579961440
DPLL1_REF_NUM_calculated=Not calculated
DPLL2_FB_CONFIG=0
DPLL2_FREQ_SHIFT=0
DPLL2_NUM=0
DPLL2_PHS1_EXP_ud=0
DPLL2_PHS1_MANT_ud=10
DPLL2_PHS_SLOPE=0.0040732
DPLL2_PHS_SLOPE_ACT=0.004073161205
DPLL2_REF_NUM_calculated=Not calculated
DPLL3_FB_CONFIG=0
DPLL3_FREQ_SHIFT=0
DPLL3_NUM=0
DPLL3_PHS1_EXP_ud=0
DPLL3_PHS1_MANT_ud=10
DPLL3_PHS_SLOPE=0.0061176
DPLL3_PHS_SLOPE_ACT=0.006117618441
DPLL3_REF_NUM_calculated=Not calculated
bDPLL1_FDECR=Decrement
bDPLL1_FINCR=Increment
bDPLL2_FDECR=Decrement
bDPLL2_FINCR=Increment
bDPLL3_FDECR=Decrement
bDPLL3_FINCR=Increment
bResetNumerator0ppb_DPLL1=Reload Original DPLL Numerator
bResetNumerator0ppb_DPLL2=Reload Original DPLL Numerator
bResetNumerator0ppb_DPLL3=Reload Original DPLL Numerator
bSet_GPIO_DCO_DPLL1=Set GPIO for DCO
bSet_GPIO_DCO_DPLL2=Set GPIO for DCO
bSet_GPIO_DCO_DPLL3=Set GPIO for DCO
cbDCO_MODE_DPLL1=0
cbDCO_MODE_DPLL2=0
cbDCO_MODE_DPLL3=0
sDPLL1_DCO_FREQPPB_ACT=Original DPLL1 Numerator unknown
sDPLL1_DCO_STEP=0
sDPLL1_DCO_STEP_ACT=0
sDPLL2_DCO_FREQPPB_ACT=Original DPLL2 Numerator unknown
sDPLL2_DCO_STEP=10366.604
sDPLL2_DCO_STEP_ACT=10366.6036356843
sDPLL3_DCO_FREQPPB_ACT=Not calculated
sDPLL3_DCO_STEP=0
sDPLL3_DCO_STEP_ACT=0
stDPLL1_PHS1_THRESH_time=1.24 ps
stDPLL1_PHS1_VAL=3.20 us
stDPLL2_PHS1_THRESH_time=13.34 fs
stDPLL2_PHS1_VAL=5.00 us
stDPLL3_PHS1_THRESH_time=36.34 fs
stDPLL3_PHS1_VAL=10.00 us
DPLL1_HIST_EXP_ud=18
DPLL1_HIST_MANT_ud=12
stDPLL1_HIST_VAL=1.01 s
DPLL2_HIST_EXP_ud=18
DPLL2_HIST_MANT_ud=12
stDPLL2_HIST_VAL=1.57 s
DPLL3_HIST_EXP_ud=18
DPLL3_HIST_MANT_ud=12
stDPLL3_HIST_VAL=3.15 s
btnScan_I2C=Scan I2C
st_save_info=0
st_save_vco_listboxes={'VCO2_selected_index': 0, 'VCO1_selected_index': 0, 'VCO3_selected_index': 0, 'VCO1_choices': [Fraction(4900, 1), Fraction(5000, 1), Fraction(5100, 1), Fraction(5200, 1), Fraction(4800, 1)], 'VCO2_choices': [Fraction(5600, 1), Fraction(5700, 1), Fraction(5800, 1)], 'VCO3_choices': [Fraction(2500, 1)]}