AIC3xxx PA_MiniDSP 005.095.35815.001 main Model.ADC3x01App2x_1 ADC3x01App2x_TI_v1 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 miniDSP_A_Adaptive 62 31 Enum RateAll Disabled main RateAll Disabled Adaptive mode for miniDSP_A Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled miniDSP_A_Cycles 62 31 Int RateAll 226 main RateAll 226 Available instruction cycles for miniDSP_A 128 256 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 2 0 1 0 1 Delay24bit false 226 miniDSP_A_Memory 62 31 Int RateAll 511 main RateAll 511 Available instruction memory for miniDSP_A 0 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 511 TargetType 62 31 String RateAll TypeB main RateAll TypeB -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false TypeB FrameworkType 62 31 0.00000011920928955078125 String RateAll ADC3101App2x main RateAll ADC3101App2x -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false ADC3101App2x SystemSettingsCode 62 31 0.00000011920928955078125 String RateAll ;IADC = %%prop(miniDSP_A_Cycles) reg[47][95]=0x00 ;zero fill the last memory location reg[47][96]=0x00 reg[47][97]=0x00 reg[0][1]=0x01 reg[0][61] = 0x00 ; reg(0)(0x3d => 61) ADC ADC prog mode reg[0][4] = 0x03 ; PLL_CLKIN = MCLK, CODEC_CLKIN=PLL_CLK reg[0][5] = 0x91 ; P=1, R=1 reg[0][6] = 0x08 ; J=8, settings are for fs = 88.2KHz reg[0][18] = 0x84 ; reg(0)(0x12 => 18) ADC Powerup NADC = 4, mkmkmk add an additional divide by 2 vs 3254 since only 512 instructions available reg[0][19] = 0x84 ; ADC Powerup MADC = 4 reg[0][27] = 0x00 ; reg(0)(0x1b => 27) Mode = i2s & wordlength = 16 reg[0][20] = 64 ; reg(0)(0x14 => 20) ADC AOSR = 64 reg[0][83] = 0x0 ; adc vol control = 0db reg[0][84] = 0x0 ; adc vol control = 0db reg[0][22] = 2 ; Decimation Ratio = 2 reg[0][21] = %%eval(%%prop(miniDSP_A_Cycles)/2) ; IADC; PROGRAM_MINIDSP_A reg[1][52] = 0xfc ; reg(1)(0x34 => 52) ADC IN1_L is selected for left P ;reg[1][54] = 0x3c ; reg(1)(0x36 => 54) ADC CM1 is selected for left M reg[1][55] = 0xfc ; reg(1)(0x37 => 55) ADC IN1_R is selected for right P ;reg[1][57] = 0x3c ; reg(1)(0x39 => 57) ADC CM1 is selected for right M reg[1][59] = 0x00 ; reg(1)(0x3b => 59) ADC unmute left mic PGA reg[1][60] = 0x00 ; reg(1)(0x3c => 60) ADC unmute right mic PGA reg[0][81] = 0xc2 ; reg(0)(0x51 => 81) ADC Powerup ADC left and right channels (soft-stepping disable) reg[0][82] = 0x00 ; reg(0)(0x52 => 82) ADC Unmute ADC left and right channels main RateAll ;IADC = %%prop(miniDSP_A_Cycles) reg[47][95]=0x00 ;zero fill the last memory location reg[47][96]=0x00 reg[47][97]=0x00 reg[0][1]=0x01 reg[0][61] = 0x00 ; reg(0)(0x3d => 61) ADC ADC prog mode reg[0][4] = 0x03 ; PLL_CLKIN = MCLK, CODEC_CLKIN=PLL_CLK reg[0][5] = 0x91 ; P=1, R=1 reg[0][6] = 0x08 ; J=8, settings are for fs = 88.2KHz reg[0][18] = 0x84 ; reg(0)(0x12 => 18) ADC Powerup NADC = 4, mkmkmk add an additional divide by 2 vs 3254 since only 512 instructions available reg[0][19] = 0x84 ; ADC Powerup MADC = 4 reg[0][27] = 0x00 ; reg(0)(0x1b => 27) Mode = i2s & wordlength = 16 reg[0][20] = 64 ; reg(0)(0x14 => 20) ADC AOSR = 64 reg[0][83] = 0x0 ; adc vol control = 0db reg[0][84] = 0x0 ; adc vol control = 0db reg[0][22] = 2 ; Decimation Ratio = 2 reg[0][21] = %%eval(%%prop(miniDSP_A_Cycles)/2) ; IADC; PROGRAM_MINIDSP_A reg[1][52] = 0xfc ; reg(1)(0x34 => 52) ADC IN1_L is selected for left P ;reg[1][54] = 0x3c ; reg(1)(0x36 => 54) ADC CM1 is selected for left M reg[1][55] = 0xfc ; reg(1)(0x37 => 55) ADC IN1_R is selected for right P ;reg[1][57] = 0x3c ; reg(1)(0x39 => 57) ADC CM1 is selected for right M reg[1][59] = 0x00 ; reg(1)(0x3b => 59) ADC unmute left mic PGA reg[1][60] = 0x00 ; reg(1)(0x3c => 60) ADC unmute right mic PGA reg[0][81] = 0xc2 ; reg(0)(0x51 => 81) ADC Powerup ADC left and right channels (soft-stepping disable) reg[0][82] = 0x00 ; reg(0)(0x52 => 82) ADC Unmute ADC left and right channels System settings reg[] code -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false ;IADC = %%prop(miniDSP_A_Cycles) reg[47][95]=0x00 ;zero fill the last memory location reg[47][96]=0x00 reg[47][97]=0x00 reg[0][1]=0x01 reg[0][61] = 0x00 ; reg(0)(0x3d => 61) ADC ADC prog mode reg[0][4] = 0x03 ; PLL_CLKIN = MCLK, CODEC_CLKIN=PLL_CLK reg[0][5] = 0x91 ; P=1, R=1 reg[0][6] = 0x08 ; J=8, settings are for fs = 88.2KHz reg[0][18] = 0x84 ; reg(0)(0x12 => 18) ADC Powerup NADC = 4, mkmkmk add an additional divide by 2 vs 3254 since only 512 instructions available reg[0][19] = 0x84 ; ADC Powerup MADC = 4 reg[0][27] = 0x00 ; reg(0)(0x1b => 27) Mode = i2s & wordlength = 16 reg[0][20] = 64 ; reg(0)(0x14 => 20) ADC AOSR = 64 reg[0][83] = 0x0 ; adc vol control = 0db reg[0][84] = 0x0 ; adc vol control = 0db reg[0][22] = 2 ; Decimation Ratio = 2 reg[0][21] = %%eval(%%prop(miniDSP_A_Cycles)/2) ; IADC; PROGRAM_MINIDSP_A reg[1][52] = 0xfc ; reg(1)(0x34 => 52) ADC IN1_L is selected for left P ;reg[1][54] = 0x3c ; reg(1)(0x36 => 54) ADC CM1 is selected for left M reg[1][55] = 0xfc ; reg(1)(0x37 => 55) ADC IN1_R is selected for right P ;reg[1][57] = 0x3c ; reg(1)(0x39 => 57) ADC CM1 is selected for right M reg[1][59] = 0x00 ; reg(1)(0x3b => 59) ADC unmute left mic PGA reg[1][60] = 0x00 ; reg(1)(0x3c => 60) ADC unmute right mic PGA reg[0][81] = 0xc2 ; reg(0)(0x51 => 81) ADC Powerup ADC left and right channels (soft-stepping disable) reg[0][82] = 0x00 ; reg(0)(0x52 => 82) ADC Unmute ADC left and right channels SystemSettingsXML 62 31 0.00000011920928955078125 String RateAll main RateAll System settings information -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false InstanceId 32 31 String RateAll ADC3x01App2x_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false ADC3x01App2x_1 Rate44 ADC3x01App2x Yellow 255 255 Yellow 90 Solid ADC3x01App2x_1 Black ADC3x01App2x_1 180 36 false false false false false false true false false false false false None ADC3101 TypeB ADC3101App2x 226 511 0 0 false 44100 44100 6056 all false false Model.MonoI2S_Out_1 MonoI2S_Out_TI_v1 InputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_A main RateAll miniDSP_A miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A InstanceId 32 31 String RateAll MonoI2S_Out_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false MonoI2S_Out_1 Rate44 MonoI2S_Out LightSteelBlue 255 255 Yellow 90 Solid MonoI2S_Out_1 Black MonoI2S_Out_1 756 180 false false false false false false true false false false false false None ADC3101 TypeB ADC3101App2x 226 511 0 0 false 44100 44100 5641 all false false Model.Probe_1 Probe_TI_v1 InputChannels 62 31 Enum RateAll 1 main RateAll 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 OutputChannels 62 31 Enum RateAll 1 main RateAll 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 TargetProcessor 62 31 Enum RateAll miniDSP_A main RateAll miniDSP_A Processor where this component instance resides miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A InstanceId 32 31 String RateAll Probe_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Probe_1 DSPCoefBlockStart1 62 31 Int RateAll 1 Probepoint 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 0 1 1 1 0 1 0 1 Delay24bit true 1 DSPCoefBlockLength1 62 31 Int RateAll 1 Probepoint 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 0 1 1 1 0 1 0 1 Delay24bit true 1 I2CPage1 62 31 Int RateAll 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 4 I2CRegister1 62 31 Int RateAll 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 2 DSPCoefBlockStart2 62 31 Int RateAll 0 Probepoint 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 0 2 2 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength2 62 31 Int RateAll 1 Probepoint 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 0 2 2 1 0 1 0 1 Delay24bit true 1 I2CPage2 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister2 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart3 62 31 Int RateAll 0 Probepoint 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 0 3 3 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength3 62 31 Int RateAll 1 Probepoint 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 0 3 3 1 0 1 0 1 Delay24bit true 1 I2CPage3 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister3 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart4 62 31 Int RateAll 0 Probepoint 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 0 4 4 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength4 62 31 Int RateAll 1 Probepoint 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 0 4 4 1 0 1 0 1 Delay24bit true 1 I2CPage4 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister4 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart5 62 31 Int RateAll 0 Probepoint 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 0 5 5 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength5 62 31 Int RateAll 1 Probepoint 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 0 5 5 1 0 1 0 1 Delay24bit true 1 I2CPage5 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister5 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart6 62 31 Int RateAll 0 Probepoint 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 0 6 6 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength6 62 31 Int RateAll 1 Probepoint 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 0 6 6 1 0 1 0 1 Delay24bit true 1 I2CPage6 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister6 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart7 62 31 Int RateAll 0 Probepoint 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 0 7 7 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength7 62 31 Int RateAll 1 Probepoint 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 0 7 7 1 0 1 0 1 Delay24bit true 1 I2CPage7 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister7 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart8 62 31 Int RateAll 0 Probepoint 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 0 8 8 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength8 62 31 Int RateAll 1 Probepoint 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 0 8 8 1 0 1 0 1 Delay24bit true 1 I2CPage8 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister8 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 Rate44 Probe LightGreen 255 255 Yellow 90 Solid Probe_1 Black Probe_1 492 336 false false false false false false true false false false false false None ADC3101 TypeB ADC3101App2x 226 511 0 0 false 44100 44100 5598 all false false Model.MonoDec1xIn_1 MonoDec1xIn_TI_v2 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_A main RateAll miniDSP_A miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A InstanceId 32 31 String RateAll MonoDec1xIn_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false MonoDec1xIn_1 AGC_Enable 62 31 0.00000011920928955078125 Enum RateAll Enable main RateAll Enable Enable Disable 128 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enable Volume_Control_dB 16 1 0.5 QFixed RateAll 0,0 main RateAll 0,0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -12,0 20.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0,0 Left_Fine_Gain 62 31 0.00000011920928955078125 Enum RateAll 0dB main RateAll 0dB 0dB -0.1dB -0.2dB -0.3dB -0.4db Muted 0 1 2 3 4 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0dB Right_Fine_Gain 62 31 0.00000011920928955078125 Enum RateAll 0dB main RateAll 0dB 0dB -0.1dB -0.2dB -0.3dB -0.4db Muted 0 1 2 3 4 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0dB Alpha 24 23 0.00000011920928955078125 QFixed RateAll 0,00560283660888671875 main RateAll 0,00560283660888671875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1,0 0.99999988079071044921875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0,00560283660888671875 1minus2alpha 24 23 0.00000011920928955078125 QFixed RateAll 0,9887943267822265625 main RateAll 0,9887943267822265625 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1,0 0.99999988079071044921875 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 0,9887943267822265625 Energy_Time_Constant_ms 62 31 0.000030517578125 Enum RateAll 2_ms main RateAll 2_ms 1_ms 2_ms 3_ms 4_ms 5_ms 6_ms 7_ms 8_ms 9_ms 10_ms 20_ms 30_ms 40_ms 50_ms 60_ms 70_ms 80_ms 90_ms 100_ms 150_ms 200_ms 250_ms 300_ms 350_ms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 2_ms AGC_Target_Level 62 31 0.00000011920928955078125 Enum RateAll -10dB main RateAll -10dB -5.5dB -8.0dB -10dB -12dB -14dB -17dB -20dB -24dB 0 1 2 3 4 5 6 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false -10dB AGC_Gain_Hysteresis 62 31 0.00000011920928955078125 Enum RateAll Disable main RateAll Disable Disable 0.5dB 1.0dB 1.5dB 0 1 2 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disable AGC_Hysteresis_Setting 62 31 0.00000011920928955078125 Enum RateAll Disable main RateAll Disable 1.0dB 2.0dB 4.0dB Disable 0 1 2 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disable AGC_Noise_Threshold 62 31 0.00000011920928955078125 Enum RateAll -90dB main RateAll -90dB Disable -30dB -32dB -34dB -36dB -38dB -40dB -42dB -44dB -46dB -48dB -50dB -52dB -54dB -56dB -58dB -60dB -62dB -64dB -66dB -68dB -70dB -72dB -74dB -76dB -78dB -80dB -82dB -84dB -86dB -88dB -90dB -28 -30 -32 -34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 -74 -76 -78 -80 -82 -84 -86 -88 -90 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 2 0 1 0 1 Delay24bit false -90dB AGC_Maximum_Gain 16 1 0.5 QFixed RateAll 0,0 main RateAll 0,0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 58.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0,0 AGC_Attack_Time 62 31 0.00000011920928955078125 Int RateAll 27 main RateAll 27 1 63 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 27 AGC_Attack_Time_Factor 62 31 0.00000011920928955078125 Enum RateAll 1x main RateAll 1x 1x 2x 4x 8x 16x 32x 64x 128x 0 1 2 3 4 5 6 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1x AGC_Decay_Time 62 31 0.00000011920928955078125 Int RateAll 43 main RateAll 43 1 63 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 43 AGC_Decay_Time_Factor 62 31 0.00000011920928955078125 Enum RateAll 1x main RateAll 1x 1x 2x 4x 8x 16x 32x 64x 128x 0 1 2 3 4 5 6 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1x AGC_Noise_Debounce_Time 62 31 0.00000011920928955078125 Enum RateAll 128x1WordCLK main RateAll 128x1WordCLK 0x1WordCLK 4x1WordCLK 8x1WordCLK 16x1WordCLK 32x1WordCLK 64x1WordCLK 128x1WordCLK 256x1WordCLK 512x1WordCLK 1024x1WordCLK 2048x1WordCLK 4096x1WordCLK 4096x2WordCLK 4096x3WordCLK 4096x4WordCLK 4096x5WordCLK 4096x6WordCLK 4096x7WordCLK 4096x8WordCLK 4096x9WordCLK 4096x10WordCLK 4096x11WordCLK 4096x12WordCLK 4096x13WordCLK 4096x14WordCLK 4096x15WordCLK 4096x16WordCLK 4096x17WordCLK 4096x18WordCLK 4096x19WordCLK 4096x20WordCLK 4096x21WordCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 128x1WordCLK AGC_Signal_Debounce_Time 62 31 0.00000011920928955078125 Enum RateAll 0x1WordCLK main RateAll 0x1WordCLK 0x1WordCLK 4x1WordCLK 8x1WordCLK 16x1WordCLK 32x1WordCLK 64x1WordCLK 128x1WordCLK 256x1WordCLK 512x1WordCLK 1024x1WordCLK 2048x1WordCLK 2048x2WordCLK 2048x3WordCLK 2048x4WordCLK 2048x5WordCLK 2048x6WordCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0x1WordCLK AGC_Gain_Flag 16 1 0.5 QFixed RateAll 0,0 main RateAll 0,0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -12,0 58.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0,0 AGC_HPF_n0 24 23 0.00000011920928955078125 QFixed RateAll 0,99999988079071044921875 main RateAll 0,99999988079071044921875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1,0 0.99999988079071044921875 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 0,99999988079071044921875 AGC_HPF_n1 24 23 0.00000011920928955078125 QFixed RateAll 0,0 main RateAll 0,0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1,0 0.99999988079071044921875 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 0,0 AGC_HPF_d1 24 23 0.00000011920928955078125 QFixed RateAll 0,0 main RateAll 0,0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1,0 0.99999988079071044921875 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 0,0 DSPCoefBlockStart1 62 31 Int RateAll 6 Alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 6 DSPCoefBlockLength1 62 31 Int RateAll 1 Alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage1 62 31 Int RateAll 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 4 I2CRegister1 62 31 Int RateAll 12 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 12 DSPCoefBlockStart2 62 31 Int RateAll 7 1minus2alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 7 DSPCoefBlockLength2 62 31 Int RateAll 1 1minus2alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage2 62 31 Int RateAll 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 4 I2CRegister2 62 31 Int RateAll 14 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 14 DSPCoefBlockStart3 62 31 Int RateAll 8 AGC HPF n0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 8 DSPCoefBlockLength3 62 31 Int RateAll 1 AGC HPF n0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage3 62 31 Int RateAll 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 4 I2CRegister3 62 31 Int RateAll 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 16 DSPCoefBlockStart4 62 31 Int RateAll 9 AGC HPF n1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 9 DSPCoefBlockLength4 62 31 Int RateAll 1 AGC HPF n1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage4 62 31 Int RateAll 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 4 I2CRegister4 62 31 Int RateAll 18 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 18 DSPCoefBlockStart5 62 31 Int RateAll 10 AGC HPF d1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 10 DSPCoefBlockLength5 62 31 Int RateAll 1 AGC HPF d1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage5 62 31 Int RateAll 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 4 I2CRegister5 62 31 Int RateAll 20 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 20 Rate44 MonoDec1xIn Yellow 255 255 Yellow 90 Solid MonoDec1xIn_1 Black MonoDec1xIn_1 204 252 false false false false false false true false false false false false None ADC3101 TypeB ADC3101App2x 226 511 0 0 false 44100 44100 5703 all false false Model.Probe_Data_1 Probe_Data_TI_v1 InputChannels 62 31 Enum RateAll 1 main RateAll 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 OutputChannels 62 31 Enum RateAll 1 main RateAll 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 TargetProcessor 62 31 Enum RateAll miniDSP_A main RateAll miniDSP_A Processor where this component instance resides miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A Instances 62 31 0.00000011920928955078125 Int RateAll 1 main RateAll 1 Number of instances of the algorithm in this component 1 16 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true 1 ProbeAddress1 62 31 0.000030517578125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress2 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress3 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress4 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress5 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress6 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress7 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress8 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress9 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress10 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress11 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 11 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress12 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 12 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress13 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 13 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress14 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 14 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress15 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 15 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 ProbeAddress16 62 31 0.00000011920928955078125 String RateAll 0 main RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 16 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 InstanceId 32 31 String RateAll Probe_Data_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Probe_Data_1 DSPCoefBlockStart1 62 31 Int RateAll 11 DSPCoefBlockStart1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 11 DSPCoefBlockLength1 62 31 Int RateAll 1 DSPCoefBlockStart1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage1 62 31 Int RateAll 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 4 I2CRegister1 62 31 Int RateAll 22 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 22 DSPCoefBlockStart2 62 31 Int RateAll 0 DSPCoefBlockStart2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength2 62 31 Int RateAll 1 DSPCoefBlockStart2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage2 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister2 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart3 62 31 Int RateAll 0 DSPCoefBlockStart3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength3 62 31 Int RateAll 1 DSPCoefBlockStart3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage3 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister3 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart4 62 31 Int RateAll 0 DSPCoefBlockStart4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength4 62 31 Int RateAll 1 DSPCoefBlockStart4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage4 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister4 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart5 62 31 Int RateAll 0 DSPCoefBlockStart5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength5 62 31 Int RateAll 1 DSPCoefBlockStart5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage5 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister5 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart6 62 31 Int RateAll 0 DSPCoefBlockStart6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 6 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength6 62 31 Int RateAll 1 DSPCoefBlockStart6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 6 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage6 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister6 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart7 62 31 Int RateAll 0 DSPCoefBlockStart7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 7 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength7 62 31 Int RateAll 1 DSPCoefBlockStart7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 7 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage7 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister7 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart8 62 31 Int RateAll 0 DSPCoefBlockStart8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 8 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength8 62 31 Int RateAll 1 DSPCoefBlockStart8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 8 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage8 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister8 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart9 62 31 Int RateAll 0 DSPCoefBlockStart9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 9 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength9 62 31 Int RateAll 1 DSPCoefBlockStart9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 9 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage9 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister9 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart10 62 31 Int RateAll 0 DSPCoefBlockStart10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 10 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength10 62 31 Int RateAll 1 DSPCoefBlockStart10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 10 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage10 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister10 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart11 62 31 Int RateAll 0 DSPCoefBlockStart11 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 11 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength11 62 31 Int RateAll 1 DSPCoefBlockStart11 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 11 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage11 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister11 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart12 62 31 Int RateAll 0 DSPCoefBlockStart12 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 12 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength12 62 31 Int RateAll 1 DSPCoefBlockStart12 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 12 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage12 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister12 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart13 62 31 Int RateAll 0 DSPCoefBlockStart13 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 13 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength13 62 31 Int RateAll 1 DSPCoefBlockStart13 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 13 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage13 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister13 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart14 62 31 Int RateAll 0 DSPCoefBlockStart14 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 14 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength14 62 31 Int RateAll 1 DSPCoefBlockStart14 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 14 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage14 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister14 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart15 62 31 Int RateAll 0 DSPCoefBlockStart15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 15 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength15 62 31 Int RateAll 1 DSPCoefBlockStart15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 15 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage15 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister15 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart16 62 31 Int RateAll 0 DSPCoefBlockStart16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 16 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength16 62 31 Int RateAll 1 DSPCoefBlockStart16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false 16 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage16 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister16 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 Rate44 Probe_Data LightGreen 255 255 Yellow 90 Solid Probe_Data_1 Black Probe_Data_1 360 336 false false false false false false true false false false false false None ADC3101 TypeB ADC3101App2x 226 511 0 0 false 44100 44100 5733 all false false Model.MonoDec1xIn_1 Model.Probe_Data_1 Model.MonoDec1xIn_1.Ch1_Out Model.Probe_Data_1.Ch1_In 228 264 359.999969 347.999969 Black 2 Model.MonoDec1xIn_1.Ch1_Out Model.Probe_Data_1.Ch1_In Model.MonoDec1xIn_1 Model.Probe_Data_1 false all Probe_Data_TI_v1 MonoDec1xIn_TI_v2 Model.Probe_Data_1 Model.Probe_1 Model.Probe_Data_1.Ch1_Out Model.Probe_1.Ch1_In 383.999969 347.999969 491.999969 347.999969 Black 2 Model.Probe_Data_1.Ch1_Out Model.Probe_1.Ch1_In Model.Probe_Data_1 Model.Probe_1 false all Probe_TI_v1 Probe_Data_TI_v1 Model.Probe_1 Model.MonoI2S_Out_1 Model.Probe_1.Ch1_Out Model.MonoI2S_Out_1.Ch1_In 515.999939 347.999969 756 192 Black 2 Model.Probe_1.Ch1_Out Model.MonoI2S_Out_1.Ch1_In Model.Probe_1 Model.MonoI2S_Out_1 false all MonoI2S_Out_TI_v1 Probe_TI_v1 0 0 1000 800 0 0 1000 800 &F &d &T &p/&P White PowderBlue Rate44 RateAll false false false false false false true false false false false false main base base 1 main Rate44 false false false false false false true false false false false false true false