//*****************************************************************************
//! @file       cc26x0f128.icf
//! @brief      CC26x0F128 PG2 linker configuration file for IAR EWARM.
//!
//! Revised     $Date: 2015-07-21 13:39:51 +0200 (ti, 21 jul 2015) $
//! Revision    $Revision: 15951 $
//
//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
//
//
//  Redistribution and use in source and binary forms, with or without
//  modification, are permitted provided that the following conditions
//  are met:
//
//    Redistributions of source code must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//
//    Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimer in the
//    documentation and/or other materials provided with the distribution.
//
//    Neither the name of Texas Instruments Incorporated nor the names of
//    its contributors may be used to endorse or promote products derived
//    from this software without specific prior written permission.
//
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//****************************************************************************/


/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__   = 0x0001FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__   = 0x1000;
/**** End of ICF editor section. ###ICF###*/

define symbol __FLASH_START__   = 0x00000000;
define symbol __FLASH_END__     = 0x0001FFFF;
define symbol __FLASH_SIZE__    = 0x00020000;
define symbol __FLASH_SECTOR_SIZE__ = 0x1000;

define symbol __GPRAM_START__   = 0x11000000;
define symbol __GPRAM_END__     = 0x11001FFF;

//
// Define a memory region that covers the entire 4 GB addressable space of the
// processor.
//
define memory mem with size = 4G;

//
// Define a region for the on-chip flash.
//
define region FLASH_region   = mem:[from __FLASH_START__ size __FLASH_SECTOR_SIZE__] | mem:[from __FLASH_START__ + __FLASH_SIZE__ - __FLASH_SECTOR_SIZE__ size __FLASH_SECTOR_SIZE__] ;
define region FLASH_LAST_SECT_region = mem:[from __FLASH_START__ + __FLASH_SIZE__ - __FLASH_SECTOR_SIZE__ size __FLASH_SECTOR_SIZE__] ;

//
// Define a region for the on-chip SRAM.
//
define region SRAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];

//
// Place the interrupt vectors at the start of flash.
//
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
keep { section .intvec };

//
// Place the CCFG area at the end of flash
//
place at end of FLASH_LAST_SECT_region { readonly section .ccfg };
keep { section .ccfg };

//
// Place remaining 'read only' in Flash
//
place in FLASH_region { readonly };


//
// Place .vtable_ram in start of RAM
//
place at start of SRAM_region { section .vtable_ram };

//
// Define CSTACK block to contain .stack section. This enables the IAR IDE
// to properly show the stack content during debug. Place stack at end of
// retention RAM, do not initialize (initializing the stack will destroy the
// return address from the initialization code, causing the processor to branch
// to zero and fault)
//
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { section .stack };
place at end of SRAM_region { block CSTACK };
do not initialize { section .stack, section .noinit};

//
// Export stack top symbol. Used by startup file.
//
define exported symbol STACK_TOP = __ICFEDIT_region_RAM_end__ + 1;

//
// Define a block for the heap.  The size should be set to something other
// than zero if things in the C library that require the heap are used.
//
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place in SRAM_region { block HEAP };

//
// Place all read/write items into RAM.
//
place in SRAM_region   { readwrite };
initialize by copy { readwrite };

//
// The USE_TIRTOS_ROM symbol is defined internally in the build flow (using
// --config_def USE_TIRTOS_ROM=1) for TI-RTOS applications whose app.cfg file
// specifies to use the ROM.
//
if (isdefinedsymbol(USE_TIRTOS_ROM)) {
    include "TIRTOS_ROM.icf";
}

//
// Define a region for the on-chip GPRAM/cache. 
// Application can use this region as RAM if cache is disabled in the CCFG
// (DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0)
//
define region GPRAM_region    = mem:[from __GPRAM_START__ to __GPRAM_END__];
place in GPRAM_region {section .gpram};

