# The following script is used for playback via USB 

# RESET RESET THIS IS MASTER RESET FOR SRC (48kHz)

# Page 0 = DEFAULT for Control

# Write to page 0
w E0 7F 00

# Register 01, Bit 7 = 1 resets to default
d 100
w E0 01 80

# Delay 0.1 sec to allow part to reset
d 100

# Systeme mode "StandbyMode"
w E0 02 01 
# Disable all clock missing detectors and clock auto mode
w E0 25 7F 

# Register 01, Bit 7 = 0 for normal operation
w E0 01 00
d 100

#----- Setup Port A ------#

# power on port A and B
w E0 01 38

# set up port A as master, 24 bit I2S sourced from port B
w E0 03 19 

# PLL enable 
w E0 04 01

# port B slave, 24 bit I2S
w E0 05 01 


#----- PLL Configuration -----#

# Registers configured by default cannot be written
w E0 0F 22
w E0 10 1B
w E0 11 A3

# PLLCK = CLKIN x R x (J.D) / P = 11.3MHz x 1 x 8 / 1 = 90.316 MHz
# PLL clock source = SCK
w E0 0D 00 
# P = 1
w E0 14 00 
# J = 8
w E0 15 08 
# Decimal value = 0
# R = 0
w E0 18 00 

#DSP CLK = PLLCLK/DDSP = 90.316 MHz /2 = 45.15 MHz
# division by 2
w E0 1B 01 
# DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz
# Division by 16
w E0 1C 0F 
# CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz
# Division by  4
w E0 1D 03 
#  Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz
# Division by 8
w E0 1E 07 


#----- GPIO Configuration -----#
# GPIO1 Config
# GPIO1 = RCVR non-audio data
w E0 1B 06
# GPIO2 Config
# GPIO2 = RCVR non-valid data
w E0 1C 07

# Power Status
# Disable RCVR (/PDRX) and Port B(/PDPB) power down and enable All Function power down
#w E0 01 14

#w E0 03 29