u16 codec_initial_CH1_2[CODEC_SIZE] =
{
// MCLK = 12.288 Mhz(WCLK * 256)) / BCLK = 3.072 Mhz(WCLK * 64) / WCLK = 48khz
// PCM 24 Fix
////////////////Page 0////////////////// Example Page 87
0x0000,
0x0400,	// PLL_CLKIN=MCLK, CODEC_CLKIN=MCLK

///////////////DAC Set////////////////////
0x0B81,	// NDAC=1 powered up
0x0C82,	// MDAC=2 powered up
0x0D00,	// MSB DOSR=0
0x0E80,	// DOSR=128
0x1B20,	// I2S, 24 bits, slave mode
0x3C01,	// PRB_P1

///////////////ADC Set////////////////////
0x1281,	// NADC=1 powered up
0x1382,	// MADC=2 powered up
0x1480,	// AOSR=128
0x3D01,	// PRB_R1

////////////////Page 1//////////////////
0x0001,
0x0108,	// Disabled AVDD to DVDD -> AVDD is powered and provided externally
0x0200,	// DVDD=1.72V, Analog block enabled, AVDD LDO powered down

///////////////DAC Set////////////////////
0x0300,	// Left DAC to HPL with class-AB
0x0400,	// Right DAC to HPL with class-AB
0x0930,	// HPL and HPR powered by AVDD
0x0C08,	// Left DAC + term to HPL
0x0D08,	// Right DAC + term to HPR
0x1000,	// HPL not muted with 0dB gain
0x1100,	// HPR not muted with 0dB gain
0x1425,	// HP driver ramp up 5 Tc
0x1675,	// IN1L to HPL volume muted
0x1775,	// IN1R to HPR volume muted
0x1828,	// MAL volume muted
0x1928,	// MAR volume muted

///////////////ADC Set////////////////////
0x0A00,	// CM=0.9V for HPL and HPR powered with AVDD
0x3D00,	// Powertune PTM_R4
0x4732,	// Analog input powered up in 6.4ms
0x7B01,	// Reference power up in 40ms
0x34C0,	// IN1L to Left PGA with 40K
0x36C0,	// CM to Left PGA with 40K
0x37C0,	// IN1R to Right PGA with 40K
0x39C0,	// CM to Right PGA with 40K
0x3B80,	// Left PGA Gain = 0dB
0x3C80,	// Right PGA Gain = 0dB

////////////////Page 0//////////////////
0x0000,
0x3FD6,	// Left and Right DAC powered up 
0x4000,	// Left and Right DAC not muted
0x4100,	// Left Digital volume = 0dB
0x4200,	// Right Digital volume = 0dB

0x51C0,	// Left and Right ADC powered up
0x5200,	// Left and Right ADC not muted with gain = 0dB
0x5300,	// Left ADC volume = 0dB
0x5400,	// Right ADC volume = 0dB