AIC3xxx PA_MiniDSP 005.095.35815.001 main Model.AIC3268App8x4x_1 AIC3268App8x4x_TI_v1 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 miniDSP_A_Adaptive 62 31 0.00000011920928955078125 Enum RateAll Enabled main RateAll Enabled Adaptive mode for miniDSP_A Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled miniDSP_A_Cycles 62 31 0.00000011920928955078125 Int RateAll 1024 main RateAll 1024 Available instruction cycles for miniDSP_A 256 6144 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 4 0 1 0 1 Delay24bit false 1024 miniDSP_A_Memory 62 31 Int RateAll 1536 main RateAll 1536 Available instruction memory for miniDSP_A 0 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1536 miniDSP_D_Adaptive 62 31 Enum RateAll Enabled main RateAll Enabled Adaptive mode for miniDSP_D Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled miniDSP_D_Memory 62 31 Int RateAll 3072 main RateAll 3072 Available instruction memory for miniDSP_D 0 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 3072 miniDSP_D_Cycles 62 31 Int RateAll 1024 main RateAll 1024 Available instruction cycles for miniDSP_D 352 6144 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 8 0 1 0 1 Delay24bit false 1024 FrameworkType 62 31 0.00000011920928955078125 String RateAll AIC3268App8x4x main RateAll AIC3268App8x4x -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false AIC3268App8x4x TargetType 62 31 0.00000011920928955078125 String RateAll TypeC main RateAll TypeC -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false TypeC SystemSettingsCode 62 31 0.00000011920928955078125 String RateAll reg[0][0][1] = 0x01 ; reg(0)(1)(0x00 => 0 ) S/W Reset reg[0][0][4] = 0x33 ; ADC_CLKIN = PLL_MCLK, DAC_CLKIN = PLL_MCLK reg[0][0][5] = 0x00 ; PLL_CLKIN = MCLK1 reg[0][0][6] = 0x91 ; P=1, R=1 %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) reg[0][0][7] = 0x07 ; P=1, R=1, J=7 reg[0][0][13] = 0x00 ; DOSR = 128 (MSB) reg[0][0][14] = 0x80 ; DOSR = 128 (LSB) reg[0][0][18] = 0x07 ; NADC Powerdown NADC = 2 reg[0][0][19] = 0x82 ; NADC Powerup MADC = 2 reg[0][0][20] = 0x80 ; AOSR = 128 %%endif %%if (%%prop(SynchMode) == 1) reg[0][0][11] = 0x07 ; NDAC = 7, divider powered off %%else reg[0][0][11] = 0x87 ; NDAC = 7, divider powered on %%endif reg[0][0][8] = 0x06 ; D=1680 (MSB) reg[0][0][9] = 0x90 ; D=1680 (LSB) reg[0][0][10] = 0x01 ; PLL_CLKIN_DIV=1 reg[0][0][12] = 0x82 ; reg(0)(0)(0x0c => 12) DAC Powerup MDAC = 2 reg[120][0][50] = 0x88 ; Interpolation Ratio is 8, FIFO = Enabled reg[100][0][50] = 0xa4 ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled %%if (%%prop(SynchMode) == 1) reg[0][0][60] = 0x80 ; reg(0)(0)(0x3c => 60) DAC prog Mode, DAC & ADC filter engines powered up together %%else reg[0][0][60] = 0x00 ; reg(0)(0)(0x3c => 60) DAC prog Mode, DAC & ADC filter engines not powered up together %%endif reg[0][0][61] = 0x00 ; reg(0)(0)(0x3d => 61) ADC prog mode reg[0][0][83] = 0x0 ; adc vol control = 0db reg[0][0][84] = 0x0 ; adc vol control = 0db reg[0][1][1 ] = 0x00 ; reg(0)(1)(0x01 => 0 ) Crude avdd disabled reg[0][1][3 ] = 0x00 ; reg(0)(1)(0x03 => 3 ) LDAC FIR reg[0][1][4 ] = 0x00 ; reg(0)(1)(0x04 => 4 ) RDAC FIR ;reg[0][1][11] = 0x35 ; reg(0)(1)(0xB =>11 ) DePop HP reg[0][1][31] = 0x80 ; reg(0)(1)(0x1F =>31 ) HP in ground Centered mode; HPL gain 0 dB reg[0][1][32] = 0x00 ; reg(0)(1)(0x20 =>32 ) HPR independent gain 0 dB reg[0][1][33] = 0x28 ; reg(0)(1)(0x21 =>33 ) Charge pump runs on Osc./4 reg[0][1][34] = 0x33 ;0x3e ; reg(0)(1)(0x22 =>34 ) Set CP mode reg[0][1][35] = 0x10 ; reg(0)(1)(0x23 =>35 ) Power up CP with HP reg[0][1][52] = 0x40 ; reg(0)(1)(0x34 => 52) ADC IN1_L is selected for left P reg[0][1][54] = 0x40 ; reg(0)(1)(0x36 => 54) ADC CM1 is selected for left M reg[0][1][55] = 0x40 ; reg(0)(1)(0x37 => 55) ADC IN1_R is selected for right P reg[0][1][57] = 0x40 ; reg(0)(1)(0x39 => 57) ADC CM1 is selected for right M reg[0][1][121] = 0x33 ; reg(0)(1)(0x79 => 121) Quick charge time for Mic inputs reg[0][1][122] = 0x01 ; reg(0)(1)(0x7A => 122) Vref charge time - 40 ms. PROGRAM_MINIDSP_A PROGRAM_MINIDSP_D %%if (%%prop(miniDSP_A_Adaptive) == 1) reg[40][0][1] = 0x04 ; adaptive mode for ADC %%endif %%if (%%prop(miniDSP_D_Adaptive) == 1) reg[80][0][1] = 0x04 ; adaptive mode for DAC %%endif ;IADC = %%prop(miniDSP_A_Cycles) ; ;IDAC = %%prop(miniDSP_D_Cycles) ; %%if (%%prop(SynchMode) == 1) %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) ;IDAC = %%eval(8*128) ; MDAC*DOSR ;IADC = %%eval(8*128) ; MADC*AOSR reg[100][0][48] = 4 reg[100][0][49] = 0 reg[120][0][48] = 4 reg[120][0][49] = 0 %%endif %%else // Asych mode reg[100][0][48] = %%eval(Math.floor(%%prop(miniDSP_A_Cycles)/256)) reg[100][0][49] = %%eval(%%prop(miniDSP_A_Cycles) - Math.floor(%%prop(miniDSP_A_Cycles)/256)*256) reg[120][0][48] = %%eval(Math.floor(%%prop(miniDSP_D_Cycles)/256)) reg[120][0][49] = %%eval(%%prop(miniDSP_D_Cycles) - Math.floor(%%prop(miniDSP_D_Cycles)/256)*256) %%endif reg[0][0][63] = 0xc2 ; reg(0)(0)(0x3f => 63) DAC L&R DAC powerup Ldata-LDAC Rdata-RDAC (soft-stepping disable) reg[0][0][64] = 0x00 ; reg(0)(0)(0x40 => 64) DAC Left and Right DAC unmuted with indep. vol. ctrl %%if (%%prop(Include_DigMic) == 1) reg[0][0][81] = 0xd6 ; reg(0)(0)(0x51 => d6) ADC Powerup ADC left and right channels in Digital mode(soft-stepping disable) %%else reg[0][0][81] = 0xc2 ; reg(0)(0)(0x51 => 81) ADC Powerup ADC left and right channels (soft-stepping disable) %%endif reg[0][0][82] = 0x00 ; reg(0)(0)(0x52 => 82) ADC Unmute ADC left and right channels,L,R fine gain=0dB reg[0][1][27] = 0x33 ; reg(0)(1)(0x1B =>27 ) LDAC -> HPL, RDAC -> HPR; Power on HPL + HPR reg[0][1][59] = 0x00 ; reg(0)(1)(0x3b => 59) ADC unmute left mic PGA with 0 dB gain reg[0][1][60] = 0x00 ; reg(0)(1)(0x3c => 60) ADC unmute right mic PGA with 0 dB gain ;ASI1 reg[0][4][1] = 0x38 ; asi1 audio format DSP/32bit/Dout not high imp reg[0][4][2] = 0x00 ; asi1 left chn offset ;reg[0][4][3] = 0x20 ; asi1 right chn offset reg[0][4][3] = 0x00 ; asi1 right chn offset reg[0][4][4] = 0xC0 ; asi1 chn setup DAC&ADC left & right chns reg[0][4][4] = 0x00 ; asi1 chn setup DAC&ADC left & right chns reg[0][4][5] = 0x00 ; asi1 adc bus format Use R1 settings reg[0][4][6] = 0x00 ; asi1 multipin Data in & out single pins reg[0][4][7] = 0x01 ; asi1 adc input ctrl minidsp ADC data fed to ASI1 ;reg[0][4][8] = 0x51 ; asi1 dac data path left-left right-right, tdm -mode reg[0][4][8] = 0x50 ; asi1 dac data path left-left right-right reg[0][4][9] = 0x00 ; asi1 adc chn tristate nothing tristated reg[0][4][10] = 0x24 ; asi1 clock outputs bclk & wclk output reg[0][4][11] = 0x02 ; asi1 bit clock adc/dac clk 12.28MHz reg[0][4][12] = 0x81 ; asi1 bit clk n-div 1 reg[0][4][13] = 0x80 ; asi1 word clk n-div 128 reg[0][4][14] = 0x01 ; asi1 bclk & wclk output bclk->div outp, wclk->adc_fs clk reg[0][4][15] = 0x00 ; asi1 dout1 from asi1 reg[0][4][16] = 0x00 ; asi1 bclk & wclk adc same as dac ;ASI2 reg[0][4][17] = 0x00 ;asi2 format ctrl i2s, 16bit, not Hi-Z reg[0][4][18] = 0x00 ;asi2 data offset 0 bclks reg[0][4][21] = 0x00 ;asi2 adc format sames as r17 ;reg[0][4][21] = 0x3C ;asi2 secondary adc format DSP, 32-bit, this reg ;reg[0][4][23] = 0x01 ;asi2 format ctrl asi2[1:2] = minidsp_a_dataoutput[1:2] ;reg[0][4][23] = 0x03 ;asi2 format ctrl asi2[1:2] = asi2[1:2] reg[0][4][23] = 0x05 ;asi2 format ctrl asi2[1:2] = minidsp_a_dataoutput[3:4] reg[0][4][24] = 0x50 ;asi2 dac output ctrl left - dac data left, right - dac data right reg[0][4][26] = 0x24 ;asi2 wrd/bit ctrl bclk and wclk as output reg[0][4][27] = 0x02 ;asi2 bdiv input ADC_CLK reg[0][4][28] = 0x88 ;asi2 bclk div powered up, 8 reg[0][4][29] = 0xA0 ;asi2 wclk div powered up, 32 reg[0][4][30] = 0x24 ;asi2 bclk, wclk output bclk - div outp, wclk - div outp reg[0][4][31] = 0x00 ;asi2 dout DOUT2 from ASI2 reg[0][4][32] = 0x00 ;asi2 adc w/bclk wclk - same as dac wclk, bclk - same as dac bclk ;ASI3 reg[0][4][33] = 0x00 ;asi3 format ctrl i2s, 16bit, not Hi-Z reg[0][4][34] = 0x00 ;asi3 data offset 0 bclks ;reg[0][4][37] = 0x3C ;asi3 tertiary data format DSP, 32-bit reg[0][4][37] = 0x00 ;asi3 tertiary data format same as r33 ;reg[0][4][39] = 0x04 ;asi3 ADC inp ctrl asi3[1:2] = asi3[1:2] reg[0][4][39] = 0x06 ;asi3 ADC inp ctrl asi3[1:2] = minidsp_a_dataoutput[5:6] reg[0][4][40] = 0x50 ;asi3 dac output ctrl left - dac data left, right - dac data right reg[0][4][42] = 0x00 ;asi3 wrd/bit clk ctrl bclk default polarity, b/wclk power down when codec power down reg[0][4][43] = 0x02 ;asi3 bdiv input ADC_CLK reg[0][4][44] = 0x88 ;asi3 bclk div powered up, 8 reg[0][4][45] = 0xA0 ;asi3 wclk div powered up, 32 reg[0][4][46] = 0x46 ;asi3 bclk, wclk output bclk - div outp, wclk - div outp reg[0][4][47] = 0x00 ;asi3 dout DOUT3 from ASI3 reg[0][4][55] = 0x21 ;asi3 GPIO1/2 GPIO1 - ASI3_BCLK, GPIO2 - ASI3_WCLK reg[0][4][56] = 0x03 ;asi3 GPIO3 GPIO3 - ASI3_DIN reg[0][4][86] = 0x54 ;asi3 GPIO1 GPIO1 - ASI3_BCLK reg[0][4][87] = 0x50 ;asi3 GPIO2 GPIO1 - ASI3_WCLK reg[0][4][88] = 0x04 ;asi3 GPIO3 GPIO3 - ASI3_DIN reg[0][4][89] = 0x74 ;asi3 GPIO4 GPIO4 - ASI3_DOUT %%if (%%prop(SynchMode) == 1) reg[100][0][20] = 0x00 ; Disable ADC double buffer mode reg[120][0][20] = 0x00 ; Disable DAC double buffer mode %%else reg[100][0][20] = 0x80 ; Enable ADC double buffer mode reg[120][0][20] = 0x80 ; Enable DAC double buffer mode %%endif %%if (%%prop(SynchMode) == 1) reg[0][0][11] = 0x87 ; NDAC = 2, divider powered off %%endif %%if (%%prop(Include_MultiDigital) == 1) ; Assume CODEC slave mode for Multi channel, For master mode uncomment the reg writes below reg[0][4][1] = 0x20 ; ASI1 Audio Interface = DSP mode ;reg[0][4][11] = 0x01 ; DAC_MOD_CLK = ASI1_BDIV_CLKIN %%if (%%prop(Multi_I2S_Num_In_Channels) == 8) reg[0][4][4] = 0xc0 ;reg[0][4][12] = 0x81 ; ASI1 master, BCLK = 6.144Mhz ;reg[0][4][13] = 0x80 ; ASI1_WDIV = 128 %%endif %%if (%%prop(Multi_I2S_Num_In_Channels) == 6) reg[0][4][4] = 0x80 %%endif %%if (%%prop(Multi_I2S_Num_In_Channels) == 4) reg[0][4][4] = 0x40 ; For 4 channel digmic, ;reg[0][4][12] = 0x82 ; ASI1 master, BCLK = 3.072Mhz ;reg[0][4][13] = 0xc0 ; ASI1_WDIV = 64 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 8) reg[0][4][4] = 0xc0 ;reg[0][4][12] = 0x81 ; ASI1 master, BCLK = 6.144Mhz ;reg[0][4][13] = 0x80 ; ASI1_WDIV = 128 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 6) reg[0][4][4] = 0x80 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 4) reg[0][4][4] = 0x40 ;reg[0][4][12] = 0x82 ; ASI1 master, BCLK = 3.072Mhz ;reg[0][4][13] = 0xc0 ; ASI1_WDIV = 64 %%endif %%endif main RateAll reg[0][0][1] = 0x01 ; reg(0)(1)(0x00 => 0 ) S/W Reset reg[0][0][4] = 0x33 ; ADC_CLKIN = PLL_MCLK, DAC_CLKIN = PLL_MCLK reg[0][0][5] = 0x00 ; PLL_CLKIN = MCLK1 reg[0][0][6] = 0x91 ; P=1, R=1 %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) reg[0][0][7] = 0x07 ; P=1, R=1, J=7 reg[0][0][13] = 0x00 ; DOSR = 128 (MSB) reg[0][0][14] = 0x80 ; DOSR = 128 (LSB) reg[0][0][18] = 0x07 ; NADC Powerdown NADC = 2 reg[0][0][19] = 0x82 ; NADC Powerup MADC = 2 reg[0][0][20] = 0x80 ; AOSR = 128 %%endif %%if (%%prop(SynchMode) == 1) reg[0][0][11] = 0x07 ; NDAC = 7, divider powered off %%else reg[0][0][11] = 0x87 ; NDAC = 7, divider powered on %%endif reg[0][0][8] = 0x06 ; D=1680 (MSB) reg[0][0][9] = 0x90 ; D=1680 (LSB) reg[0][0][10] = 0x01 ; PLL_CLKIN_DIV=1 reg[0][0][12] = 0x82 ; reg(0)(0)(0x0c => 12) DAC Powerup MDAC = 2 reg[120][0][50] = 0x88 ; Interpolation Ratio is 8, FIFO = Enabled reg[100][0][50] = 0xa4 ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled %%if (%%prop(SynchMode) == 1) reg[0][0][60] = 0x80 ; reg(0)(0)(0x3c => 60) DAC prog Mode, DAC & ADC filter engines powered up together %%else reg[0][0][60] = 0x00 ; reg(0)(0)(0x3c => 60) DAC prog Mode, DAC & ADC filter engines not powered up together %%endif reg[0][0][61] = 0x00 ; reg(0)(0)(0x3d => 61) ADC prog mode reg[0][0][83] = 0x0 ; adc vol control = 0db reg[0][0][84] = 0x0 ; adc vol control = 0db reg[0][1][1 ] = 0x00 ; reg(0)(1)(0x01 => 0 ) Crude avdd disabled reg[0][1][3 ] = 0x00 ; reg(0)(1)(0x03 => 3 ) LDAC FIR reg[0][1][4 ] = 0x00 ; reg(0)(1)(0x04 => 4 ) RDAC FIR ;reg[0][1][11] = 0x35 ; reg(0)(1)(0xB =>11 ) DePop HP reg[0][1][31] = 0x80 ; reg(0)(1)(0x1F =>31 ) HP in ground Centered mode; HPL gain 0 dB reg[0][1][32] = 0x00 ; reg(0)(1)(0x20 =>32 ) HPR independent gain 0 dB reg[0][1][33] = 0x28 ; reg(0)(1)(0x21 =>33 ) Charge pump runs on Osc./4 reg[0][1][34] = 0x33 ;0x3e ; reg(0)(1)(0x22 =>34 ) Set CP mode reg[0][1][35] = 0x10 ; reg(0)(1)(0x23 =>35 ) Power up CP with HP reg[0][1][52] = 0x40 ; reg(0)(1)(0x34 => 52) ADC IN1_L is selected for left P reg[0][1][54] = 0x40 ; reg(0)(1)(0x36 => 54) ADC CM1 is selected for left M reg[0][1][55] = 0x40 ; reg(0)(1)(0x37 => 55) ADC IN1_R is selected for right P reg[0][1][57] = 0x40 ; reg(0)(1)(0x39 => 57) ADC CM1 is selected for right M reg[0][1][121] = 0x33 ; reg(0)(1)(0x79 => 121) Quick charge time for Mic inputs reg[0][1][122] = 0x01 ; reg(0)(1)(0x7A => 122) Vref charge time - 40 ms. PROGRAM_MINIDSP_A PROGRAM_MINIDSP_D %%if (%%prop(miniDSP_A_Adaptive) == 1) reg[40][0][1] = 0x04 ; adaptive mode for ADC %%endif %%if (%%prop(miniDSP_D_Adaptive) == 1) reg[80][0][1] = 0x04 ; adaptive mode for DAC %%endif ;IADC = %%prop(miniDSP_A_Cycles) ; ;IDAC = %%prop(miniDSP_D_Cycles) ; %%if (%%prop(SynchMode) == 1) %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) ;IDAC = %%eval(8*128) ; MDAC*DOSR ;IADC = %%eval(8*128) ; MADC*AOSR reg[100][0][48] = 4 reg[100][0][49] = 0 reg[120][0][48] = 4 reg[120][0][49] = 0 %%endif %%else // Asych mode reg[100][0][48] = %%eval(Math.floor(%%prop(miniDSP_A_Cycles)/256)) reg[100][0][49] = %%eval(%%prop(miniDSP_A_Cycles) - Math.floor(%%prop(miniDSP_A_Cycles)/256)*256) reg[120][0][48] = %%eval(Math.floor(%%prop(miniDSP_D_Cycles)/256)) reg[120][0][49] = %%eval(%%prop(miniDSP_D_Cycles) - Math.floor(%%prop(miniDSP_D_Cycles)/256)*256) %%endif reg[0][0][63] = 0xc2 ; reg(0)(0)(0x3f => 63) DAC L&R DAC powerup Ldata-LDAC Rdata-RDAC (soft-stepping disable) reg[0][0][64] = 0x00 ; reg(0)(0)(0x40 => 64) DAC Left and Right DAC unmuted with indep. vol. ctrl %%if (%%prop(Include_DigMic) == 1) reg[0][0][81] = 0xd6 ; reg(0)(0)(0x51 => d6) ADC Powerup ADC left and right channels in Digital mode(soft-stepping disable) %%else reg[0][0][81] = 0xc2 ; reg(0)(0)(0x51 => 81) ADC Powerup ADC left and right channels (soft-stepping disable) %%endif reg[0][0][82] = 0x00 ; reg(0)(0)(0x52 => 82) ADC Unmute ADC left and right channels,L,R fine gain=0dB reg[0][1][27] = 0x33 ; reg(0)(1)(0x1B =>27 ) LDAC -> HPL, RDAC -> HPR; Power on HPL + HPR reg[0][1][59] = 0x00 ; reg(0)(1)(0x3b => 59) ADC unmute left mic PGA with 0 dB gain reg[0][1][60] = 0x00 ; reg(0)(1)(0x3c => 60) ADC unmute right mic PGA with 0 dB gain ;ASI1 reg[0][4][1] = 0x38 ; asi1 audio format DSP/32bit/Dout not high imp reg[0][4][2] = 0x00 ; asi1 left chn offset ;reg[0][4][3] = 0x20 ; asi1 right chn offset reg[0][4][3] = 0x00 ; asi1 right chn offset reg[0][4][4] = 0xC0 ; asi1 chn setup DAC&ADC left & right chns reg[0][4][4] = 0x00 ; asi1 chn setup DAC&ADC left & right chns reg[0][4][5] = 0x00 ; asi1 adc bus format Use R1 settings reg[0][4][6] = 0x00 ; asi1 multipin Data in & out single pins reg[0][4][7] = 0x01 ; asi1 adc input ctrl minidsp ADC data fed to ASI1 ;reg[0][4][8] = 0x51 ; asi1 dac data path left-left right-right, tdm -mode reg[0][4][8] = 0x50 ; asi1 dac data path left-left right-right reg[0][4][9] = 0x00 ; asi1 adc chn tristate nothing tristated reg[0][4][10] = 0x24 ; asi1 clock outputs bclk & wclk output reg[0][4][11] = 0x02 ; asi1 bit clock adc/dac clk 12.28MHz reg[0][4][12] = 0x81 ; asi1 bit clk n-div 1 reg[0][4][13] = 0x80 ; asi1 word clk n-div 128 reg[0][4][14] = 0x01 ; asi1 bclk & wclk output bclk->div outp, wclk->adc_fs clk reg[0][4][15] = 0x00 ; asi1 dout1 from asi1 reg[0][4][16] = 0x00 ; asi1 bclk & wclk adc same as dac ;ASI2 reg[0][4][17] = 0x00 ;asi2 format ctrl i2s, 16bit, not Hi-Z reg[0][4][18] = 0x00 ;asi2 data offset 0 bclks reg[0][4][21] = 0x00 ;asi2 adc format sames as r17 ;reg[0][4][21] = 0x3C ;asi2 secondary adc format DSP, 32-bit, this reg ;reg[0][4][23] = 0x01 ;asi2 format ctrl asi2[1:2] = minidsp_a_dataoutput[1:2] ;reg[0][4][23] = 0x03 ;asi2 format ctrl asi2[1:2] = asi2[1:2] reg[0][4][23] = 0x05 ;asi2 format ctrl asi2[1:2] = minidsp_a_dataoutput[3:4] reg[0][4][24] = 0x50 ;asi2 dac output ctrl left - dac data left, right - dac data right reg[0][4][26] = 0x24 ;asi2 wrd/bit ctrl bclk and wclk as output reg[0][4][27] = 0x02 ;asi2 bdiv input ADC_CLK reg[0][4][28] = 0x88 ;asi2 bclk div powered up, 8 reg[0][4][29] = 0xA0 ;asi2 wclk div powered up, 32 reg[0][4][30] = 0x24 ;asi2 bclk, wclk output bclk - div outp, wclk - div outp reg[0][4][31] = 0x00 ;asi2 dout DOUT2 from ASI2 reg[0][4][32] = 0x00 ;asi2 adc w/bclk wclk - same as dac wclk, bclk - same as dac bclk ;ASI3 reg[0][4][33] = 0x00 ;asi3 format ctrl i2s, 16bit, not Hi-Z reg[0][4][34] = 0x00 ;asi3 data offset 0 bclks ;reg[0][4][37] = 0x3C ;asi3 tertiary data format DSP, 32-bit reg[0][4][37] = 0x00 ;asi3 tertiary data format same as r33 ;reg[0][4][39] = 0x04 ;asi3 ADC inp ctrl asi3[1:2] = asi3[1:2] reg[0][4][39] = 0x06 ;asi3 ADC inp ctrl asi3[1:2] = minidsp_a_dataoutput[5:6] reg[0][4][40] = 0x50 ;asi3 dac output ctrl left - dac data left, right - dac data right reg[0][4][42] = 0x00 ;asi3 wrd/bit clk ctrl bclk default polarity, b/wclk power down when codec power down reg[0][4][43] = 0x02 ;asi3 bdiv input ADC_CLK reg[0][4][44] = 0x88 ;asi3 bclk div powered up, 8 reg[0][4][45] = 0xA0 ;asi3 wclk div powered up, 32 reg[0][4][46] = 0x46 ;asi3 bclk, wclk output bclk - div outp, wclk - div outp reg[0][4][47] = 0x00 ;asi3 dout DOUT3 from ASI3 reg[0][4][55] = 0x21 ;asi3 GPIO1/2 GPIO1 - ASI3_BCLK, GPIO2 - ASI3_WCLK reg[0][4][56] = 0x03 ;asi3 GPIO3 GPIO3 - ASI3_DIN reg[0][4][86] = 0x54 ;asi3 GPIO1 GPIO1 - ASI3_BCLK reg[0][4][87] = 0x50 ;asi3 GPIO2 GPIO1 - ASI3_WCLK reg[0][4][88] = 0x04 ;asi3 GPIO3 GPIO3 - ASI3_DIN reg[0][4][89] = 0x74 ;asi3 GPIO4 GPIO4 - ASI3_DOUT %%if (%%prop(SynchMode) == 1) reg[100][0][20] = 0x00 ; Disable ADC double buffer mode reg[120][0][20] = 0x00 ; Disable DAC double buffer mode %%else reg[100][0][20] = 0x80 ; Enable ADC double buffer mode reg[120][0][20] = 0x80 ; Enable DAC double buffer mode %%endif %%if (%%prop(SynchMode) == 1) reg[0][0][11] = 0x87 ; NDAC = 2, divider powered off %%endif %%if (%%prop(Include_MultiDigital) == 1) ; Assume CODEC slave mode for Multi channel, For master mode uncomment the reg writes below reg[0][4][1] = 0x20 ; ASI1 Audio Interface = DSP mode ;reg[0][4][11] = 0x01 ; DAC_MOD_CLK = ASI1_BDIV_CLKIN %%if (%%prop(Multi_I2S_Num_In_Channels) == 8) reg[0][4][4] = 0xc0 ;reg[0][4][12] = 0x81 ; ASI1 master, BCLK = 6.144Mhz ;reg[0][4][13] = 0x80 ; ASI1_WDIV = 128 %%endif %%if (%%prop(Multi_I2S_Num_In_Channels) == 6) reg[0][4][4] = 0x80 %%endif %%if (%%prop(Multi_I2S_Num_In_Channels) == 4) reg[0][4][4] = 0x40 ; For 4 channel digmic, ;reg[0][4][12] = 0x82 ; ASI1 master, BCLK = 3.072Mhz ;reg[0][4][13] = 0xc0 ; ASI1_WDIV = 64 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 8) reg[0][4][4] = 0xc0 ;reg[0][4][12] = 0x81 ; ASI1 master, BCLK = 6.144Mhz ;reg[0][4][13] = 0x80 ; ASI1_WDIV = 128 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 6) reg[0][4][4] = 0x80 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 4) reg[0][4][4] = 0x40 ;reg[0][4][12] = 0x82 ; ASI1 master, BCLK = 3.072Mhz ;reg[0][4][13] = 0xc0 ; ASI1_WDIV = 64 %%endif %%endif System settings reg[] code -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false reg[0][0][1] = 0x01 ; reg(0)(1)(0x00 => 0 ) S/W Reset reg[0][0][4] = 0x33 ; ADC_CLKIN = PLL_MCLK, DAC_CLKIN = PLL_MCLK reg[0][0][5] = 0x00 ; PLL_CLKIN = MCLK1 reg[0][0][6] = 0x91 ; P=1, R=1 %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) reg[0][0][7] = 0x07 ; P=1, R=1, J=7 reg[0][0][13] = 0x00 ; DOSR = 128 (MSB) reg[0][0][14] = 0x80 ; DOSR = 128 (LSB) reg[0][0][18] = 0x07 ; NADC Powerdown NADC = 2 reg[0][0][19] = 0x82 ; NADC Powerup MADC = 2 reg[0][0][20] = 0x80 ; AOSR = 128 %%endif %%if (%%prop(SynchMode) == 1) reg[0][0][11] = 0x07 ; NDAC = 7, divider powered off %%else reg[0][0][11] = 0x87 ; NDAC = 7, divider powered on %%endif reg[0][0][8] = 0x06 ; D=1680 (MSB) reg[0][0][9] = 0x90 ; D=1680 (LSB) reg[0][0][10] = 0x01 ; PLL_CLKIN_DIV=1 reg[0][0][12] = 0x82 ; reg(0)(0)(0x0c => 12) DAC Powerup MDAC = 2 reg[120][0][50] = 0x88 ; Interpolation Ratio is 8, FIFO = Enabled reg[100][0][50] = 0xa4 ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled %%if (%%prop(SynchMode) == 1) reg[0][0][60] = 0x80 ; reg(0)(0)(0x3c => 60) DAC prog Mode, DAC & ADC filter engines powered up together %%else reg[0][0][60] = 0x00 ; reg(0)(0)(0x3c => 60) DAC prog Mode, DAC & ADC filter engines not powered up together %%endif reg[0][0][61] = 0x00 ; reg(0)(0)(0x3d => 61) ADC prog mode reg[0][0][83] = 0x0 ; adc vol control = 0db reg[0][0][84] = 0x0 ; adc vol control = 0db reg[0][1][1 ] = 0x00 ; reg(0)(1)(0x01 => 0 ) Crude avdd disabled reg[0][1][3 ] = 0x00 ; reg(0)(1)(0x03 => 3 ) LDAC FIR reg[0][1][4 ] = 0x00 ; reg(0)(1)(0x04 => 4 ) RDAC FIR ;reg[0][1][11] = 0x35 ; reg(0)(1)(0xB =>11 ) DePop HP reg[0][1][31] = 0x80 ; reg(0)(1)(0x1F =>31 ) HP in ground Centered mode; HPL gain 0 dB reg[0][1][32] = 0x00 ; reg(0)(1)(0x20 =>32 ) HPR independent gain 0 dB reg[0][1][33] = 0x28 ; reg(0)(1)(0x21 =>33 ) Charge pump runs on Osc./4 reg[0][1][34] = 0x33 ;0x3e ; reg(0)(1)(0x22 =>34 ) Set CP mode reg[0][1][35] = 0x10 ; reg(0)(1)(0x23 =>35 ) Power up CP with HP reg[0][1][52] = 0x40 ; reg(0)(1)(0x34 => 52) ADC IN1_L is selected for left P reg[0][1][54] = 0x40 ; reg(0)(1)(0x36 => 54) ADC CM1 is selected for left M reg[0][1][55] = 0x40 ; reg(0)(1)(0x37 => 55) ADC IN1_R is selected for right P reg[0][1][57] = 0x40 ; reg(0)(1)(0x39 => 57) ADC CM1 is selected for right M reg[0][1][121] = 0x33 ; reg(0)(1)(0x79 => 121) Quick charge time for Mic inputs reg[0][1][122] = 0x01 ; reg(0)(1)(0x7A => 122) Vref charge time - 40 ms. PROGRAM_MINIDSP_A PROGRAM_MINIDSP_D %%if (%%prop(miniDSP_A_Adaptive) == 1) reg[40][0][1] = 0x04 ; adaptive mode for ADC %%endif %%if (%%prop(miniDSP_D_Adaptive) == 1) reg[80][0][1] = 0x04 ; adaptive mode for DAC %%endif ;IADC = %%prop(miniDSP_A_Cycles) ; ;IDAC = %%prop(miniDSP_D_Cycles) ; %%if (%%prop(SynchMode) == 1) %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) ;IDAC = %%eval(8*128) ; MDAC*DOSR ;IADC = %%eval(8*128) ; MADC*AOSR reg[100][0][48] = 4 reg[100][0][49] = 0 reg[120][0][48] = 4 reg[120][0][49] = 0 %%endif %%else // Asych mode reg[100][0][48] = %%eval(Math.floor(%%prop(miniDSP_A_Cycles)/256)) reg[100][0][49] = %%eval(%%prop(miniDSP_A_Cycles) - Math.floor(%%prop(miniDSP_A_Cycles)/256)*256) reg[120][0][48] = %%eval(Math.floor(%%prop(miniDSP_D_Cycles)/256)) reg[120][0][49] = %%eval(%%prop(miniDSP_D_Cycles) - Math.floor(%%prop(miniDSP_D_Cycles)/256)*256) %%endif reg[0][0][63] = 0xc2 ; reg(0)(0)(0x3f => 63) DAC L&R DAC powerup Ldata-LDAC Rdata-RDAC (soft-stepping disable) reg[0][0][64] = 0x00 ; reg(0)(0)(0x40 => 64) DAC Left and Right DAC unmuted with indep. vol. ctrl %%if (%%prop(Include_DigMic) == 1) reg[0][0][81] = 0xd6 ; reg(0)(0)(0x51 => d6) ADC Powerup ADC left and right channels in Digital mode(soft-stepping disable) %%else reg[0][0][81] = 0xc2 ; reg(0)(0)(0x51 => 81) ADC Powerup ADC left and right channels (soft-stepping disable) %%endif reg[0][0][82] = 0x00 ; reg(0)(0)(0x52 => 82) ADC Unmute ADC left and right channels,L,R fine gain=0dB reg[0][1][27] = 0x33 ; reg(0)(1)(0x1B =>27 ) LDAC -> HPL, RDAC -> HPR; Power on HPL + HPR reg[0][1][59] = 0x00 ; reg(0)(1)(0x3b => 59) ADC unmute left mic PGA with 0 dB gain reg[0][1][60] = 0x00 ; reg(0)(1)(0x3c => 60) ADC unmute right mic PGA with 0 dB gain ;ASI1 reg[0][4][1] = 0x38 ; asi1 audio format DSP/32bit/Dout not high imp reg[0][4][2] = 0x00 ; asi1 left chn offset ;reg[0][4][3] = 0x20 ; asi1 right chn offset reg[0][4][3] = 0x00 ; asi1 right chn offset reg[0][4][4] = 0xC0 ; asi1 chn setup DAC&ADC left & right chns reg[0][4][4] = 0x00 ; asi1 chn setup DAC&ADC left & right chns reg[0][4][5] = 0x00 ; asi1 adc bus format Use R1 settings reg[0][4][6] = 0x00 ; asi1 multipin Data in & out single pins reg[0][4][7] = 0x01 ; asi1 adc input ctrl minidsp ADC data fed to ASI1 ;reg[0][4][8] = 0x51 ; asi1 dac data path left-left right-right, tdm -mode reg[0][4][8] = 0x50 ; asi1 dac data path left-left right-right reg[0][4][9] = 0x00 ; asi1 adc chn tristate nothing tristated reg[0][4][10] = 0x24 ; asi1 clock outputs bclk & wclk output reg[0][4][11] = 0x02 ; asi1 bit clock adc/dac clk 12.28MHz reg[0][4][12] = 0x81 ; asi1 bit clk n-div 1 reg[0][4][13] = 0x80 ; asi1 word clk n-div 128 reg[0][4][14] = 0x01 ; asi1 bclk & wclk output bclk->div outp, wclk->adc_fs clk reg[0][4][15] = 0x00 ; asi1 dout1 from asi1 reg[0][4][16] = 0x00 ; asi1 bclk & wclk adc same as dac ;ASI2 reg[0][4][17] = 0x00 ;asi2 format ctrl i2s, 16bit, not Hi-Z reg[0][4][18] = 0x00 ;asi2 data offset 0 bclks reg[0][4][21] = 0x00 ;asi2 adc format sames as r17 ;reg[0][4][21] = 0x3C ;asi2 secondary adc format DSP, 32-bit, this reg ;reg[0][4][23] = 0x01 ;asi2 format ctrl asi2[1:2] = minidsp_a_dataoutput[1:2] ;reg[0][4][23] = 0x03 ;asi2 format ctrl asi2[1:2] = asi2[1:2] reg[0][4][23] = 0x05 ;asi2 format ctrl asi2[1:2] = minidsp_a_dataoutput[3:4] reg[0][4][24] = 0x50 ;asi2 dac output ctrl left - dac data left, right - dac data right reg[0][4][26] = 0x24 ;asi2 wrd/bit ctrl bclk and wclk as output reg[0][4][27] = 0x02 ;asi2 bdiv input ADC_CLK reg[0][4][28] = 0x88 ;asi2 bclk div powered up, 8 reg[0][4][29] = 0xA0 ;asi2 wclk div powered up, 32 reg[0][4][30] = 0x24 ;asi2 bclk, wclk output bclk - div outp, wclk - div outp reg[0][4][31] = 0x00 ;asi2 dout DOUT2 from ASI2 reg[0][4][32] = 0x00 ;asi2 adc w/bclk wclk - same as dac wclk, bclk - same as dac bclk ;ASI3 reg[0][4][33] = 0x00 ;asi3 format ctrl i2s, 16bit, not Hi-Z reg[0][4][34] = 0x00 ;asi3 data offset 0 bclks ;reg[0][4][37] = 0x3C ;asi3 tertiary data format DSP, 32-bit reg[0][4][37] = 0x00 ;asi3 tertiary data format same as r33 ;reg[0][4][39] = 0x04 ;asi3 ADC inp ctrl asi3[1:2] = asi3[1:2] reg[0][4][39] = 0x06 ;asi3 ADC inp ctrl asi3[1:2] = minidsp_a_dataoutput[5:6] reg[0][4][40] = 0x50 ;asi3 dac output ctrl left - dac data left, right - dac data right reg[0][4][42] = 0x00 ;asi3 wrd/bit clk ctrl bclk default polarity, b/wclk power down when codec power down reg[0][4][43] = 0x02 ;asi3 bdiv input ADC_CLK reg[0][4][44] = 0x88 ;asi3 bclk div powered up, 8 reg[0][4][45] = 0xA0 ;asi3 wclk div powered up, 32 reg[0][4][46] = 0x46 ;asi3 bclk, wclk output bclk - div outp, wclk - div outp reg[0][4][47] = 0x00 ;asi3 dout DOUT3 from ASI3 reg[0][4][55] = 0x21 ;asi3 GPIO1/2 GPIO1 - ASI3_BCLK, GPIO2 - ASI3_WCLK reg[0][4][56] = 0x03 ;asi3 GPIO3 GPIO3 - ASI3_DIN reg[0][4][86] = 0x54 ;asi3 GPIO1 GPIO1 - ASI3_BCLK reg[0][4][87] = 0x50 ;asi3 GPIO2 GPIO1 - ASI3_WCLK reg[0][4][88] = 0x04 ;asi3 GPIO3 GPIO3 - ASI3_DIN reg[0][4][89] = 0x74 ;asi3 GPIO4 GPIO4 - ASI3_DOUT %%if (%%prop(SynchMode) == 1) reg[100][0][20] = 0x00 ; Disable ADC double buffer mode reg[120][0][20] = 0x00 ; Disable DAC double buffer mode %%else reg[100][0][20] = 0x80 ; Enable ADC double buffer mode reg[120][0][20] = 0x80 ; Enable DAC double buffer mode %%endif %%if (%%prop(SynchMode) == 1) reg[0][0][11] = 0x87 ; NDAC = 2, divider powered off %%endif %%if (%%prop(Include_MultiDigital) == 1) ; Assume CODEC slave mode for Multi channel, For master mode uncomment the reg writes below reg[0][4][1] = 0x20 ; ASI1 Audio Interface = DSP mode ;reg[0][4][11] = 0x01 ; DAC_MOD_CLK = ASI1_BDIV_CLKIN %%if (%%prop(Multi_I2S_Num_In_Channels) == 8) reg[0][4][4] = 0xc0 ;reg[0][4][12] = 0x81 ; ASI1 master, BCLK = 6.144Mhz ;reg[0][4][13] = 0x80 ; ASI1_WDIV = 128 %%endif %%if (%%prop(Multi_I2S_Num_In_Channels) == 6) reg[0][4][4] = 0x80 %%endif %%if (%%prop(Multi_I2S_Num_In_Channels) == 4) reg[0][4][4] = 0x40 ; For 4 channel digmic, ;reg[0][4][12] = 0x82 ; ASI1 master, BCLK = 3.072Mhz ;reg[0][4][13] = 0xc0 ; ASI1_WDIV = 64 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 8) reg[0][4][4] = 0xc0 ;reg[0][4][12] = 0x81 ; ASI1 master, BCLK = 6.144Mhz ;reg[0][4][13] = 0x80 ; ASI1_WDIV = 128 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 6) reg[0][4][4] = 0x80 %%endif %%if (%%prop(Multi_I2S_Num_Out_Channels) == 4) reg[0][4][4] = 0x40 ;reg[0][4][12] = 0x82 ; ASI1 master, BCLK = 3.072Mhz ;reg[0][4][13] = 0xc0 ; ASI1_WDIV = 64 %%endif %%endif SystemSettingsXML 62 31 0.00000011920928955078125 String RateAll main RateAll System settings information -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false SynchMode 62 31 Enum RateAll Enabled main RateAll Enabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled Include_iDSP 62 31 0.00000011920928955078125 Enum RateAll Yes main RateAll Yes Support data transfer between miniDSPs No Yes 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Yes miniDSP_A_D_Clock_Ratio 62 31 0.00000011920928955078125 Enum RateAll Equal main RateAll Equal miniDSP_A_CLK / miniDSP_D CLK Equal 2x 4x 0.5x 0.25x 0 1 2 3 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Equal Include_I2S_Capture_A 62 31 0.00000011920928955078125 Enum RateAll No main RateAll No Indicate usage of I2S_Capture_A No Yes 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false No Include_I2S_Capture_D 62 31 0.00000011920928955078125 Enum RateAll No main RateAll No Indicate usage of I2S_Capture_D No Yes 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false No Include_DigMic 62 31 0.00000011920928955078125 Enum RateAll No main RateAll No Supports 4 channel DigMic on AIC3263 and AIC3268 No Yes 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false No Include_MultiDigital 62 31 0.00000011920928955078125 Enum RateAll Yes main RateAll Yes MultiChannel Digital in/out component is used No Yes 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Yes Multi_I2S_Num_In_Channels 62 31 0.00000011920928955078125 Int RateAll 8 main RateAll 8 Number of channes in multi channel input component 4 8 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 8 Multi_I2S_Num_Out_Channels 62 31 0.00000011920928955078125 Int RateAll 8 main RateAll 8 Number of channel in multi channel output component 4 8 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 8 TargetStream 32 31 Enum RateAll Primary main RateAll Primary Primary Secondary None 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Primary InstanceId 32 31 String RateAll AIC3268App8x4x_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false AIC3268App8x4x_1 Rate48 AIC3268App8x4x Yellow 255 255 Yellow 90 Solid AIC3268App8x4x_1 Black AIC3268App8x4x_1 156 168 false false false false false false false true false false false false None AIC3268 TypeC AIC3268App8x4x 1024 1536 1024 3072 false 48000 48000 6514 all false false Model.I2S_In2_1 I2S_In2_TI_v1 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 2 main RateAll 2 2 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_D main RateAll miniDSP_D miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_D TargetStream 32 31 Enum RateAll Primary main RateAll Primary Primary Secondary None 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Primary SynchMode 62 31 Enum RateAll Enabled main RateAll Enabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled InstanceId 32 31 String RateAll I2S_In2_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false I2S_In2_1 Rate48 I2S_In2 LightSteelBlue 255 255 Yellow 90 Solid I2S_In2_1 Black I2S_In2_1 108 252 false false false false false false false true false false false false None AIC3268 TypeC AIC3268App8x4x 1024 1536 1024 3072 false 48000 48000 6520 all false false Model.I2S_Out2_1 I2S_Out2_TI_v1 InputChannels 62 31 Enum RateAll 2 main RateAll 2 2 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_A main RateAll miniDSP_A miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A TargetStream 32 31 Enum RateAll Primary main RateAll Primary Primary Secondary None 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Primary SynchMode 62 31 Enum RateAll Enabled main RateAll Enabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled InstanceId 32 31 String RateAll I2S_Out2_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false I2S_Out2_1 Rate48 I2S_Out2 LightSteelBlue 255 255 Yellow 90 Solid I2S_Out2_1 Black I2S_Out2_1 432 408 false false false false false false false true false false false false None AIC3268 TypeC AIC3268App8x4x 1024 1536 1024 3072 false 48000 48000 6520 all false false Model.I2S_Out3_1 I2S_Out3_TI_v1 InputChannels 62 31 Enum RateAll 2 main RateAll 2 2 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_A main RateAll miniDSP_A miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A TargetStream 32 31 Enum RateAll Primary main RateAll Primary Primary Secondary None 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Primary SynchMode 62 31 Enum RateAll Enabled main RateAll Enabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled InstanceId 32 31 String RateAll I2S_Out3_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false I2S_Out3_1 Rate48 I2S_Out3 LightSteelBlue 255 255 Yellow 90 Solid I2S_Out3_1 Black I2S_Out3_1 432 492 false false false false false false false true false false false false None AIC3268 TypeC AIC3268App8x4x 1024 1536 1024 3072 false 48000 48000 6520 all false false Model.iDSP_D_A_1 iDSP_D_A_TI_v1 InputChannels 62 31 Enum RateAll 4 main RateAll 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 4 OutputChannels 62 31 Enum RateAll 4 main RateAll 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 4 ComponentVisibleFilter 62 31 0.00000011920928955078125 String RateAll not gde.GetProperty(gde.GetFramework(), "FrameworkType").startswith("AIC3262App8x4xArbiter") main RateAll not gde.GetProperty(gde.GetFramework(), "FrameworkType").startswith("AIC3262App8x4xArbiter") -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false not gde.GetProperty(gde.GetFramework(), "FrameworkType").startswith("AIC3262App8x4xArbiter") TargetStream 32 31 Enum RateAll Primary main RateAll Primary Primary Secondary None 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Primary SynchMode 62 31 Enum RateAll Enabled main RateAll Enabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled InstanceId 32 31 String RateAll iDSP_D_A_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false iDSP_D_A_1 Rate48 iDSP_D_A Yellow 255 255 Yellow 90 Solid iDSP_D_A_1 Black iDSP_D_A_1 228 312 false false false false false false false true false false false false None AIC3268 TypeC AIC3268App8x4x 1024 1536 1024 3072 false 48000 48000 0 all false false Model.I2S_In3_1 I2S_In3_TI_v1 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 2 main RateAll 2 2 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_D main RateAll miniDSP_D miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_D TargetStream 32 31 Enum RateAll Primary main RateAll Primary Primary Secondary None 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Primary SynchMode 62 31 Enum RateAll Enabled main RateAll Enabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled InstanceId 32 31 String RateAll I2S_In3_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false I2S_In3_1 Rate48 I2S_In3 LightSteelBlue 255 255 Yellow 90 Solid I2S_In3_1 Black I2S_In3_1 108 336 false false false false false false false true false false false false None AIC3268 TypeC AIC3268App8x4x 1024 1536 1024 3072 false 48000 48000 6520 all false false Model.Multi_Channel_Digital_In_1 Multi_Channel_Digital_In_TI_v1 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 8 main RateAll 8 4 6 8 4 6 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 8 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_D main RateAll miniDSP_D miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_D TargetStream 32 31 Enum RateAll Primary main RateAll Primary Primary Secondary None 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Primary SynchMode 62 31 Enum RateAll Enabled main RateAll Enabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled InstanceId 32 31 String RateAll Multi_Channel_Digital_In_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Multi_Channel_Digital_In_1 Rate48 Multi_Channel_Digital_In LightSteelBlue 255 255 Yellow 90 Solid Multi_Channel_Digital_In_1 Black Multi_Channel_Digital_In_1 108 420 false false false false false false false true false false false false None AIC3268 TypeC AIC3268App8x4x 1024 1536 1024 3072 false 48000 48000 6520 all false false Model.Multi_Channel_Digital_Out_1 Multi_Channel_Digital_Out_TI_v1 InputChannels 62 31 Enum RateAll 8 main RateAll 8 4 6 8 4 6 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 8 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_A main RateAll miniDSP_A miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A TargetStream 32 31 Enum RateAll Primary main RateAll Primary Primary Secondary None 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Primary SynchMode 62 31 Enum RateAll Enabled main RateAll Enabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0,0 0,0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled InstanceId 32 31 String RateAll Multi_Channel_Digital_Out_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Multi_Channel_Digital_Out_1 Rate48 Multi_Channel_Digital_Out LightSteelBlue 255 255 Yellow 90 Solid Multi_Channel_Digital_Out_1 Black Multi_Channel_Digital_Out_1 432 252 false false false false false false false true false false false false None AIC3268 TypeC AIC3268App8x4x 1024 1536 1024 3072 false 48000 48000 5370 all false false Model.I2S_In2_1 Model.iDSP_D_A_1 Model.I2S_In2_1.Ch1_Out Model.iDSP_D_A_1.Ch1_In 227.999985 323.999969 132 264 Black 2 Model.iDSP_D_A_1.Ch1_In Model.I2S_In2_1.Ch1_Out Model.iDSP_D_A_1 Model.I2S_In2_1 false all iDSP_D_A_TI_v1 I2S_In2_TI_v1 Model.iDSP_D_A_1 Model.Multi_Channel_Digital_Out_1 Model.iDSP_D_A_1.Ch1_Out Model.Multi_Channel_Digital_Out_1.Ch1_In 251.999985 323.999969 432 264 Black 2 Model.iDSP_D_A_1.Ch1_Out Model.Multi_Channel_Digital_Out_1.Ch1_In Model.iDSP_D_A_1 Model.Multi_Channel_Digital_Out_1 false all Multi_Channel_Digital_Out_TI_v1 iDSP_D_A_TI_v1 0 0 1000 800 0 0 1000 800 &F &d &T &p/&P White PowderBlue Rate48 Rate48 false false false false false false false true false false false false main base base 1 main Rate48 false false false false false false false true false false false false true false