typedef unsigned char cfg_u8;
typedef union {
    struct {
        cfg_u8 offset;
        cfg_u8 value;
    };
    struct {
        cfg_u8 command;
        cfg_u8 param;
    };
} cfg_reg;

#define CFG_META_SWITCH (255)
#define CFG_META_DELAY  (254)
#define CFG_META_BURST  (253)

/* Example C code */
/*
    // Externally implemented function that can write n-bytes to the device
    // PCM51xx and TAS5766 targets require the high bit (0x80) of the I2C register to be set on multiple writes.
    // Refer to the device data sheet for more information.
    extern int i2c_write(unsigned char *data, int n);
    // Externally implemented function that delays execution by n milliseconds
    extern int delay(int n);
    // Example implementation.  Call like:
    //     transmit_registers(registers, sizeof(registers)/sizeof(registers[0]));
    void transmit_registers(cfg_reg *r, int n)
    {
        int i = 0;
        while (i < n) {
            switch (r[i].command) {
            case CFG_META_SWITCH:
                // Used in legacy applications.  Ignored here.
                break;
            case CFG_META_DELAY:
                delay(r[i].param);
                break;
            case CFG_META_BURST:
                i2c_write((unsigned char *)&r[i+1], r[i].param);
                i +=  (r[i].param / 2) + 1;
                break;
            default:
                i2c_write((unsigned char *)&r[i], 2);
                break;
            }
            i++;
        }
    }
 */

cfg_reg registers[] = {
    { 0x00, 0x00 },
    { 0x7f, 0x00 },
    { 0x01, 0x19 },
    { CFG_META_DELAY, 5 },
// Book 0, Page 0
// 1SPW to BD soft start
    { 0x07, 0x81 },
// Input Word Length = 32 bits
    { 0x23, 0x0f },
// Output Word Length = 32 bits
    { 0x25, 0x1f },
// LSB offset of LL Ch1-4
    { 0x29, 0x00 },
// MSB offset of output audio
    { 0x2c, 0x0f },
// V-predict LSB offset
    { 0x2d, 0x00 },
// Audio Processing Enable/disable controls =  PVDD Foldback: Disable; Thermal Gain Foldback: Disable; Class-H Control: Disable;
    { 0x3a, 0x04 },

    { 0x3e, 0x30 },
// Digital Volume (Ch1) = -10 dB
    { 0x40, 0x44 },
// Digital Volume (Ch2) = -10 dB
    { 0x41, 0x44 },
// Digital Volume Ramp up/down controls
    { 0x44, 0x27 },

    { 0x45, 0xf0 },
// Bandwidth setting 200k
    { 0x6d, 0x2d },
// Output function of GPIO 2 = FAULT
    { 0x96, 0x0b },
// Output function of GPIO 3 = LOW
    { 0x97, 0x00 },
// Input function of GPIO 1, 2 & 3
    { 0x9f, 0x10 },
// Set GPIO1, GPIO2, GPIO3 as input/output
    { 0xa0, 0x62 },
// RAM Program Configurations
// Book 64
    { 0x7f, 0x64 },
    { 0x00, 0x01 },
    { 0x04, 0x02 },
    { 0x05, 0xc0 },
    { 0x06, 0x00 },
    { 0x07, 0x01 },
    { 0x08, 0x02 },
    { 0x09, 0xd0 },
    { 0x0a, 0x00 },
    { 0x0b, 0x00 },
    { 0x0c, 0x00 },
    { 0x0d, 0xf6 },
    { 0x0e, 0x20 },
    { 0x0f, 0x05 },
    { 0x10, 0x08 },
    { 0x11, 0xfc },
    { 0x12, 0x03 },
    { 0x13, 0xf9 },
    { 0x14, 0x02 },
    { 0x15, 0xd0 },
    { 0x16, 0x00 },
    { 0x17, 0x01 },
    { 0x18, 0x08 },
    { 0x19, 0x00 },
    { 0x1a, 0x10 },
    { 0x1b, 0x40 },
    { 0x1c, 0x08 },
    { 0x1d, 0x20 },
    { 0x1e, 0x26 },
    { 0x1f, 0x30 },
    { 0x20, 0x08 },
    { 0x21, 0x00 },
    { 0x22, 0x30 },
    { 0x23, 0x00 },
    { 0x24, 0x00 },
    { 0x25, 0xfc },
    { 0x26, 0x00 },
    { 0x27, 0x00 },
    { 0x28, 0x00 },
    { 0x29, 0xfc },
    { 0x2a, 0x00 },
    { 0x2b, 0x00 },
    { 0x2c, 0x00 },
    { 0x2d, 0x22 },
    { 0x2e, 0x20 },
    { 0x2f, 0x0e },
    { 0x30, 0x84 },
    { 0x31, 0xc3 },
    { 0x32, 0x08 },
    { 0x33, 0x1f },
    { 0x34, 0x00 },
    { 0x35, 0xfc },
    { 0x36, 0x00 },
    { 0x37, 0x00 },
    { 0x38, 0x00 },
    { 0x39, 0xfc },
    { 0x3a, 0x00 },
    { 0x3b, 0x00 },
    { 0x3c, 0x84 },
    { 0x3d, 0xa0 },
    { 0x3e, 0x06 },
    { 0x3f, 0x01 },
    { 0x40, 0x86 },
    { 0x41, 0xa3 },
    { 0x42, 0x00 },
    { 0x43, 0xaf },
    { 0x44, 0x86 },
    { 0x45, 0xa3 },
    { 0x46, 0x00 },
    { 0x47, 0xb4 },
    { 0x48, 0x00 },
    { 0x49, 0xfe },
    { 0x4a, 0x00 },
    { 0x4b, 0x40 },
    { 0x4c, 0x00 },
    { 0x4d, 0xfc },
    { 0x4e, 0x00 },
    { 0x4f, 0x00 },
    { 0x6c, 0x00 },
    { 0x6d, 0xfc },
    { 0x6e, 0x50 },
    { 0x6f, 0x00 },
    { 0x70, 0x00 },
    { 0x71, 0xfc },
    { 0x72, 0x00 },
    { 0x73, 0x00 },
// Book 0x8c
    { 0x00, 0x00 },
    { 0x7f, 0x8c },
    { 0x00, 0x03 },
    { 0x6c, 0x0d }, //  OL Threshold
    { 0x6d, 0x00 },
    { 0x6e, 0x00 },
    { 0x6f, 0x00 },
    { 0x70, 0x01 }, //  SL Threshold
    { 0x71, 0x10 },
    { 0x72, 0x00 },
    { 0x73, 0x00 },
// Channel state
    { 0x00, 0x00 },
    { 0x7f, 0x00 },
    { 0x03, 0x44 },
    { 0x04, 0x00 },
// Clear Fault
    { 0x01, 0x08 },

};