//************************************************************************* // AIC Init //************************************************************************ void AIC3204_rset( Uint16 regnum, Uint16 regval ) { Uint16 cmd[2]; cmd[0] = (regnum & 0x00FF); // 7-bit Device Register cmd[1] = (regval & 0x00FF); // 8-bit Register Data Uint16 startStop = ((CSL_I2C_START) | (CSL_I2C_STOP)); I2C_write(cmd, 2, AIC3204_I2C_ADDR, TRUE, startStop, CSL_I2C_MAX_TIMEOUT); Wait(1000); } //----------------------------------------------------------------------- void aic_init() { // Configure AIC3204 /*page 0*/AIC3204_rset( 0, 0x00 ); AIC3204_rset( 1, 0x01 ); // Reset codec Wait(10000); // Wait 1ms after reset /*page 1*/AIC3204_rset( 0, 0x01 ); AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD AIC3204_rset( 2, 0x01 ); // Enable Analog Blocks, use LDO power AIC3204_rset( 123,0x05 ); // Force reference to power up in 40ms Wait(50000); // Wait at least 40ms /*page 0*/AIC3204_rset( 0, 0x00 ); // PLL and Clocks config and Power Up if(AIC_SAMPLE_SIZE == 32) AIC3204_rset( 27, 0x3d ); // BCLK and WCLK are set as o/p; AIC3204(Master); 32-bit sample else AIC3204_rset( 27, 0x0d ); // BCLK and WCLK are set as o/p; AIC3204(Master); 16-bit sample AIC3204_rset( 28, 0x00 ); // Data ofset = 0 AIC3204_rset( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK. Wait(10000); // Wait 1ms after reset // 22,050к√ц (16bit) //CODEC_CLKIN = MCLK * R * J,D / P //CODEC_CLKIN = 12.000.000 * 1 * 8,4672 / 1 = 101.606.400 √ц AIC3204_rset( 5, 0x91 ); // Power up PLL, P=1 and R=1 AIC3204_rset( 6, 0x08 ); // J=8 AIC3204_rset( 7, 0x12 ); // HI_BYTE(D=4672) AIC3204_rset( 8, 0x40 ); // LO_BYTE(D=4672) //FS = CODEC_CLK / NDAC * MDAC * DOSR //FS = 101.606.400 / 128 * 4 * 9 = 22 050 AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR=128) AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR=128) AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6 AIC3204_rset( 11, 0x84 ); // Power up NDAC and set NDAC = 4 AIC3204_rset( 12, 0x89 ); // Power up MDAC and set MDAC = 9 AIC3204_rset( 18, 0x89 ); // Power up NADC and set NADC = 9 AIC3204_rset( 19, 0x84 ); // Power up MADC and set MADC = 4 AIC3204_rset( 30, 0x92 ); // For 16 bit clocks per frame in Master mode ONLY, fs = 22050 // BCLK= DAC_CLK(CODEC_CLK/NDAC) / N = (101.606.400/4) / 18 = 1.411.200 = 32*fs*2 AIC3204_rset( 60, 0x19 ); // DAC Signal Processing Block PRB_P25 // DAC /*page 0*/AIC3204_rset( 0, 0x00 ); AIC3204_rset( 68, 0x7F ); // DRC Enabled for both channels, Threshold = -24 db, Hysteresis = 3 dB AIC3204_rset( 69, 0x00 ); // DRC Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs' AIC3204_rset( 70, 0xB6 ); // Attack Rate = 1.9531e-4 dB/Frame , DRC Decay Rate =2.4414e-5 dB/Frame /*page 46*/AIC3204_rset( 0, 0x2E ); // #DRC HPF coefficients AIC3204_rset( 52, 0x7F ); AIC3204_rset( 53, 0xAB ); AIC3204_rset( 54, 0x00 ); AIC3204_rset( 55, 0x00 ); AIC3204_rset( 56, 0x80 ); AIC3204_rset( 57, 0x55 ); AIC3204_rset( 58, 0x00 ); AIC3204_rset( 59, 0x00 ); AIC3204_rset( 60, 0x7F ); AIC3204_rset( 61, 0x56 ); AIC3204_rset( 62, 0x00 ); AIC3204_rset( 63, 0x00 ); // #DRC LPF coefficients AIC3204_rset( 64, 0x00 ); AIC3204_rset( 65, 0x11 ); AIC3204_rset( 66, 0x00 ); AIC3204_rset( 67, 0x00 ); AIC3204_rset( 68, 0x00 ); AIC3204_rset( 69, 0x11 ); AIC3204_rset( 70, 0x00 ); AIC3204_rset( 71, 0x00 ); AIC3204_rset( 72, 0x7F ); AIC3204_rset( 73, 0xDE ); AIC3204_rset( 74, 0x00 ); AIC3204_rset( 75, 0x00 ); /*page 1*/AIC3204_rset( 0, 0x01 ); AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR AIC3204_rset( 3, 0x08 ); //(C8 - class D) Left DAC rout to HPL class AB fnd set PTM_P1 AIC3204_rset( 4, 0x08 ); // Right DAC rout to HPR class AB fnd set PTM_P1 AIC3204_rset( 16, 0x00 ); // UnMute HPL , 0dB gain AIC3204_rset( 17, 0x40 ); // Mute HPR , 0dB gain AIC3204_rset( 18, 0x40 ); // Mute LOL , 0dB gain AIC3204_rset( 19, 0x40 ); // Mute LOR , 0dB gain *** AIC3204_rset( 9 , 0x20 ); // Power up only HPL /*page 0*/AIC3204_rset( 0, 0x00 ); AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left AIC3204_rset( 63, 0xd4 ); // Power up DAC left,right data paths and set channel AIC3204_rset( 64, 0x02 ); // Unmute the DAC, Left vol=right vol // ADC ROUTING /*page 1*/AIC3204_rset( 0, 0x01 ); AIC3204_rset( 51, 0x48); // power up MICBIAS with AVDD (0x40)or LDOIN 3.3V (0x78) or 1.2V (0x48)//MM - added micbias //MIC_1 - Right AIC3204_rset( 55, 0x40); //IN1R -> Right Positive, 10k AIC3204_rset( 57, 0x10); //IN1L -> Right Negative, 10k //MIC_2 - Left AIC3204_rset( 52, 0x0C); //IN3L -> Left Positive, 40k AIC3204_rset( 54, 0x0C); //IN3R -> Left Negative, 40k // AGC /*page 0*/AIC3204_rset( 0, 0x00 ); // Left AIC3204_rset( 86, 0xA2 ); // AGC enable, T -10dB, HC 1dB AIC3204_rset( 87, 0x7E ); // Hist 2dB, Noise -90dB AIC3204_rset( 88, 0x32 ); // Max PGA 25dB AIC3204_rset( 89, 0x30 ); // Attack 20ms = 13(6) * 32 * 1/fs AIC3204_rset( 90, 0x50 ); // Dacay 500ms = 21(10) * 512 * 1/fs AIC3204_rset( 91, 0x00 ); // дребезг time from noise to signal AIC3204_rset( 92, 0x02 ); // дребезг time from signal to noise // Rigth AIC3204_rset( 94, 0xA2 ); // AGC enable, T -10dB, HC 1dB AIC3204_rset( 95, 0x7E ); // Hist 2dB, Noise -90dB AIC3204_rset( 96, 0x32 ); // Max PGA 25dB AIC3204_rset( 97, 0x30 ); // Attack 20ms = 13(6) * 32 * 1/fs AIC3204_rset( 98, 0x50 ); // Dacay 500ms = 21(10) * 512 * 1/fs AIC3204_rset( 99, 0x00 ); // дребезг time from noise to signal AIC3204_rset( 100, 0x02 ); // дребезг time from signal to noise // Power Up AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC }