{ // Page Select Register: Selects Page 0. .reg = 0x00, .data = 0x00, }, { // Software Reset Register: Asserts a self-clearing software reset to initialize registers. .reg = 0x01, .data = 0x01, }, { // Page Select Register: Selects Page 1. .reg = 0x00, .data = 0x01, }, { // Playback Configuration Register 1: DAC is enabled in High Performance Mode (PTM_P3, PTM_P4). .reg = 0x03, .data = 0x20, }, { // LDO Control Register: AVDD LDO output is nominally 1.8V, and PLL/HP Level Shifters are powered up. .reg = 0x02, .data = 0x04, }, { // Page Select Register: Selects Page 0. .reg = 0x00, .data = 0x00, }, { // Audio Interface Setting 1: 16-bit word length, I2S mode, BCLK & WCLK are inputs to the device. .reg = 0x1B, .data = 0x00, }, { // Clock Setting 1 (Multiplexers): High PLL Clock Range, BCLK pin is input to PLL, PLL Clock is CODEC_CLKIN. .reg = 0x04, .data = 0x47, }, { // Clock Setting 2: PLL is powered up, PLL divider P = 1, PLL multiplier R = 3. .reg = 0x05, .data = 0x93, }, { // Clock Setting 3: PLL multiplier J = 10. .reg = 0x06, .data = 0x0A, }, { // Clock Setting 6: NDAC divider powered up, NDAC value = 5. .reg = 0x0B, .data = 0x85, }, { // Clock Setting 7: MDAC divider powered up, MDAC value = 3. .reg = 0x0C, .data = 0x83, }, { // DAC OSR Setting 1: DOSR MSB value = 0. .reg = 0x0d, .data = 0x00, }, { // DAC OSR Setting 2: DOSR LSB value = 128 (Total DOSR = 128). .reg = 0x0E, .data = 0x80, }, { // DAC Channel Setup 1: DAC channel powered up, DAC data picked from Mono Mix of Left and Right, Soft-Stepping is 1 step per 2 DAC Word Clocks. .reg = 0x3f, .data = 0xB4, }, { // DAC Channel Setup 2: Auto Mute disabled, DAC Channel NOT muted. .reg = 0x40, .data = 0x04, }, { // Page Select Register: Selects Page 1. .reg = 0x00, .data = 0x01, }, { // Speaker Amplifier Volume Control 2: Speaker Driver Volume = +6 dB. .reg = 0x30, .data = 0x10, }, { // Speaker Amplifier Control 1: SPK output driver is powered up. .reg = 0x2d, .data = 0x02, }, { // Page Select Register: Return to Page 0. .reg = 0x00, .data = 0x00, } }