i i2cstd

#     --------------------------------------------------------------- page 0 is selected 
w 30 00 00
#      0:1  -- RESET:     s/w reset
> 01
#      0:51 -- GPIO1:     GPIO1 is mapped to INT1 output
w 30 33 16
#      0:48 -- INT1CTRL:  HS detect, BUTTON detect, short circuit, engine interrupts enabled
w 30 30 cc
#      0:27 -- IFACE1:    mode is i2s, wordlength is 16
w 30 1b 0c
#      0:27 -- IFACE2:    BCLK is inverted
w 30 1d 08
#      0:48 -- INT1CTRL:  HS detect, BUTTON detect, short circuit, engine interrupts enabled
w 30 30 cc
#      0:51 -- GPIO1:     GPIO1 is mapped to INT1 output
w 30 33 16
#
#     Note: the following AGC configuration was added manually (not from i2c log)
#      0:83 -- ADCVOL:    ADC coarse gain: 20 dB
w 30 53 28
#      0:86 -- AGCCTL1:   AGC enabled, target level -10 dB
w 30 56 a0
#      0:87 -- AGCCTL2:   2 dB hysteresis, noise threshold -90 dB
w 30 57 7e
#      0:88 -- AGCMAXGAIN: 50 dB maximum gain
w 30 58 64
#      0:89 -- AGCATTACK:  20 ms attack time
w 30 59 78
#      0:90 -- AGCDECAY:  500 ms decay time
w 30 5a b8
#      0:91 -- AGCNSDEB:  0 ms noise debounce time 
w 30 5b 00
#      0:92 -- AGCDIDEB:  2 ms signal debounce time 
w 30 5c 07
#     --------------------------------------------------------------- page 1 is selected 
w 30 00 01
#      1:31 -- HPDRIVER:  OCMV = 1.65 V
w 30 1f 14
#     --------------------------------------------------------------- page 0 is selected 
w 30 00 00
#      0:67 -- HSDETECT:  HS detect enabled, 64 ms glitch reject HS only, 8 ms glitch reject button
w 30 43 89
#     --------------------------------------------------------------- page 1 is selected 
w 30 00 01
#      1:47 -- MICPGA:    Mic PGA = 0 dB
w 30 2f 80
#      1:36 -- LANALOGHPL: ?
w 30 24 1b
#      1:37 -- RANALOGHPR: ?
w 30 25 1b
#      1:35 -- DACMIXERROUTE: DAC_R is routed to the right-channel mixer amplifier
w 30 23 40
#      1:35 -- DACMIXERROUTE: DAC_L and DAC_R routed to mixer amplifiers
w 30 23 44
#      1:36 -- LANALOGHPL: Set left analog HPL volume to mute
w 30 24 7f
#      1:37 -- RANALOGHPR: Set right analog HPR volume to mute
w 30 25 7f
#      1:38 -- LANALOGSPL: ?
w 30 26 00
#      1:39 -- RANALOGSPR: ?
w 30 27 00
#      1:42 -- SPLGAIN:   SPL driver not muted, gain set to 6 dB
w 30 2a 04
#      1:43 -- SPRGAIN:   SPR driver not muted, gain set to 6 dB
w 30 2b 04
#      1:38 -- LANALOGSPL: Set left SPL gain to 0 dB
w 30 26 80
#      1:39 -- RANALOGSPR: Set right SPR gain to 0 dB
w 30 27 80
#     -----Note: I think boot-up is complete here-----
#              Large (18 second) delay
#              Probably this next part is to set up for audible boot signal:
#     --------------------------------------------------------------- page 0 is selected 
w 30 00 00
#      0:4  -- CLKMUX:    PLL_clkin = MCLK, codec_clkin = PLL_CLK
w 30 04 03
#      0:6  -- PLLJ:      J = 8
w 30 06 08
#      0:7  -- PLLDMSB:   D = 1920 (0x780), D(13:8) = 7
w 30 07 07
#      0:8  -- PLLDLSB:   D(7:0) = 80
w 30 08 80
#      0:11 -- NDAC:      NDAC divider is set to 8
w 30 0b 08
#      0:12 -- MDAC:      MDAC divider is set to 2
w 30 0c 02
#      0:13 -- DOSR_LSB:  DAC DOSR MSB set to 0
w 30 0d 00
#      0:14 -- DOSR_MSB:  DAC DOSR LSB set to 0x80
w 30 0e 80
#      0:18 -- NADC:      NADC divider is powered up, set to 8
w 30 12 08
#      0:19 -- MADC:      MADC divider is powered up, set to 2
w 30 13 02
#      0:20 -- AOSR:      ADC AOSR set to 128
w 30 14 80
#      0:30 -- BCLKN:     Set BCLK N divider to 8
w 30 1e 08
#      0:5  -- PLLPR:     PLL Power up, P = 1, R = 1
w 30 05 91
#      0:11 -- NDAC:      Power up NDAC divider (set to 8)
w 30 0b 88
#      0:12 -- MDAC:      Power up MDAC divider (set to 2)
w 30 0c 82
#      0:18 -- NADC:      Power up NADC divider (set to 8)
w 30 12 88
#      0:19 -- MADC:      Power up MADC divider (set to 2)
w 30 13 82
#      0:30 -- BCLKN:     Power up BCLK N divider (set to 8)
w 30 1e 88
#      0:27 -- IFACE2:    BCLK is inverted, BCLK and WCLK active always
w 30 1d 0c
#      0:63 -- DACSETUP:  DAC left and right channels powered, set to corresponding data
w 30 3f d4
#      0:37 -- DACFLAG1:  Wait for left and right DAC channels to power up
f 30 25 1xxx1xxx
#     --------------------------------------------------------------- page 1 is selected 
w 30 00 01
#      1:32 -- SPKAMP:    Power up left and right Class D SPL and SPR outputs
w 30 20 c6
#     --------------------------------------------------------------- page 0 is selected 
w 30 00 00
#      0:37 -- DACFLAG1:  Wait for left and right Class D outputs to power up
f 30 25 1xx11xx1
#      0:64 -- DACMUTE:   Un-mute DAC outputs
w 30 40 00
#     -----Note: there is a time-out delay here before channels are muted-----
#                         Probably audible boot signal is complete
#      0:64 -- DACMUTE:   Mute DAC outputs
w 30 40 0c
#     --------------------------------------------------------------- page 1 is selected 
w 30 00 01
#      1:32 -- SPKAMP:    Power down left and right Class D SPL and SPR outputs
w 30 20 06
#     --------------------------------------------------------------- page 0 is selected 
w 30 00 00
#      0:37 -- DACFLAG1:  Wait for left and right Class D outputs to power down
f 30 25 xxx0xxx0
#      0:63 -- DACSETUP:  DAC left and right channels powered down
w 30 3f 14
#      0:37 -- DACFLAG1:  Wait for left and right DAC channels to power down
f 30 25 0xxx0xxx
#      0:27 -- IFACE2:    Disable BCLK and WCLK active when codec powered
w 30 1d 08
#      0:30 -- BCLKN:     Power down BCLK N divider (leave divider set to 8)
w 30 1e 08
#      0:19 -- MADC:      Power down MADC divider (leave divider set to 2)
w 30 13 02
#      0:18 -- NADC:      Power down NADC divider (leave divider set to 8)
w 30 12 08
#      0:12 -- MDAC:      Power down MDAC divider (leave divider set to 2)
w 30 0c 02
#      0:11 -- NDAC:      Power down NDAC divider (leave divider set to 8)
w 30 0b 08
#      0:5  -- PLLPR:     Power down PLL
w 30 05 11