w a0 00 00 #page 0
w a0 01 01 #reset
d 10       #wait for 16 ms
w a0 02 0b #not sleep mode, IOVDD at 1.8V /1.2V only, AVDD 3.3V, DREG and VREF enabled, VREF 3.5ms
w a0 03 00 #stay in sleep mode
w a0 04 00 #I2C broadcast disabled, clock error enabled
w a0 05 14 #DREG active for 25ms, DREG remains active to enable a clean shutdown, INxP, INxM 2.5ms
w a0 06 35 #HP Amp 100ms, HP Amp 0.25k, HP Amp 1K
w a0 07 00 #hard reset disabled, DAC power up delayed 64-128ms, DAC power up delayed disabled, DAC dc blocking disabled
w a0 0a 10 #Hi-Z output, GPIO1 = input
w a0 0b 31 #drive active low and active high, GPIO2 = IRQ
w a0 0c 41 #drive active low and active high, GPO1 = PDMCLK
w a0 0d 02 #GPI1 = input
w a0 0e 00 #GPO1 GPIO2 GPIO1 values set to 0
w a0 0f 20 #PASI FSYNC = FSYNC, PASI BLCK = BCLK, PASI DIN2 = disabled, CCLK = GPIO1
w a0 10 51 #drive active low and active high, DOUT value is set to 0, DOUT = PASI DOUT
w a0 11 80 #SASI BCLK = disabled, SASI FSYNC = disabled, PASI DIN = enabled
w a0 12 00 #SASI DIN2 = disabled, SASI DIN = disabled
w a0 13 03 #PDM ch3+4 = GPI1, PDM ch1+2 = disabled, PDM ch3 edge = negative PDM ch4 edge = positive, PDM ch1 edge = negative PDM ch2 edge = positive, ch2 = ADC, ch1 = ADC
w a0 14 00 #GPA disabled, PLIM disabled, power down DAC disabled, power down ADC disabled, DOUT = DOUT_SEL, PDM ch1+2/ch3+4 no override
w a0 15 00 #IADC disabled, MICBIAS disabled
w a0 18 40 #daisy input disabled, daisy chain disabled, SASI independent, SASI = disabled, PASI = enabled
w a0 19 00 #ASI DOUT daisy, 1 input for PASI+SASI, 1 output for PASI+SASI
w a0 1a 40 #auto resume, bus error detection enabled, PASI BCLK = default polarity, PASI FSYNC = default polarity, 16 bits, I2S mode
w a0 1b 06 #FSYNC = 1 BCLK period, internal FSYNC, internal BCLK, PASI bus keeper disabled, PASI LSB full cycle, PASI 0 for unused cycles, PASI BCLK = default edge
w a0 1c 00 #PASI MSB no offset
w a0 1d 00 #PASI all channels = DOUT
w a0 1e 20 #PASI ch1 = I2S left slot 0, PASI ch1 = ADC/PDM ch1
w a0 1f 21 #PASI ch2 = I2S left slot 1, PASI ch2 = ADC/PDM ch2
w a0 20 30 #PASI ch3 = I2S right slot 0, PASI ch3 = PDM ch3
w a0 21 11 #PASI ch4 = I2S right slot 1, PASI ch4 = Hi-Z
w a0 22 04 #PASI ch5 = I2S left slot 4, PASI ch5 = Hi-Z
w a0 23 05 #PASI ch6 = I2S left slot 5, PASI ch6 = Hi-Z
w a0 24 06 #PASI ch7 = I2S left slot 6, PASI ch7 = Hi-Z
w a0 25 07 #PASI ch8 = I2S left slot 7, PASI ch8 = Hi-Z
w a0 26 60 #PASI MSB no offset, internal BCLK, internal FSYNC, PASI BCLK = default edge
w a0 27 00 #PASI all channels = DIN
w a0 28 20 #PASI ch1 = I2S left slot 0, PASI ch1 = DAC ch1
w a0 29 21 #PASI ch2 = I2S left slot 1, PASI ch2 = DAC ch2
w a0 2a 30 #PASI ch3 = I2S right slot 0, PASI ch3 = DAC ch3
w a0 2b 31 #PASI ch4 = I2S right slot 1, PASI ch4 = DAC ch4
w a0 2c 04 #PASI ch5 = I2S left slot 4, PASI ch5 = Hi-Z
w a0 2d 05 #PASI ch6 = I2S left slot 5, PASI ch6 = Hi-Z
w a0 2e 06 #PASI ch7 = I2S left slot 6, PASI ch7 = Hi-Z
w a0 2f 07 #PASI ch8 = I2S left slot 7, PASI ch8 = Hi-Z
w a0 32 84 #PASI auto clock configuration, 1% tolerance, Fs = 8000
w a0 33 00 #SASI auto clock configuration, 1% tolerance, Fs = auto detected
w a0 34 48 #rising edge for ratio detection, fixed CCLK, PLL fractional on, PLL enabled
w a0 35 80 #auto detect ratio, PDM clock = 705.6 or 768 kHz
w a0 36 00 #auto detect ratio
w a0 37 30 #multiple of 48kHz, SASI = target, PASI = controller, CCLK = 12.288MHz
w a0 38 80 #MSB PASI BCLK FSYNC ratio = 0, PASI BCLK polarity not inverted, internal BCLK for FSYNC generation in PASI
w a0 39 40 #LSB PASI BCLK FSYNC ratio = 64
w a0 3a 00 #MSB SASI BCLK FSYNC ratio = 0, SASI BCLK polarity not inverted, external BCLK for FSYNC generation in SASI
w a0 3b 00 #LSB SASI BCLK FSYNC ratio = 0
w a0 42 00 #LTCH reg bits cleared only if live status = 0, ADC auto recovery, all interrupts readable, no fault for power down, INT asserted on unmasked latched interrupts, INT = IRQZ
w a0 43 50 #AREG short circuit enabled, DAC fault enabled, disable during power-up, no DAC power down on fault, manual DAC recovery, only unmasked DAC faults for power down
w a0 4b 00 #mute ADC ch2 = disabled, mute ADC ch1 = disabled
w a0 4c 5c #IADC OSR = 128, IADC NRESET = 75 = IADC NSKIP = 576
w a0 4d 00 #VREF = 2.75V, MICBIAS = VREF, LDO gain = 1
w a0 4e 00 #ADC LP filter = off, ADC DEM = 0, ADC FIR BYPASS = off, ADC CIC ORDER = 5th order, ADC MOD CLK 3.072MHz or 12.8224MHz
w a0 4f 00 #DAC IREF = VREF/R, DAC LP filter = disable, DAC DEM = default, DAC MOD CLK 3MHz
w a0 50 50 #24kHz mode, 1Vrms single-ended, 50mVpp, 10kOhm, ADC ch1 = analog single-ended
w a0 51 00 #IADC one shot conversion not done, IADC sequential conversion running, IADC no conversion, IADC one-shot single, IADC disabled
w a0 52 a1 #ADC ch1 digital volume = 0dB
w a0 53 80 #ADC ch1 fine gain = 0dB
w a0 54 00 #ADC ch1 PCAL for both Ana-Dig, ADC ch1 = no phase calibration
w a0 55 50 #24kHz mode, 1Vrms single-ended, 50mVpp, 10kOhm, ADC ch2 = analog single-ended
w a0 57 a1 #ADC ch2 digital volume = 0dB
w a0 58 80 #ADC ch2 fine gain = 0dB
w a0 59 00 #ADC ch2 PCAL for both Ana-Dig, ADC ch2 = no phase calibration
w a0 5a 00 #ADC ch3 clone disabled
w a0 5b a1 #ADC ch3 digital volume = 0dB
w a0 5c 80 #ADC ch3 fine gain = 0dB
w a0 5d 00 #ADC ch3 = no phase calibration
w a0 5e 00 #ADC ch4 clone disabled
w a0 5f a1 #ADC ch4 digital volume = 0dB
w a0 60 80 #ADC ch4 fine gain = 0dB 
w a0 61 00 #ADC ch4 = no phase calibration
w a0 62 00 #ADC data not inverted, ADC bit to tweak = default
w a0 64 24 #0.6 * VREF, stereo single-ended, out1 = DAC
w a0 65 18 #24kHz mode, IN1x analog bypass = FD, AIN1M =4.4kOhm, OUT1P level = 6dB, OUT1P = line out
w a0 66 18 #DAC ch1 = AC coupled, AIN1P = 4.4kOhm, OUT1M level = 6dB, OUT1M = line out
w a0 67 c9 #DAC ch1a digital volume = 0dB
w a0 68 80 #DAC ch1a fine gain = 0dB
w a0 69 c9 #DAC ch1b digital volume = 0dB
w a0 6a 80 #DAC ch1b fine gain = 0dB
w a0 6b 24 #0.6 * VREF, stereo single-ended, out2 = DAC
w a0 6c 18 #24kHz mode, IN1x analog bypass = FD, AIN2M =4.4kOhm, OUT2P level = 6dB, OUT2P = line out
w a0 6d 18 #DAC ch2 = AC coupled, AIN2P = 4.4kOhm, OUT2M level = 6dB, OUT2M = line out
w a0 6e c9 #DAC ch2a digital volume = 0dB
w a0 6f 80 #DAC ch2a fine gain = 0dB
w a0 70 c9 #DAC ch2b digital volume = 0dB
w a0 71 80 #DAC ch2b fine gain = 0dB
w a0 72 18 #ADC dvol independent, soft-stepping enabled, 2 biquads per channel, HFP with cutoff 0.00002 * fs, linear phase
w a0 73 18 #DAC dvol independent, soft-stepping enabled, 2 biquads per channel, HFP with cutoff 0.00002 * fs, linear phase
w a0 77 f0 #DAC no swap, ADC no swap, no different ADC MOD CLK and PDM CLK, DAC ch1-4 dynamic mode, dynamic DAC, ADC ch1-4 dynamic mode, dynamic ADC
w a0 00 01 #page 1
w a0 03 00 #disable on the fly biquad changes
w a0 0d 04 #external FSYNC for SASI, internal FSYNC for PASI, controller-target as per SASI_CNT_CFG bit, controller-target as per PASI_CNT_CFG bit
w a0 24 80 #DRC ch4 = off, DRC ch3 = off, DRC ch2 = off, DRC ch1 = off, AGC ch4 = off, AGC ch3 = off, AGC ch2 = off, AGC ch1 = on
w a0 00 03 #page 3
w a0 32 00 #PASI BCLK divider = PLL, PLL PDIV divider = PASI BCLK
w a0 33 00 #SASI BCLK divider = PLL
w a0 34 00 #ANA_NM divider = PLL output, DIG_NM divider = PASI BCLK
w a0 35 01 #PLL_PDIV = 1
w a0 36 00 #PLL_DMUL_MSB = 0, PLL DIV by 2 = no, PLL_JMUL_MSB = 0
w a0 37 00 #PLL_DMUL_LSB = 0
w a0 38 07 #PLL_JMUL_MSB = 7
w a0 39 30 #PDM_DIV = 16, NDIV = 1
w a0 3a 1e #DIG_ADC_MODCLK_DIV = 4, MDIV = 7
w a0 3b 20 #SASI_BDIV_MSB = 0, PASI_BDIV_MSB = 0, DAC MOD clock 2x enabled, DIG_DAC_MODCLK_DIV = 4
w a0 3c a8 #PASI_BDIV_LSB = 168
w a0 3d 00 #SASI_BDIV_LSB = 512
w a0 3e 07 #ANA_NM_DIV = 7
w a0 3f 00 #ANA_DAC_DEM_DIV = 1, ANA_ADC_DEM_DIV = 1
w a0 44 00 #PDM divider disabled, MDIV divider disabled, NDIV divider disabled
w a0 45 00 #SASI FSYNC DIV divider disabled, PASI FSYNC DIV divider disabled, SASI BDIV divider disabled, PASI BDIV divider disabled, DAC_MODCLK divider disabled, DAC_DEMOD divider disabled, ADC_MODCLK divider disabled, ADC_DEMOD divider disabled
w a0 46 00 #CLKOUT = PLL output
w a0 47 00 #CLKOUT_DIV = 128, CLKOUT divider disabled
w a0 00 08 #page 8
w a0 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 1
w a0 1c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 2
w a0 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 3
w a0 44 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 4
w a0 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 5
w a0 6c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 6
w a0 00 09 #page 9
w a0 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 7
w a0 1c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 8
w a0 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 9
w a0 44 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 10
w a0 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 11
w a0 6c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 #ADC biquad 12
w a0 00 1b #page 27
w a0 5c ff fe b0 00 #AGC noise floor = -84dB
w a0 60 ff ff e8 00 #AGC target level = -6dB
w a0 64 00 00 01 90 #AGC noise count max = 41.65ms
w a0 68 00 00 60 00 #AGC max gain = 21.5dB
w a0 6c ff ff 88 00 #AGC min gain = 30dB
w a0 70 00 00 24 00 #AGC noise hysteresis = 6dB
w a0 74 00 00 00 01 #AGC attack hold count = 0.104ms
w a0 78 00 00 00 fa #AGC release hold count = 26ms
w a0 7c 00 00 08 00 #AGC release hysteresis = 2dB
w a0 00 1c #page 28
w a0 08 50 fc 64 5c #AGC attack rate = 0.632ms
w a0 0c 7f c4 0e 57 #AGC release rate = 0.998ms
w a0 00 00 #page 0
w a0 76 ef #input ch1-3 enabled, ch4 disabled, out ch1-4 enabled
w a0 78 c0 #UAG off, VAD off, UAD off, MICBIAS off, DAC on, ADC and PDM on