CHx_LTCH[7] summary latched bit is expected to clear when we read CH1_LTCH register (0x2E) & INT_LTCH1 (0x35) & INT_LTCH2 (0x36). 
CHx_LTCH[6] summary latched bit is expected to clear when we read CH2_LTCH register (0x2F) & INT_LTCH1 (0x35) & INT_LTCH2 (0x36). 
CHx_LTCH[5] summary latched bit is expected to clear when we read CH3_LTCH register (0x30) & INT_LTCH1 (0x35) & INT_LTCH2 (0x36). 
CHx_LTCH[4] summary latched bit is expected to clear when we read CH4_LTCH register (0x31) & INT_LTCH1 (0x35) & INT_LTCH2 (0x36). 
CHx_LTCH[3] summary latched bit is expected to clear when we read CH5_LTCH register (0x32) & INT_LTCH1 (0x35) & INT_LTCH2 (0x36). 
CHx_LTCH[2] summary latched bit is expected to clear when we read CH6_LTCH register (0x33) & INT_LTCH1 (0x35) & INT_LTCH2 (0x36). 
CHx_LTCH[1] summary latched bit is expected to clear when we read CH1~6_LTCH register (0x2E~0x33) & INT_LTCH1 (0x35) & INT_LTCH2 (0x36). Depending upon which channel fault occurred by reading CHx_LTCH[7-2] bits, the read from CH1~6_LTCH can be optimized accordingly.