{  0,0x00}, //PAGE 0 select
{  2,0x01}, // system standby mode
{  1,0x11}, // Reset
{ 37,0x7F}, //Disable all clock missing detectors and clock auto mode


//  PLLCK = (CLK) x R x (J.D)       2.8224 * 2 *16
//          ------------------  == --------------  = 90.3168MHz
//               P                      1
// CLK = BCK = 2.8224

{ 13,0x10}, // PLL clock source = BCK
//{ 14,0x10}, // DAC clock source PLL clock - TI: Not necessary

{  4,0x01},  // PLL enable

{ 20,0x00}, //P value = 1
{ 21,0x10}, // J value = 16
{ 22,0x00}, // 22,23 D value (0)
{ 23,0x00},

{ 24,0x01}, // R value = 2

// DSP CLK = PLLCK/DDSP = 90.3168 / 2 = 45.1584MHz
//
{ 27,0x01},// DDSP (2)
//
// DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz
//
{ 28,0x0f}, // DDAC (16)
//
// CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz
//
{ 29,0x03}, // NCP (4)
//
// Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz
//
{ 30,0x07}, // DOSR (8)


{ 40,0x00}, // I2S Format I2S 16bits
//{ 41,0x00}, // I2S Shift 1 BCK
//{ 42,0x11}, // Left, Right DAC Data Path  - TI:not necessary
//{  9,0x00}, - TI:not necessary
//{ 12,0x03}, // Master Mode BCK, LRCK divider functional- TI:not necessary

{ 35,0x04}, // IDSP =1024
{ 36,0x00},

{ 60,0x01}, // Right channel volume follows left channel setting
{ 61,120}, //

//{  0,0x01},- TI:not recommended
//{  3,0x4},- TI:not recommended

{  0,0x00},
{  3,0x11}, // left/right mute


.... miniDSP coef & instructions....

//////////////////////////////////////////////////////////////
//run code from RAM
{  0,0x00},
{ 43,0x1f},
////////////////////////////////////////////////////////////
//16x, 8x
//{ 34,0x10}, TI: Original
{ 34,0x00} //TI: It is not recommended to change the interpolator to 16x in this case.  This have greater impact on the DSP and the number of instructions that can be supported.
////////////////////////////////////////////////////////////
//Enable adaptive mode for DAC
{  0,0x2C},
{  1,0x00},
{  1,0x04},
///////////////////////////////////////////////////////////////
//Normal mode DAC
{  0,0x00},
{  2,0x00}, //Stanby -> Normal operation
{  3,0x00}  // Mute remove