#/* --COPYRIGHT--,BSD_EX
# Copyright (c) 2013, Texas Instruments Incorporated
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#
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#
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#******************************************************************************
#  PCM512x,4x,5x Code Example: 3pin I2S input (no master clock)
#
#  Description: The PCM51xx family in software mode (I2C or SPI) require the Clock Tree and PLL 
#	to be configured based on knowledge of the incoming Bit clock (BCK) reference. The code below assumes
#  a 64fs BCK on 48kHz data. The PLL needs to be configured to create a faster clock rate for the miniDSP.
#	(the miniDSP typically runs at ~50MHz).
#
#	#### CLK divider setting ###################
#  #### Use VREF PLL settings when in VREF mode to look up the sample rate, and the SCK ## 
#  #### The table assumes SCK as a reference - but the same frequency can be used with a BCK reference##
#  #### In this example, look for 48kHz rate, with 3.072MHz SCK ####
#
#	Connection
#
#	SCK : do not connect
#	BCK : input terminal 
#	LRCK : input terminal
#	DATA : input terminal
#
# 	Commands below are written in the TI-Tools for for I2C. (Codec Control, Purepath Console and Purepath Studio all support this format).
# 	Format: 
# 	A BBh CCh DDh
#
# 	A = R or W (read or write)
# 	BBh = I2C Address (98 in this case)
# 	CCh = Register
# 	DDh = for Writes, it's the data, for reads, it's the number of bytes to read back.
# 	Either # or # can be used for comments.
#
#  Dafydd Roche
#  Texas Instruments, Inc
#  August 2013
#******************************************************************************



# Auto divider setting : disable auto config and ignore SCK losses
w 98 25 1A
# PLL P divider to 3
w 98 14 01     
# PLL J divider to 16.D1D2
w 98 15 10    
# PLL D1 divider to J.00
w 98 16 00     
# PLL D2 divider to J.00
w 98 17 00
# PLL R divider to 2
w 98 18 01
# miniDSP CLK divider (NMAC) to 2
w 98 1B 01
# DAC CLK divider to 16
w 98 1C 0F
# NCP CLK divider to 4
w 98 1D 03
# OSC CLK divider is set to one (as its based on the output from the DAC CLK, which is already PLL/16)
w 98 1E 00
# FS setting should be set to single rate speed (48kHZ).
w 98 22 00
# IDAC1  sets the number of miniDSP instructions per clock. (set to 1024)
w 98 23 04
# IDAC2  
w 98 24 00
#############################################


# Set PLL Clock Source to be BCK instead of SCK
w 98 0D 10



#### Stand-by request and release ############
# Stand-by request
w 98 02 10
# Stand-by release
w 98 02 00
##############################################
