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#******************************************************************************
#  PCM512x,4x,5x Code Example: I2S Master Mode with an Audio rate SCK input (e.g. 24.576MHz for 48kHz)
#
#  Description: The PCM51xx family in software mode (I2C or SPI) can be configured to drive LRCK and BCK as outputs.
#	This is known as master mode. The PLL must still be configured for the miniDSP etc.
#
#	#### CLK divider setting ###################
#  #### Use VREF PLL settings when in VREF mode to look up the sample rate, and the SCK ## 
#  #### The table assumes SCK as a reference - but the same frequency can be used with a BCK reference##
#  #### In this example, look for 96kHz rate, with 6.144MHz SCK ####
#
# 	Connection
#
#	SCK : Input 24.576MHz from External Source
#	BCK : output terminal, which must be input to BCK terminal of AP2 through pullup res of 1kohm  (Need pull-up resistor)
#	LRCK : output terminal, which must be input to LRCK terminal of AP2 through pullup res of 1kohm
#	DATA : input from external data source
#
# 	Commands below are written in the TI-Tools for for I2C. (Codec Control, Purepath Console and Purepath Studio all support this format).
# 	Format: 
# 	A BBh CCh DDh
#
# 	A = R or W (read or write)
# 	BBh = I2C Address (98 in this case)
# 	CCh = Register
# 	DDh = for Writes, it's the data, for reads, it's the number of bytes to read back.
# 	Either # or # can be used for comments.
#
#  Dafydd Roche
#  Texas Instruments, Inc
#  August 2013
#******************************************************************************


#### CLK divider setting ###################
#### Use VREF PLL settings when in VREF mode to look up the sample rate, and the SCK ## 
#### In this example, look for 48kHz rate, with 3.072MHz SCK ####

# Disable Auto Clock Configuration
w 98 25 72
# PLL P divider to 3
w 98 14 03     
# PLL J divider to 12.D1D2
w 98 15 0C    
# PLL D1 divider to J.00
w 98 16 00     
# PLL D2 divider to J.00
w 98 17 00
# PLL R divider to 1
w 98 18 00
# miniDSP CLK divider (NMAC) to 2
w 98 1B 01
# DAC CLK divider to 16
w 98 1C 0F
# NCP CLK divider to 4
w 98 1D 03
# OSC CLK divider is set to one (as its based on the output from the DAC CLK, which is already PLL/16)
w 98 1E 00
# FS setting should be set to single rate speed (48kHZ).
w 98 22 00
# IDAC1  sets the number of miniDSP instructions per clock. (set to 1024)
w 98 23 04
# IDAC2  
w 98 24 00
#############################################

#### Master mode setting ####################
# BCK, LRCK output
w 98 09 11
# Master mode BCK divider setting (making 64fs)
w 98 20 03
# Master mode LRCK divider setting (divide BCK by a further 64 to make 1fs)
w 98 21 3F
# Master mode BCK, LRCK divider reset release
w 98 0C 7F
##############################################

#### Stand-by request and release ############
# Stand-by request
w 98 02 10
# Stand-by release
w 98 02 00
##############################################