res=TLV320_Write_Reg(0,0); //select Bank0 delay_ms(2); res=TLV320_Write_Reg(0x01,0X01); // reset delay_ms(2); res=TLV320_Write_Reg(0x02,0X81); //SLEEP_CFG Register ; Internally generated 1.8-V AREG supply , Device is not in sleep mode delay_ms(2); res=TLV320_Write_Reg(0x07,0X80); //ASI_CFG0 Register ; I2S mode, 16 bits, Always transmit 0 for unused cycles delay_ms(2); res=TLV320_Write_Reg(0x08,0X20); //ASI_CFG1 Register; Transmit the LSB for a full cycle ,Bus keeper is always enabled delay_ms(2); res=TLV320_Write_Reg(0x13,0XC3); //MST_CFG0 Register; Device is in master mode, Auto clock configuration is disabled,PLL is enabled,16 MHz delay_ms(2); res=TLV320_Write_Reg(0x14,0X1A); // MST_CFG1 Register; sample rate 16 kHz,BCLK to FSYNC frequency ratio of 512 delay_ms(2); res=TLV320_Write_Reg(0x73,0XF0); //IN_CH_EN Register; Channel 1-4 is enabled delay_ms(2); res=TLV320_Write_Reg(0x74,0XF0); //ASI_OUT_CH_EN Register£» Channel 1-4 output slot is enabled delay_ms(2); res=TLV320_Write_Reg(0x75,0XFF); //PWR_CFG Register£» Power up MICBIAS£¬Power up all enabled ADC and PDM channels£¬Power up the PLL delay_ms(2); res=TLV320_Write_Reg(0x76,0XF0); //DEV_STS0 Register£»channel 1-4 ADC or PDM channel is powered up delay_ms(2); res=TLV320_Write_Reg(0x77,0Xe0); //DEV_STS1 Register£»Device is in active mode with at least one ADC or PDM channel turned on delay_ms(2);