typedef unsigned char cfg_u8;
typedef union {
    struct {
        cfg_u8 offset;
        cfg_u8 value;
    };
    struct {
        cfg_u8 command;
        cfg_u8 param;
    };
} cfg_reg;

#define CFG_META_SWITCH (255)
#define CFG_META_DELAY  (254)
#define CFG_META_BURST  (253)

/* Example C code */
/*
    // Externally implemented function that can write n-bytes to the device
    // Refer to the device data sheet for more information.
    extern int i2c_write(unsigned char *data, int n);
    // Externally implemented function that delays execution by n milliseconds
    extern int delay(int n);
    // Example implementation.  Call like:
    //     transmit_registers(registers, sizeof(registers)/sizeof(registers[0]));
    void transmit_registers(cfg_reg *r, int n)
    {
        int i = 0;
        while (i < n) {
            switch (r[i].command) {
            case CFG_META_SWITCH:
                // Used in legacy applications.  Ignored here.
                break;
            case CFG_META_DELAY:
                delay(r[i].param);
                break;
            case CFG_META_BURST:
                i2c_write((unsigned char *)&r[i+1], r[i].param);
                i +=  (r[i].param / 2) + 1;
                break;
            default:
                i2c_write((unsigned char *)&r[i], 2);
                break;
            }
            i++;
        }
    }
 */

cfg_reg registers[] = {
#define CHECKSUM (0)
// Generated by ADCx120EVM-SW v3.0.5
// TLV320ADC3120 device configuration
// -----------------------------------------------------------------------------
// Reset
// -----------------------------------------------------------------------------
// Select Page 0
    { 0x00, 0x00 },
// Reset Device
    { 0x01, 0x01 },
// 1mS Delay
// -----------------------------------------------------------------------------
// Begin Device Memory
// -----------------------------------------------------------------------------
// Page 0 (0x00) Dump
// Select Page 0
    { 0x00, 0x00 },
// Wake up and Enable AREG
    { 0x02, 0x81 },
    { 0x05, 0x01 },
// ASI configuration
    { 0x07, 0x70 },
    { 0x09, 0x20 },
// ASI Channel configuration
    { 0x0c, 0x20 },
// ASI master mode
    { 0x13, 0x42 },
// PDM Configuration
    { 0x1f, 0xb0 },
// GPIO Configuration
    { 0x21, 0xa0 },
// DSP Configuration
    { 0x6c, 0x48 },
// input and output Configuration
    { 0x74, 0xc0 },