AudioHAL_I2CReg configRegs16Bit[] =
{
    {TI3254_PAGE_0, TI3254_SW_RESET_REG, 0x01},                         /* R1 Reset the codec */
    {TI3254_PAGE_0, TI3254_AUDIO_IF_1_REG, 0x0C},                       /* R27 16bit, I2S, WCLK, BCLK is output from the device */
};


AudioHAL_I2CReg clockRegs16k[] =
{
    {TI3254_PAGE_0, TI3254_CLK_MUX_REG, 0x03},                          /* R4 PLL Clock is CODEC_CLKIN */
    {TI3254_PAGE_0, TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x01},        /* R5 PLL is powered up, P=1, R=1 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_J_REG, 0x008},                       /* R6 J=8 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_D_MSB_REG, 0x07},                    /* R7 Set MSB of D value D=0x0780 */
    {TI3254_PAGE_0, TI3254_CLK_PLL_D_LSB_REG, 0x80},                    /* R8 Set LSB of D value */
    {TI3254_PAGE_0, TI3254_CLK_NDAC_REG, 0x80 | 0x10},                  /* R11 NDAC divider powered on, NDAC = 16 */
    {TI3254_PAGE_0, TI3254_CLK_MDAC_REG, 0x80 | 0x03},                  /* R12 MDAC divider powered on, MDAC = 3 */
    {TI3254_PAGE_0, TI3254_DAC_OSR_MSB_REG, 0x00},                      /* R13 DOSR = 128 */
    {TI3254_PAGE_0, TI3254_DAC_OSR_LSB_REG, 0x80},                      /* R14 DOSR = 128 */
    {TI3254_PAGE_0, TI3254_CLK_NADC_REG, 0x80 | 0x10},                  /* R18 NADC divider powered on, NADC = 16 */
    {TI3254_PAGE_0, TI3254_CLK_MADC_REG, 0x80 | 0x03},                  /* R19 MADC divider powered on, MADC = 3 */
    {TI3254_PAGE_0, TI3254_ADC_OSR_REG, 0x80},                          /* R20 AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A) */
    {TI3254_PAGE_0, TI3254_BCLK_N_DIV, 0x80 | 0x0C},                    /* R30 BCLK divider powered up, val = 12 */
    {TI3254_PAGE_0, TI3254_AUDIO_IF_3_REG, 0x04},                       /* R29 Primary BCLK and Primary WCLK buffers are powered up */
    {TI3254_PAGE_0, 0x34, 0x10},        /* R52 CLKOUT on MFP5 */
    {TI3254_PAGE_0, 0x1A, 0x80 | 0x64}, /* R26 CLKOUT M powered up and divider = 100 */
    {TI3254_PAGE_0, 0x19, 0x00},        /* R25 MCLK on CDIV_CLKIN */
};


AudioHAL_I2CReg openScript[] =
{
    /* Configure Analog I/O */
    {TI3254_PAGE_1, TI3254_PWR_CTRL_REG, 0x08},                         /* R1 Disabled weak connection of AVdd with DVdd */
    {TI3254_PAGE_1, TI3254_LDO_CTRL_REG, 0x08 | 0x01},                  /* R2 Analog blocks enabled, Power AVdd from LDO */
    {TI3254_PAGE_1, TI3254_ANALOG_IP_QCHRG_CTRL_REG, 0x32},             /* R71 Analog inputs power up time is 6.4 ms */
    {TI3254_PAGE_1, TI3254_REF_PWR_UP_CTRL_REG, 0x01},                  /* R123 Reference will power up in 40ms when analog blocks are powered up */

    /* Configure ADC */
    /* Set low-pass filter to pass everything above 1Hz (0.00045 * ADC_FS) */
    {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_N0_REG_BASE, 0x7F},         /* ADC AGC Low-pass filter Coefficient MSB N0 = 8,288,607 */
    {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N0_REG_BASE+1), 0xFF},         /* ADC AGC Low-pass filter Coefficient N0 */
    {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N0_REG_BASE+2), 0xFF},         /* ADC AGC Low-pass filter Coefficient LSB N0 */
    {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_N1_REG_BASE, 0xFF},         /* ADC AGC Low-pass filter Coefficient MSB N1 = -20,992 */
    {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N1_REG_BASE+1), 0xAE},         /* ADC AGC Low-pass filter Coefficient N1 */
    {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N1_REG_BASE+2), 0x00},         /* ADC AGC Low-pass filter Coefficient LSB N1 */
    {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_D1_REG_BASE, 0x00},         /* ADC AGC Low-pass filter Coefficient MSB D1 = 512 */
    {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_D1_REG_BASE+1), 0x02},         /* ADC AGC Low-pass filter Coefficient D1 */
    {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_D1_REG_BASE+2), 0x00},         /* ADC AGC Low-pass filter Coefficient LSB D1 */
    /* IIR filter cutoff at approx. 400 Hz */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE, 0x3A},  /* ADC C36 MSB Right Channel IIR N0 = 3,863,296 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE+1), 0xF3}, /* ADC C36 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE+2), 0x00}, /* ADC C36 LSB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE, 0xF4},  /* ADC C37 MSB Right Channel IIR N1 = -736,512 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE+1), 0xC3},  /* ADC C37  */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE+2), 0x00},  /* ADC C37 LSB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE, 0x50},  /* ADC C38 MSB Right Channel IIR D1 = 5,262,080 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE+1), 0x4B},  /* ADC C38  */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE+2), 0x00},  /* ADC C38 LSB */
    /* EQ filter to remove 475 Hz, 10 Hz bandwidth, -24dB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE, 0x7E},  /* ADC C39 MSB Right Channel Biquad A N0 = 8,300,800 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE+1), 0xA9},  /* ADC C39  */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE+2), 0x00},  /* ADC C39 LSB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE, 0x81},  /* ADC C40 MSB Right Channel Biquad A N1 = -8,275,968 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE+1), 0xB8},  /* ADC C40 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE+2), 0x00},  /* ADC C40 LSB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE, 0x7E},  /* ADC C41 MSB Right Channel Biquad A N2 = 8,289,024 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE+1), 0x7B},  /* ADC C41 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE+2), 0x00},  /* ADC C41 LSB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE, 0x7E},  /* ADC C42 MSB Right Channel Biquad A D1 = 8,275,968 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE+1), 0x48},  /* ADC C42 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE+2), 0x00},  /* ADC C42 LSB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE, 0x82},  /* ADC C43 MSB Right Channel Biquad A D2 = -8,201,216 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE+1), 0xDC},  /* ADC C43 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE+2), 0x00},  /* ADC C43 LSB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE, 0x00},  /* ADC C44 MSB Right Channel Biquad A N0 = 0 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE+1), 0x00},  /* ADC C44 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE+2), 0x00},  /* ADC C44 LSB */
    {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE, 0x40},  /* ADC C45 MSB Right Channel Biquad A N1 = 4,194,304 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE+1), 0x00},  /* ADC C45 */
    {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE+2), 0x00},  /* ADC C45 LSB */
    /* Enable filtering and set Mic bias */
    {TI3254_PAGE_8, TI3254_ADC_ADP_FILTER_CTRL_REG, 0x04},              /* Adaptive Filtering enabled for ADC */
    {TI3254_PAGE_1, TI3254_COMMON_MODE_CONTROL_REG, 0x40},              /* R10 Full Chip Common Mode = 0.75v */
    {TI3254_PAGE_1, TI3254_MICBIAS_CTRL_REG, 0x40 | 0x20 | 0x04},       /* R51 Mic bias power enabled, 2.075V, Source = LDOIN */
    {TI3254_PAGE_0, TI3254_ADC_SIG_P_BLK_CTRL_REG, 0x02},               /* R61 ADC Signal Processing Block PRB_P2 */
    {TI3254_PAGE_1, TI3254_MICBIAS_CTRL_REG, 0x40},                     /* R51 MICBIAS powered up */

    /* TI3254_LINE_IN */
    {TI3254_PAGE_1, TI3254_LEFT_MICPGA_P_CTRL_REG, 0x40},               /* R52 IN1L is routed to Left MICPGA with 10k resistance */
    {TI3254_PAGE_1, TI3254_LEFT_MICPGA_N_CTRL_REG, 0x40},               /* R54 CM is routed to Left MICPGA via CM1L with 10k resistance */
    {TI3254_PAGE_1, TI3254_RIGHT_MICPGA_P_CTRL_REG, 0x40},              /* R55 IN1R is routed to Right MICPGA with 10k resistance */
    {TI3254_PAGE_1, TI3254_FLOAT_IP_CTRL_REG, 0xC0},                    /* R58 IN1L input is weakly driven to common mode. Use when not routing IN1L to Left and Right MICPGA and HPL, HPR */

    /* Enable ADC */
    {TI3254_PAGE_1, TI3254_LEFT_MICPGA_VOL_CTRL_REG, 0x80},             /* R59 0.0dB */
    {TI3254_PAGE_1, TI3254_RIGHT_MICPGA_VOL_CTRL_REG, 0x0C},            /* R60 6.0dB with 20K impedance yields 0.0dB */

    {TI3254_PAGE_0, TI3254_LEFT_ADC_VOL_CTRL_REG, 0x68},                /* R83 -12dB */
    {TI3254_PAGE_0, TI3254_RIGHT_ADC_VOL_CTRL_REG, 0x68},               /* R84 -12dB */
    {TI3254_PAGE_0, TI3254_ADC_CHANNEL_SETUP_REG, 0x40},                /* R81 Right Channel ADC is powered up, Left Channel ADC is powered down */
    {TI3254_PAGE_0, TI3254_ADC_FINE_GAIN_ADJ_REG, 0x80}                 /* R82 Right ADC Channel Un-muted. Left Muted. Left and Right ADC Channel Fine Gain = 0dB */
};


AudioHAL_I2CReg startScript[] =
{
    {TI3254_PAGE_0, TI3254_LEFT_DAC_VOL_CTRL_REG, 0x10},		/* R65
    {TI3254_PAGE_0, TI3254_RIGHT_DAC_VOL_CTRL_REG, 0x10},		/* R66
    {TI3254_PAGE_0, TI3254_LEFT_ADC_VOL_CTRL_REG, 0x0C},		/* R83
    {TI3254_PAGE_0, TI3254_RIGHT_ADC_VOL_CTRL_REG, 0x0C}		/* R84
};