AIC3xxx PA_MiniDSP 005.095.35815.001 main Model.AIC3254App8x4x_1 AIC3254App8x4x_TI_v1 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 miniDSP_A_Adaptive 62 31 0.00000011920928955078125 Enum RateAll Enabled main RateAll Enabled Adaptive mode for miniDSP_A Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled miniDSP_A_Cycles 62 31 0.00000011920928955078125 Int RateAll 904 main RateAll 904 Available instruction cycles for miniDSP_A 256 6144 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 4 0 1 0 1 Delay24bit false 904 miniDSP_A_Memory 62 31 Int RateAll 1024 main RateAll 1024 Available instruction memory for miniDSP_A 0 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1024 miniDSP_D_Adaptive 62 31 Enum RateAll Enabled main RateAll Enabled Adaptive mode for miniDSP_D Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Enabled miniDSP_D_Memory 62 31 Int RateAll 1024 main RateAll 1024 Available instruction memory for miniDSP_D 0 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1024 miniDSP_D_Cycles 62 31 Int RateAll 904 main RateAll 904 Available instruction cycles for miniDSP_D 352 6144 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 8 0 1 0 1 Delay24bit false 904 SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled FrameworkType 62 31 0.00000011920928955078125 String RateAll AIC3254App8x4x main RateAll AIC3254App8x4x -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false AIC3254App8x4x TargetType 62 31 0.00000011920928955078125 String RateAll TypeA main RateAll TypeA -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false TypeA SystemSettingsCode 62 31 0.00000011920928955078125 String RateAll ;----------------------------------------------------------------------------------- ; Software Reset ;----------------------------------------------------------------------------------- reg[ 0][ 1] = 0x01 ; Initialize the device through software reset reg[254][ 0] = 0x0a ; Delay 10ms ;----------------------------------------------------------------------------------- ; Configure Power Supplies ;----------------------------------------------------------------------------------- %%if (%%prop(TargetBoard) == 2) ; AIC3254EVM-U specific configuration reg[ 1][ 2] = 0xa9 ; Power up AVDD LDO reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection reg[ 1][ 2] = 0xa1 ; Enable Master Analog Power Control, AVDD LDO Powered %%else ; AIC3254EVM-K specific configuration reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control %%endif reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic) ; reg[254][0] = 0x28 ; Delay 40ms for REF to Power Up ;----------------------------------------------------------------------------------- ; Load miniDSP Code ;----------------------------------------------------------------------------------- PROGRAM_ADC ; miniDSP_A coefficients and instructions PROGRAM_DAC ; miniDSP_D coefficients and instructions ;----------------------------------------------------------------------------------- ; Signal Processing Settings ;----------------------------------------------------------------------------------- %%if (%%prop(SynchMode) == 1) ; SynchMode is enabled reg[ 0][ 60] = 0x80 ; DAC prog Mode: miniDSP_A and miniDSP_D ARE powered up together, miniDSP_A used for signal processing %%else ; SynchMode is disabled reg[ 0][ 60] = 0x00 ; DAC prog Mode: miniDSP_A and miniDSP_D NOT powered up together, miniDSP_A used for signal processing %%endif reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing %%if ("%%prop(FrameworkType)" == "AIC3254App8x4x") reg[ 0][ 17] = 0x08 ; 8x Interpolation reg[ 0][ 23] = 0x04 ; 4x Decimation %%endif %%if ("%%prop(FrameworkType)" == "AIC3254App4x2x") reg[ 0][ 17] = 0x04 ; 4x Interpolation reg[ 0][ 23] = 0x02 ; 2x Decimation %%endif %%if ("%%prop(FrameworkType)" == "AIC3254App2x1x") reg[ 0][ 17] = 0x02 ; 2x Interpolation reg[ 0][ 23] = 0x01 ; 1x Decimation %%endif IDAC = %%prop(miniDSP_D_Cycles) IADC = %%prop(miniDSP_A_Cycles) %%if (%%prop(miniDSP_A_Adaptive) == 1) reg[ 8][ 1] = 0x04 ; adaptive mode for ADC %%endif %%if (%%prop(miniDSP_D_Adaptive) == 1) reg[ 44][ 1] = 0x04 ; adaptive mode for DAC %%endif ;----------------------------------------------------------------------------------- ; Clock and Interface Configuration ;----------------------------------------------------------------------------------- ; USB Audio supports 8kHz to 48kHz sample rates ; An external audio interface is required for 88.2kHz to 192kHz sample rates ;----------------------------------------------------------------------------------- %%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 32 (MSB) reg[ 0][ 14] = 0x20 ; DOSR = 32 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x20 ; AOSR = 32 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 64 (MSB) reg[ 0][ 14] = 0x40 ; DOSR = 64 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x40 ; AOSR = 64 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB) reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 32000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 192 (MSB) reg[ 0][ 14] = 0xc0 ; DOSR = 192 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x8c ; MADC = 12, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x01 ; DOSR = 256 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 256 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x90 ; MADC = 16, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 16000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24 reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x01 ; DOSR = 384 (MSB) reg[ 0][ 14] = 0x80 ; DOSR = 384 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x98 ; MADC = 24, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 11025) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=16 reg[ 0][ 6] = 0x10 ; P=1, R=1, J=16 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x02 ; DOSR = 512 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 512 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0xa0 ; MADC = 32, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 8000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24 reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x03 ; DOSR = 768 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 768 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0xb0 ; MADC = 48, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif ;----------------------------------------------------------------------------------- ; ADC Channel Configuration ;----------------------------------------------------------------------------------- reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V %%if (%%prop(TargetBoard) == 2) ; AIC3254EVM-U specific configuration reg[ 1][ 52] = 0x10 ; Route IN2L to LEFT_P with 10K input impedance reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance reg[ 1][ 55] = 0x10 ; Route IN2R to RIGHT_P with 10K input impedance %%else ; AIC3254EVM-K specific configuration reg[ 1][ 52] = 0x40 ; Route IN1L to LEFT_P with 10K input impedance reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance %%endif reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC ;----------------------------------------------------------------------------------- ; DAC Channel Configuration ;----------------------------------------------------------------------------------- reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance reg[ 1][ 12] = 0x08 ; Route LDAC to HPL reg[ 1][ 13] = 0x08 ; Route RDAC to HPR reg[ 1][ 14] = 0x08 ; Route LDAC to LOL reg[ 1][ 15] = 0x08 ; Route LDAC to LOR reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC main RateAll ;----------------------------------------------------------------------------------- ; Software Reset ;----------------------------------------------------------------------------------- reg[ 0][ 1] = 0x01 ; Initialize the device through software reset reg[254][ 0] = 0x0a ; Delay 10ms ;----------------------------------------------------------------------------------- ; Configure Power Supplies ;----------------------------------------------------------------------------------- %%if (%%prop(TargetBoard) == 2) ; AIC3254EVM-U specific configuration reg[ 1][ 2] = 0xa9 ; Power up AVDD LDO reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection reg[ 1][ 2] = 0xa1 ; Enable Master Analog Power Control, AVDD LDO Powered %%else ; AIC3254EVM-K specific configuration reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control %%endif reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic) ; reg[254][0] = 0x28 ; Delay 40ms for REF to Power Up ;----------------------------------------------------------------------------------- ; Load miniDSP Code ;----------------------------------------------------------------------------------- PROGRAM_ADC ; miniDSP_A coefficients and instructions PROGRAM_DAC ; miniDSP_D coefficients and instructions ;----------------------------------------------------------------------------------- ; Signal Processing Settings ;----------------------------------------------------------------------------------- %%if (%%prop(SynchMode) == 1) ; SynchMode is enabled reg[ 0][ 60] = 0x80 ; DAC prog Mode: miniDSP_A and miniDSP_D ARE powered up together, miniDSP_A used for signal processing %%else ; SynchMode is disabled reg[ 0][ 60] = 0x00 ; DAC prog Mode: miniDSP_A and miniDSP_D NOT powered up together, miniDSP_A used for signal processing %%endif reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing %%if ("%%prop(FrameworkType)" == "AIC3254App8x4x") reg[ 0][ 17] = 0x08 ; 8x Interpolation reg[ 0][ 23] = 0x04 ; 4x Decimation %%endif %%if ("%%prop(FrameworkType)" == "AIC3254App4x2x") reg[ 0][ 17] = 0x04 ; 4x Interpolation reg[ 0][ 23] = 0x02 ; 2x Decimation %%endif %%if ("%%prop(FrameworkType)" == "AIC3254App2x1x") reg[ 0][ 17] = 0x02 ; 2x Interpolation reg[ 0][ 23] = 0x01 ; 1x Decimation %%endif IDAC = %%prop(miniDSP_D_Cycles) IADC = %%prop(miniDSP_A_Cycles) %%if (%%prop(miniDSP_A_Adaptive) == 1) reg[ 8][ 1] = 0x04 ; adaptive mode for ADC %%endif %%if (%%prop(miniDSP_D_Adaptive) == 1) reg[ 44][ 1] = 0x04 ; adaptive mode for DAC %%endif ;----------------------------------------------------------------------------------- ; Clock and Interface Configuration ;----------------------------------------------------------------------------------- ; USB Audio supports 8kHz to 48kHz sample rates ; An external audio interface is required for 88.2kHz to 192kHz sample rates ;----------------------------------------------------------------------------------- %%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 32 (MSB) reg[ 0][ 14] = 0x20 ; DOSR = 32 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x20 ; AOSR = 32 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 64 (MSB) reg[ 0][ 14] = 0x40 ; DOSR = 64 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x40 ; AOSR = 64 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB) reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 32000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 192 (MSB) reg[ 0][ 14] = 0xc0 ; DOSR = 192 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x8c ; MADC = 12, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x01 ; DOSR = 256 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 256 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x90 ; MADC = 16, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 16000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24 reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x01 ; DOSR = 384 (MSB) reg[ 0][ 14] = 0x80 ; DOSR = 384 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x98 ; MADC = 24, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 11025) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=16 reg[ 0][ 6] = 0x10 ; P=1, R=1, J=16 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x02 ; DOSR = 512 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 512 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0xa0 ; MADC = 32, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 8000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24 reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x03 ; DOSR = 768 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 768 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0xb0 ; MADC = 48, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif ;----------------------------------------------------------------------------------- ; ADC Channel Configuration ;----------------------------------------------------------------------------------- reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V %%if (%%prop(TargetBoard) == 2) ; AIC3254EVM-U specific configuration reg[ 1][ 52] = 0x10 ; Route IN2L to LEFT_P with 10K input impedance reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance reg[ 1][ 55] = 0x10 ; Route IN2R to RIGHT_P with 10K input impedance %%else ; AIC3254EVM-K specific configuration reg[ 1][ 52] = 0x40 ; Route IN1L to LEFT_P with 10K input impedance reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance %%endif reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC ;----------------------------------------------------------------------------------- ; DAC Channel Configuration ;----------------------------------------------------------------------------------- reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance reg[ 1][ 12] = 0x08 ; Route LDAC to HPL reg[ 1][ 13] = 0x08 ; Route RDAC to HPR reg[ 1][ 14] = 0x08 ; Route LDAC to LOL reg[ 1][ 15] = 0x08 ; Route LDAC to LOR reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC System settings reg[] code -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false ;----------------------------------------------------------------------------------- ; Software Reset ;----------------------------------------------------------------------------------- reg[ 0][ 1] = 0x01 ; Initialize the device through software reset reg[254][ 0] = 0x0a ; Delay 10ms ;----------------------------------------------------------------------------------- ; Configure Power Supplies ;----------------------------------------------------------------------------------- %%if (%%prop(TargetBoard) == 2) ; AIC3254EVM-U specific configuration reg[ 1][ 2] = 0xa9 ; Power up AVDD LDO reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection reg[ 1][ 2] = 0xa1 ; Enable Master Analog Power Control, AVDD LDO Powered %%else ; AIC3254EVM-K specific configuration reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control %%endif reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic) ; reg[254][0] = 0x28 ; Delay 40ms for REF to Power Up ;----------------------------------------------------------------------------------- ; Load miniDSP Code ;----------------------------------------------------------------------------------- PROGRAM_ADC ; miniDSP_A coefficients and instructions PROGRAM_DAC ; miniDSP_D coefficients and instructions ;----------------------------------------------------------------------------------- ; Signal Processing Settings ;----------------------------------------------------------------------------------- %%if (%%prop(SynchMode) == 1) ; SynchMode is enabled reg[ 0][ 60] = 0x80 ; DAC prog Mode: miniDSP_A and miniDSP_D ARE powered up together, miniDSP_A used for signal processing %%else ; SynchMode is disabled reg[ 0][ 60] = 0x00 ; DAC prog Mode: miniDSP_A and miniDSP_D NOT powered up together, miniDSP_A used for signal processing %%endif reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing %%if ("%%prop(FrameworkType)" == "AIC3254App8x4x") reg[ 0][ 17] = 0x08 ; 8x Interpolation reg[ 0][ 23] = 0x04 ; 4x Decimation %%endif %%if ("%%prop(FrameworkType)" == "AIC3254App4x2x") reg[ 0][ 17] = 0x04 ; 4x Interpolation reg[ 0][ 23] = 0x02 ; 2x Decimation %%endif %%if ("%%prop(FrameworkType)" == "AIC3254App2x1x") reg[ 0][ 17] = 0x02 ; 2x Interpolation reg[ 0][ 23] = 0x01 ; 1x Decimation %%endif IDAC = %%prop(miniDSP_D_Cycles) IADC = %%prop(miniDSP_A_Cycles) %%if (%%prop(miniDSP_A_Adaptive) == 1) reg[ 8][ 1] = 0x04 ; adaptive mode for ADC %%endif %%if (%%prop(miniDSP_D_Adaptive) == 1) reg[ 44][ 1] = 0x04 ; adaptive mode for DAC %%endif ;----------------------------------------------------------------------------------- ; Clock and Interface Configuration ;----------------------------------------------------------------------------------- ; USB Audio supports 8kHz to 48kHz sample rates ; An external audio interface is required for 88.2kHz to 192kHz sample rates ;----------------------------------------------------------------------------------- %%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 32 (MSB) reg[ 0][ 14] = 0x20 ; DOSR = 32 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x20 ; AOSR = 32 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 64 (MSB) reg[ 0][ 14] = 0x40 ; DOSR = 64 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x40 ; AOSR = 64 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB) reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 32000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 192 (MSB) reg[ 0][ 14] = 0xc0 ; DOSR = 192 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x8c ; MADC = 12, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x01 ; DOSR = 256 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 256 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x90 ; MADC = 16, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 16000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24 reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x01 ; DOSR = 384 (MSB) reg[ 0][ 14] = 0x80 ; DOSR = 384 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x98 ; MADC = 24, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 11025) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=16 reg[ 0][ 6] = 0x10 ; P=1, R=1, J=16 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x02 ; DOSR = 512 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 512 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0xa0 ; MADC = 32, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 8000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24 reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x03 ; DOSR = 768 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 768 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0xb0 ; MADC = 48, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif ;----------------------------------------------------------------------------------- ; ADC Channel Configuration ;----------------------------------------------------------------------------------- reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V %%if (%%prop(TargetBoard) == 2) ; AIC3254EVM-U specific configuration reg[ 1][ 52] = 0x10 ; Route IN2L to LEFT_P with 10K input impedance reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance reg[ 1][ 55] = 0x10 ; Route IN2R to RIGHT_P with 10K input impedance %%else ; AIC3254EVM-K specific configuration reg[ 1][ 52] = 0x40 ; Route IN1L to LEFT_P with 10K input impedance reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance %%endif reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC ;----------------------------------------------------------------------------------- ; DAC Channel Configuration ;----------------------------------------------------------------------------------- reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance reg[ 1][ 12] = 0x08 ; Route LDAC to HPL reg[ 1][ 13] = 0x08 ; Route RDAC to HPR reg[ 1][ 14] = 0x08 ; Route LDAC to LOL reg[ 1][ 15] = 0x08 ; Route LDAC to LOR reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC SystemSettingsXML 62 31 0.00000011920928955078125 String RateAll main RateAll System settings information -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false TargetBoard 62 31 0.00000011920928955078125 Enum RateAll Unknown main RateAll Unknown Target Board Unknown TLV320AIC3254EVM-K TLV320AIC3254EVM-U 0 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Unknown InstanceId 32 31 String RateAll AIC3254App8x4x_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false AIC3254App8x4x_1 Rate8 AIC3254App8x4x Yellow 255 255 Yellow 90 Solid AIC3254App8x4x_1 Black AIC3254App8x4x_1 216 96 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 6055 all false false Model.nrvar_1 nrvar_TI_v1 InputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 OutputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_A main RateAll miniDSP_A Processor where this component instance resides miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A NumBanks 62 31 0.00000011920928955078125 Enum RateAll 8_Filters main RateAll 8_Filters Number of Filter Banks used for the band splitting 4_Filters 5_Filters 6_Filters 7_Filters 8_Filters 9_Filters 10_Filters 11_Filters 12_Filters 13_Filters 14_Filters 15_Filters 16_Filters 4 5 6 7 8 9 10 11 12 13 14 15 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true 8_Filters Enable_Noise_Readout 62 31 0.00000011920928955078125 Enum RateAll FALSE main RateAll FALSE If True, enables I2C readable registers which represent noise measurment in each band TRUE FALSE 1 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true FALSE SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll nrvar_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false nrvar_1 Threshold 16 15 0.000030517578125 QFixed RateAll 0.25115966796875 main RateAll 0.25115966796875 Threshold Value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.25115966796875 Attenuation 16 15 0.000030517578125 QFixed RateAll 0.25 main RateAll 0.25 Attenuation value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.25 Inst1_B0 16 15 0.000030517578125 QFixed RateAll 0.0106201171875 main RateAll 0.0106201171875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0106201171875 Inst2_B0 16 15 0.000030517578125 QFixed RateAll 0.0150146484375 main RateAll 0.0150146484375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0150146484375 Inst1_A2 16 15 0.000030517578125 QFixed RateAll -0.978729248046875 main RateAll -0.978729248046875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.978729248046875 Inst1_A1O2 16 15 0.000030517578125 QFixed RateAll 0.98846435546875 main RateAll 0.98846435546875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.98846435546875 Inst1_B2 16 15 0.000030517578125 QFixed RateAll -0.0106201171875 main RateAll -0.0106201171875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.0106201171875 Inst2_A2 16 15 0.000030517578125 QFixed RateAll -0.969940185546875 main RateAll -0.969940185546875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.969940185546875 Inst9_B0 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst9_B2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst9_A1O2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst9_A2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst10_B0 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst10_B2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst10_A1O2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst10_A2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst11_B0 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst11_B2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst11_A1O2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst11_A2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst12_B0 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst12_B2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst12_A1O2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst12_A2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst13_B0 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst13_B2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst13_A1O2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst13_A2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst14_B0 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst14_B2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst14_A1O2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst14_A2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst15_B0 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst15_B2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst15_A1O2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst15_A2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst16_B0 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst16_B2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst16_A1O2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Inst16_A2 16 15 0.000030517578125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 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-0.88116455078125 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.88116455078125 Inst7_A2 16 15 0.000030517578125 QFixed RateAll -0.833740234375 main RateAll -0.833740234375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.833740234375 Inst8_A2 16 15 0.000030517578125 QFixed RateAll -0.769439697265625 main RateAll -0.769439697265625 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.769439697265625 Inst8_A1O2 16 15 0.000030517578125 QFixed RateAll 0.782928466796875 main RateAll 0.782928466796875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.782928466796875 Inst8_B2 16 15 0.000030517578125 QFixed RateAll -0.115264892578125 main RateAll -0.115264892578125 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.115264892578125 Inst8_B0 16 15 0.000030517578125 QFixed RateAll 0.115264892578125 main RateAll 0.115264892578125 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.115264892578125 Inst7_A1O2 16 15 0.000030517578125 QFixed RateAll 0.8636474609375 main RateAll 0.8636474609375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.8636474609375 Inst7_B2 16 15 0.000030517578125 QFixed RateAll -0.0831298828125 main RateAll -0.0831298828125 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.0831298828125 Inst7_B0 16 15 0.000030517578125 QFixed RateAll 0.0831298828125 main RateAll 0.0831298828125 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0831298828125 Inst6_A1O2 16 15 0.000030517578125 QFixed RateAll 0.91314697265625 main RateAll 0.91314697265625 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.91314697265625 Inst6_B2 16 15 0.000030517578125 QFixed RateAll -0.059417724609375 main RateAll -0.059417724609375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.059417724609375 Inst6_B0 16 15 0.000030517578125 QFixed RateAll 0.059417724609375 main RateAll 0.059417724609375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.059417724609375 Inst5_A1O2 16 15 0.000030517578125 QFixed RateAll 0.943756103515625 main RateAll 0.943756103515625 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.943756103515625 Inst5_B2 16 15 0.000030517578125 QFixed RateAll -0.042266845703125 main RateAll -0.042266845703125 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.042266845703125 Inst5_B0 16 15 0.000030517578125 QFixed RateAll 0.042266845703125 main RateAll 0.042266845703125 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.042266845703125 Inst4_A1O2 16 15 0.000030517578125 QFixed RateAll 0.96295166015625 main RateAll 0.96295166015625 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.96295166015625 Inst4_B2 16 15 0.000030517578125 QFixed RateAll -0.02996826171875 main RateAll -0.02996826171875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.02996826171875 Inst4_B0 16 15 0.000030517578125 QFixed RateAll 0.02996826171875 main RateAll 0.02996826171875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.02996826171875 Inst3_A1O2 16 15 0.000030517578125 QFixed RateAll 0.975189208984375 main RateAll 0.975189208984375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.975189208984375 Inst3_B2 16 15 0.000030517578125 QFixed RateAll -0.021240234375 main RateAll -0.021240234375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.021240234375 Inst3_B0 16 15 0.000030517578125 QFixed RateAll 0.021240234375 main RateAll 0.021240234375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.021240234375 Inst2_A1O2 16 15 0.000030517578125 QFixed RateAll 0.983184814453125 main RateAll 0.983184814453125 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.983184814453125 Inst2_B2 16 15 0.000030517578125 QFixed RateAll -0.0150146484375 main RateAll -0.0150146484375 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.999969482421875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.0150146484375 LowFreq 62 31 0.00000011920928955078125 String RateAll 300 main RateAll 300 Storage location for low frequency setting -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 300 HighFreq 62 31 0.00000011920928955078125 String RateAll 3400 main RateAll 3400 Storage for high frequency setting -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 3400 DSPCoefBlockStart1 62 31 Int RateAll 0 Non Linear Coefficients -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength1 62 31 Int RateAll 2 Non Linear Coefficients -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false -1 0 -1 -1 1 0 1 0 1 Delay24bit true 2 I2CPage1 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 I2CRegister1 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 DSPCoefBlockStart2 62 31 Int RateAll 2 BiQuad Coefficients for Filter 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 2 DSPCoefBlockLength2 62 31 Int RateAll 4 BiQuad Coefficients for Filter 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage2 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 I2CRegister2 62 31 Int RateAll 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 16 DSPCoefBlockStart3 62 31 Int RateAll 6 BiQuad Coefficients for Filter 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 6 DSPCoefBlockLength3 62 31 Int RateAll 4 BiQuad Coefficients for Filter 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage3 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 I2CRegister3 62 31 Int RateAll 32 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 32 DSPCoefBlockStart4 62 31 Int RateAll 10 BiQuad Coefficients for Filter 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 10 DSPCoefBlockLength4 62 31 Int RateAll 4 BiQuad Coefficients for Filter 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage4 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 I2CRegister4 62 31 Int RateAll 48 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 48 DSPCoefBlockStart5 62 31 Int RateAll 14 BiQuad Coefficients for Filter 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 14 DSPCoefBlockLength5 62 31 Int RateAll 4 BiQuad Coefficients for Filter 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage5 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 I2CRegister5 62 31 Int RateAll 64 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 64 DSPCoefBlockStart6 62 31 Int RateAll 18 BiQuad Coefficients for Filter 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 18 DSPCoefBlockLength6 62 31 Int RateAll 4 BiQuad Coefficients for Filter 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage6 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 I2CRegister6 62 31 Int RateAll 80 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 80 DSPCoefBlockStart7 62 31 Int RateAll 22 BiQuad Coefficients for Filter 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 0 -1 -1 1 0 1 0 1 Delay24bit true 22 DSPCoefBlockLength7 62 31 Int RateAll 4 BiQuad Coefficients for Filter 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 6 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage7 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 I2CRegister7 62 31 Int RateAll 96 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 96 DSPCoefBlockStart8 62 31 Int RateAll 26 BiQuad Coefficients for Filter 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 0 -1 -1 1 0 1 0 1 Delay24bit true 26 DSPCoefBlockLength8 62 31 Int RateAll 4 BiQuad Coefficients for Filter 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 7 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage8 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 I2CRegister8 62 31 Int RateAll 112 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 112 DSPCoefBlockStart9 62 31 Int RateAll 30 BiQuad Coefficients for Filter 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 0 -1 -1 1 0 1 0 1 Delay24bit true 30 DSPCoefBlockLength9 62 31 Int RateAll 4 BiQuad Coefficients for Filter 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 8 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage9 62 31 Int RateAll 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 9 I2CRegister9 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 DSPCoefBlockStart10 62 31 Int RateAll 34 BiQuad Coefficients for Filter 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 0 -1 -1 1 0 1 0 1 Delay24bit true 34 DSPCoefBlockLength10 62 31 Int RateAll 4 BiQuad Coefficients for Filter 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 9 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage10 62 31 Int RateAll 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 9 I2CRegister10 62 31 Int RateAll 24 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 24 DSPCoefBlockStart11 62 31 Int RateAll 38 BiQuad Coefficients for Filter 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 0 -1 -1 1 0 1 0 1 Delay24bit true 38 DSPCoefBlockLength11 62 31 Int RateAll 4 BiQuad Coefficients for Filter 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 10 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage11 62 31 Int RateAll 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 9 I2CRegister11 62 31 Int RateAll 40 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 40 DSPCoefBlockStart12 62 31 Int RateAll 42 BiQuad Coefficients for Filter 11 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 11 0 -1 -1 1 0 1 0 1 Delay24bit true 42 DSPCoefBlockLength12 62 31 Int RateAll 4 BiQuad Coefficients for Filter 11 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 11 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage12 62 31 Int RateAll 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 9 I2CRegister12 62 31 Int RateAll 56 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 56 DSPCoefBlockStart13 62 31 Int RateAll 46 BiQuad Coefficients for Filter 12 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 12 0 -1 -1 1 0 1 0 1 Delay24bit true 46 DSPCoefBlockLength13 62 31 Int RateAll 4 BiQuad Coefficients for Filter 12 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 12 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage13 62 31 Int RateAll 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 9 I2CRegister13 62 31 Int RateAll 72 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 72 DSPCoefBlockStart14 62 31 Int RateAll 50 BiQuad Coefficients for Filter 13 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 13 0 -1 -1 1 0 1 0 1 Delay24bit true 50 DSPCoefBlockLength14 62 31 Int RateAll 4 BiQuad Coefficients for Filter 13 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 13 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage14 62 31 Int RateAll 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 9 I2CRegister14 62 31 Int RateAll 88 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 88 DSPCoefBlockStart15 62 31 Int RateAll 54 BiQuad Coefficients for Filter 14 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 14 0 -1 -1 1 0 1 0 1 Delay24bit true 54 DSPCoefBlockLength15 62 31 Int RateAll 4 BiQuad Coefficients for Filter 14 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 14 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage15 62 31 Int RateAll 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 9 I2CRegister15 62 31 Int RateAll 104 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 104 DSPCoefBlockStart16 62 31 Int RateAll 58 BiQuad Coefficients for Filter 15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 15 0 -1 -1 1 0 1 0 1 Delay24bit true 58 DSPCoefBlockLength16 62 31 Int RateAll 4 BiQuad Coefficients for Filter 15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 15 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage16 62 31 Int RateAll 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 9 I2CRegister16 62 31 Int RateAll 120 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 120 DSPCoefBlockStart17 62 31 Int RateAll 62 BiQuad Coefficients for Filter 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 16 0 -1 -1 1 0 1 0 1 Delay24bit true 62 DSPCoefBlockLength17 62 31 Int RateAll 4 BiQuad Coefficients for Filter 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 16 0 -1 -1 1 0 1 0 1 Delay24bit true 4 I2CPage17 62 31 Int RateAll 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 10 I2CRegister17 62 31 Int RateAll 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 16 DSPCoefBlockStart18 62 31 Int RateAll 66 Noise Measurement Readout -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 17 0 -1 -1 1 0 1 0 1 Delay24bit true 66 DSPCoefBlockLength18 62 31 Int RateAll 17 Noise Measurement Readout -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 17 0 -1 -1 1 0 1 0 1 Delay24bit true 17 I2CPage18 62 31 Int RateAll 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 10 I2CRegister18 62 31 Int RateAll 32 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 32 Rate8 nrvar Yellow 255 255 Yellow 90 Solid nrvar_1 Black nrvar_1 216 264 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 5460 all false false Model.Dec4xIn_1 Dec4xIn_TI_v3 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 2 main RateAll 2 2 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_A main RateAll miniDSP_A miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll Dec4xIn_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Dec4xIn_1 AGC_Enable 62 31 0.00000011920928955078125 Enum RateAll Disable main RateAll Disable Enable Disable 128 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disable Volume_Control_dB 16 1 0.5 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -12.0 20.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Left_Fine_Gain 62 31 0.00000011920928955078125 Enum RateAll 0dB main RateAll 0dB 0dB -0.1dB -0.2dB -0.3dB -0.4db Muted 0 1 2 3 4 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0dB Right_Fine_Gain 62 31 0.00000011920928955078125 Enum RateAll 0dB main RateAll 0dB 0dB -0.1dB -0.2dB -0.3dB -0.4db Muted 0 1 2 3 4 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0dB Alpha 24 23 0.00000011920928955078125 QFixed RateAll 0.00560283660888671875 main RateAll 0.00560283660888671875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.00560283660888671875 1minus2alpha 24 23 0.00000011920928955078125 QFixed RateAll 0.9887943267822265625 main RateAll 0.9887943267822265625 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.9887943267822265625 Energy_Time_Constant_ms 62 31 0.000030517578125 Enum RateAll 2_ms main RateAll 2_ms 1_ms 2_ms 3_ms 4_ms 5_ms 6_ms 7_ms 8_ms 9_ms 10_ms 20_ms 30_ms 40_ms 50_ms 60_ms 70_ms 80_ms 90_ms 100_ms 150_ms 200_ms 250_ms 300_ms 350_ms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 2_ms AGC_Target_Level 62 31 0.00000011920928955078125 Enum RateAll -10dB main RateAll -10dB -5.5dB -8.0dB -10dB -12dB -14dB -17dB -20dB -24dB 0 1 2 3 4 5 6 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false -10dB AGC_Gain_Hysteresis 62 31 0.00000011920928955078125 Enum RateAll Disable main RateAll Disable Disable 0.5dB 1.0dB 1.5dB 0 1 2 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disable AGC_Hysteresis_Setting 62 31 0.00000011920928955078125 Enum RateAll Disable main RateAll Disable 1.0dB 2.0dB 4.0dB Disable 0 1 2 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disable AGC_Noise_Threshold 62 31 0.00000011920928955078125 Enum RateAll -90dB main RateAll -90dB Disable -30dB -32dB -34dB -36dB -38dB -40dB -42dB -44dB -46dB -48dB -50dB -52dB -54dB -56dB -58dB -60dB -62dB -64dB -66dB -68dB -70dB -72dB -74dB -76dB -78dB -80dB -82dB -84dB -86dB -88dB -90dB -28 -30 -32 -34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 -74 -76 -78 -80 -82 -84 -86 -88 -90 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 2 0 1 0 1 Delay24bit false -90dB AGC_Maximum_Gain 16 1 0.5 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 58.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 AGC_Attack_Time 62 31 0.00000011920928955078125 Int RateAll 27 main RateAll 27 1 63 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 27 AGC_Attack_Time_Factor 62 31 0.00000011920928955078125 Enum RateAll 1x main RateAll 1x 1x 2x 4x 8x 16x 32x 64x 128x 0 1 2 3 4 5 6 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1x AGC_Decay_Time 62 31 0.00000011920928955078125 Int RateAll 43 main RateAll 43 1 63 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 43 AGC_Decay_Time_Factor 62 31 0.00000011920928955078125 Enum RateAll 1x main RateAll 1x 1x 2x 4x 8x 16x 32x 64x 128x 0 1 2 3 4 5 6 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1x AGC_Noise_Debounce_Time 62 31 0.00000011920928955078125 Enum RateAll 128x1WordCLK main RateAll 128x1WordCLK 0x1WordCLK 4x1WordCLK 8x1WordCLK 16x1WordCLK 32x1WordCLK 64x1WordCLK 128x1WordCLK 256x1WordCLK 512x1WordCLK 1024x1WordCLK 2048x1WordCLK 4096x1WordCLK 4096x2WordCLK 4096x3WordCLK 4096x4WordCLK 4096x5WordCLK 4096x6WordCLK 4096x7WordCLK 4096x8WordCLK 4096x9WordCLK 4096x10WordCLK 4096x11WordCLK 4096x12WordCLK 4096x13WordCLK 4096x14WordCLK 4096x15WordCLK 4096x16WordCLK 4096x17WordCLK 4096x18WordCLK 4096x19WordCLK 4096x20WordCLK 4096x21WordCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 128x1WordCLK AGC_Signal_Debounce_Time 62 31 0.00000011920928955078125 Enum RateAll 0x1WordCLK main RateAll 0x1WordCLK 0x1WordCLK 4x1WordCLK 8x1WordCLK 16x1WordCLK 32x1WordCLK 64x1WordCLK 128x1WordCLK 256x1WordCLK 512x1WordCLK 1024x1WordCLK 2048x1WordCLK 2048x2WordCLK 2048x3WordCLK 2048x4WordCLK 2048x5WordCLK 2048x6WordCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0x1WordCLK AGC_Gain_Flag 16 1 0.5 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -12.0 58.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 AGC_HPF_n0 24 23 0.00000011920928955078125 QFixed RateAll 0.99999988079071044921875 main RateAll 0.99999988079071044921875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.99999988079071044921875 AGC_HPF_n1 24 23 0.00000011920928955078125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 AGC_HPF_d1 24 23 0.00000011920928955078125 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 DSPCoefBlockStart1 62 31 Int RateAll 83 Alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 83 DSPCoefBlockLength1 62 31 Int RateAll 1 Alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage1 62 31 Int RateAll 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 10 I2CRegister1 62 31 Int RateAll 100 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 100 DSPCoefBlockStart2 62 31 Int RateAll 84 1minus2alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 84 DSPCoefBlockLength2 62 31 Int RateAll 1 1minus2alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage2 62 31 Int RateAll 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 10 I2CRegister2 62 31 Int RateAll 104 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 104 DSPCoefBlockStart3 62 31 Int RateAll 85 AGC HPF n0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 85 DSPCoefBlockLength3 62 31 Int RateAll 1 AGC HPF n0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage3 62 31 Int RateAll 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 10 I2CRegister3 62 31 Int RateAll 108 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 108 DSPCoefBlockStart4 62 31 Int RateAll 86 AGC HPF n1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 86 DSPCoefBlockLength4 62 31 Int RateAll 1 AGC HPF n1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage4 62 31 Int RateAll 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 10 I2CRegister4 62 31 Int RateAll 112 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 112 DSPCoefBlockStart5 62 31 Int RateAll 87 AGC HPF d1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 87 DSPCoefBlockLength5 62 31 Int RateAll 1 AGC HPF d1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage5 62 31 Int RateAll 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 10 I2CRegister5 62 31 Int RateAll 116 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 116 Rate8 Dec4xIn Yellow 255 255 Yellow 90 Solid Dec4xIn_1 Black Dec4xIn_1 72 264 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 5697 all false false Model.HPF Biquad_TI_v1 InputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 OutputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 TargetProcessor 62 31 Enum RateAll miniDSP_A main RateAll miniDSP_A Processor where this component instance resides miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A Instances 62 31 Int RateAll 1 main RateAll 1 Number of biquad instances 1 10 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true 1 Inst1_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst1_FilterType 62 31 String RateAll High Pass main RateAll High Pass Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false High Pass Inst1_FilterSubType 62 31 String RateAll ButterWorth 1 main RateAll ButterWorth 1 Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false ButterWorth 1 Inst1_CornerFrequency 62 31 Float RateAll 100 main RateAll 100 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 100 Inst1_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst1_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst1_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst1_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst2_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst2_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst2_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst2_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst2_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst2_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst2_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst2_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst3_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst3_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst3_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst3_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst3_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst3_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst3_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst3_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst4_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst4_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst4_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst4_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst4_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst4_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst4_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst4_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst5_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst5_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst5_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst5_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst5_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst5_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst5_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst5_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst6_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst6_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst6_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst6_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst6_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst6_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst6_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst6_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst7_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst7_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst7_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst7_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst7_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst7_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst7_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst7_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst8_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst8_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst8_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst8_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst8_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst8_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst8_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst8_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst9_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst9_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst9_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst9_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst9_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst9_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst9_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst9_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst10_On 62 31 Int RateAll 1 main RateAll 1 1 if graph button selected in popup GUI, 0 otherwise. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst10_FilterType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Type. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst10_FilterSubType 62 31 String RateAll InitialValue main RateAll InitialValue Filter Subtype. -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false InitialValue Inst10_CornerFrequency 62 31 Float RateAll 1.0 main RateAll 1.0 Corner Frequency -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst10_Gain 62 31 Float RateAll 1.0 main RateAll 1.0 Gain -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst10_Bandwidth 62 31 Float RateAll 1.0 main RateAll 1.0 Bandwidth -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst10_Q 62 31 Float RateAll 1.0 main RateAll 1.0 Q value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 Inst10_PB 62 31 Float RateAll 1.0 main RateAll 1.0 Pass Band -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false 1.0 SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll HPF -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false HPF Inst1_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.96219503879547119140625 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.9929263591766357421875 Rate48 0.99349725246429443359375 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.96219503879547119140625 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.9929263591766357421875 Rate48 0.99349725246429443359375 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst1_B1 24 23 0.00000011920928955078125 QFixed Rate8 -0.4810974597930908203125 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 -0.49646317958831787109375 Rate48 -0.49674856662750244140625 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 -0.4810974597930908203125 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 -0.49646317958831787109375 Rate48 -0.49674856662750244140625 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B1 for Biquad Instance 1 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst1_B2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B2 for Biquad Instance 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst1_A1 24 23 0.00000011920928955078125 QFixed Rate8 0.4621951580047607421875 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.4929263591766357421875 Rate48 0.493497371673583984375 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.4621951580047607421875 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.4929263591766357421875 Rate48 0.493497371673583984375 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A1 for Biquad Instance 1 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst1_A2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A2 for Biquad Instance 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst1_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst2_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst2_B1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B1 for Biquad Instance 2 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst2_B2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B2 for Biquad Instance 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst2_A1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A1 for Biquad Instance 2 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst2_A2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A2 for Biquad Instance 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst2_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst3_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst3_B1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B1 for Biquad Instance 3 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst3_B2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B2 for Biquad Instance 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst3_A1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A1 for Biquad Instance 3 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst3_A2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A2 for Biquad Instance 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst3_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst4_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst4_B1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B1 for Biquad Instance 4 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst4_B2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B2 for Biquad Instance 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst4_A1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A1 for Biquad Instance 4 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst4_A2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A2 for Biquad Instance 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst4_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst5_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst5_B1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B1 for Biquad Instance 5 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst5_B2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B2 for Biquad Instance 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst5_A1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A1 for Biquad Instance 5 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst5_A2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A2 for Biquad Instance 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst5_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst6_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst6_B1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B1 for Biquad Instance 6 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst6_B2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B2 for Biquad Instance 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst6_A1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A1 for Biquad Instance 6 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst6_A2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter A2 for Biquad Instance 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 6 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst6_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst7_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst7_B1 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B1 for Biquad Instance 7 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst7_B2 24 23 0.00000011920928955078125 QFixed Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 main Rate8 0.0 Rate11 0.0 Rate16 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate88 0.0 Rate96 0.0 Rate176 0.0 Rate192 0.0 Rate22 0.0 Biquad Filter B2 for Biquad Instance 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst7_A1 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter A1 for Biquad Instance 7 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst7_A2 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter A2 for Biquad Instance 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 7 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst7_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst8_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst8_B1 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter B1 for Biquad Instance 8 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst8_B2 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter B2 for Biquad Instance 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst8_A1 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter A1 for Biquad Instance 8 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst8_A2 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter A2 for Biquad Instance 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 8 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst8_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst9_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst9_B1 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter B1 for Biquad Instance 9 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst9_B2 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter B2 for Biquad Instance 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst9_A1 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter A1 for Biquad Instance 9 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst9_A2 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter A2 for Biquad Instance 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 9 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst9_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 Inst10_B0 24 23 0.00000011920928955078125 QFixed Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 main Rate8 0.99999988079071044921875 Rate11 0.99999988079071044921875 Rate16 0.99999988079071044921875 Rate24 0.99999988079071044921875 Rate32 0.99999988079071044921875 Rate44 0.99999988079071044921875 Rate48 0.99999988079071044921875 Rate88 0.99999988079071044921875 Rate96 0.99999988079071044921875 Rate176 0.99999988079071044921875 Rate192 0.99999988079071044921875 Rate22 0.0 Biquad Filter B0 for Biquad Instance 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst10_B1 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter B1 for Biquad Instance 10 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst10_B2 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter B2 for Biquad Instance 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst10_A1 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter A1 for Biquad Instance 10 (actual value / 2) -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst10_A2 24 23 0.00000011920928955078125 QFixed Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 main Rate16 0.0 Rate8 0.0 Rate24 0.0 Rate32 0.0 Rate44 0.0 Rate48 0.0 Rate96 0.0 Rate192 0.0 Rate11 0.0 Rate22 0.0 Rate88 0.0 Rate176 0.0 Biquad Filter A2 for Biquad Instance 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 10 -1 -1 -1 1 0 1 0 1 Delay24bit false Inst10_Scale 62 31 String RateAll 1 main RateAll 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1 DSPCoefBlockStart1 62 31 Int RateAll 93 BiQuad Coefficients for Instance 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 93 DSPCoefBlockLength1 62 31 Int RateAll 5 BiQuad Coefficients for Instance 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage1 62 31 Int RateAll 11 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 11 I2CRegister1 62 31 Int RateAll 20 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 20 DSPCoefBlockStart2 62 31 Int RateAll 0 BiQuad Coefficients for Instance 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength2 62 31 Int RateAll 5 BiQuad Coefficients for Instance 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage2 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister2 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart3 62 31 Int RateAll 0 BiQuad Coefficients for Instance 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength3 62 31 Int RateAll 5 BiQuad Coefficients for Instance 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage3 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister3 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart4 62 31 Int RateAll 0 BiQuad Coefficients for Instance 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength4 62 31 Int RateAll 5 BiQuad Coefficients for Instance 4 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage4 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister4 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart5 62 31 Int RateAll 0 BiQuad Coefficients for Instance 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength5 62 31 Int RateAll 5 BiQuad Coefficients for Instance 5 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage5 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister5 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart6 62 31 Int RateAll 0 BiQuad Coefficients for Instance 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 6 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength6 62 31 Int RateAll 5 BiQuad Coefficients for Instance 6 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 6 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage6 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister6 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart7 62 31 Int RateAll 0 BiQuad Coefficients for Instance 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 7 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength7 62 31 Int RateAll 5 BiQuad Coefficients for Instance 7 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 7 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage7 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister7 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart8 62 31 Int RateAll 0 BiQuad Coefficients for Instance 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 8 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength8 62 31 Int RateAll 5 BiQuad Coefficients for Instance 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 8 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage8 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister8 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart9 62 31 Int RateAll 0 BiQuad Coefficients for Instance 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 9 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength9 62 31 Int RateAll 5 BiQuad Coefficients for Instance 9 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 9 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage9 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister9 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 DSPCoefBlockStart10 62 31 Int RateAll 0 BiQuad Coefficients for Instance 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 10 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength10 62 31 Int RateAll 5 BiQuad Coefficients for Instance 10 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 10 0 -1 -1 1 0 1 0 1 Delay24bit true 5 I2CPage10 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 I2CRegister10 62 31 Int RateAll 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 0 Rate8 Biquad LightCyan 255 255 Yellow 90 Solid HPF Black HPF 144 264 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 5564 all false false Model.DSP_A_DSP_D_1 DSP_A_DSP_D_TI_v1 InputChannels 62 31 Enum RateAll 2 main RateAll 2 1 2 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 OutputChannels 62 31 Enum RateAll 2 main RateAll 2 1 2 1 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll DSP_A_DSP_D_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false DSP_A_DSP_D_1 Rate8 DSP_A_DSP_D Yellow 255 255 Yellow 90 Solid DSP_A_DSP_D_1 Black DSP_A_DSP_D_1 348 276 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 2402 all false false Model.Int8xOut_1 Int8xOut_TI_v1 InputChannels 62 31 Enum RateAll 2 main RateAll 2 2 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_D main RateAll miniDSP_D miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_D Include_DRC 62 31 0.00000011920928955078125 Enum RateAll NO main RateAll NO NO YES 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true NO ComponentVisibleFilter 62 31 0.00000011920928955078125 String RateAll not '2x1x' in gde.GetProperty(gde.GetFramework(), "FrameworkType") main RateAll not '2x1x' in gde.GetProperty(gde.GetFramework(), "FrameworkType") -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false not '2x1x' in gde.GetProperty(gde.GetFramework(), "FrameworkType") SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll Int8xOut_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Int8xOut_1 DRC_Enable 62 31 0.00000011920928955078125 Enum RateAll Disable main RateAll Disable Enable Disable 96 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disable Volume_Control_dB 16 1 0.5 QFixed RateAll 0.0 main RateAll 0.0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -63.5 24.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 Alpha 24 23 0.00000011920928955078125 QFixed RateAll 0.000566959381103515625 main RateAll 0.000566959381103515625 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false true false 1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.000566959381103515625 1minus2alpha 24 23 0.00000011920928955078125 QFixed RateAll 0.99886608123779296875 main RateAll 0.99886608123779296875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false true false 2 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.99886608123779296875 Energy_Time_Constant_ms 62 31 0.000030517578125 Enum RateAll 20_ms main RateAll 20_ms 1_ms 2_ms 3_ms 4_ms 5_ms 6_ms 7_ms 8_ms 9_ms 10_ms 20_ms 30_ms 40_ms 50_ms 60_ms 70_ms 80_ms 90_ms 100_ms 150_ms 200_ms 250_ms 300_ms 350_ms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 20_ms DRC_Hysteresis 62 31 0.00000011920928955078125 Enum RateAll 3dB main RateAll 3dB 0dB 1dB 2dB 3dB 0 1 2 3 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 3dB DRC_Threshold_dBFS 62 31 0.00000011920928955078125 Int RateAll -24 main RateAll -24 -24 -3 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 3 0 1 0 1 Delay24bit false -24 DRC_HOLD_Time_WordCLK 62 31 0.00000011920928955078125 Enum RateAll 0 main RateAll 0 0 32 64 128 256 512 1024 2048 4096 2x4096 4x4096 8x4096 16x4096 32x4096 64x4096 128x4096 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 DRC_Attack_Rate_perWCLK 62 31 0.00000011920928955078125 Enum RateAll 1div1024dB main RateAll 1div1024dB 4dB 2dB 1dB 0.5dB 0.25dB 0.125dBperWCLK 1div16dB 1div32dB 1div64dB 1div128dB 1div256dB 1div512dB 1div1024dB 1div2048dB 1div4096dB 1div8192dB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1div1024dB DRC_Decay_Rate_perWCLK 62 31 0.00000011920928955078125 Enum RateAll 1div4096dB main RateAll 1div4096dB 1div64dB 1div128dB 1div256dB 1div512dB 1div1024dB 1div2048dB 1div4096dB 1div8192dB 1div16384dB 1div32768dB 1div65536dB 1div131072dB 1div262144 1div524288 1div1048576dB 1div2097152dB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 1div4096dB HPF_n0 24 23 0.00000011920928955078125 QFixed RateAll 0.999725341796875 main RateAll 0.999725341796875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 3 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.999725341796875 HPF_n1 24 23 0.00000011920928955078125 QFixed RateAll -0.999725341796875 main RateAll -0.999725341796875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 4 -1 -1 -1 1 0 1 0 1 Delay24bit false -0.999725341796875 HPF_d1 24 23 0.00000011920928955078125 QFixed RateAll 0.999481201171875 main RateAll 0.999481201171875 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false 5 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.999481201171875 DSPCoefBlockStart1 62 31 Int RateAll 0 Alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 0 DSPCoefBlockLength1 62 31 Int RateAll 1 Alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 1 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage1 62 31 Int RateAll 44 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 44 I2CRegister1 62 31 Int RateAll 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 8 DSPCoefBlockStart2 62 31 Int RateAll 1 1minus2alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 1 DSPCoefBlockLength2 62 31 Int RateAll 1 1minus2alpha -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 2 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage2 62 31 Int RateAll 44 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 44 I2CRegister2 62 31 Int RateAll 12 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 12 DSPCoefBlockStart3 62 31 Int RateAll 2 HPF n0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 2 DSPCoefBlockLength3 62 31 Int RateAll 1 HPF n0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 3 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage3 62 31 Int RateAll 44 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 44 I2CRegister3 62 31 Int RateAll 16 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 16 DSPCoefBlockStart4 62 31 Int RateAll 3 HPF n1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 3 DSPCoefBlockLength4 62 31 Int RateAll 1 HPF n1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 4 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage4 62 31 Int RateAll 44 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 44 I2CRegister4 62 31 Int RateAll 20 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 20 DSPCoefBlockStart5 62 31 Int RateAll 4 HPF d1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 4 DSPCoefBlockLength5 62 31 Int RateAll 1 HPF d1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false 5 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage5 62 31 Int RateAll 44 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 44 I2CRegister5 62 31 Int RateAll 24 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 24 Rate8 Int8xOut Yellow 255 255 Yellow 90 Solid Int8xOut_1 Black Int8xOut_1 480 276 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 5021 all false false Model.I2S_Out_1 I2S_Out_TI_v1 InputChannels 62 31 Enum RateAll 2 main RateAll 2 2 2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 TargetProcessor 62 31 0.00000011920928955078125 Enum RateAll miniDSP_A main RateAll miniDSP_A miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll I2S_Out_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false I2S_Out_1 Rate8 I2S_Out LightSteelBlue 255 255 Yellow 90 Solid I2S_Out_1 Black I2S_Out_1 480 204 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 6520 all false false Model.Split_1 Split_TI_v1 InputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 OutputChannels 62 31 Enum RateAll 2 main RateAll 2 2 3 4 5 6 7 8 2 3 4 5 6 7 8 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 2 TargetProcessor 62 31 Enum RateAll miniDSP_A main RateAll miniDSP_A Processor where this component instance will reside miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll Split_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false Split_1 Rate8 Split Yellow 255 255 Yellow 90 Solid Split_1 Black Split_1 276 264 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 1975 all false false Model.D_to_C_1 D_to_C_TI_v3 InputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 OutputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 TargetProcessor 62 31 Enum RateAll miniDSP_A main RateAll miniDSP_A Processor where this component instance resides miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A Shift 62 31 Int RateAll 2 main RateAll 2 Shift Factor -16 15 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 2 SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll D_to_C_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false D_to_C_1 Coef 24 22 0.0000002384185791015625 QFixed RateAll 0.0 main RateAll 0.0 2.xx Coef value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -2.0 1.9999997615814208984375 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 DSPCoefBlockStart1 62 31 Int RateAll 98 Coef -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 0 -1 -1 1 0 1 0 1 Delay24bit true 98 DSPCoefBlockLength1 62 31 Int RateAll 1 Coef -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false -1 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage1 62 31 Int RateAll 11 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 11 I2CRegister1 62 31 Int RateAll 40 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 40 Rate8 D_to_C LightGreen 255 255 Yellow 90 Solid D_to_C_1 Black D_to_C_1 120 336 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 2484 all false false Model.C_to_D_1 C_to_D_TI_v3 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 TargetProcessor 62 31 Enum RateAll miniDSP_D main RateAll miniDSP_D Processor where this component instance resides miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_D Shift 62 31 Int RateAll 0 main RateAll 0 Shift value -16 2 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll C_to_D_1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false C_to_D_1 Coef 24 23 0.00000011920928955078125 QFixed RateAll 0.0 main RateAll 0.0 1.xx Coef -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 DSPCoefBlockStart1 62 31 Int RateAll 5 Coef Value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 0 -1 -1 1 0 1 0 1 Delay24bit true 5 DSPCoefBlockLength1 62 31 Int RateAll 1 Coef Value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false -1 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage1 62 31 Int RateAll 44 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 44 I2CRegister1 62 31 Int RateAll 28 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 28 Rate8 C_to_D LightGreen 255 255 Yellow 90 Solid C_to_D_1 Black C_to_D_1 396 336 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 3896 all false false Model.C_to_D_2 C_to_D_TI_v3 InputChannels 62 31 Enum RateAll 0 main RateAll 0 0 0 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 0 OutputChannels 62 31 Enum RateAll 1 main RateAll 1 1 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false 0 0 0 0 1 0 1 0 1 Delay24bit true 1 TargetProcessor 62 31 Enum RateAll miniDSP_A main RateAll miniDSP_A Processor where this component instance resides miniDSP_A miniDSP_D 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit true miniDSP_A Shift 62 31 Int RateAll 0 main RateAll 0 Shift value -16 2 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0 SynchMode 62 31 Enum RateAll Disabled main RateAll Disabled miniDSP_A and miniDSP_D operate in synchronous mode Disabled Enabled 0 1 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true false true -1 -1 -1 -1 1 0 1 0 1 Delay24bit false Disabled InstanceId 32 31 String RateAll C_to_D_2 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 false false false 0 0 0 0 1 0 1 0 1 Delay24bit false C_to_D_2 Coef 24 23 0.00000011920928955078125 QFixed RateAll 0.0 main RateAll 0.0 1.xx Coef -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 -1.0 0.99999988079071044921875 false false false -1 -1 -1 -1 1 0 1 0 1 Delay24bit false 0.0 DSPCoefBlockStart1 62 31 Int RateAll 99 Coef Value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false -1 0 -1 -1 1 0 1 0 1 Delay24bit true 99 DSPCoefBlockLength1 62 31 Int RateAll 1 Coef Value -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 true true false -1 0 -1 -1 1 0 1 0 1 Delay24bit true 1 I2CPage1 62 31 Int RateAll 11 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 11 I2CRegister1 62 31 Int RateAll 44 -2147483648 2147483647 -1.7976931348623157E+308 1.7976931348623157E+308 -4 0 3 536870911 0.0 0.0 false true false 0 0 0 0 1 0 1 0 1 Delay24bit false 44 Rate8 C_to_D LightGreen 255 255 Yellow 90 Solid C_to_D_2 Black C_to_D_2 396 240 true false false false false false false false false false false false None AIC3254 TypeA AIC3254App8x4x 904 1024 904 1024 false 8000 44100 3896 all false false Model.Dec4xIn_1 Model.HPF Model.Dec4xIn_1.Ch1_Out Model.HPF.Ch1_In 96 276 144 276 Black 2 Model.Dec4xIn_1.Ch1_Out Model.HPF.Ch1_In Model.Dec4xIn_1 Model.HPF false all Biquad_TI_v1 Dec4xIn_TI_v3 Model.HPF Model.nrvar_1 Model.HPF.Ch1_Out Model.nrvar_1.Ch1_In 168 276 216 276 Black 2 Model.HPF.Ch1_Out Model.nrvar_1.Ch1_In Model.HPF Model.nrvar_1 false all nrvar_TI_v1 Biquad_TI_v1 Model.DSP_A_DSP_D_1 Model.Int8xOut_1 Model.DSP_A_DSP_D_1.Ch1_Out Model.Int8xOut_1.Ch1_In 372 288 480 288 Black 2 Model.DSP_A_DSP_D_1.Ch1_Out Model.Int8xOut_1.Ch1_In Model.DSP_A_DSP_D_1 Model.Int8xOut_1 false all Int8xOut_TI_v1 DSP_A_DSP_D_TI_v1 Model.nrvar_1 Model.Split_1 Model.nrvar_1.Ch1_Out Model.Split_1.Ch1_In 240 276 275.999969 275.999969 Black 2 Model.nrvar_1.Ch1_Out Model.Split_1.Ch1_In Model.nrvar_1 Model.Split_1 false all Split_TI_v1 nrvar_TI_v1 Model.Split_1 Model.DSP_A_DSP_D_1 Model.Split_1.Ch2_Out Model.DSP_A_DSP_D_1.Ch1_In 299.999969 287.999969 348 288 Black 2 Model.Split_1.Ch2_Out Model.DSP_A_DSP_D_1.Ch1_In Model.Split_1 Model.DSP_A_DSP_D_1 false all DSP_A_DSP_D_TI_v1 Split_TI_v1 Model.Split_1 Model.I2S_Out_1 Model.Split_1.Ch1_Out Model.I2S_Out_1.Ch1_In 299.999969 275.999969 324 276 324 216 480 216 Black 2 Model.Split_1.Ch1_Out Model.I2S_Out_1.Ch1_In Model.Split_1 Model.I2S_Out_1 false all I2S_Out_TI_v1 Split_TI_v1 Model.Dec4xIn_1 Model.D_to_C_1 Model.Dec4xIn_1.Ch2_Out Model.D_to_C_1.Ch1_In 120 348 96 288 Black 2 Model.D_to_C_1.Ch1_In Model.Dec4xIn_1.Ch2_Out Model.D_to_C_1 Model.Dec4xIn_1 false all D_to_C_TI_v3 Dec4xIn_TI_v3 Model.C_to_D_1 Model.Int8xOut_1 Model.C_to_D_1.Ch1_Out Model.Int8xOut_1.Ch2_In 420 348 480 300 Black 2 Model.C_to_D_1.Ch1_Out Model.Int8xOut_1.Ch2_In Model.C_to_D_1 Model.Int8xOut_1 false all Int8xOut_TI_v1 C_to_D_TI_v3 Model.C_to_D_2 Model.I2S_Out_1 Model.C_to_D_2.Ch1_Out Model.I2S_Out_1.Ch2_In 480 228 420 252 Black 2 Model.I2S_Out_1.Ch2_In Model.C_to_D_2.Ch1_Out Model.I2S_Out_1 Model.C_to_D_2 false all I2S_Out_TI_v1 C_to_D_TI_v3 0 0 1000 800 0 0 1000 800 &F &d &T &p/&P White PowderBlue Rate8 RateAll true false false false false false false false false false false false main base base 1 main Rate8 true false false false false false false false false false false false true false