Application:  PurePath Studio (Portable Audio) MiniDSP GDE
File Name:    ProcessFlowListing.txt
Date:         2014/7/17 上午 11:52:51
Version:      version 5.95 build 1 revision 17483
================================================================================

Commands during Code Generation
===============================


Configurations and Rates Supported
==================================

main:
   8kHz


Component name: AEC_1
================================================================================

ComponentVersion: AEC_TI_v1
ComponentRevision: 5286
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 2
OutputChannels
   (all configs): 2
TailLength
   main: 32ms
TargetProcessor
   (all configs): miniDSP_A
mu_step
   main: 1677568
mu_step_slow
   main: 0
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): AEC_1

[Runtime properties]
CCFactor
   main: -0.75
CL
   main: 3.0
NLP_Gr_DT
   main: 0.60000002384185791015625
NLP_Gs_DT
   main: 0.60000002384185791015625
NLP_Gs_FE
   main: 0.0844237804412841796875
NLP_G_IDLE
   main: 0.70794677734375
MIN_FAR_POW
   main: -0.00003159046173095703125
Rout_G_TH
   main: -0.10000002384185791015625

Component name: AEC_CNG_1
================================================================================

ComponentVersion: AEC_CNG_TI_v2
ComponentRevision: 4315
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 1
OutputChannels
   (all configs): 1
CNG_b0
   main: 0.06000006198883056640625
CNG_a1
   main: 1.6629831790924072265625
CNG_a2
   main: -0.809999942779541015625
TargetProcessor
   (all configs): miniDSP_D
MicConnectedTo
   main: Left
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): AEC_CNG_1

[Runtime properties]
   (none)

Component name: AIC3262App8x4x_1
================================================================================

ComponentVersion: AIC3262App8x4x_TI_v1
ComponentRevision: 6183
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 0
OutputChannels
   (all configs): 0
miniDSP_A_Adaptive
   main: Enabled
miniDSP_A_Cycles
   main: 6144
miniDSP_A_Memory
   main: 1536
miniDSP_D_Adaptive
   main: Enabled
miniDSP_D_Memory
   main: 3072
miniDSP_D_Cycles
   main: 6144
FrameworkType
   main: AIC3262App8x4x
TargetType
   main: TypeC
SystemSettingsCode
   main: reg[0][0][1] = 0x01                        ; reg(0)(1)(0x00 => 0 )     S/W Reset 

reg[0][0][4] = 0x33                        ; ADC_CLKIN = PLL_MCLK, DAC_CLKIN = PLL_MCLK

reg[0][0][5] = 0x00                        ; PLL_CLKIN = MCLK1

reg[0][0][6] = 0x91                        ; P=1, R=1

 

;-----------------------------------------------------------------------------------

; Clock and Interface Configuration

;-----------------------------------------------------------------------------------

; USB Audio supports 8kHz to 48kHz sample rates

; An external audio interface is required for 88.2kHz to 192kHz sample rates

;-----------------------------------------------------------------------------------

%%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000)

    reg[0][0][7]  = 0x08            ; P=1, R=1, J=8

    reg[0][0][13] = 0x00            ; DOSR = 32 (MSB)

    reg[0][0][14] = 0x20            ; DOSR = 32 (LSB)

    reg[0][0][18] = 0x02            ; NADC Powerdown NADC = 2

    reg[0][0][19] = 0x88            ; NADC Powerup MADC = 8

    reg[0][0][20] = 0x20            ; AOSR = 32

%%endif

 

%%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000)

    reg[0][0][7]  = 0x08            ; P=1, R=1, J=8

    reg[0][0][13] = 0x00            ; DOSR = 64 (MSB)

    reg[0][0][14] = 0x40            ; DOSR = 64 (LSB)

    reg[0][0][18] = 0x02            ; NADC Powerdown NADC = 2

    reg[0][0][19] = 0x88            ; NADC Powerup MADC = 8

    reg[0][0][20] = 0x40            ; AOSR = 64

%%endif

 

%%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)

    reg[0][0][7]  = 0x08            ; P=1, R=1, J=8

    reg[0][0][13] = 0x00            ; DOSR = 128 (MSB)

    reg[0][0][14] = 0x80            ; DOSR = 128 (LSB)

    reg[0][0][18] = 0x02            ; NADC Powerdown NADC = 2

    reg[0][0][19] = 0x88            ; NADC Powerup MADC = 8

    reg[0][0][20] = 0x80            ; AOSR = 128

%%endif

 

%%if (%%prop(SampleRate) == 32000)

    reg[0][0][7]  = 0x08            ; P=1, R=1, J=8

    reg[0][0][13] = 0x00            ; DOSR = 192 (MSB)

    reg[0][0][14] = 0xc0            ; DOSR = 192 (LSB)

    reg[0][0][18] = 0x02            ; NADC Powerdown NADC = 2

    reg[0][0][19] = 0x8c            ; NADC Powerup MADC = 12

    reg[0][0][20] = 0x80            ; AOSR = 128

%%endif

 

%%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000)

    reg[0][0][7]  = 0x08            ; P=1, R=1, J=8

    reg[0][0][13] = 0x01            ; DOSR = 256 (MSB)

    reg[0][0][14] = 0x00            ; DOSR = 256 (LSB)

    reg[0][0][18] = 0x02            ; NADC Powerdown NADC = 2

    reg[0][0][19] = 0x90            ; NADC Powerup MADC = 16

    reg[0][0][20] = 0x80            ; AOSR = 128

%%endif

 

%%if (%%prop(SampleRate) == 16000)

    reg[0][0][7]  = 0x18            ; P=1, R=1, J=24

    reg[0][0][13] = 0x01           ; DOSR = 384 (MSB)

    reg[0][0][14] = 0x80            ; DOSR = 384 (LSB)

    reg[0][0][18] = 0x02            ; NADC Powerdown NADC = 2

    reg[0][0][19] = 0x98            ; NADC Powerup MADC = 24

    reg[0][0][20] = 0x80            ; AOSR = 128

%%endif

 

%%if (%%prop(SampleRate) == 11025)

    reg[0][0][7]  = 0x10            ; P=1, R=1, J=16

    reg[0][0][13] = 0x02            ; DOSR = 512 (MSB)

    reg[0][0][14] = 0x00            ; DOSR = 512 (LSB)

    reg[0][0][18] = 0x02            ; NADC Powerdown NADC = 2

    reg[0][0][19] = 0xa0            ; NADC Powerup MADC = 32

    reg[0][0][20] = 0x80            ; AOSR = 128

%%endif

 

%%if (%%prop(SampleRate) == 8000)

    reg[0][0][7]  = 0x18            ; P=1, R=1, J=24

    reg[0][0][13] = 0x03            ; DOSR = 768 (MSB)

    reg[0][0][14] = 0x00            ; DOSR = 768 (LSB)

    reg[0][0][18] = 0x02            ; NADC Powerdown NADC = 2

    reg[0][0][19] = 0xb0            ; NADC Powerup MADC = 48

    reg[0][0][20] = 0x80            ; AOSR = 128

%%endif

%%if (%%prop(SynchMode) == 1)

    reg[0][0][11] = 0x02            ; NDAC = 2, divider powered off

%%else

    reg[0][0][11] = 0x82            ; NDAC = 2, divider powered on

%%endif

 

reg[0][0][8] = 0x00                        ; D=0000 (MSB)

reg[0][0][9] = 0x00                        ; D=0000 (LSB)

reg[0][0][12] = 0x88                       ; reg(0)(0)(0x0c => 12)     DAC Powerup MDAC = 8

reg[120][0][50] = 0x88                     ; Interpolation Ratio is 8, FIFO = Enabled

reg[100][0][50] = 0xa4                     ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled

 

%%if (%%prop(SynchMode) == 1)

reg[0][0][60] = 0x80                       ; reg(0)(0)(0x3c => 60)     DAC prog Mode, DAC & ADC filter engines powered up together                          

%%else

reg[0][0][60] = 0x00                       ; reg(0)(0)(0x3c => 60)     DAC prog Mode, DAC & ADC filter engines not powered up together                          

%%endif

 

reg[0][0][61] = 0x00                       ; reg(0)(0)(0x3d => 61)     ADC prog mode

reg[0][0][83] = 0x18                     ; adc vol control = 12db

reg[0][0][84] = 0x18                     ; adc vol control = 12db

 

reg[0][1][1 ] = 0x00                       ; reg(0)(1)(0x01 => 0 )     Crude avdd disabled

reg[0][1][3 ] = 0x00                       ; reg(0)(1)(0x03 => 3 )     LDAC FIR

reg[0][1][4 ] = 0x00                       ; reg(0)(1)(0x04 => 4 )     RDAC FIR

;reg[0][1][11] = 0x35                       ; reg(0)(1)(0xB  =>11 )     DePop HP

;reg[0][1][31] = 0x8E                       ; reg(0)(1)(0x1F =>31 )     HP in ground Centered mode; HPL gain 14 dB

;reg[0][1][32] = 0x0E                       ; reg(0)(1)(0x20 =>32 )     HPR independent gain 14 dB

reg[0][1][46] = 0x04                       ; LOL selected, -2.86dB gain applied

reg[0][1][47] = 0x00                       ; LOR selected

reg[0][1][45] = 0x03                       ; Power up speaker gain

reg[0][1][48] = 0x32;21;41 ;0x45                         ; write 18dB (24dB) to speaker gain

;reg[0][1][37] = 0x80                             ; RecL and RecR volume control locked together

reg[0][1][22] = 0xc3                       ; LDAC_P, RDAC_P   

;reg[0][1][36] = 0x00                             ; Volume of Rec set to 0dB

;reg[0][1][40] = 0xc0                           ; Unmute RecP

;reg[0][1][41] = 0x80                           ; Unmute RecM

reg[0][1][33] = 0x28                       ; reg(0)(1)(0x21 =>33 )     Charge pump runs on Osc./4

reg[0][1][34] = 0x3e                       ; reg(0)(1)(0x22 =>34 )     Set CP mode

reg[0][1][35] = 0x10                       ; reg(0)(1)(0x23 =>35 )     Power up CP with HP

reg[0][1][52] = 0x10                       ; reg(0)(1)(0x34 => 52)     ADC IN2_L and IN1_R are selected for left P

reg[0][1][51] = 0x04                      ; This enables int mic bias to 3.3V

reg[0][1][54] = 0x40                       ; reg(0)(1)(0x36 => 54)     ADC CM1 is selected for left M

reg[0][1][55] = 0x10                       ; reg(0)(1)(0x37 => 55)     ADC IN2_R is selected for right P

reg[0][1][57] = 0x40                       ; reg(0)(1)(0x39 => 57)     ADC CM1 is selected for right M

reg[0][1][82] = 0xD5                     ;

reg[0][1][121] = 0x33                      ; reg(0)(1)(0x79 => 121)    Quick charge time for Mic inputs

reg[0][1][122] = 0x01                      ; reg(0)(1)(0x7A => 122)    Vref charge time - 40 ms.

 

reg[120][0][24] = 0x80                   ;Setup for 1 cycle jump on Rev. D of device

 

PROGRAM_MINIDSP_A 

PROGRAM_MINIDSP_D

 

%%if (%%prop(miniDSP_A_Adaptive) == 1)

reg[40][0][1] = 0x04                        ; adaptive mode for ADC

%%endif

%%if (%%prop(miniDSP_D_Adaptive) == 1)

reg[80][0][1] = 0x04                        ; adaptive mode for DAC

%%endif

 

;IADC  = %%prop(miniDSP_A_Cycles)        ; 

;IDAC  = %%prop(miniDSP_D_Cycles)        ;

 

%%if (%%prop(SynchMode) == 1)

%%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000)

    ;IDAC  = %%eval(8*32)    ; MDAC*DOSR

    ;IADC  = %%eval(8*32)    ; MADC*AOSR

    reg[100][0][48] = 1

    reg[100][0][49] = 0

    reg[120][0][48] = 1

    reg[120][0][49] = 0

%%endif

%%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000)

    ;IDAC  = %%eval(8*64)    ; MDAC*DOSR

    ;IADC  = %%eval(8*64)    ; MADC*AOSR

    reg[100][0][48] = 2

    reg[100][0][49] = 0

    reg[120][0][48] = 2

    reg[120][0][49] = 0

%%endif

%%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)

    ;IDAC  = %%eval(8*128)    ; MDAC*DOSR

    ;IADC  = %%eval(8*128)    ; MADC*AOSR

    reg[100][0][48] = 4

    reg[100][0][49] = 0

    reg[120][0][48] = 4

    reg[120][0][49] = 0

%%endif

%%if (%%prop(SampleRate) == 32000)

    ;IDAC  = %%eval(8*192)    ; MDAC*DOSR

    ;IADC  = %%eval(12*128)   ; MADC*AOSR

    reg[100][0][48] = 6

    reg[100][0][49] = 0

    reg[120][0][48] = 6

    reg[120][0][49] = 0

%%endif

%%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000)

    ;IDAC  = %%eval(8*256)    ; MDAC*DOSR

    ;IADC  = %%eval(16*128)   ; MADC*AOSR

    reg[100][0][48] = 8

    reg[100][0][49] = 0

    reg[120][0][48] = 8

    reg[120][0][49] = 0

%%endif

%%if (%%prop(SampleRate) == 16000)

    ;IDAC  = %%eval(8*384)    ; MDAC*DOSR

    ;IADC  = %%eval(24*128)   ; MADC*AOSR

    reg[100][0][48] = 12

    reg[100][0][49] = 0

    reg[120][0][48] = 12

    reg[120][0][49] = 0

%%endif

%%if (%%prop(SampleRate) == 11025)

    ;IDAC  = %%eval(8*512)    ; MDAC*DOSR

    ;IADC  = %%eval(32*128)   ; MADC*AOSR

    reg[100][0][48] = 16

    reg[100][0][49] = 0

    reg[120][0][48] = 16

    reg[120][0][49] = 0

%%endif

%%if (%%prop(SampleRate) == 8000)

    ;IDAC  = %%eval(8*768)    ; MDAC*DOSR

    ;IADC  = %%eval(48*128)   ; MADC*AOSR

    reg[100][0][48] = 24

    reg[100][0][49] = 0

    reg[120][0][48] = 24

    reg[120][0][49] = 0

%%endif

 

%%else // Asych mode

reg[100][0][48] = %%eval(Math.floor(%%prop(miniDSP_A_Cycles)/256))

reg[100][0][49] = %%eval(%%prop(miniDSP_A_Cycles) - Math.floor(%%prop(miniDSP_A_Cycles)/256)*256)

 

reg[120][0][48] = %%eval(Math.floor(%%prop(miniDSP_D_Cycles)/256))

reg[120][0][49] = %%eval(%%prop(miniDSP_D_Cycles) - Math.floor(%%prop(miniDSP_D_Cycles)/256)*256)

%%endif

 

 

reg[0][0][63] = 0xd6                       ; reg(0)(0)(0x3f => 63)     DAC L&R DAC powerup Ldata-LDAC Rdata-RDAC (soft-stepping disable)

reg[0][0][64] = 0x00                       ; reg(0)(0)(0x40 => 64)     DAC Left and Right DAC unmuted with indep.  vol. ctrl

reg[0][0][65] = 0xfa ;E2 ;E8 ;EE ;F4 ;00                       ; reg(0)(0)(0x3f => 63)     DAC L&R DAC powerup Ldata-LDAC Rdata-RDAC (soft-stepping disable)

reg[0][0][66] = 0xfa ;E2 ;E8 ;EE ;F4 ;00                       ; reg(0)(0)(0x40 => 64)     DAC Left and Right DAC unmuted with indep.  vol. ctrl

 

 

reg[0][0][81] = 0xc2                       ; reg(0)(0)(0x51 => 81)     ADC Powerup ADC left and right channels (soft-stepping disable)

reg[0][0][82] = 0x00                       ; reg(0)(0)(0x52 => 82)     ADC Unmute ADC left and right channels,L,R fine gain=0dB

 

;reg[0][1][27] = 0x33                       ; reg(0)(1)(0x1B =>27 )     LDAC -> HPL, RDAC -> HPR; Power on HPL + HPR

reg[0][1][59] = 0x5A;3c ;28 ;32                       ; reg(0)(1)(0x3b => 59)     ADC unmute left mic PGA with 21 (30) dB gain

reg[0][1][60] = 0x5A;3c ;28 ;32                       ; reg(0)(1)(0x3c => 60)     ADC unmute right mic PGA with 21 (30) dB gain

 

reg[0][4][1]  = 0                          ; ASI1 Audio Interface = I2S

reg[0][4][10] = 0                          ; ASI1 Audio Interface WCLK and BCLK 

reg[0][4][8]  = 0x50                       ; ASI1 Left DAC Datapath = Left Data, ASI1 Right DAC Datapath = Right Data

 

%%if (%%prop(SynchMode) == 1)

reg[100][0][20] = 0x00 ; Disable ADC double buffer mode

reg[120][0][20] = 0x00 ; Disable DAC double buffer mode

%%else

reg[100][0][20] = 0x80 ; Enable ADC double buffer mode

reg[120][0][20] = 0x80 ; Enable DAC double buffer mode

%%endif

 

%%if (%%prop(SynchMode) == 1)

    reg[0][0][11] = 0x82                  ; NDAC = 2, divider powered off

%%endif
SynchMode
   main: Enabled
miniDSP_A_D_Clock_Ratio
   main: Equal
TargetStream
   main: Primary
InstanceId
   (all configs): AIC3262App8x4x_1

[Runtime properties]
   (none)

Component name: Biquad_1
================================================================================

ComponentVersion: Biquad_TI_v1
ComponentRevision: 5564
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 1
OutputChannels
   (all configs): 1
TargetProcessor
   (all configs): miniDSP_D
Instances
   (all configs): 2
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): Biquad_1

[Runtime properties]
Inst1_B0
   main: 0.82320058345794677734375 (8kHz)
Inst1_B1
   main: -0.82320058345794677734375 (8kHz)
Inst1_B2
   main: 0.82320058345794677734375 (8kHz)
Inst1_A1
   main: 0.8074514865875244140625 (8kHz)
Inst1_A2
   main: -0.6778995990753173828125 (8kHz)
Inst2_B0
   main: 0.99999988079071044921875 (8kHz)
Inst2_B1
   main: 0.0 (8kHz)
Inst2_B2
   main: 0.0 (8kHz)
Inst2_A1
   main: 0.0 (8kHz)
Inst2_A2
   main: 0.0 (8kHz)

Component name: Biquad_2
================================================================================

ComponentVersion: Biquad_TI_v1
ComponentRevision: 5564
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 1
OutputChannels
   (all configs): 1
TargetProcessor
   (all configs): miniDSP_A
Instances
   (all configs): 2
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): Biquad_2

[Runtime properties]
Inst1_B0
   main: 0.94596922397613525390625 (8kHz)
Inst1_B1
   main: -0.94596922397613525390625 (8kHz)
Inst1_B2
   main: 0.94596922397613525390625 (8kHz)
Inst1_A1
   main: 0.94450891017913818359375 (8kHz)
Inst1_A2
   main: -0.89485919475555419921875 (8kHz)
Inst2_B0
   main: 0.81862652301788330078125 (8kHz)
Inst2_B1
   main: -0.81862652301788330078125 (8kHz)
Inst2_B2
   main: 0.81862652301788330078125 (8kHz)
Inst2_A1
   main: 0.80204498767852783203125 (8kHz)
Inst2_A2
   main: -0.67041623592376708984375 (8kHz)

Component name: Dec4xIn_1
================================================================================

ComponentVersion: Dec4xIn_TI_v3
ComponentRevision: 5697
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 0
OutputChannels
   (all configs): 2
TargetProcessor
   (all configs): miniDSP_A
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): Dec4xIn_1

[Runtime properties]
AGC_Enable
   main: Disable
Volume_Control_dB
   main: 0.0
Left_Fine_Gain
   main: 0dB
Right_Fine_Gain
   main: 0dB
Alpha
   main: 0.00560283660888671875
1minus2alpha
   main: 0.9887943267822265625
Energy_Time_Constant_ms
   main: 2_ms
AGC_Target_Level
   main: -5.5dB
AGC_Gain_Hysteresis
   main: Disable
AGC_Hysteresis_Setting
   main: Disable
AGC_Noise_Threshold
   main: -90dB
AGC_Maximum_Gain
   main: 45.0
AGC_Attack_Time
   main: 27
AGC_Attack_Time_Factor
   main: 1x
AGC_Decay_Time
   main: 43
AGC_Decay_Time_Factor
   main: 1x
AGC_Noise_Debounce_Time
   main: 128x1WordCLK
AGC_Signal_Debounce_Time
   main: 0x1WordCLK
AGC_Gain_Flag
   main: 0.0

Component name: Fb_Delay_1
================================================================================

ComponentVersion: Fb_Delay_TI_v1
ComponentRevision: 3981
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 1
OutputChannels
   (all configs): 1
TargetProcessor
   (all configs): miniDSP_D
Delay1
   (all configs): 1
Delay2
   (all configs): 2
Delay3
   (all configs): 3
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): Fb_Delay_1

[Runtime properties]
   (none)

Component name: I2S_In_1
================================================================================

ComponentVersion: I2S_In_TI_v1
ComponentRevision: 5550
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 0
OutputChannels
   (all configs): 2
TargetProcessor
   (all configs): miniDSP_D
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): I2S_In_1

[Runtime properties]
   (none)

Component name: I2S_Out_1
================================================================================

ComponentVersion: I2S_Out_TI_v1
ComponentRevision: 5370
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 2
OutputChannels
   (all configs): 0
TargetProcessor
   (all configs): miniDSP_A
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): I2S_Out_1

[Runtime properties]
   (none)

Component name: iDSP_A_D_1
================================================================================

ComponentVersion: iDSP_A_D_TI_v1
ComponentRevision: 0
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 2
OutputChannels
   (all configs): 2
ComponentVisibleFilter
   main: not gde.GetProperty(gde.GetFramework(), "FrameworkType").startswith("AIC3262App8x4xArbiter")
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): iDSP_A_D_1

[Runtime properties]
   (none)

Component name: iDSP_D_A_1
================================================================================

ComponentVersion: iDSP_D_A_TI_v1
ComponentRevision: 0
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 2
OutputChannels
   (all configs): 2
ComponentVisibleFilter
   main: not gde.GetProperty(gde.GetFramework(), "FrameworkType").startswith("AIC3262App8x4xArbiter")
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): iDSP_D_A_1

[Runtime properties]
   (none)

Component name: Int8xOut_1
================================================================================

ComponentVersion: Int8xOut_TI_v1
ComponentRevision: 5021
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 2
OutputChannels
   (all configs): 0
TargetProcessor
   (all configs): miniDSP_D
Include_DRC
   (all configs): NO
ComponentVisibleFilter
   main: not '2x1x' in gde.GetProperty(gde.GetFramework(), "FrameworkType")
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): Int8xOut_1

[Runtime properties]
DRC_Enable
   main: Disable
Volume_Control_dB
   main: 0.0
Energy_Time_Constant_ms
   main: 20_ms
DRC_Hysteresis
   main: 3dB
DRC_Threshold_dBFS
   main: -24
DRC_HOLD_Time_WordCLK
   main: 0
DRC_Attack_Rate_perWCLK
   main: 1div1024dB
DRC_Decay_Rate_perWCLK
   main: 1div4096dB

Component name: nrvar2_1
================================================================================

ComponentVersion: nrvar2_TI_v1
ComponentRevision: 5469
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 1
OutputChannels
   (all configs): 1
TargetProcessor
   (all configs): miniDSP_D
NumBanks
   (all configs): 8_Filters
Enable_Noise_Readout
   (all configs): FALSE
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): nrvar2_1

[Runtime properties]
Threshold
   main: 0.501190185546875
Attenuation
   main: 0.398101806640625
LowFreq
   main: 316
HighFreq
   main: 3400

Component name: Scale_2
================================================================================

ComponentVersion: Shift_Scale_TI_v1
ComponentRevision: 4019
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 1
OutputChannels
   (all configs): 1
TargetProcessor
   (all configs): miniDSP_D
Shift
   main: 3
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): Scale_2

[Runtime properties]
Coef
   main: 0.5499999523162841796875

Component name: Shift_Scale_1
================================================================================

ComponentVersion: Shift_Scale_TI_v1
ComponentRevision: 4019
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 1
OutputChannels
   (all configs): 1
TargetProcessor
   (all configs): miniDSP_D
Shift
   main: 1
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): Shift_Scale_1

[Runtime properties]
Coef
   main: 0.9900000095367431640625

Component name: Split_1
================================================================================

ComponentVersion: Split_TI_v1
ComponentRevision: 1975
AliasOf: None
Overlay: all

[Design properties]
InputChannels
   (all configs): 1
OutputChannels
   (all configs): 2
TargetProcessor
   (all configs): miniDSP_A
TargetStream
   main: Primary
SynchMode
   main: Enabled
InstanceId
   (all configs): Split_1

[Runtime properties]
   (none)

