/* SPDX-License-Identifier: GPL-2.0-only */ /* * Audio Codec Driver Supporting Devices * TAA5X1X, TAC5X1X, TAD5X1X * * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com * * Author: Kevin Lu * Author: Kokila Karuppusamy * Author: Niranjan H Y */ #ifndef _TAC5X1X_H #define _TAC5X1X_H #define TAC5X1X_RATES SNDRV_PCM_RATE_8000_192000 #define TAC5X1X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \ | SNDRV_PCM_FMTBIT_S20_3LE \ | SNDRV_PCM_FMTBIT_S24_LE \ | SNDRV_PCM_FMTBIT_S24_3LE \ | SNDRV_PCM_FMTBIT_S32_LE) /*PAGE Control Register (available in page0 of each book) */ #define TAC_PAGE_SELECT 0x00 #define TAC_PAGE_ID(reg) ((reg) / 128) #define TAC_PAGE_REG(reg) ((reg) % 128) #define TAC5X1X_REG(page, reg) (((page) * 128) + (reg)) //#define TAC5X1X_PGSEL TAC5X1X_REG(0, 0x0) #define TAC5X1X_RESET TAC5X1X_REG(0, 0x1) #define TAC5X1X_VREF TAC5X1X_REG(0, 0x2) #define TAC5X1X_VDDSTS TAC5X1X_REG(0, 0x3) #define TAC5X1X_MISC TAC5X1X_REG(0, 0x4) #define TAC5X1X_MISC1 TAC5X1X_REG(0, 0x5) #define TAC5X1X_DACA0 TAC5X1X_REG(0, 0x6) #define TAC5X1X_MISC0 TAC5X1X_REG(0, 0x7) #define TAC5X1X_GPIO1 TAC5X1X_REG(0, 0xa) #define TAC5X1X_GPIO2 TAC5X1X_REG(0, 0xb) #define TAC5X1X_GPO1 TAC5X1X_REG(0, 0xc) #define TAC5X1X_GPI1 TAC5X1X_REG(0, 0xd) #define TAC5X1X_GPIOVAL TAC5X1X_REG(0, 0xe) #define TAC5X1X_INTF0 TAC5X1X_REG(0, 0xf) #define TAC5X1X_INTF1 TAC5X1X_REG(0, 0x10) #define TAC5X1X_INTF2 TAC5X1X_REG(0, 0x11) #define TAC5X1X_INTF3 TAC5X1X_REG(0, 0x12) #define TAC5X1X_INTF4 TAC5X1X_REG(0, 0x13) #define TAC5X1X_INTF5 TAC5X1X_REG(0, 0x14) #define TAC5X1X_INTF6 TAC5X1X_REG(0, 0x15) #define TAC5X1X_ASI0 TAC5X1X_REG(0, 0x18) #define TAC5X1X_ASI1 TAC5X1X_REG(0, 0x19) #define TAC5X1X_PASI0 TAC5X1X_REG(0, 0x1a) #define TAC5X1X_PASITX0 TAC5X1X_REG(0, 0x1b) #define TAC5X1X_PASITX1 TAC5X1X_REG(0, 0x1c) #define TAC5X1X_PASITX2 TAC5X1X_REG(0, 0x1d) #define TAC5X1X_PASITXCH1 TAC5X1X_REG(0, 0x1e) #define TAC5X1X_PASITXCH2 TAC5X1X_REG(0, 0x1f) #define TAC5X1X_PASITXCH3 TAC5X1X_REG(0, 0x20) #define TAC5X1X_PASITXCH4 TAC5X1X_REG(0, 0x21) #define TAC5X1X_PASITXCH5 TAC5X1X_REG(0, 0x22) #define TAC5X1X_PASITXCH6 TAC5X1X_REG(0, 0x23) #define TAC5X1X_PASITXCH7 TAC5X1X_REG(0, 0x24) #define TAC5X1X_PASITXCH8 TAC5X1X_REG(0, 0x25) #define TAC5X1X_PASIRX0 TAC5X1X_REG(0, 0x26) #define TAC5X1X_PASIRX1 TAC5X1X_REG(0, 0x27) #define TAC5X1X_PASIRXCH1 TAC5X1X_REG(0, 0x28) #define TAC5X1X_PASIRXCH2 TAC5X1X_REG(0, 0x29) #define TAC5X1X_PASIRXCH3 TAC5X1X_REG(0, 0x2a) #define TAC5X1X_PASIRXCH4 TAC5X1X_REG(0, 0x2b) #define TAC5X1X_PASIRXCH5 TAC5X1X_REG(0, 0x2c) #define TAC5X1X_PASIRXCH6 TAC5X1X_REG(0, 0x2d) #define TAC5X1X_PASIRXCH7 TAC5X1X_REG(0, 0x2e) #define TAC5X1X_PASIRXCH8 TAC5X1X_REG(0, 0x2f) #define TAC5X1X_CLK0 TAC5X1X_REG(0, 0x32) #define TAC5X1X_CLK1 TAC5X1X_REG(0, 0x33) #define TAC5X1X_CLK2 TAC5X1X_REG(0, 0x34) #define TAC5X1X_CNTCLK0 TAC5X1X_REG(0, 0x35) #define TAC5X1X_CNTCLK1 TAC5X1X_REG(0, 0x36) #define TAC5X1X_CNTCLK2 TAC5X1X_REG(0, 0x37) #define TAC5X1X_CNTCLK3 TAC5X1X_REG(0, 0x38) #define TAC5X1X_CNTCLK4 TAC5X1X_REG(0, 0x39) #define TAC5X1X_CNTCLK5 TAC5X1X_REG(0, 0x3a) #define TAC5X1X_CNTCLK6 TAC5X1X_REG(0, 0x3b) #define TAC5X1X_CLKERRSTS0 TAC5X1X_REG(0, 0x3c) #define TAC5X1X_CLKERRSTS1 TAC5X1X_REG(0, 0x3d) #define TAC5X1X_CLKDETSTS0 TAC5X1X_REG(0, 0x3e) #define TAC5X1X_CLKDETSTS1 TAC5X1X_REG(0, 0x3f) #define TAC5X1X_CLKDETSTS2 TAC5X1X_REG(0, 0x40) #define TAC5X1X_CLKDETSTS3 TAC5X1X_REG(0, 0x41) #define TAC5X1X_INT TAC5X1X_REG(0, 0x42) #define TAC5X1X_DAC_FLT TAC5X1X_REG(0, 0x43) #define TAC5X1X_ADCDACMISC TAC5X1X_REG(0, 0x4b) #define TAC5X1X_IADC TAC5X1X_REG(0, 0x4c) #define TAC5X1X_VREFCFG TAC5X1X_REG(0, 0x4d) #define TAC5X1X_PWRTUNE0 TAC5X1X_REG(0, 0x4e) #define TAC5X1X_PWRTUNE1 TAC5X1X_REG(0, 0x4f) #define TAC5X1X_ADCCH1C0 TAC5X1X_REG(0, 0x50) #define TAC5X1X_ADCCH TAC5X1X_REG(0, 0x51) #define TAC5X1X_ADCCH1C2 TAC5X1X_REG(0, 0x52) #define TAC5X1X_ADCCH1C3 TAC5X1X_REG(0, 0x53) #define TAC5X1X_ADCCH1C4 TAC5X1X_REG(0, 0x54) #define TAC5X1X_ADCCH2C0 TAC5X1X_REG(0, 0x55) #define TAC5X1X_ADCCH2C2 TAC5X1X_REG(0, 0x57) #define TAC5X1X_ADCCH2C3 TAC5X1X_REG(0, 0x58) #define TAC5X1X_ADCCH2C4 TAC5X1X_REG(0, 0x59) #define TAC5X1X_ADCCH3C0 TAC5X1X_REG(0, 0x5a) #define TAC5X1X_ADCCH3C2 TAC5X1X_REG(0, 0x5b) #define TAC5X1X_ADCCH3C3 TAC5X1X_REG(0, 0x5c) #define TAC5X1X_ADCCH3C4 TAC5X1X_REG(0, 0x5d) #define TAC5X1X_ADCCH4C0 TAC5X1X_REG(0, 0x5e) #define TAC5X1X_ADCCH4C2 TAC5X1X_REG(0, 0x5f) #define TAC5X1X_ADCCH4C3 TAC5X1X_REG(0, 0x60) #define TAC5X1X_ADCCH4C4 TAC5X1X_REG(0, 0x61) #define TAC5X1X_ADCCFG1 TAC5X1X_REG(0, 0x62) #define TAC5X1X_OUT1CFG0 TAC5X1X_REG(0, 0x64) #define TAC5X1X_OUT1CFG1 TAC5X1X_REG(0, 0x65) #define TAC5X1X_OUT1CFG2 TAC5X1X_REG(0, 0x66) #define TAC5X1X_DACCH1A0 TAC5X1X_REG(0, 0x67) #define TAC5X1X_DACCH1A1 TAC5X1X_REG(0, 0x68) #define TAC5X1X_DACCH1B0 TAC5X1X_REG(0, 0x69) #define TAC5X1X_DACCH1B1 TAC5X1X_REG(0, 0x6a) #define TAC5X1X_OUT2CFG0 TAC5X1X_REG(0, 0x6b) #define TAC5X1X_OUT2CFG1 TAC5X1X_REG(0, 0x6c) #define TAC5X1X_OUT2CFG2 TAC5X1X_REG(0, 0x6d) #define TAC5X1X_DACCH2A0 TAC5X1X_REG(0, 0x6e) #define TAC5X1X_DACCH2A1 TAC5X1X_REG(0, 0x6f) #define TAC5X1X_DACCH2B0 TAC5X1X_REG(0, 0x70) #define TAC5X1X_DACCH2B1 TAC5X1X_REG(0, 0x71) #define TAC5X1X_DSP0 TAC5X1X_REG(0, 0x72) #define TAC5X1X_DSP1 TAC5X1X_REG(0, 0x73) #define TAC5X1X_CH_EN TAC5X1X_REG(0, 0x76) #define TAC5X1X_DYN_PUPD TAC5X1X_REG(0, 0x77) #define TAC5X1X_PWR_CFG TAC5X1X_REG(0, 0x78) #define TAC5X1X_DEVSTS0 TAC5X1X_REG(0, 0x79) #define TAC5X1X_DEVSTS1 TAC5X1X_REG(0, 0x7a) #define TAC5X1X_CLKCFG0 TAC5X1X_REG(1, 0xd) #define TAC5X1X_MICBIAS1 TAC5X1X_REG(1, 0x16) #define TAC5X1X_AGC_DRC TAC5X1X_REG(1, 0x24) #define TAC5X1X_PLIM TAC5X1X_REG(1, 0x2b) #define TAC5X1X_MIXER TAC5X1X_REG(1, 0x2c) #define TAC5X1X_DIAG_CFG0 TAC5X1X_REG(1, 0x46) #define TAC5X1X_DIAG_CFG1 TAC5X1X_REG(1, 0x47) #define TAC5X1X_DIAG_CFG2 TAC5X1X_REG(1, 0x48) #define TAC5X1X_DIAG_CFG8 TAC5X1X_REG(1, 0x4e) #define TAC5X1X_DIAG_CFG9 TAC5X1X_REG(1, 0x4b) #define TAC5X1X_DIAG_CFG6 TAC5X1X_REG(1, 0x4c) #define TAC5X1X_DIAG_CFG7 TAC5X1X_REG(1, 0x4d) /* interrupt latches */ #define TAC5X1X_INT_LTCH0 TAC5X1X_REG(0x1, 0x34) #define TAC5X1X_CHX_LTCH TAC5X1X_REG(0x1, 0x35) #define TAC5X1X_IN_CH1_LTCH TAC5X1X_REG(0x1, 0x36) #define TAC5X1X_IN_CH2_LTCH TAC5X1X_REG(0x1, 0x37) #define TAC5X1X_OUT_CH1_LTCH TAC5X1X_REG(0x1, 0x38) #define TAC5X1X_OUT_CH2_LTCH TAC5X1X_REG(0x1, 0x39) #define TAC5X1X_INT_LTCH1 TAC5X1X_REG(0x1, 0x3A) #define TAC5X1X_INT_LTCH2 TAC5X1X_REG(0x1, 0x3B) #define TAC5X1X_OVERLD_FLAG TAC5X1X_REG(0x1, 0x5B) #define TAC5X1X_TP_START TAC5X1X_REG(0xfd, 0x0) #define TAC5X1X_TP_DREG TAC5X1X_REG(0xfd, 0xd) #define TAC5X1X_TP_AREG TAC5X1X_REG(0xfd, 0x1a) #define TAC5X1X_TP_END TAC5X1X_REG(0xfd, 0x7f) /* Bits, masks, and shifts */ /* TAC5X1X_CH_EN */ #define TAC5X1X_CH_EN_ADC_MASK GENMASK(7, 4) #define TAC5X1X_CH_EN_ADC_CH1 BIT(7) #define TAC5X1X_CH_EN_ADC_CH2 BIT(6) #define TAC5X1X_CH_EN_ADC_CH3 BIT(5) #define TAC5X1X_CH_EN_ADC_CH4 BIT(4) #define TAC5X1X_CH_EN_DAC_MASK GENMASK(3, 0) #define TAC5X1X_CH_EN_DAC_CH1 BIT(3) #define TAC5X1X_CH_EN_DAC_CH2 BIT(2) #define TAC5X1X_CH_EN_DAC_CH3 BIT(1) #define TAC5X1X_CH_EN_DAC_CH4 BIT(0) /* TAC5X1X_GPIOVAL */ #define TAC5X1X_GPIO1_VAL BIT(7) #define TAC5X1X_GPIO2_VAL BIT(6) #define TAC5X1X_GPO1_VAL BIT(5) #define TAC5X1X_GPIO1_MON BIT(3) #define TAC5X1X_GPIO2_MON BIT(2) #define TAC5X1X_GPI1_MON BIT(1) /* TAC5X1X_DIAG_CFG0 */ #define TAC5X1X_IN_CH_DIAG_EN_MASK 0xc0 #define TAC5X1X_INCL_SE_INM_MASK 0x20 #define TAC5X1X_INCL_AC_COUP_MASK 0x10 #define TAC5X1X_OUT1P_DIAG_EN_MASK 0x0f #define TAC5X1X_MICBIAS_LOW_THRESHOLD 0x48 #define TAC5X1X_MICBIAS_HIGH_THRESHOLD 0xa2 #define TAC5X1X_GPA_LOW_THRESHOLD 0x4b #define TAC5X1X_GPA_HIGH_THRESHOLD 0xba /* TAC5X1X_PASI */ #define TAC5X1X_PASI_SAMP_RATE_MASK GENMASK(7, 2) #define TAC5X1X_PASI_FMT_MASK GENMASK(7, 6) #define TAC5X1X_PASI_FMT_TDM 0x00 #define TAC5X1X_PASI_FMT_I2S 0x40 #define TAC5X1X_PASI_FMT_LJ 0x80 #define TAC5X1X_PASI_DATALEN_MASK GENMASK(5, 4) #define TAC5X1X_WORD_LEN_16BITS 0x00 #define TAC5X1X_WORD_LEN_20BITS 0x10 #define TAC5X1X_WORD_LEN_24BITS 0x20 #define TAC5X1X_WORD_LEN_32BITS 0x30 /* TAC5X1X_CNTCLK2 */ #define TAC5X1X_PASI_MODE_MASK 0x10 #define TAC5X1X_SASI_MODE_MASK 0x08 #define TAC5X1X_ASI_RATE_MASK 0x01 #define TAC5X1X_PASI_RATE_48000 0x00 #define TAC5X1X_PASI_RATE_44100 0x01 /* TAC5X1X_PASITX0 */ #define TAC5X1X_PASITX_OFFSET_MASK 0x1f /* TAC5X1X_PASIRX0 */ #define TAC5X1X_PASIRX_OFFSET_MASK 0x1f /* TAC5X1X_VREF */ #define TAC5X1X_VREF_SLEEP_EXIT_VREF_EN 0x80 #define TAC5X1X_VREF_SLEEP_ACTIVE_MASK 0x01 /* TAC5X1X_PWRCFG */ #define TAC5X1X_PWR_CFG_ADC_PDZ BIT(7) #define TAC5X1X_PWR_CFG_DAC_PDZ BIT(6) #define TAC5X1X_PWR_CFG_MICBIAS BIT(5) #define TAC5X1X_PWR_CFG_UAD_EN BIT(3) #define TAC5X1X_PWR_CFG_VAD_EN BIT(2) #define TAC5X1X_PWR_CFG_UAG_EN BIT(1) /* TAC5X1X_GPIOx */ #define TAC5X1X_GPIO1_DEFAULT_VAL 0x32 #define TAC5X1X_GPIO2_DEFAULT_VAL 0x00 #define TAC5X1X_GPI1_DEFAULT_VAL 0x00 #define TAC5X1X_GPO1_DEFAULT_VAL 0x00 #define TAC5X1X_GPIOX_CFG_MASK 0xf0 #define TAC5X1X_GPIOX_DRV_MASK 0x07 #define TAC5X1X_GPIO_DISABLE 0 #define TAC5X1X_GPIO_GPI 1 #define TAC5X1X_GPIO_GPO 2 #define TAC5X1X_GPIO_IRQ 3 #define TAC5X1X_GPIO_PDMCLK 4 #define TAC5X1X_GPIO_P_DOUT 5 #define TAC5X1X_GPIO_P_DOUT2 6 #define TAC5X1X_GPIO_S_DOUT 7 #define TAC5X1X_GPIO_S_DOUT2 8 #define TAC5X1X_GPIO_S_BCLK 9 #define TAC5X1X_GPIO_S_FSYNC 10 #define TAC5X1X_GPIO_CLKOUT 11 #define TAC5X1X_GPIO_DOUT_MUX 12 #define TAC5X1X_GPIO_DAISY_OUT 13 #define TAC5X1X_GPIO_DRV_HIZ 0 #define TAC5X1X_GPIO_DRV_ALAH 1 #define TAC5X1X_GPIO_DRV_ALWH 2 #define TAC5X1X_GPIO_DRV_ALHIZ 3 #define TAC5X1X_GPIO_DRV_WLAH 4 #define TAC5X1X_GPIO_DRV_HIZAH 5 /* TAC5X1X_GPI1 */ #define TAC5X1X_GPI1_CFG_MASK BIT(1) #define TAC5X1X_GPA_CFG_MASK BIT(0) /* TAC5X1X_VREFCFG */ #define TAC5X1X_VREFCFG_MICBIAS_VAL_MASK GENMASK(3, 2) #define TAC5X1X_VREFCFG_VREF_FSCALE_MASK GENMASK(1, 0) #define TAC5X1X_ADCCH1C0_IMPEDANCE_MASK GENMASK(5, 4) #define TAC5X1X_ADCCH2C0_IMPEDANCE_MASK GENMASK(5, 4) #define TAC5X1X_OUT2CFG0_VCOM_MASK BIT(1) #define TAC5X1X_MICBIAS_VREF 0 #define TAC5X1X_MICBIAS_0_5VREF 1 #define TAC5X1X_MICBIAS_AVDD 3 #define TAC5X1X_VERF_2_75V 0 #define TAC5X1X_VERF_2_5V 1 #define TAC5X1X_VERF_1_375V 2 enum tac5x1x_type { TAA5212 = 0, TAA5412, TAC5111, TAC5112, TAC5211, TAC5212, TAC5311, TAC5312, TAC5411, TAC5412, TAD5112, TAD5212, }; #endif /* _TAC5X1X_H */