> AT+PAIR=0 < < OK > AT+MUTEPIO=0 < OK > AT+BTEN=1 < OK > AT+I2SCFG < +I2SCFG=33 < OK > AT+PROFILE < +PROFILE=168 < OK > AT+AVRCPCFG < +AVRCPCFG=33 < OK > AT+NAME < +NAME=KiddVoX < OK > AT+AUTOCONN < +AUTOCONN=3 < OK > AT+WRS < ERROR > AT+REBOOT < OK > AT+BTEN < +BTEN=1 < OK > AT+VER < +VER=FSC-BT1058,V1.0.3,20251030 < OK > AT+DEVSTAT < +DEVSTAT=0 < OK > AT+PLIST < +PLIST=1,980D6FCE25B5 < +PLIST=2,00025B00FF04 < +PLIST=E < OK > AT+PLIST=0 < OK > AT+PLIST < +PLIST=1,980D6FCE25B5 < +PLIST=2,00025B00FF04 < +PLIST=E < OK WAIT CODEC INIT -> [CODEC Write] Page 0, Reg 0x01 = 0x01 Software Reset Register -> [CODEC Write] Page 1, Reg 0x01 = 0x08 Power Configuration Register -> [CODEC Write] Page 1, Reg 0x02 = 0x01 LDO Control Register -> [CODEC Write] Page 1, Reg 0x0A = 0x3B Common Mode Control Register -> [CODEC Write] Page 1, Reg 0x47 = 0x31 Analog Input Quick Charging Configuration Register -> [CODEC Write] Page 1, Reg 0x7B = 0x01 Reference Power-up Configuration Register [CODEC] MiniDSP download starting -> [CODEC Write] Page 8, Reg 0x08 = 0x00 -> [CODEC Write] Page 8, Reg 0x18 = 0x00 -> [CODEC Write] Page 8, Reg 0x28 = 0x40 -> [CODEC Write] Page 8, Reg 0x38 = 0x26 -> [CODEC Write] Page 8, Reg 0x48 = 0xFF -> [CODEC Write] Page 8, Reg 0x58 = 0xFF -> [CODEC Write] Page 8, Reg 0x68 = 0xFF -> [CODEC Write] Page 8, Reg 0x78 = 0xFD -> [CODEC Write] Page 9, Reg 0x08 = 0x03 -> [CODEC Write] Page 9, Reg 0x18 = 0x00 -> [CODEC Write] Page 9, Reg 0x28 = 0x00 -> [CODEC Write] Page 9, Reg 0x38 = 0x07 -> [CODEC Write] Page 80, Reg 0x08 = 0x00 -> [CODEC Write] Page 80, Reg 0x18 = 0x38 -> [CODEC Write] Page 80, Reg 0x28 = 0xF0 -> [CODEC Write] Page 80, Reg 0x38 = 0x38 -> [CODEC Write] Page 80, Reg 0x48 = 0x38 -> [CODEC Write] Page 80, Reg 0x58 = 0x38 -> [CODEC Write] Page 80, Reg 0x68 = 0x38 -> [CODEC Write] Page 80, Reg 0x78 = 0x38 -> [CODEC Write] Page 81, Reg 0x08 = 0x38 -> [CODEC Write] Page 81, Reg 0x18 = 0x38 -> [CODEC Write] Page 81, Reg 0x28 = 0x38 -> [CODEC Write] Page 81, Reg 0x38 = 0x38 -> [CODEC Write] Page 81, Reg 0x48 = 0x38 -> [CODEC Write] Page 81, Reg 0x58 = 0x38 -> [CODEC Write] Page 81, Reg 0x68 = 0x38 -> [CODEC Write] Page 81, Reg 0x78 = 0x38 -> [CODEC Write] Page 82, Reg 0x08 = 0x38 -> [CODEC Write] Page 82, Reg 0x18 = 0x38 -> [CODEC Write] Page 82, Reg 0x28 = 0x38 -> [CODEC Write] Page 82, Reg 0x38 = 0x50 -> [CODEC Write] Page 82, Reg 0x48 = 0x60 -> [CODEC Write] Page 82, Reg 0x58 = 0x00 -> [CODEC Write] Page 82, Reg 0x68 = 0x00 -> [CODEC Write] Page 82, Reg 0x78 = 0x08 -> [CODEC Write] Page 83, Reg 0x08 = 0xF0 -> [CODEC Write] Page 83, Reg 0x18 = 0x38 -> [CODEC Write] Page 83, Reg 0x28 = 0x38 -> [CODEC Write] Page 83, Reg 0x38 = 0x00 -> [CODEC Write] Page 83, Reg 0x48 = 0x38 -> [CODEC Write] Page 83, Reg 0x58 = 0x00 -> [CODEC Write] Page 44, Reg 0x08 = 0xFF -> [CODEC Write] Page 44, Reg 0x18 = 0x7F -> [CODEC Write] Page 44, Reg 0x28 = 0x04 -> [CODEC Write] Page 44, Reg 0x38 = 0x25 -> [CODEC Write] Page 44, Reg 0x48 = 0x61 -> [CODEC Write] Page 44, Reg 0x58 = 0x69 -> [CODEC Write] Page 44, Reg 0x68 = 0x16 -> [CODEC Write] Page 44, Reg 0x78 = 0xD2 -> [CODEC Write] Page 45, Reg 0x08 = 0xD7 -> [CODEC Write] Page 45, Reg 0x18 = 0x09 -> [CODEC Write] Page 45, Reg 0x28 = 0x16 -> [CODEC Write] Page 45, Reg 0x38 = 0xF9 -> [CODEC Write] Page 45, Reg 0x48 = 0xF5 -> [CODEC Write] Page 45, Reg 0x58 = 0x04 -> [CODEC Write] Page 45, Reg 0x68 = 0x04 -> [CODEC Write] Page 45, Reg 0x78 = 0xFD -> [CODEC Write] Page 46, Reg 0x08 = 0xFD -> [CODEC Write] Page 46, Reg 0x18 = 0x00 -> [CODEC Write] Page 46, Reg 0x28 = 0x00 -> [CODEC Write] Page 152, Reg 0x08 = 0x08 -> [CODEC Write] Page 152, Reg 0x18 = 0x30 -> [CODEC Write] Page 152, Reg 0x28 = 0x00 -> [CODEC Write] Page 152, Reg 0x38 = 0x10 -> [CODEC Write] Page 152, Reg 0x48 = 0x38 -> [CODEC Write] Page 152, Reg 0x58 = 0x00 -> [CODEC Write] Page 152, Reg 0x68 = 0x20 -> [CODEC Write] Page 152, Reg 0x78 = 0x38 -> [CODEC Write] Page 153, Reg 0x08 = 0x00 -> [CODEC Write] Page 153, Reg 0x18 = 0x20 -> [CODEC Write] Page 153, Reg 0x28 = 0x38 -> [CODEC Write] Page 153, Reg 0x38 = 0x00 -> [CODEC Write] Page 153, Reg 0x48 = 0x00 -> [CODEC Write] Page 153, Reg 0x58 = 0x10 -> [CODEC Write] Page 153, Reg 0x68 = 0x38 -> [CODEC Write] Page 153, Reg 0x78 = 0x38 -> [CODEC Write] Page 154, Reg 0x08 = 0x50 -> [CODEC Write] Page 154, Reg 0x18 = 0x38 -> [CODEC Write] Page 154, Reg 0x28 = 0x38 -> [CODEC Write] Page 154, Reg 0x38 = 0x38 -> [CODEC Write] Page 154, Reg 0x48 = 0x38 -> [CODEC Write] Page 154, Reg 0x58 = 0x50 -> [CODEC Write] Page 154, Reg 0x68 = 0x38 -> [CODEC Write] Page 154, Reg 0x78 = 0x38 -> [CODEC Write] Page 155, Reg 0x08 = 0x50 -> [CODEC Write] Page 155, Reg 0x18 = 0x31 -> [CODEC Write] Page 155, Reg 0x28 = 0x10 -> [CODEC Write] Page 155, Reg 0x38 = 0x38 -> [CODEC Write] Page 155, Reg 0x48 = 0x38 -> [CODEC Write] Page 155, Reg 0x58 = 0x38 -> [CODEC Write] Page 155, Reg 0x68 = 0x38 -> [CODEC Write] Page 155, Reg 0x78 = 0x50 -> [CODEC Write] Page 156, Reg 0x08 = 0x00 -> [CODEC Write] Page 156, Reg 0x18 = 0x38 -> [CODEC Write] Page 156, Reg 0x28 = 0x10 -> [CODEC Write] Page 156, Reg 0x38 = 0x38 -> [CODEC Write] Page 156, Reg 0x48 = 0x00 -> [CODEC Write] Page 156, Reg 0x58 = 0x20 -> [CODEC Write] Page 156, Reg 0x68 = 0x38 -> [CODEC Write] Page 156, Reg 0x78 = 0x30 -> [CODEC Write] Page 157, Reg 0x08 = 0x20 -> [CODEC Write] Page 157, Reg 0x18 = 0x38 -> [CODEC Write] Page 157, Reg 0x28 = 0x30 -> [CODEC Write] Page 157, Reg 0x38 = 0x38 -> [CODEC Write] Page 157, Reg 0x48 = 0x00 -> [CODEC Write] Page 157, Reg 0x58 = 0x20 -> [CODEC Write] Page 157, Reg 0x68 = 0x88 -> [CODEC Write] Page 157, Reg 0x78 = 0x30 -> [CODEC Write] Page 158, Reg 0x08 = 0x38 -> [CODEC Write] Page 158, Reg 0x18 = 0x38 -> [CODEC Write] Page 158, Reg 0x28 = 0x38 -> [CODEC Write] Page 158, Reg 0x38 = 0x38 -> [CODEC Write] Page 158, Reg 0x48 = 0x50 -> [CODEC Write] Page 158, Reg 0x58 = 0x38 -> [CODEC Write] Page 158, Reg 0x68 = 0x38 -> [CODEC Write] Page 158, Reg 0x78 = 0x00 -> [CODEC Write] Page 159, Reg 0x08 = 0x31 -> [CODEC Write] Page 159, Reg 0x18 = 0x00 -> [CODEC Write] Page 159, Reg 0x28 = 0x00 -> [CODEC Write] Page 159, Reg 0x38 = 0x10 -> [CODEC Write] Page 159, Reg 0x48 = 0x38 -> [CODEC Write] Page 159, Reg 0x58 = 0x00 -> [CODEC Write] Page 159, Reg 0x68 = 0x10 -> [CODEC Write] Page 0, Reg 0x52 = 0x00 ! ADC Fine Gain Adjust Register / ADC Mute D7: Left Mute, D4: Right Mute -> [CODEC Write] Page 0, Reg 0x56 = 0x20 Left Channel AGC Control Register 1 [CODEC] MiniDSP download done <- [CODEC Read] Page 8, Reg 0x38 = 0x26 <- [CODEC Read] Page 44, Reg 0x48 = 0x61 <- [CODEC Read] Page 80, Reg 0x28 = 0xF0 <- [CODEC Read] Page 152, Reg 0x68 = 0x20 <- [CODEC Read] Page 157, Reg 0x68 = 0x88 -> [CODEC Write] Page 0, Reg 0x3C = 0x80 DAC Signal Processing Block Control Register -> [CODEC Write] Page 0, Reg 0x3D = 0x00 ADC Signal Processing Block Control Register -> [CODEC Write] Page 0, Reg 0x11 = 0x08 miniDSP_D Interpolation Factor Setting Register -> [CODEC Write] Page 0, Reg 0x17 = 0x04 miniDSP_A Decimation Factor Setting Register -> [CODEC Write] Page 8, Reg 0x01 = 0x00 -> [CODEC Write] Page 44, Reg 0x01 = 0x00 -> [CODEC Write] Page 0, Reg 0x05 = 0x94 Clock Setting Register 2, PLL P and R Values -> [CODEC Write] Page 0, Reg 0x06 = 0x0A Clock Setting Register 3, PLL J Values -> [CODEC Write] Page 0, Reg 0x07 = 0x1A Clock Setting Register 4, PLL D Values (MSB) -> [CODEC Write] Page 0, Reg 0x08 = 0x0B Clock Setting Register 5, PLL D Values (LSB) -> [CODEC Write] Page 0, Reg 0x04 = 0x07 Clock Setting Register 1, Multiplexers -> [CODEC Write] Page 0, Reg 0x0C = 0x88 Clock Setting Register 7, MDAC Values -> [CODEC Write] Page 0, Reg 0x0D = 0x00 DAC OSR Setting Register 1, MSB Value -> [CODEC Write] Page 0, Reg 0x0E = 0x80 DAC OSR Setting Register 2, LSB Value -> [CODEC Write] Page 0, Reg 0x12 = 0x82 Clock Setting Register 8, NADC Values -> [CODEC Write] Page 0, Reg 0x13 = 0x88 Clock Setting Register 9, MADC Values -> [CODEC Write] Page 0, Reg 0x14 = 0x80 ADC Oversampling (AOSR) Register -> [CODEC Write] Page 0, Reg 0x0B = 0x82 Clock Setting Register 6, NDAC Values -> [CODEC Write] Page 0, Reg 0x15 = 0x01 miniDSP_A Instruction Control Register 1 -> [CODEC Write] Page 0, Reg 0x16 = 0x00 miniDSP_A Instruction Control Register 2 -> [CODEC Write] Page 0, Reg 0x1B = 0x20 Audio Interface Setting Register 1 -> [CODEC Write] Page 0, Reg 0x1C = 0x00 Audio Interface Setting Register 2, Data offset setting -> [CODEC Write] Page 0, Reg 0x1D = 0x00 Audio Interface Setting Register 3 -> [CODEC Write] Page 1, Reg 0x33 = 0x68 MICBIAS Configuration Register -> [CODEC Write] Page 1, Reg 0x34 = 0x40 Left MICPGA Positive Terminal Input Routing Configuration Register -> [CODEC Write] Page 1, Reg 0x36 = 0x40 Left MICPGA Negative Terminal Input Routing Configuration Register -> [CODEC Write] Page 1, Reg 0x37 = 0x01 Right MICPGA Positive Terminal Input Routing Configuration Register -> [CODEC Write] Page 1, Reg 0x39 = 0x40 Right MICPGA Negative Terminal Input Routing Configuration Register -> [CODEC Write] Page 1, Reg 0x3B = 0x0A ! Left MICPGA Volume Control Register -> [CODEC Write] Page 1, Reg 0x3C = 0x0A ! Right MICPGA Volume Control Register -> [CODEC Write] Page 0, Reg 0x51 = 0xC0 ! ADC Channel Setup Register D7: Left Power, D6: Right Power, D5-2 Dig mic, D1-0: ADC vol soft stepping -> [CODEC Write] Page 0, Reg 0x52 = 0x00 ! ADC Fine Gain Adjust Register / ADC Mute D7: Left Mute, D4: Right Mute -> [CODEC Write] Page 0, Reg 0x53 = 0x00 ! Left ADC Channel Volume Control Register D7-0: Volume -> [CODEC Write] Page 0, Reg 0x54 = 0x00 ! Right ADC Channel Volume Control Register D7-0: Volume -> [CODEC Write] Page 0, Reg 0x56 = 0x00 Left Channel AGC Control Register 1 -> [CODEC Write] Page 0, Reg 0x5E = 0x00 Right Channel AGC Control Register 1 -> [CODEC Write] Page 1, Reg 0x0C = 0x08 ! HPL Routing Selection Register -> [CODEC Write] Page 1, Reg 0x0D = 0x08 ! HPR Routing Selection Register -> [CODEC Write] Page 1, Reg 0x0E = 0x08 ! LOL Routing Selection Register -> [CODEC Write] Page 1, Reg 0x0F = 0x08 ! LOR Routing Selection Register -> [CODEC Write] Page 0, Reg 0x3F = 0xD4 ! DAC Channel Setup Register 1 -> [CODEC Write] Page 1, Reg 0x10 = 0x40 ! HPL Driver Gain Setting Register D6: Mute, D5-0: Gain -> [CODEC Write] Page 1, Reg 0x11 = 0x40 ! HPR Driver Gain Setting Register D6: Mute, D5-0: Gain -> [CODEC Write] Page 1, Reg 0x12 = 0x00 ! LOL Driver Gain Setting Register D6: Mute, D5-0: Gain -> [CODEC Write] Page 1, Reg 0x13 = 0x00 ! LOR Driver Gain Setting Register D6: Mute, D5-0: Gain -> [CODEC Write] Page 1, Reg 0x09 = 0x0C ! Output Driver Power Control Register D5-4: HPx, D3-2: LOx, D1-0: MAx -> [CODEC Write] Page 0, Reg 0x40 = 0x00 ! DAC Channel Setup Register 2 -> [CODEC Write] Page 0, Reg 0x41 = 0x00 ! Left DAC Channel Digital Volume Control Register -> [CODEC Write] Page 0, Reg 0x42 = 0x00 ! Right DAC Channel Digital Volume Control Register -> [CODEC Write] Page 0, Reg 0x43 = 0x00 Headset Detection Configuration Register > AT+SPKVOL=15 < OK [CODEC DIAG] ===== TLV320AIC3254 diagnostics (power/mute/gain/flags focus) ===== [CODEC DIAG] Note: Sticky flag registers clear-on-read. <- [CODEC Read] Page 0, Reg 0x04 = 0x07 Clock Setting Register 1, Multiplexers <- [CODEC Read] Page 0, Reg 0x05 = 0x94 Clock Setting Register 2, PLL P and R Values <- [CODEC Read] Page 0, Reg 0x06 = 0x0A Clock Setting Register 3, PLL J Values <- [CODEC Read] Page 0, Reg 0x07 = 0x1A Clock Setting Register 4, PLL D Values (MSB) <- [CODEC Read] Page 0, Reg 0x08 = 0x0B Clock Setting Register 5, PLL D Values (LSB) <- [CODEC Read] Page 0, Reg 0x0B = 0x82 Clock Setting Register 6, NDAC Values <- [CODEC Read] Page 0, Reg 0x0C = 0x88 Clock Setting Register 7, MDAC Values <- [CODEC Read] Page 0, Reg 0x0D = 0x00 DAC OSR Setting Register 1, MSB Value <- [CODEC Read] Page 0, Reg 0x0E = 0x80 DAC OSR Setting Register 2, LSB Value <- [CODEC Read] Page 0, Reg 0x0F = 0x02 miniDSP_D Instruction Control Register 1 <- [CODEC Read] Page 0, Reg 0x10 = 0x00 miniDSP_D Instruction Control Register 2 <- [CODEC Read] Page 0, Reg 0x11 = 0x08 miniDSP_D Interpolation Factor Setting Register <- [CODEC Read] Page 0, Reg 0x12 = 0x82 Clock Setting Register 8, NADC Values <- [CODEC Read] Page 0, Reg 0x13 = 0x88 Clock Setting Register 9, MADC Values <- [CODEC Read] Page 0, Reg 0x14 = 0x80 ADC Oversampling (AOSR) Register <- [CODEC Read] Page 0, Reg 0x15 = 0x01 miniDSP_A Instruction Control Register 1 <- [CODEC Read] Page 0, Reg 0x16 = 0x00 miniDSP_A Instruction Control Register 2 <- [CODEC Read] Page 0, Reg 0x17 = 0x04 miniDSP_A Decimation Factor Setting Register <- [CODEC Read] Page 0, Reg 0x19 = 0x00 Clock Setting Register 10, Multiplexers <- [CODEC Read] Page 0, Reg 0x1A = 0x01 Clock Setting Register 11, CLKOUT M divider value <- [CODEC Read] Page 0, Reg 0x1B = 0x20 Audio Interface Setting Register 1 <- [CODEC Read] Page 0, Reg 0x1C = 0x00 Audio Interface Setting Register 2, Data offset setting <- [CODEC Read] Page 0, Reg 0x1D = 0x00 Audio Interface Setting Register 3 <- [CODEC Read] Page 0, Reg 0x1E = 0x01 Clock Setting Register 12, BCLK N Divider <- [CODEC Read] Page 0, Reg 0x3C = 0x80 DAC Signal Processing Block Control Register <- [CODEC Read] Page 0, Reg 0x3D = 0x00 ADC Signal Processing Block Control Register <- [CODEC Read] Page 0, Reg 0x3E = 0x00 miniDSP_A and miniDSP_D Configuration Register <- [CODEC Read] Page 0, Reg 0x3F = 0xD4 ! DAC Channel Setup Register 1 <- [CODEC Read] Page 0, Reg 0x40 = 0x00 ! DAC Channel Setup Register 2 <- [CODEC Read] Page 0, Reg 0x41 = 0x00 ! Left DAC Channel Digital Volume Control Register <- [CODEC Read] Page 0, Reg 0x42 = 0x00 ! Right DAC Channel Digital Volume Control Register <- [CODEC Read] Page 0, Reg 0x43 = 0x00 Headset Detection Configuration Register <- [CODEC Read] Page 0, Reg 0x44 = 0x6F DRC Control Register 1 <- [CODEC Read] Page 0, Reg 0x45 = 0x38 DRC Control Register 2 <- [CODEC Read] Page 0, Reg 0x46 = 0x00 DRC Control Register 3 <- [CODEC Read] Page 0, Reg 0x51 = 0xC0 ! ADC Channel Setup Register D7: Left Power, D6: Right Power, D5-2 Dig mic, D1-0: ADC vol soft stepping <- [CODEC Read] Page 0, Reg 0x52 = 0x00 ! ADC Fine Gain Adjust Register / ADC Mute D7: Left Mute, D4: Right Mute <- [CODEC Read] Page 0, Reg 0x53 = 0x00 ! Left ADC Channel Volume Control Register D7-0: Volume <- [CODEC Read] Page 0, Reg 0x54 = 0x00 ! Right ADC Channel Volume Control Register D7-0: Volume <- [CODEC Read] Page 0, Reg 0x56 = 0x00 Left Channel AGC Control Register 1 <- [CODEC Read] Page 0, Reg 0x5E = 0x00 Right Channel AGC Control Register 1 <- [CODEC Read] Page 0, Reg 0x24 = 0xCC ADC Flag Register <- [CODEC Read] Page 0, Reg 0x25 = 0xCC DAC Flag Register 1 <- [CODEC Read] Page 0, Reg 0x26 = 0x11 DAC Flag Register 2 <- [CODEC Read] Page 0, Reg 0x2A = 0x00 Sticky Flag Register 1 <- [CODEC Read] Page 0, Reg 0x2B = 0x00 Interrupt Flag Register 1 <- [CODEC Read] Page 0, Reg 0x2C = 0x00 Sticky Flag Register 2 <- [CODEC Read] Page 0, Reg 0x2D = 0x00 Sticky Flag Register 3 <- [CODEC Read] Page 0, Reg 0x2E = 0x00 Interrupt Flag Register 2 <- [CODEC Read] Page 0, Reg 0x2F = 0x00 Interrupt Flag Register 3 <- [CODEC Read] Page 0, Reg 0x30 = 0x00 INT1 Interrupt Control Register <- [CODEC Read] Page 0, Reg 0x31 = 0x00 INT2 Interrupt Control Register <- [CODEC Read] Page 1, Reg 0x01 = 0x08 Power Configuration Register <- [CODEC Read] Page 1, Reg 0x02 = 0x01 LDO Control Register <- [CODEC Read] Page 1, Reg 0x0A = 0x3B Common Mode Control Register <- [CODEC Read] Page 1, Reg 0x7B = 0x01 Reference Power-up Configuration Register <- [CODEC Read] Page 1, Reg 0x09 = 0x0C ! Output Driver Power Control Register D5-4: HPx, D3-2: LOx, D1-0: MAx <- [CODEC Read] Page 1, Reg 0x0B = 0x10 Over Current Protection Configuration Register <- [CODEC Read] Page 1, Reg 0x0C = 0x08 ! HPL Routing Selection Register <- [CODEC Read] Page 1, Reg 0x0D = 0x08 ! HPR Routing Selection Register <- [CODEC Read] Page 1, Reg 0x0E = 0x08 ! LOL Routing Selection Register <- [CODEC Read] Page 1, Reg 0x0F = 0x08 ! LOR Routing Selection Register <- [CODEC Read] Page 1, Reg 0x10 = 0x40 ! HPL Driver Gain Setting Register D6: Mute, D5-0: Gain <- [CODEC Read] Page 1, Reg 0x11 = 0x40 ! HPR Driver Gain Setting Register D6: Mute, D5-0: Gain <- [CODEC Read] Page 1, Reg 0x12 = 0x00 ! LOL Driver Gain Setting Register D6: Mute, D5-0: Gain <- [CODEC Read] Page 1, Reg 0x13 = 0x00 ! LOR Driver Gain Setting Register D6: Mute, D5-0: Gain <- [CODEC Read] Page 1, Reg 0x3E = 0x03 ADC Analog Volume Control Flag Register <- [CODEC Read] Page 1, Reg 0x3F = 0x30 DAC Analog Gain Control Flag Register [CODEC DIAG] Clocks / interface P0 0x04 = 0x07 Clock mux (raw) PLL input sel: code=1 (BCLK) CODEC_CLKIN sel: code=3 (PLL_CLK) P0 0x05 = 0x94 PLL: pwr=1 P=1 (code=1) R=4 P0 0x06 = 0x0A PLL J=10 P0 0x07/0x08 = 0x1A0B PLL D=6667 P0 0x0B = 0x82 NDAC: ON, N=2 P0 0x0C = 0x88 MDAC: ON, M=8 P0 0x0D/0x0E = 0x0080 DOSR=128 P0 0x0F/0x10 = 0x0200 miniDSP_D IDAC=512 P0 0x11 = 0x08 miniDSP_D INTERP=8 P0 0x12 = 0x82 NADC: ON, N=2 P0 0x13 = 0x88 MADC: ON, M=8 P0 0x14 = 0x80 AOSR=128 P0 0x15 = 0x01 miniDSP_A instr ctrl1 P0 0x16 = 0x00 miniDSP_A instr ctrl2 P0 0x17 = 0x04 miniDSP_A decimation factor P0 0x1E = 0x01 BCLK N divider P0 0x1B = 0x20 IF1 P0 0x1C = 0x00 IF2 (offset) P0 0x1D = 0x00 IF3 P0 0x19 = 0x00 Clock setting 10 (mux) P0 0x1A = 0x01 CLKOUT divider [CODEC DIAG] Analog power / reference P1 0x01 = 0x08 Power Configuration P1 0x02 = 0x01 LDO Control AVDD LDO: ON LDO OC detect (RO): DVDD=0 AVDD=0 Analog blocks disable bit: 0 P1 0x0A = 0x3B Common mode / supplies P1 0x7B = 0x01 Reference Power-up config [CODEC DIAG] Signal processing blocks P0 0x3C = 0x80 DAC Signal Processing Block Control P0 0x3D = 0x00 ADC Signal Processing Block Control P0 0x3E = 0x00 miniDSP_A/D configuration DAC PRB sel: miniDSP_D (custom) (code=0) [CODEC DIAG] DRC (Dynamic Range Compression) P0 0x44 = 0x6F DRC Control 1 P0 0x45 = 0x38 DRC Control 2 P0 0x46 = 0x00 DRC Control 3 enabled: L=1 R=1 threshold: code=3 (-12 dBFS) hysteresis: code=3 hold_code=7 attack_code=0 (raw from 0x45) decay/maxAtten raw=0x00 (0x46) NOTE: DRC is only active if the selected DAC PRB supports DRC. [CODEC DIAG] DAC (digital control) P0 0x3F = 0xD4 DAC Channel Setup 1 P0 0x40 = 0x00 DAC Channel Setup 2 P0 0x41 = 0x00 L DAC volume = +0.0 dB P0 0x42 = 0x00 R DAC volume = +0.0 dB P0 0x43 = 0x00 Headset detect config [CODEC DIAG] ADC (digital control) P0 0x51 = 0xC0 ADC Channel Setup P0 0x52 = 0x00 ADC Fine Gain / Mute P0 0x53 = 0x00 L ADC volume = +0.0 dB P0 0x54 = 0x00 R ADC volume = +0.0 dB P0 0x56 = 0x00 L AGC ctrl1 (enabled=0) P0 0x5E = 0x00 R AGC ctrl1 (enabled=0) [CODEC DIAG] ADC/DAC flag registers (raw) P0 0x24 = 0xCC ADC Flag Register (live) P0 0x25 = 0xCC DAC Flag Register 1 (live) P0 0x26 = 0x11 DAC Flag Register 2 (live) [CODEC DIAG] Outputs (routing + power + gains) P1 0x09 = 0x0C Output Driver Power Control P1 0x0C = 0x08 HPL routing P1 0x0D = 0x08 HPR routing P1 0x0E = 0x08 LOL routing P1 0x0F = 0x08 LOR routing P1 0x10 = 0x40 HPL driver: mute=1 gain_code=0x00 (~+0 dB) P1 0x11 = 0x40 HPR driver: mute=1 gain_code=0x00 (~+0 dB) P1 0x12 = 0x00 LOL driver: mute=0 gain_code=0x00 (~+0 dB) P1 0x13 = 0x00 LOR driver: mute=0 gain_code=0x00 (~+0 dB) [CODEC DIAG] Over-current / OC detect P1 0x0B = 0x10 Over-current protection configuration (HPL/HPR) enable=1 debounce_code=0 response_code=0 P0 0x2E = 0x00 Interrupt Flag Reg2 (live) P0 0x2C = 0x00 Sticky Flag Reg2 (sticky, clears-on-read) Headphone OC live: HPL=0 HPR=0 Headphone OC sticky: HPL=0 HPR=0 miniDSP_D IRQ sticky: STD=0 AUX=0 [CODEC DIAG] Overflow / DSP status (IMPORTANT) P0 0x2B = 0x00 Interrupt Flag Reg1 (live overflow flags) P0 0x2A = 0x00 Sticky Flag Reg1 (sticky overflow flags, clears-on-read) LIVE: LDAC_OV=0 RDAC_OV=0 miniDSP_D_OV=0 LADC_OV=0 RADC_OV=0 miniDSP_A_OV=0 STICKY: LDAC_OV=0 RDAC_OV=0 miniDSP_D_OV=0 LADC_OV=0 RADC_OV=0 miniDSP_A_OV=0 DRC threshold sticky: L=0 R=0 [CODEC DIAG] Interrupt + sticky flags (raw) P0 0x2D = 0x00 Sticky Flag Reg3 (sticky, clears-on-read) P0 0x2F = 0x00 Interrupt Flag Reg3 (live) P0 0x30 = 0x00 Interrupt Control Reg1 P0 0x31 = 0x00 Interrupt Control Reg2 [CODEC DIAG] Analog volume/gain flags (1 = applied == programmed) P1 0x3E = 0x03 ADC Analog Volume Control Flag P1 0x3F = 0x30 DAC Analog Gain Control Flag ADC analog volume settled: L=1 R=1 DAC analog gain settled: HPL=0 HPR=0 LOL=1 LOR=1 MAL=0 MAR=0 [CODEC DIAG] Playback sanity (LOL/LOR) OK: No obvious register-level mute/power/routing blockers for LOL/LOR playback. If you still get "brief distorted audio then silence", focus on: - miniDSP_D overflow (P0 0x2A/0x2B bit5) - headphone OC bits (P0 0x2C/0x2E bits7..6) - DSP/PRB selection (P0 0x3C) and DSP clocking (P0 0x0F..0x11) [CODEC DIAG] ===============================================================