0:	begin    Areg <= 7 'h0D;Dreg <=16'h0000;end                //JESD RESET AB/CD = 0 JESD INIT AB/CD = 0                                                                                                                      
                  64:   begin    Areg <= 7 'h0D;Dreg <=16'h0202;end                //JESD INIT  AB/CD = 1
                 128:   begin    Areg <= 7 'h0D;Dreg <=16'h0303;end                //JESD RESET AB/CD = 1
                   
                 192:   begin    Areg <= 7 'h00;Dreg <=16'h4000;end                //3 wire SPI / offset binary / decimation filter disable / 
                 256:   begin    Areg <= 7 'h01;Dreg <=16'h2F7A;end                //OVRA THRESH AB/CD = 111       FOVR LENGTH AB/CD = 4 clock cycle    
      
                 320:   begin    Areg <= 7 'h03;Dreg <=16'h0040;end                 // clock for channel CD = CD divider source  clock for channel AB =                                                                                         AB clock source
                                                                                    // SYSREF_CD  = use sysref AB inputs  clk_div = 1
                 384:   begin    Areg <= 7 'h04;Dreg <=16'hC00B;end                 //OVRA OVRB ENABLE OVRC OVRD disable  SYSREF AB/CD input 0 - delay
                                                                                    // SYNC AB enable  SYNC CD disable
                                                                                    
                 448:   begin    Areg <= 7 'h05;Dreg <=16'h00DA;end                 //light sleep channel AB =1  light sleep channel CD = 0 
                                                                                    //TEMP sensor = 1 clock buffer = 1 clock divider channel AB = 1                                                                                        clock divider channel CD =0
                                                                                    // Buffer SYSREF AB = 1   Buffer SYSREF CD = 0
                                                                                    
                 512:   begin    Areg <= 7 'h06;Dreg <=16'hFFFF;end                 //POWER DOWN MODE through SPI
                 // step
                 576:   begin    Areg <= 7 'h07;Dreg <=16'h0144;end                // 改时钟分频比的时候用
                 640:   begin    Areg <= 7 'h08;Dreg <=16'h0144;end                // 改时钟分频比的时候用
                 704:   begin    Areg <= 7 'h0C;Dreg <=16'h31C2;end                // channel CD don;t use sysref   channel AB use only the next one
                 768:   begin    Areg <= 7 'h0E;Dreg <=16'h000F;end                // channel AB enable / channel CD disable 
       //JESD204B parameters AB          
                 832:   begin    Areg <= 7 'h0F;Dreg <=16'h0001;end                // channel AB F =1  M =2
                 896:   begin    Areg <= 7 'h10;Dreg <=16'h03A3;end                // K = 32 L = 4
                 960:   begin    Areg <= 7 'h13;Dreg <=16'h0020;end                // SYNCbAB input non - invert HD =1 SCRAMBLE MODE DISABLE
       
       //JESD204B paramater CD
                1024:  begin     Areg <= 7 'h16;Dreg <=16'h0001;end                //  channel CD F =1  M =2              
                1088:  begin     Areg <= 7 'h17;Dreg <=16'h03A3;end                //  K = 32 L =4
                1152:  begin     Areg <= 7 'h1A;Dreg <=16'h0020;end                //  SYNCbCD input non - invert HD =1 SCRAMBLE MODE DISABLE
       
                1216:  begin     Areg <= 7 'h1D;Dreg <=16'h0000;end                // test pattern disable / normal operation
                             
       // JESD204B power down mode
                1280:  begin     Areg <= 7 'h1E;Dreg <=16'h010F;end                //JESD PLL channel CD power down  Channel CD power down   
                1344:  begin     Areg <= 7 'h1F;Dreg <=16'hFFFF;end                //JESD204 power down mode
       
                1408:  begin     Areg <= 7 'h20;Dreg <=16'h0000;end                //lane non - invert / don't output PRBS pattern
                1472:   begin    Areg <= 7 'h21;Dreg <=16'h0000;end                //PRBS pattern  Full scale is 1.25Vpp      

      // pre_emhasis           
                1536:  begin     Areg <= 7 'h64;Dreg <=16'h0000;end                // pre_emphasis disable AB
                1600:  begin     Areg <= 7 'h67;Dreg <=16'h0000;end                // pre_emphasis current AB
                
                1664:  begin     Areg <= 7 'h68;Dreg <=16'h0000;end                // pre-emphasis disable CD                              
                1728:  begin     Areg <= 7 'h6B;Dreg <=16'h0000;end                // pew_emphasis disable CD
      // JESD INITIAL AGAIN
                1792:  begin     Areg <= 7 'h0D;Dreg <=16'h0202;end                //JESD RESET AB/CD = 0 
                1856:  begin     Areg <= 7 'h0D;Dreg <=16'h0303;end                //JESD RESET AB/CD = 1                             
                1920:  begin     Areg <= 7 'h0D;Dreg <=16'h0101;end                //JESD INIT AB/CD = 0