Synthesis and Ngdbuild Report #Build: Synplify Pro E-2010.09L-SP2, Build 081R, Feb 16 2011 #install: C:\lscc\diamond\1.2\synpbase #OS: Windows_NT #Hostname: LTA0840029A $ Start of Compile #Sun Jan 08 17:39:12 2012 Synopsys Verilog Compiler, version comp520rcp2, Build 118R, built Feb 11 2011 @N|Running in 32-bit mode Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @I::"C:\lscc\diamond\1.2\synpbase\lib\lucent\ecp3.v" @I::"C:\lscc\diamond\1.2\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v" @W: CS133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":132:26:132:44|ignoring property FREQUENCY_PIN_CLKOS @W: CS133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":133:26:133:44|ignoring property FREQUENCY_PIN_CLKOP @W: CS133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":134:26:134:43|ignoring property FREQUENCY_PIN_CLKI @W: CS133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":135:26:135:44|ignoring property FREQUENCY_PIN_CLKOK @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v" @W: CG921 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":70:7:70:10|done is already declared in this scope. @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_dp.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_dpfifodc.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_mspi.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_rctrl.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_top.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\jtag_interface.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\orcastra.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\tsw1405_reset.v" @I::"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\TSW1405.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module TSW1405_1ch_bit_wise @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":1202:7:1202:10|Synthesizing module OSCF @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\tsw1405_reset.v":24:7:24:19|Synthesizing module tsw1405_reset @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":1196:7:1196:13|Synthesizing module CLKDIVB @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":1796:7:1796:12|Synthesizing module DELAYB @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":1695:7:1695:14|Synthesizing module IDDRX2D1 @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":12:7:12:11|Synthesizing module adcif @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":39:24:39:30|No assignment to wire adc_sen @W: CG133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":40:24:40:31|No assignment to adc_sclk @W: CG133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":41:24:41:32|No assignment to adc_sdata @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":42:24:42:31|No assignment to wire adc_cfg1 @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":43:24:43:31|No assignment to wire adc_cfg2 @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":44:24:44:31|No assignment to wire adc_cfg3 @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":45:24:45:31|No assignment to wire adc_cfg4 @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":46:24:46:27|No assignment to wire clk2 @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":47:9:47:16|No assignment to wire clkintfb @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":49:9:49:13|No assignment to wire clkos @W: CL169 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":65:0:65:5|Pruning Register cntr[15:0] @W: CL169 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":65:0:65:5|Pruning Register cntr_r[15:0] @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[28] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[27] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[26] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[25] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[24] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[23] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[22] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[21] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[20] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[19] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[18] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[17] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[16] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[15] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[14] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[13] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[8] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[3] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[2] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[1] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Pruning instance Inst1_IDDRX2D0[0] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[28] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[27] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[26] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[25] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[24] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[23] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[22] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[21] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[20] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[19] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[18] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[17] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[16] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[15] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[14] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[13] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[8] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[3] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[2] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[1] - not in use ... @W: CL168 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Pruning instance delay0[0] - not in use ... @N: CL177 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":74:0:74:5|Sharing sequential element format_dout2. @N: CL177 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":74:0:74:5|Sharing sequential element format_dout3. @N: CL177 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":74:0:74:5|Sharing sequential element format_dout4. @N: CL177 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":74:0:74:5|Sharing sequential element format_dout6. @N: CL177 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":74:0:74:5|Sharing sequential element format_dout7. @N: CL177 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":74:0:74:5|Sharing sequential element format_dout8. @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":43:7:43:10|Synthesizing module AND2 @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":457:7:457:9|Synthesizing module INV @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":834:7:834:9|Synthesizing module OR2 @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":1078:7:1078:10|Synthesizing module XOR2 @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":956:7:956:14|Synthesizing module ROM16X1A @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":1253:7:1253:12|Synthesizing module DP16KC @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":186:7:186:13|Synthesizing module FD1P3BX @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":197:7:197:13|Synthesizing module FD1P3DX @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":258:7:258:13|Synthesizing module FD1S3DX @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":248:7:248:13|Synthesizing module FD1S3BX @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":148:7:148:12|Synthesizing module FADD2B @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":129:7:129:9|Synthesizing module CU2 @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":25:7:25:11|Synthesizing module AGEB2 @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":1025:7:1025:9|Synthesizing module VHI @N: CG364 :"C:\lscc\diamond\1.2\cae_library\synthesis\verilog\ecp3.v":1029:7:1029:9|Synthesizing module VLO @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":8:7:8:22|Synthesizing module dumpmem_dpfifodc @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_dp.v":22:7:22:16|Synthesizing module dumpmem_dp @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v":22:7:22:19|Synthesizing module dumpmem_wctrl @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_rctrl.v":26:7:26:19|Synthesizing module dumpmem_rctrl @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_mspi.v":21:7:21:18|Synthesizing module dumpmem_mspi @W: CL169 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_mspi.v":76:0:76:5|Pruning Register clkspi_negedge_r @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":20:7:20:13|Synthesizing module dumpmem @W: CL169 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":250:0:250:5|Pruning Register oe_fifo_d1_r2[7:0] @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\orcastra.v":57:7:57:28|Synthesizing module ORCAstra_JTAGE_Hub_sub @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\jtag_interface.v":176:7:176:16|Synthesizing module jtagconn16 @W: CG146 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\jtag_interface.v":176:7:176:16|Creating black box for empty module jtagconn16 @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\orcastra.v":4:7:4:14|Synthesizing module orcastra @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\jtag_interface.v":4:7:4:20|Synthesizing module jtag_interface @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_top.v":21:7:21:17|Synthesizing module dumpmem_top @N: CG364 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\TSW1405.v":4:7:4:26|Synthesizing module TSW1405_1ch_bit_wise @W: CG133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\TSW1405.v":43:11:43:14|No assignment to wren @W: CG360 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\TSW1405.v":53:13:53:21|No assignment to wire dout_fifo @W: CG133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\TSW1405.v":67:8:67:22|No assignment to capture_sync1_r @W: CG133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\TSW1405.v":68:8:68:22|No assignment to capture_sync2_r @W: CG133 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\TSW1405.v":69:13:69:21|No assignment to testcnt_r @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_top.v":48:8:48:11|Input mosi is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\jtag_interface.v":9:16:9:25|Input dout_fifo1 is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\orcastra.v":80:14:80:20|Input jupdate is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\orcastra.v":81:14:81:18|Input jrstn is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":37:12:37:20|Input cap_depth is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":38:12:38:21|Input cap_format is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":39:12:39:20|Input cap_chans is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":40:8:40:15|Input inv_data is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":41:8:41:14|Input inv_clk is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem.v":42:8:42:16|Input lsb_first is unused @W: CL190 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_mspi.v":106:0:106:5|Optimizing register bit bytecntr_r[1] to a constant 0 @W: CL260 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_mspi.v":106:0:106:5|Pruning Register bit 1 of bytecntr_r[1:0] @W: CL260 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Pruning Register bit 7 of be_fifo_m3_r[7:0] @W: CL260 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Pruning Register bit 6 of be_fifo_m3_r[7:0] @W: CL260 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Pruning Register bit 5 of be_fifo_m3_r[7:0] @W: CL260 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Pruning Register bit 4 of be_fifo_m3_r[7:0] @W: CL260 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Pruning Register bit 3 of be_fifo_m3_r[7:0] @W: CL260 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Pruning Register bit 2 of be_fifo_m3_r[7:0] @W: CL260 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Pruning Register bit 1 of be_fifo_m3_r[7:0] @W: CL246 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":15:26:15:28|Input port bits 28 to 13 of din[28:0] are unused @W: CL247 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":15:26:15:28|Input port bit 8 of din[28:0] is unused @W: CL246 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":15:26:15:28|Input port bits 3 to 0 of din[28:0] are unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":18:13:18:21|Input cap_depth is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":19:13:19:22|Input cap_format is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":20:13:20:21|Input cap_chans is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":21:9:21:16|Input inv_data is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":22:9:22:15|Input inv_clk is unused @W: CL159 :"C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\source\adcif.v":23:9:23:17|Input lsb_first is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Jan 08 17:39:13 2012 ###########################################################] Synopsys Lattice Technology Constraint Extraction, Version maplat, Build 064R, Built Feb 17 2011 10:52:05 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version E-2010.09L-SP2 @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled Finished Timing Extraction Phase. (Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 81MB) Timing Extraction successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Jan 08 17:39:15 2012 ###########################################################] Synopsys Lattice Technology Mapper, Version maplat, Build 064R, Built Feb 17 2011 10:52:05 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version E-2010.09L-SP2 @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF203 |Set autoconstraint_io @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Removing sequential instance be_fifo_m2_r[7:0] of view:PrimLib.sdffpatre(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Removing sequential instance be_fifo_m0_r[7:0] of view:PrimLib.sdffpatre(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Removing sequential instance be_fifo_m3_r[0] of view:PrimLib.sdffse(prim) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 87MB) @W: BN132 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Removing instance dumpmem_top_inst.dumpmem_inst.dumpmem_wctrl_inst.be_fifo_m1_r[4], because it is equivalent to instance dumpmem_top_inst.dumpmem_inst.dumpmem_wctrl_inst.be_fifo_m1_r[0] @W: BN132 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Removing instance dumpmem_top_inst.dumpmem_inst.dumpmem_wctrl_inst.be_fifo_m1_r[5], because it is equivalent to instance dumpmem_top_inst.dumpmem_inst.dumpmem_wctrl_inst.be_fifo_m1_r[1] @W: BN132 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Removing instance dumpmem_top_inst.dumpmem_inst.dumpmem_wctrl_inst.be_fifo_m1_r[6], because it is equivalent to instance dumpmem_top_inst.dumpmem_inst.dumpmem_wctrl_inst.be_fifo_m1_r[2] @W: BN132 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":54:0:54:5|Removing instance dumpmem_top_inst.dumpmem_inst.dumpmem_wctrl_inst.be_fifo_m1_r[7], because it is equivalent to instance dumpmem_top_inst.dumpmem_inst.dumpmem_wctrl_inst.be_fifo_m1_r[3] @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":117:0:117:5|Removing sequential instance winc_fifo_r[3] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":117:0:117:5|Removing sequential instance winc_fifo_r[2] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":117:0:117:5|Removing sequential instance winc_fifo_r[0] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":99:0:99:5|Removing sequential instance afull_fifo_pr[3] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":99:0:99:5|Removing sequential instance afull_fifo_pr[2] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":99:0:99:5|Removing sequential instance afull_fifo_pr[1] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":99:0:99:5|Removing sequential instance afull_fifo_pr[0] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":99:0:99:5|Removing sequential instance afull_fifo_r[3] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":99:0:99:5|Removing sequential instance afull_fifo_r[2] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":99:0:99:5|Removing sequential instance afull_fifo_r[1] of view:PrimLib.dff(prim) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_wctrl.v":99:0:99:5|Removing sequential instance afull_fifo_r[0] of view:PrimLib.dff(prim) because there are no references to its outputs @N:"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":119:0:119:5|Found counter in view:work.ORCAstra_JTAGE_Hub_sub(verilog) inst shift_cnt[4:0] @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":616:13:616:18|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.LUT4_1 of black_box view:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":620:13:620:18|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.LUT4_0 of black_box view:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1488:12:1488:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_14 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1492:12:1492:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_13 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1496:12:1496:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_12 of view:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1500:12:1500:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1504:12:1504:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1508:12:1508:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1512:12:1512:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_8 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1516:12:1516:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_7 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1520:12:1520:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_6 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1524:12:1524:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_5 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1528:12:1528:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_4 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1532:12:1532:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_3 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1536:12:1536:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_2 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1540:12:1540:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_1 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1544:12:1544:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1747:10:1747:21|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.af_set_cmp_6 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1744:10:1744:21|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.af_set_cmp_5 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1741:10:1741:21|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.af_set_cmp_4 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1738:10:1738:21|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.af_set_cmp_3 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1735:10:1735:21|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.af_set_cmp_2 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1732:10:1732:21|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.af_set_cmp_1 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1729:10:1729:21|Removing instance dumpmem_inst.dumpmem_dp_inst3.dumpmem_dpfifodc_inst.af_set_cmp_0 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":616:13:616:18|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.LUT4_1 of black_box view:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":620:13:620:18|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.LUT4_0 of black_box view:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1488:12:1488:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_14 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1492:12:1492:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_13 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1496:12:1496:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_12 of view:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1500:12:1500:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1504:12:1504:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1508:12:1508:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1512:12:1512:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_8 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1516:12:1516:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_7 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1520:12:1520:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_6 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1524:12:1524:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_5 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1528:12:1528:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_4 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1532:12:1532:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_3 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1536:12:1536:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_2 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1540:12:1540:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_1 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1544:12:1544:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1747:10:1747:21|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.af_set_cmp_6 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1744:10:1744:21|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.af_set_cmp_5 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1741:10:1741:21|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.af_set_cmp_4 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1738:10:1738:21|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.af_set_cmp_3 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1735:10:1735:21|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.af_set_cmp_2 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1732:10:1732:21|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.af_set_cmp_1 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1729:10:1729:21|Removing instance dumpmem_inst.dumpmem_dp_inst2.dumpmem_dpfifodc_inst.af_set_cmp_0 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":616:13:616:18|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.LUT4_1 of black_box view:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":620:13:620:18|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.LUT4_0 of black_box view:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1488:12:1488:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_14 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1492:12:1492:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_13 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1496:12:1496:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_12 of view:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1500:12:1500:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1504:12:1504:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1508:12:1508:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1512:12:1512:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_8 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1516:12:1516:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_7 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1520:12:1520:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_6 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1524:12:1524:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_5 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1528:12:1528:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_4 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1532:12:1532:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_3 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1536:12:1536:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_2 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1540:12:1540:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_1 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1544:12:1544:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1747:10:1747:21|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.af_set_cmp_6 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1744:10:1744:21|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.af_set_cmp_5 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1741:10:1741:21|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.af_set_cmp_4 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1738:10:1738:21|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.af_set_cmp_3 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1735:10:1735:21|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.af_set_cmp_2 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1732:10:1732:21|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.af_set_cmp_1 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1729:10:1729:21|Removing instance dumpmem_inst.dumpmem_dp_inst1.dumpmem_dpfifodc_inst.af_set_cmp_0 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":616:13:616:18|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.LUT4_1 of black_box view:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":620:13:620:18|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.LUT4_0 of black_box view:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1488:12:1488:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_14 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1492:12:1492:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_13 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1496:12:1496:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_12 of view:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1500:12:1500:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1504:12:1504:16|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1508:12:1508:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1512:12:1512:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_8 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1516:12:1516:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_7 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1520:12:1520:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_6 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1524:12:1524:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_5 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1528:12:1528:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_4 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1532:12:1532:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_3 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1536:12:1536:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_2 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1540:12:1540:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_1 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1544:12:1544:15|Removing sequential instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1747:10:1747:21|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.af_set_cmp_6 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1744:10:1744:21|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.af_set_cmp_5 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1741:10:1741:21|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.af_set_cmp_4 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1738:10:1738:21|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.af_set_cmp_3 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1735:10:1735:21|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.af_set_cmp_2 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1732:10:1732:21|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.af_set_cmp_1 of black_box view:work.AGEB2(verilog) because there are no references to its outputs @N: BN114 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1729:10:1729:21|Removing instance dumpmem_inst.dumpmem_dp_inst0.dumpmem_dpfifodc_inst.af_set_cmp_0 of black_box view:work.AGEB2(verilog) because there are no references to its outputs Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 87MB) #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== reset_sys_inst.rst_n:C Not Done adcif_inst.format_dout5[4]:C Not Done dumpmem_top_inst.jtag_interface_inst.jcex_r:C Not Done dumpmem_top_inst.jtag_interface_inst.ORCAstra_inst.ORCAstra_sub_inst.shift_dr_reg:C Not Done dumpmem_top_inst.jtag_interface_inst.ORCAstra_inst.ORCAstra_sub_inst.shift_cnt[4:0]:C Not Done ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 89MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 89MB) @N: BN114 :|Removing instance un2_counter_1_pt_0 of black_box view:LUCENT.MULT18X18C(PRIM) because there are no references to its outputs @N: BN114 :|Removing instance un2_counter_1_pt of black_box view:LUCENT.MULT18X18C(PRIM) because there are no references to its outputs Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 88MB peak: 89MB) Finished Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 89MB peak: 89MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:04s; Memory used current: 88MB peak: 89MB) Finished preparing to map (Time elapsed 0h:00m:05s; Memory used current: 89MB peak: 89MB) Finished technology mapping (Time elapsed 0h:00m:05s; Memory used current: 93MB peak: 94MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:06s -0.94ns 486 / 444 2 0h:00m:06s -0.92ns 486 / 444 3 0h:00m:06s -0.88ns 486 / 444 4 0h:00m:06s -0.66ns 486 / 444 5 0h:00m:06s -0.66ns 486 / 444 6 0h:00m:06s -0.66ns 486 / 444 ------------------------------------------------------------ @N: FX271 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Instance "jcex_reg" with 8 loads has been replicated 1 time(s) to improve timing @N: FX271 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Instance "shift_dr_reg" with 8 loads has been replicated 1 time(s) to improve timing Added 2 Registers via timing driven replication Added 1 LUTs via timing driven replication Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:15s -0.23ns 516 / 446 2 0h:00m:15s -0.23ns 516 / 446 3 0h:00m:15s -0.23ns 516 / 446 4 0h:00m:16s -0.23ns 516 / 446 5 0h:00m:16s -0.23ns 516 / 446 6 0h:00m:16s -0.23ns 516 / 446 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:16s -0.23ns 511 / 446 2 0h:00m:16s -0.23ns 511 / 446 3 0h:00m:16s -0.23ns 511 / 446 4 0h:00m:17s -0.23ns 511 / 446 ------------------------------------------------------------ @N: FX103 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dp.v":61:13:61:28|Instance "dumpmem_top_inst.dumpmem_inst.dumpmem_dp_inst4.un1_Reset_i" with "103" loads has been replicated "1" time(s) due to a soft fanout limit of "100" @N: FX103 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dp.v":61:13:61:28|Instance "dumpmem_top_inst.dumpmem_inst.dumpmem_dp_inst5.un1_Reset_i" with "103" loads has been replicated "1" time(s) due to a soft fanout limit of "100" @N: FX103 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":401:8:401:14|Instance "dumpmem_top_inst.dumpmem_inst.dumpmem_dp_inst7.un1_Reset_0_i" with "103" loads has been replicated "1" time(s) due to a soft fanout limit of "100" @N: FX103 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":401:8:401:14|Instance "dumpmem_top_inst.dumpmem_inst.dumpmem_dp_inst6.un1_Reset_0_i" with "103" loads has been replicated "1" time(s) due to a soft fanout limit of "100" Net buffering Report for view:work.TSW1405_1ch_bit_wise(verilog): Added 0 Buffers Added 0 Registers via replication Added 4 LUTs via replication Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:17s; Memory used current: 115MB peak: 117MB) @N: FX164 |The option to pack flops in the IOB has not been specified @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din54_r_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din76_r_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din32_r_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_mspi.v":176:0:176:5|Boundary register dumpmem_top_inst.dumpmem_inst.dumpmem_mspi_inst.din10_r_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":82:1:82:6|Boundary register dumpmem_top_inst.jtag_interface_inst.sync_sciwstn.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl0_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl0_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl0_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl0_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl0_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl0_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl0_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl0_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl1_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl1_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl1_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl1_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl1_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl1_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl1_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl1_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl3_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl3_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl3_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl3_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl3_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl3_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl3_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl3_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl4_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl4_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl4_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl4_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl4_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl4_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl4_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl4_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl5_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl5_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl5_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl5_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl5_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl5_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl5_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl5_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl6_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl6_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl6_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl6_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl6_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl6_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl6_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl6_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl7_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl7_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl7_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl7_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl7_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl7_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl7_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl7_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl8_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl8_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl8_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl8_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl8_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl8_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl8_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl8_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl9_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl9_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl9_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl9_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl9_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl9_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl9_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl9_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlA_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlA_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlA_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlA_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlA_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlA_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlA_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlA_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlC_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlC_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlC_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlC_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlC_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlC_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlC_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlC_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlD_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlD_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlD_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlD_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlD_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlD_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlD_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlD_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlF_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlF_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlF_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlF_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlF_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlF_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlF_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlF_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlB_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlB_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlB_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlB_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlB_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlB_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlB_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlB_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlE_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlE_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlE_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlE_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlE_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlE_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlE_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrlE_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl2_r_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl2_r_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl2_r_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl2_r_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl2_r_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl2_r_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl2_r_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\jtag_interface.v":95:0:95:5|Boundary register dumpmem_top_inst.jtag_interface_inst.ctrl2_r_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register sciwstn.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_19_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_20_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_21_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_22_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_23_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_24_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":130:0:130:5|Boundary register DataInReg_25_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Boundary register scirmxdatareg_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Boundary register scirmxdatareg_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Boundary register scirmxdatareg_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Boundary register scirmxdatareg_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Boundary register scirmxdatareg_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Boundary register scirmxdatareg_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Boundary register scirmxdatareg_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":110:0:110:5|Boundary register scirmxdatareg_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. --------------------------------------- Resource Usage Report Part: lfe3_35ea-8 Register bits: 1762 of 33264 (5%) PIC Latch: 0 I/O cells: 15 Block Rams : 64 of 72 (88%) Details: AND2: 16 CCU2C: 23 CU2: 196 DP16KC: 64 FADD2B: 84 FD1P3AX: 138 FD1P3BX: 28 FD1P3DX: 816 FD1P3IX: 134 FD1P3JX: 4 FD1S3AX: 110 FD1S3BX: 16 FD1S3DX: 470 FD1S3IX: 41 FD1S3JX: 3 GSR: 1 IB: 12 IFS1P3DX: 1 INV: 56 OB: 3 OFS1P3DX: 1 OR2: 8 ORCALUT4: 453 PFUMX: 25 PUR: 1 ROM16X1A: 328 VHI: 3 VLO: 3 XOR2: 208 Finished restoring hierarchy (Time elapsed 0h:00m:18s; Memory used current: 116MB peak: 117MB) Writing Analyst data base C:\Documents and Settings\a0840029\Desktop\TSW1405 1ch_bit_wise\TSW1405_1ch_bit_wise\TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:19s; Memory used current: 113MB peak: 117MB) Writing EDIF Netlist and constraint files E-2010.09L-SP2 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:20s; Memory used current: 119MB peak: 121MB) Writing Verilog Simulation files Finished Writing Verilog Simulation files (Time elapsed 0h:00m:21s; Memory used current: 119MB peak: 121MB) Writing VHDL Simulation files Finished Writing VHDL Simulation files (Time elapsed 0h:00m:22s; Memory used current: 119MB peak: 121MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:22s; Memory used current: 119MB peak: 121MB) @N: MF276 |Gated clock conversion enabled, but no gated clocks found in design Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:22s; Memory used current: 119MB peak: 121MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:22s; Memory used current: 119MB peak: 121MB) @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:22s; Memory used current: 119MB peak: 121MB) @W: MT246 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\tsw1405.v":72:5:72:12|Blackbox OSCF is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\orcastra.v":40:11:40:29|Blackbox jtagconn16 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\dumpmem_dpfifodc.v":1747:10:1747:21|Blackbox AGEB2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\adcif.v":150:10:150:23|Blackbox IDDRX2D1 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\adcif.v":142:7:142:12|Blackbox DELAYB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\documents and settings\a0840029\desktop\tsw1405 1ch_bit_wise\tsw1405_1ch_bit_wise\source\adcif.v":97:8:97:11|Blackbox CLKDIVB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock TSW1405_1ch_bit_wise|clk_lvds_rx_p with period 5.00ns. A user-defined clock should be declared on object "p:clk_lvds_rx_p" @W: MT420 |Found inferred clock TSW1405_1ch_bit_wise|clk_osc_inferred_clock with period 5.00ns. A user-defined clock should be declared on object "n:clk_osc" @W: MT420 |Found inferred clock ORCAstra_JTAGE_Hub_sub|sciwstn_inferred_clock with period 5.00ns. A user-defined clock should be declared on object "n:dumpmem_top_inst.jtag_interface_inst.ORCAstra_inst.ORCAstra_sub_inst.sciwstn" @W: MT420 |Found inferred clock ORCAstra_JTAGE_Hub_sub|jtck_1 with period 5.00ns. A user-defined clock should be declared on object "n:dumpmem_top_inst.jtag_interface_inst.ORCAstra_inst.ORCAstra_sub_inst.jtck_1" @W: MT420 |Found inferred clock adcif|clk_adc_inferred_clock with period 5.00ns. A user-defined clock should be declared on object "n:adcif_inst.clk_adc" ##### START OF TIMING REPORT #####[ # Timing Report written on Sun Jan 08 17:39:38 2012 # Top view: TSW1405_1ch_bit_wise Requested Frequency: 200.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.. Performance Summary ******************* Worst slack in design: -1.180 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------ ORCAstra_JTAGE_Hub_sub|jtck_1 200.0 MHz 135.9 MHz 5.000 7.360 -1.180 inferred Inferred_clkgroup_3 ORCAstra_JTAGE_Hub_sub|sciwstn_inferred_clock 200.0 MHz NA 5.000 NA NA inferred Inferred_clkgroup_2 TSW1405_1ch_bit_wise|clk_lvds_rx_p 200.0 MHz 1076.1 MHz 5.000 0.929 4.071 inferred Inferred_clkgroup_4 TSW1405_1ch_bit_wise|clk_osc_inferred_clock 200.0 MHz 317.9 MHz 5.000 3.146 1.854 inferred Inferred_clkgroup_1 adcif|clk_adc_inferred_clock 200.0 MHz 339.1 MHz 5.000 2.949 2.051 inferred Inferred_clkgroup_0 System 200.0 MHz 719.4 MHz 5.000 1.390 3.610 system system_clkgroup ====================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 5.000 3.610 | No paths - | No paths - | No paths - System adcif|clk_adc_inferred_clock | 5.000 3.297 | No paths - | No paths - | No paths - System TSW1405_1ch_bit_wise|clk_osc_inferred_clock | 5.000 2.614 | No paths - | No paths - | No paths - System ORCAstra_JTAGE_Hub_sub|jtck_1 | No paths - | No paths - | 5.000 4.712 | No paths - adcif|clk_adc_inferred_clock System | 5.000 1.046 | No paths - | No paths - | No paths - adcif|clk_adc_inferred_clock adcif|clk_adc_inferred_clock | 5.000 2.051 | No paths - | No paths - | No paths - adcif|clk_adc_inferred_clock TSW1405_1ch_bit_wise|clk_osc_inferred_clock | Diff grp - | No paths - | No paths - | No paths - TSW1405_1ch_bit_wise|clk_osc_inferred_clock System | 5.000 1.046 | No paths - | No paths - | No paths - TSW1405_1ch_bit_wise|clk_osc_inferred_clock adcif|clk_adc_inferred_clock | Diff grp - | No paths - | No paths - | No paths - TSW1405_1ch_bit_wise|clk_osc_inferred_clock TSW1405_1ch_bit_wise|clk_osc_inferred_clock | 5.000 1.854 | No paths - | No paths - | No paths - TSW1405_1ch_bit_wise|clk_osc_inferred_clock ORCAstra_JTAGE_Hub_sub|jtck_1 | No paths - | No paths - | Diff grp - | No paths - TSW1405_1ch_bit_wise|clk_osc_inferred_clock TSW1405_1ch_bit_wise|clk_lvds_rx_p | Diff grp - | No paths - | No paths - | No paths - ORCAstra_JTAGE_Hub_sub|sciwstn_inferred_clock TSW1405_1ch_bit_wise|clk_osc_inferred_clock | No paths - | No paths - | No paths - | Diff grp - ORCAstra_JTAGE_Hub_sub|jtck_1 System | 5.000 4.359 | No paths - | No paths - | No paths - ORCAstra_JTAGE_Hub_sub|jtck_1 TSW1405_1ch_bit_wise|clk_osc_inferred_clock | Diff grp - | No paths - | No paths - | No paths - ORCAstra_JTAGE_Hub_sub|jtck_1 ORCAstra_JTAGE_Hub_sub|sciwstn_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - ORCAstra_JTAGE_Hub_sub|jtck_1 ORCAstra_JTAGE_Hub_sub|jtck_1 | 5.000 1.788 | No paths - | 2.500 -1.180 | 2.500 0.291 TSW1405_1ch_bit_wise|clk_lvds_rx_p System | 5.000 4.018 | No paths - | No paths - | No paths - TSW1405_1ch_bit_wise|clk_lvds_rx_p TSW1405_1ch_bit_wise|clk_lvds_rx_p | 5.000 4.071 | No paths - | No paths - | No paths - ===================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ----------------------------------------------------------------------------------------- clk_lvds_rx_p NA NA NA NA NA clk_spi System (rising) NA 0.000 3.525 lvds_rx_port0_p[0] NA NA NA NA NA lvds_rx_port0_p[1] NA NA NA NA NA lvds_rx_port0_p[2] NA NA NA NA NA lvds_rx_port0_p[3] NA NA NA NA NA lvds_rx_port0_p[4] System (rising) NA 0.000 3.610 lvds_rx_port0_p[5] System (rising) NA 0.000 3.610 lvds_rx_port0_p[6] System (rising) NA 0.000 3.610 lvds_rx_port0_p[7] System (rising) NA 0.000 3.610 lvds_rx_port0_p[8] NA NA NA NA NA lvds_rx_port0_p[9] System (rising) NA 0.000 3.610 lvds_rx_port0_p[10] System (rising) NA 0.000 3.610 lvds_rx_port0_p[11] System (rising) NA 0.000 3.610 lvds_rx_port0_p[12] System (rising) NA 0.000 3.610 lvds_rx_port0_p[13] NA NA NA NA NA lvds_rx_port0_p[14] NA NA NA NA NA lvds_rx_port0_p[15] NA NA NA NA NA lvds_rx_port0_p[16] NA NA NA NA NA lvds_rx_port1_p[0] NA NA NA NA NA lvds_rx_port1_p[1] NA NA NA NA NA lvds_rx_port1_p[2] NA NA NA NA NA lvds_rx_port1_p[3] NA NA NA NA NA lvds_rx_port1_p[4] NA NA NA NA NA lvds_rx_port1_p[5] NA NA NA NA NA lvds_rx_port1_p[6] NA NA NA NA NA lvds_rx_port1_p[7] NA NA NA NA NA lvds_rx_port1_p[8] NA NA NA NA NA lvds_rx_port1_p[9] NA NA NA NA NA lvds_rx_port1_p[10] NA NA NA NA NA lvds_rx_port1_p[11] NA NA NA NA NA reset_n NA NA NA NA NA spi_mosi NA NA NA NA NA spi_ss System (rising) NA 0.000 2.614 ========================================================================================= Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------------------------------------- led adcif|clk_adc_inferred_clock (rising) NA 3.954 5.000 regbit TSW1405_1ch_bit_wise|clk_osc_inferred_clock (rising) NA 3.954 5.000 spi_miso TSW1405_1ch_bit_wise|clk_osc_inferred_clock (rising) NA 3.910 5.000 =================================================================================================================== ##### END OF TIMING REPORT #####] Mapper successful! Process took 0h:00m:23s realtime, 0h:00m:23s cputime # Sun Jan 08 17:39:39 2012 ###########################################################]