PAR: Place And Route Diamond_1.2_Production (92).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Sun Jan 08 17:41:22 2012

C:/lscc/diamond/1.2/ispfpga\bin\nt\par -f
TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.p2t
TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise_map.ncd
TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.dir
TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.prf

Preference file: TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.prf.

Cost Table Summary
Level/      Number      Timing      Run         NCD
Cost [ncd]  Unrouted    Score       Time        Status
----------  --------    --------    -----       ------------
5_1   *     0           11628       47          Complete        


* : Design saved.

par done!

Lattice Place and Route Report for Design "TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise_map.ncd"
Sun Jan 08 17:41:22 2012


Best Par Run
PAR: Place And Route Diamond_1.2_Production (92).
Command line: C:/lscc/diamond/1.2/ispfpga\bin\nt\par -f
TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.p2t
TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise_map.ncd
TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.dir
TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.prf
Preference file: TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise_map.ncd.
Design name: TSW1405_1ch_bit_wise
NCD version: 3.2
Vendor:      LATTICE
Device:      LFE3-35EA
Package:     FPBGA484
Speed:       8
Loading device for application par from file 'ec5a71x74.nph' in environment: C:/lscc/diamond/1.2/ispfpga.
Package Status:               Final          Version 1.59
Speed Hardware Data Status:   Final          Version 28.22
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)      24/332           7% used
                     24/295           8% bonded
   IOLOGIC           10/328           3% used

   SLICE           1582/16632         9% used

   GSR                1/1           100% used
   OSC                1/1           100% used
   CLKDIV             1/2            50% used
   JTAG               1/1           100% used
   EBR               64/72           88% used


Number of Signals: 3944
Number of Connections: 11778

Pin Constraint Summary:
   15 out of 15 pins locked (100% locked).

The following 4 signals are selected to use the primary clock routing resources:
    clk_adc_c (driver: adcif_inst/div2, clk load #: 511)
    clk_osc_inferred_clock (driver: OSCInst0, clk load #: 625)
    jtaghub16_jtck (driver: ep5chub/genblk0_genblk5_jtage_u, clk load #: 72)
    dumpmem_top_inst/jtag_interface_inst/sciwstn (driver: dumpmem_top_inst/jtag_interface_inst/ORCAstra_inst/ORCAstra_sub_inst/SLICE_1185, clk load #: 14)


The following 5 signals are selected to use the secondary clock routing resources:
    sys_rst_n (driver: reset_sys_inst/SLICE_1219, clk load #: 0, sr load #: 77, ce load #: 1)
    dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst3/un1_Reset_0_i (driver: dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst3/SLICE_1572, clk load #: 0, sr load #: 52, ce load #: 0)
    dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst2/un1_Reset_i_0 (driver: dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst2/SLICE_1575, clk load #: 0, sr load #: 52, ce load #: 0)
    dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst1/un1_Reset_i_1 (driver: dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst1/SLICE_1578, clk load #: 0, sr load #: 52, ce load #: 0)
    dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst0/un1_Reset_i_2 (driver: dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst0/SLICE_1581, clk load #: 0, sr load #: 52, ce load #: 0)

Signal dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst7/dumpmem_dpfifodc_inst/rRst is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 7 secs 

CDP(congestion driven placement) auto mode does not turn on CDP.
	To force CDP on, set -exp parCDP=1
Starting Placer Phase 1.
.......................
Placer score = 1209730.
Finished Placer Phase 1.  REAL time: 19 secs 

Starting Placer Phase 2.
.
Placer score =  1198965
Finished Placer Phase 2.  REAL time: 19 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 6 (0%)
  PLL        : 0 out of 4 (0%)
  DCS        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "clk_adc_c" from CDIV2 on comp "adcif_inst/div2" on CLKDIV site "CLKDIV_R35C15", clk load = 511
  PRIMARY "clk_osc_inferred_clock" from comp "OSCInst0" on site "OSC", clk load = 625
  PRIMARY "jtaghub16_jtck" from JTCK on comp "ep5chub/genblk0_genblk5_jtage_u" on site "JTAG", clk load = 72
  PRIMARY "dumpmem_top_inst/jtag_interface_inst/sciwstn" from Q0 on comp "dumpmem_top_inst/jtag_interface_inst/ORCAstra_inst/ORCAstra_sub_inst/SLICE_1185" on site "R33C2A", clk load = 14
  SECONDARY "sys_rst_n" from Q0 on comp "reset_sys_inst/SLICE_1219" on site "R36C2C", clk load = 0, ce load = 1, sr load = 77
  SECONDARY "dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst3/un1_Reset_0_i" from F0 on comp "dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst3/SLICE_1572" on site "R34C2C", clk load = 0, ce load = 0, sr load = 52
  SECONDARY "dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst2/un1_Reset_i_0" from F0 on comp "dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst2/SLICE_1575" on site "R61C37D", clk load = 0, ce load = 0, sr load = 52
  SECONDARY "dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst1/un1_Reset_i_1" from F0 on comp "dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst1/SLICE_1578" on site "R61C36D", clk load = 0, ce load = 0, sr load = 52
  SECONDARY "dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst0/un1_Reset_i_2" from F0 on comp "dumpmem_top_inst/dumpmem_inst/dumpmem_dp_inst0/SLICE_1581" on site "R61C36A", clk load = 0, ce load = 0, sr load = 52

  PRIMARY  : 4 out of 8 (50%)
     DCS   : 0 out of 2 (0%)
     DCC   : 4 out of 6 (66%)
  SECONDARY: 5 out of 8 (62%)

Edge Clocks:
  ECLK "clk_lvds_rx_p_c" from CLK_PIN "L4", driver "clk_lvds_rx_p", LECLK2

Regional Secondary Clocks:
  No regional secondary clock selected.




I/O Usage Summary (final):
   24 out of 332 (7.2%) PIO sites used.
   24 out of 295 (8.1%) bonded PIO sites used.
   Number of PIO comps: 15; differential: 9
   Number of Vref pins used: 0

I/O Bank Usage Summary:
----------+------------------+-------+-----------------+----------------
 I/O Bank | Usage            | Vccio |  Vref1 / Vref2  |  Vtt
----------+------------------+-------+-----------------+----------------
    0     |   0 / 42  (  0%) |  OFF  |    OFF / OFF    |               
    1     |   0 / 36  (  0%) |  OFF  |    OFF / OFF    |               
    2     |   0 / 28  (  0%) |  OFF  |    OFF / OFF    |               
    3     |   0 / 58  (  0%) |  OFF  |    OFF / OFF    |               
    6     |  18 / 67  ( 26%) | 1.2V  |    OFF / OFF    | Float1.25, 1.25
    7     |   0 / 40  (  0%) |  OFF  |    OFF / OFF    |               
    8     |   6 / 24  ( 25%) | 2.5V  |    OFF / OFF    |               
----------+------------------+-------+-----------------+----------------

---------------------------------- DSP Report ----------------------------------

DSP Slice #:           1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16
# of MULT9X9C                                                        
# of MULT18X18C                                                      
# of ALU24A                                                          
# of ALU54A                                                          

DSP Slice #:          17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
# of MULT9X9C                                                        
# of MULT18X18C                                                      
# of ALU24A                                                          
# of ALU54A                                                          

------------------------------ End of DSP Report -------------------------------
Total placer CPU time: 19 secs 

Dumping design to file TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.dir/5_1.ncd.

0 connections routed; 11778 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 34 secs 

Congestion Driven Router (CDR) is turned on.
CDR effort level is set at 0.
To turn CDR off, please set "-exp parCDR=0" on command line.

Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design setup analysis has met timing constraints.

End of iteration 1
11778 successful; 0 unrouted; (0) real time: 39 secs 
Dumping design to file TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.dir/5_1.ncd.
Total CPU time 39 secs 
Total REAL time: 39 secs 
Completely routed.
End of route.  11778 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

WARNING - par: Clock compensation cannot be calculated for signal clk_lvds_rx_p_c because it is not constrained. Please add a frequency preference to it.
Timing score: 11628 

Total REAL time to completion: 47 secs 

Dumping design to file TSW1405_1ch_bit_wise_TSW1405_1ch_bit_wise.dir/5_1.ncd.


All signals are completely routed.


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.